SN65LVDS17 [TI]
2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS; 2.5 V / 3.3 V振荡器增益级/缓冲区
| 型号： | SN65LVDS17 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS |
| 文件： | 总15页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
www.ti.com
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS
FEATURES
•
2-mm × 2-mm Small-Outline
No-Lead Package
•
Low-Voltage PECL Input and Low-Voltage
PECL or LVDS Outputs
APPLICATIONS
•
•
•
Clock Rates to 2 GHz
PECL-to-LVDS Translation
Clock Signal Amplification
– 140-ps Output Transition Times
– 0.11 ps Typical Intrinsic Phase Jitter
– Less than 630 ps Propagation Delay Times
2.5-V or 3.3-V Supply Operation
•
DESCRIPTION
These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain
outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on
the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV
either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The
Q on the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended
PECL input signals. When not used, VBB should be unconnected or open.
All devices are characterized for operation from –40°C to 85°C.
SN65LVDS17, SN65LVP17
4 mA
SN65LVDS16, SN65LVP16
4 mA
Q
Q
A
Y
Z
A
B
Y
Z
V
BB
V
V
REF
V
CC
V
BB
V
CC
REF
EN
EN
GC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
www.ti.com
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS(1)
INPUT
OUTPUT
LVDS
GAIN CONTROL
BASE PART NUMBER
SN65LVDS16
SN65LVP16
PART MARKING
Single-ended
Single-ended
Differential
Differential
Yes
Yes
No
EL
EK
EN
EM
LVPECL
LVDS
SN65LVDS17
SN65LVP17
LVPECL
No
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
VCC
VI
Supply voltage(2)
–0.5 V to 4 V
–0.5 V to VCC + 0.5 V
–0.5 V to VCC + 0.5 V
±0.5 mA
Input voltage
VO
IO
Output voltage
VBB output current
HBM electrostatic discharge(3)
CDM electrostatic discharge(4)
Continuous power dissipation
±3 kV
±1500 V
See Power Dissipation Ratings Table
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to network ground see Figure 1).
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A-7
(4) Tested in accordance with JEDEC Standard 22, Test Method C101
DISSIPATION RATINGS
TA≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C(1)
TA = 85°C
POWER RATING
PACKAGE
CIRCUIT BOARD MODEL
Low-K(2)
High-K(3)
403 mW
834 mW
4.0 mW/°C
8.3 mW/°C
161 mW
333 mW
DRF
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
93.3
101.7
132
UNIT
θJB
θJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
°C/W
VCC = 3.3 V, TA = 25°C, 2 GHz, LVDS
VCC = 3.3 V, TA = 25°C, 2 GHz, LVPECL
VCC = 3.6 V, TA = 85°C, 2 GHz, LVDS
VCC = 3.6 V, TA = 85°C, 2 GHz, LVPECL
Typical
83
PD
Device power dissipation
mW
173
Maximum
108
2
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
www.ti.com
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX UNIT
VCC Supply voltage
2.375 2.5 or 3.3
3.6
V
V
V
VIC
Common-mode input voltage (VIA + VIB)/2
Differential input voltage magnitude |VIA - VIB
SN65LVDS17 or SN65LVP17
SN65LVDS17 or SN65LVP17
EN
1.2
0.08
2
VCC – (VID/2)
|VID
|
|
1
VCC
VIH
VIL
High-level input voltage to EN
Low-level input voltage to EN
V
V
SN65LVDS16 or SN65LVP16
EN
VCC– 1.17
VCC– 0.44
0.8
0
VCC– 2.25
–400(1)
90
SN65LVDS16 or SN65LVP16
VCC– 1.52
400
IO
Output current to VBB
µA
Ω
RL
TA
Differential load resistance,
Operating free-air temperature
132
-40
85
°C
(1) The algebraic convention, where the least positive (more negative) value is designated minimum, is used in this data sheet.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
RL = 100 Ω, EN at 0 V,
Other inputs open
40
48
ICC
Supply current
mA
30
Outputs unloaded,
EN at 0 V, Other inputs open
25
VBB
Reference voltage(2)
IBB = –400 µA
VI = 2 V
VCC– 1.44
–20
VCC– 1.35
VCC– 1.25
V
IIH
High-level input current, EN
High-level input current, A or B
Low-level input current, EN
Low-level input current, A or B
20
20
20
20
IIAH or IIBH
IIL
VI = VCC
–20
µA
VI = 0.8 V
VI = GND
–20
IIAL or IIBL
–20
SN65LVDS16/17 Y AND Z OUTPUT CHARACTERISTICS
Differential output voltage magnitude,
|VOD
|
247
340
454
50
|VOY– VOZ
|
mV
V
Change in differential output voltage
magnitude between logic states
∆|VOD
|
See Figure 1 and Figure 2
Steady-state common-mode output
voltage (see Figure 3)
VOC(SS)
∆VOC(SS)
VOC(PP)
1.125
-50
1.375
Change in steady-state common-
mode output voltage between logic
states
50
See Figure 3
mV
Peak-to-peak common-mode output
voltage
50
100
IOYZ or IOZZ High-impedance output current
IOYS or IOZS Short-circuit output current
EN at VCC, VO = 0 V or VCC
EN at 0 V, VOY or VOZ = 0 V
–1
1
µA
–62
62
mA
Differential short-circuit
IOS(D)
EN at 0 V, VOY = VOZ
–12
12
output current, |IOY– IOZ
|
(1) Typical values are at room temperature and with a VCC of 3.3 V.
(2) Single-ended input operation is limited to VCC≥ 3.0 V.
3
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
www.ti.com
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
SN65LVP16/17 Y AND Z OUTPUT CHARACTERISTICS
VOYH or
VOZH
High-level output voltage
VCC– 1.05
VCC– 1.83
VCC– 1.88
VCC– 0.82
3.3 V; 50 Ω from Y and Z
to VCC– 2 V
VOYL or
VOZL
Low-level output voltage
VCC– 1.57
VCC– 1.57
V
VOYL or
VOZL
2.5 V; 50 Ω from Y and Z
to VCC– 2 V
Low-level output voltage
Differential output voltage magnitude,
|VOD
|
0.6
–1
0.8
1
1
|VOH– VOL
|
IOYZ or IOZZ High-impedance output current
EN at VCC, VO = 0 V or VCC
µA
V
Q OUTPUT CHARACTERISTICS (see Figure 1)
VOH
High-level output voltage
No load
VCC– 0.94
VCC– 1.22
VCC– 1.52
VCC– 1.82
300
GC Tied to GND, No load
GC Open, No load
GC Tied to VCC, No load
GC Tied to GND
GC Open
VOL
Low-level output voltage
V
VO(pp)
Peak-to-peak output voltage
575
mV
GC Tied to VCC
860
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
A to Q
340
460
460
630
20
tPD
Propagation delay time, tPLH or tPHL
D to Y or Z
See Figure 4
ps
tSK(P)
Pulse skew, |tPLH– tPHL|
VCC = 3.3 V
VCC = 2.5 V
80
tSK(PP) Part-to-part skew(2)
ps
130
140
140
3
tr
tf
20%-to-80% differential signal rise time
20%-to-80% differential signal fall time
85
85
ps
ps
See Figure 4
tjit(per) RMS period jitter(3)
tjit(cc)
Peak cycle-to-cycle jitter(4)
tjit(ph)
2
2-GHz 50%-duty-cycle square-wave input,
See Figure 5
ps
ps
15
23
Intrinsic phase jitter
2 GHz
0.11
Propagation delay time,
high-level-to-high-impedance output
tPHZ
tPLZ
tPZH
tPZL
30
30
30
30
Propagation delay time,
low-level-to-high-impedance output
See Figure 6
ns
Propagation delay time,
high-impedance-to-high-level output
Propagation delay time,
high-impedance-to-low-level output
(1) Typical values are at room temperature and with a VCC of 3.3 V.
(2) Part-to-part skew is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
(4) Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle
pairs.
4
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
www.ti.com
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
I
CC
8
V
1
3
6
7
CC
Q
2
4
5
A
V
BB
50 W
50 W
I
IA
D.U.T.
I
BB
GC
EN
Z
S1
I
OZ
I
IGC
Y
GND
9
+
V
CC
− 2 V
I
I
_
I
OY
C
L
V
IA
V
I
V
I
+
OY
−
+
−
+
BB
−
+
−
+
+
+
+
_
_
_
V
V
OZ
V
V
O
V
OC
−
(1) CL is the instrumentation and test fixture capacitance.
(2) S1 is open for the SN65LVDS16 and closed for the SN65LVP16.
Figure 1. Output Voltage Test Circuit and Voltage and Current Definitions for LVDS/LVP16
V
CC
I
CC
8
V
1
4
6
7
CC
Q
2
3
5
A
B
V
BB
50 W
50 W
I
IA
D.U.T.
I
BB
Z
S1
I
OZ
I
IB
Y
EN
GND
9
+
V
CC
− 2 V
I
I
_
I
OY
C
L
V
IA
V
IB
V
I
+
OY
−
+
−
+
BB
−
+
−
+
+
+
+
_
_
_
V
V
OZ
V
V
O
V
OC
−
(1) CL is the instrumentation and test fixture capacitance.
(2) S1 is open for the SN65LVDS17 and closed for the SN65LVP17.
Figure 2. Output Voltage Test Circuit and Voltage and Current Definitions for LVDS/LVP17
INPUT
V
dV
OC(SS) OC(PP)
V
OC
Figure 3. VOC Definitions
5
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
www.ti.com
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
1.2 V
1.125 V
V
V
IA
1.5 V
IB
t
t
PLH
PHL
V
− V
OZ
OY
100%
80%
50%
t
f
t
r
20%
Figure 4. Propagation Delay and Transition Time Test Waveforms
50 W Cable, X + Y cm, SMA Coax
Connectors, 4 Places
TDS Oscilloscope with
TJIT3 Analysis Pack
Device Under Test
HP3104 Pattern
Generator
50 W
50 W
DC
Figure 5. Jitter Measurement Setup
6
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
www.ti.com
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
1.2 V
V
IA
1.5 V
V
IB
V to EN
I
2 V
1.4 V
t
t
0.8 V
PZH
PZL
t
t
0 V
PHZ
PLZ
V
− V
OZ
100%
OY
80%
50%
20%
Figure 6. Enable and Disable Time Test Waveforms
7
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
www.ti.com
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
DEVICE INFORMATION
FUNCTION TABLE
SN65LVDS16, SN65LVP16(1)
SN65LVDS17, SN65LVP17(1)
A
H
EN
Q
L
Y
H
L
Z
L
H
Z
?
?
A
H
B
H
EN
Q
?
H
L
?
?
?
?
Y
?
L
H
?
Z
?
?
Z
?
H
L
?
Z
?
?
L
L
L
L
H
?
L
H
L
X
H
Z
?
H
L
L
L
Open
X
L
?
L
L
Open
?
?
X
X
H
Open
X
Open
X
L
Open
(1) H = high, L = low, Z = high impedance, ? = indeterminate
DRF PACKAGE
TOP VIEW
1
8
4
9
5
BOTTOM VIEW
Package Pin Assignments - Numerical Listing
SN65LVDS16, SN65LVP16
PIN SIGNAL
SN65LVDS17, SN65LVP17
PIN SIGNAL
1
Q
1
Q
2
3
4
5
6
7
8
9
A
VBB
GC
EN
Z
2
3
4
5
6
7
8
9
A
B
VBB
EN
Z
Y
Y
VCC
GND
VCC
GND
8
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
www.ti.com
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
FREQUENCY
65
55
45
35
65
55
45
35
25
15
LVP16/17 = Load
LVDS16/17
LVP16/17 = Load
LVDS16/17
25
15
−40 −20
0
20
40
60
80
100
0
400
800
1200
1600
2000
T
A
− Free−Air Temperature − C
f − Frequency − MHz
Figure 7.
Figure 8.
LVDS16/17 RISE/FALL TIME
vs
FREE-AIR TEMPERATURE
LVP16/17 RISE/FALL TIME
vs
FREE-AIR TEMPERATURE
105
97
89
81
73
65
105
97
89
81
73
65
t
f
t
r
t
r
t
f
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T
A
− Free−Air Temperature − C
T
A
− Free−Air Temperature − C
Figure 9.
Figure 10.
LVDS16/17
PERIOD JITTER
vs
FREQUENCY
CYCLE-TO-CYCLE JITTER
PROPAGATION DELAY TIME
vs
vs
FREQUENCY
FREE-AIR TEMPERATURE
25
20
15
10
5
524
500
476
452
428
404
5
4
3
2
1
t
PLH
t
PHL
0
0
0
400
800
1200
1600
2000
0
400
800
1200
1600
2000
−40 −20
0
20
40
60
80
100
f − Frequency − MHz
T
A
− Free−Air Temperature − C
f − Frequency − MHz
Figure 11.
Figure 12.
Figure 13.
9
SN65LVDS16, SN65LVP16
SN65LVDS17, SN65LVP17
www.ti.com
SLLS625B–SEPTEMBER 2004–REVISED NOVEMBER 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
OUTPUT LVP16/17
OUTPUT LVDS16/17
V
CC
V
CC
V
CC
V
CC
V
CC
R
R
Y
V
CC
Y
Z
7 V
Z
7 V
7 V
7 V
V
CC
ENABLE
400 Ω
300 kΩ
7 V
INPUT
V
CC
OUTPUT
V
BB
V
CC
V
CC
V
CC
A
B
V
BB
V
BB
10
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
SN65LVDS16DRFR
SN65LVDS16DRFRG4
SN65LVDS16DRFT
SN65LVDS16DRFTG4
SN65LVDS17DRFR
SN65LVDS17DRFRG4
SN65LVDS17DRFT
SN65LVDS17DRFTG4
SN65LVP16DRFR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SON
DRF
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRF
DRF
DRF
DRF
DRF
DRF
DRF
DRF
DRF
DRF
DRF
DRF
DRF
DRF
DRF
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVP16DRFRG4
SN65LVP16DRFT
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVP16DRFTG4
SN65LVP17DRFR
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVP17DRFRG4
SN65LVP17DRFT
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVP17DRFTG4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 2
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