SN65LVDS179_07 [TI]
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS; 高速差分线路驱动器和接收
| 型号： | SN65LVDS179_07 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS |
| 文件： | 总27页 (文件大小：1298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS179, SN65LVDS180
SN65LVDS050, SN65LVDS051
www.ti.com
SLLS301O–APRIL 1998–REVISED MAY 2007
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
FEATURES
SN65LVDS179D (Marked as DL179 or LVD179)
SN65LVDS179DGK (Marked as S79)
(TOP VIEW)
•
Meets or Exceeds the Requirements of ANSI
TIA/EIA-644-1995 Standard
5
6
8
7
3
2
Y
Z
D
VCC
R
D
A
B
Z
Y
1
2
3
4
8
7
6
5
•
Full-Duplex Signaling Rates up to 100 Mbps
(See Table 1)
A
B
R
•
•
•
Bus-Terminal ESD Exceeds 12 kV
Operates From a Single 3.3-V Supply
GND
Low-Voltage Differential Signaling With
Typical Output Voltages of 350 mV and a
100-Ω Load
SN65LVDS180D (Marked as LVDS180)
SN65LVDS180PW (Marked as LVDS180)
(TOP VIEW)
9
•
•
Propagation Delay Times
NC
R
RE
VCC
VCC
A
1
2
3
4
5
6
7
14
13
12
11
10
9
5
Y
Z
D
10
–
–
Driver: 1.7 ns Typ
4
3
DE
RE
Receiver: 3.7 ns Typ
DE
D
B
Z
12
11
Power Dissipation at 200 MHz
A
B
2
R
–
–
Driver: 25 mW Typical
GND
GND
Y
NC
8
Receiver: 60 mW Typical
•
•
LVTTL Input Levels Are 5-V Tolerant
Receiver Maintains High Input Impedance
With VCC < 1.5 V
SN65LVDS050D (Marked as LVDS050)
SN65LVDS050PW (Marked as LVDS050)
(TOP VIEW)
14
13
15
1Y
1Z
1D
•
Receiver Has Open-Circuit Fail Safe
12
9
1B
1A
1R
VCC
1D
1Y
1Z
DE
2Z
1
2
3
4
5
6
7
8
16
15
14
13
12
11
DE
2D
10
11
2Y
2Z
DESCRIPTION
The
SN65LVDS179,
SN65LVDS180,
RE
2R
2
1
3
1A
1B
SN65LVDS050, and SN65LVDS051 are differential
line drivers and receivers that use low-voltage
differential signaling (LVDS) to achieve signaling
rates as high as 400 Mbps (see the Application
Information section). The TIA/EIA-644 standard
compliant electrical interface provides a minimum
differential output voltage magnitude of 247 mV into
a 100-Ω load and receipt of 50-mV signals with up to
1 V of ground potential difference between a
transmitter and receiver.
1R
2A
4
5
RE
2R
6
7
2B
GND
10 2Y
2D
2A
2B
9
SN65LVDS051D (Marked as LVDS051)
SN65LVDS051PW (Marked as LVDS051)
(TOP VIEW)
14
13
15
1Y
1Z
1D
1B
1A
1R
VCC
1D
1Y
1
2
3
4
5
6
7
8
16
15
14
13
12
4
3
1DE
1R
2
1
The intended application of this device and signaling
technique is for point-to-point baseband data
transmission over controlled impedance media of
approximately 100-Ω characteristic impedance. The
transmission media may be printed-circuit board
traces, backplanes, or cables. (Note: The ultimate
rate and distance of data transfer depends on the
attenuation characteristics of the media, the noise
coupling to the environment, and other application
specific characteristics).
1A
1B
1DE
2R
1Z
2DE
10
11
9
2Y
2Z
2D
2A
11 2Z
12
5
10
9
2B
GND
2Y
2D
2DE
2R
6
7
2A
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDS179, SN65LVDS180
SN65LVDS050, SN65LVDS051
www.ti.com
SLLS301O–APRIL 1998–REVISED MAY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
These devices offer various driver, receiver, and enabling combinations in industry-standard footprints. Because
these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function
does not put the differential outputs into a high-impedance state but rather disconnects the input and reduces
the quiescent power used by the device. (For these functions with a high-impedance driver output, see the
SN65LVDM series of devices.) All devices are characterized for operation from -40°C to 85°C.
Table 1. Maximum Recommended Operating Speeds
Part Number
SN65LVDS179
SN65LVDS180
SN65LVDS050
SN65LVDS051
All Buffers Active
150 Mbps
Rx Buffer Only
150 Mbps
Tx Buffer Only
400 Mbps
150 Mbps
150 Mbps
400 Mbps
100 Mbps
100 Mbps
400 Mbps
100 Mbps
100 Mbps
400 Mbps
AVAILABLE OPTIONS(1)
PACKAGE
SMALL OUTLINE
(D)
SMALL OUTLINE
(DGK)
SMALL OUTLINE
(PW)
SN65LVDS050D
SN65LVDS051D
SN65LVDS179D
SN65LVDS180D
—
SN65LVDS050PW
SN65LVDS051PW
—
—
SN65LVDS179DGK
—
SN65LVDS180PW
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
FUNCTION TABLES
SN65LVDS179 RECEIVER
INPUTS
OUTPUT(1)
VID = VA - VB
R
H
?
VID ≥ 50 mV
50 mV < VID < 50 mV
VID ≤ -50 mV
L
Open
H
(1) H = high level, L = low level, ? = indeterminate
SN65LVDS179 DRIVER(1)
INPUT
OUTPUTS
D
L
Y
L
Z
H
L
H
H
L
Open
H
(1) H = high level, L = low level
2
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SN65LVDS050, SN65LVDS051
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SLLS301O–APRIL 1998–REVISED MAY 2007
SN65LVDS180, SN65LVDS050, and
SN65LVDS051 RECEIVER(1)
INPUTS
OUTPUT
VID = VA - VB
ID≥ 50 mV
50 mV < VID < 50 mV
RE
L
R
H
?
V
L
V
ID≤ -50 mV
Open
X
L
L
L
H
Z
H
(1) H = high level, L = low level, Z = high impedance, X = don't care,
? = indeterminate
SN65LVDS180, SN65LVDS050, and
SN65LVDS051 DRIVER(1)
INPUTS
OUTPUTS
D
L
DE
H
Y
L
Z
H
H
H
H
L
Open
X
H
L
H
L
Off
Off
(1) H = high level, L = low level, Z = high impedance, X = don't care,
Off = no output
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
V
CC
300 kΩ
50 Ω
5 Ω
50 Ω
10 kΩ
Y or Z
Output
D or
RE
Input
DE
Input
7 V
7 V
7 V
300 kΩ
V
CC
V
CC
300 kΩ
300 kΩ
5 Ω
R Output
A Input
B Input
7 V
7 V
7 V
3
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SN65LVDS050, SN65LVDS051
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SLLS301O–APRIL 1998–REVISED MAY 2007
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
(2)
VCC (see
)
Supply voltage range
Voltage range:
–0.5 V to 4 V
–0.5 V to 6 V
D, R, DE, RE
Y, Z, A, and B
–0.5 V to 4 V
|VOD
|
Differential output voltage:
Electrostatic discharge:
1 V
(3)
Y, Z, A, B , and GND (see
All
)
CLass 3, A:12 kV, B:600 V
Class 3, A:7 kV, B:500 V
See Dissipation Rating Table
–65°C to 150°C
250°C
Continuous power dissipation
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
(3) Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
TA≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C(1)
TA = 85°C
POWER RATING
PACKAGE
PW(14)
PW(16)
D(8)
736 mW
839 mW
635 mW
987 mW
1110 mW
424 mW
5.9 mW/°C
6.7 mW/°C
5.1 mW/°C
7.9 mW/°C
8.9 mW/°C
3.4 mW/°C
383 mW
437 mW
330 mW/°C
513 mW/°C
577 mW/°C
220 mW
D(14)
D(16)
DGK
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no airflow.
RECOMMENDED OPERATING CONDITIONS
MIN
3
NOM
3.3
MAX
UNIT
V
VCC
VIH
VIL
Supply voltage
3.6
High-level input voltage
2
V
Low-level input voltage
0.8
0.6
520
2.4
V
|VID
|
Magnitude of differential input voltage
Magnitude of differential output voltage with disabled driver
Driver output voltage
0.1
0
V
|VOD(dis)|
VOY or VOZ
mV
V
ŤVIDŤ
2
ŤVIDŤ
VIC
Common-mode input voltage (see Figure 5)
Operating free-air temperature
2.4 *
V
2
VCC-0.8
85
TA
–40
°C
4
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SN65LVDS050, SN65LVDS051
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SLLS301O–APRIL 1998–REVISED MAY 2007
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
SN65LVDS179 No receiver load, driver RL = 100 Ω
Driver and receiver enabled, no receiver load, driver RL = 100 Ω
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
9
9
12
12
7
mA
Driver enabled, receiver disabled, RL = 100 Ω
Driver disabled, receiver enabled, no load
Disabled
5
SN65LVDS180
mA
1.5
0.5
12
10
3
2
1
Supply
current
ICC
Drivers and receivers enabled, no receiver loads, driver RL = 100 Ω
Drivers enabled, receivers disabled, RL = 100 Ω
Drivers disabled, receivers enabled, no loads
Disabled
20
16
6
SN65LVDS050
SN65LVDS051
mA
mA
0.5
12
3
1
Drivers enabled, No receiver loads, driver RL = 100 Ω
Drivers disabled, no loads
20
6
(1) All typical values are at 25°C and with a 3.3-V supply.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
|VOD
|
Differential output voltage magnitude
247
340
454
RL = 100 Ω, See
Figure 3 and Figure 2
mV
50
Change in differential output voltage magnitude between logic
states
∆|VOD
|
-50
1.125
–50
VOC(SS)
∆VOC(SS)
VOC(PP)
Steady-state common-mode output voltage
1.2 1.375
V
Change in steady-state common-mode output voltage between
logic states
See Figure 3
50
mV
mV
Peak-to-peak common-mode output voltage
50
–0.5
2
150
–20
20
DE
IIH
High-level input current
D
VIH = 5 V
µA
µA
DE
–0.5
2
–10
10
IIL
Low-level input current
D
VIL = 0.8 V
VOY or VOZ = 0 V
VOD = 0 V
3
10
IOS
Short-circuit output current
mA
3
10
DE = OV
VOY = VOZ = OV
IO(OFF)
Off-state output current
Input capacitance
–1
1
µA
pF
DE = VCC
VOY = VOZ = OV,
VCC < 1.5 V
CIN
3
5
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SN65LVDS050, SN65LVDS051
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SLLS301O–APRIL 1998–REVISED MAY 2007
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VIT+
VIT-
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
50
See Figure 5 and Table 2
mV
–50
2.4
2.8
IOH = -8 mA
IOH = -4 mA
IOL = 8 mA
VI = 0
VOH
VOL
II
High-level output voltage
Low-level output voltage
Input current (A or B inputs)
V
0.4
V
–2
–11
–3
–20
µA
VI = 2.4 V
VCC = 0
–1.2
II(OFF)
IIH
Power-off input current (A or B inputs)
High-level input current (enables)
Low-level input current (enables)
High-impedance output current
Input capacitance
±20
±10
±10
±10
µA
µA
µA
µA
pF
VIH = 5 V
IIL
VIL = 0.8 V
VO = 0 or 5 V
IOZ
CI
5
(1) All typical values are at 25°C and with a 3.3-V supply.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
Differential output signal fall time
Pulse skew (|tpHL - tpLH|)(2)
1.7
1.7
0.8
0.8
300
150
4.3
3.1
2.7
2.7
1
ns
ns
ns
ns
ps
ps
ns
ns
RL = 100 Ω,
CL = 10 pF,
See Figure 2
tf
1
tsk(p)
tsk(o)
ten
Channel-to-channel output skew(3)
Enable time
10
10
See Figure 4
tdis
Disable time
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
(3) tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tPLH
tPHL
tsk(p)
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Pulse skew (|tpHL - tpLH|)(2)
3.7
3.7
0.3
0.7
0.9
2.5
2.5
7
4.5
4.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL = 10 pF,
See Figure 6
Output signal rise time
1.5
1.5
tf
Output signal fall time
tPZH
tPZL
tPHZ
tPLZ
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
See Figure 7
4
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
6
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SN65LVDS050, SN65LVDS051
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SLLS301O–APRIL 1998–REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION
DRIVER
I
OY
Driver Enable
Y
Z
I
I
A
V
OD
V
) V
OY
OZ
I
OZ
V
OY
2
V
I
V
OC
V
OZ
Figure 1. Driver Voltage and Current Definitions
Driver Enable
Y
Z
100 Ω
±1%
V
OD
Input
C
L
= 10 pF
(2 Places)
2 V
Input
1.4 V
0.8 V
t
PHL
t
PLH
100%
80%
V
OD(H)
Output
0 V
V
OD(L)
20%
0%
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
7
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SLLS301O–APRIL 1998–REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Driver Enable
Input
49.9 Ω, ±1% (2 Places)
3 V
0 V
Y
Z
V
OC
V
OC(PP)
C
= 10 pF
L
V
OC(SS)
(2 Places)
V
OC
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
49.9 Ω, ±1% (2 Places)
Y
0.8 V or 2 V
Z
1.2 V
DE
C
= 10 pF
L
V
OY
V
OZ
(2 Places)
2 V
1.4 V
0.8 V
DE
~1.4 V
1.25 V
1.2 V
V
V
or V
D at 2 V and input to DE
D at 0.8 V and input to DE
OY
OZ
t
t
en
t
t
dis
1.2 V
1.15 V
~1 V
or V
OZ
OY
en
dis
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
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SLLS301O–APRIL 1998–REVISED MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
RECEIVER
A
V
) V
R
IA
IB
V
ID
2
V
IA
B
V
O
V
IC
V
IB
Figure 5. Receiver Voltage Definitions
Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
(V)
RESULTING DIFFERENTIAL
INPUT VOLTAGE (mV)
RESULTING COMMON-
MODE INPUT VOLTAGE (V)
VIA
1.25
1.15
2.4
2.3
0.1
0
VIB
1.15
1.25
2.3
2.4
0
VID
100
VIC
1.2
–100
100
1.2
2.35
2.35
0.05
0.05
1.2
–100
100
0.1
0.9
1.5
1.8
2.4
0
–100
600
1.5
0.9
2.4
1.8
0.6
0
–600
600
1.2
2.1
–600
600
2.1
0.3
0.6
–600
0.3
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SLLS301O–APRIL 1998–REVISED MAY 2007
V
ID
V
IA
C
L
V
O
10 pF
V
IB
V
V
1.4 V
1 V
IA
IB
0.4 V
0 V
V
ID
–0.4 V
t
t
PHL
PLH
V
V
O
OH
2.4 V
0.4 V
1.4 V
V
OL
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the
D.U.T.
Figure 6. Timing Test Circuit and Waveforms
10
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SLLS301O–APRIL 1998–REVISED MAY 2007
B
A
1.2 V
RE
500 Ω
C
10 pF
+
–
L
V
O
V
TEST
Inputs
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of
the D.U.T.
2.5 V
V
TEST
A
1 V
2 V
RE
1.4 V
0.8 V
t
PZL
t
t
PZL
PLZ
2.5 V
1.4 V
R
V
OL
+0.5 V
V
OL
0 V
V
TEST
A
1.4 V
2 V
RE
1.4 V
0.8 V
t
PZH
t
t
PZH
PHZ
V
OH
V
OH
–0.5 V
R
1.4 V
0 V
Figure 7. Enable/Disable Time Test Circuit and Waveforms
11
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SLLS301O–APRIL 1998–REVISED MAY 2007
TYPICAL CHARACTERISTICS
DISABLED DRIVER OUTPUT CURRENT
vs
OUTPUT VOLTAGE
40
30
20
10
0
V
= 3.3 V
= 25°C
CC
Other output at 0 V
Other output at 1.2 V
T
A
DE = 0 V
V
OZ
= V
OY
−10
−20
−30
Other output at 2.4 V
0
0.5
1
1.5
2
2.5
3
V
− Output Voltage − V
O
Figure 8.
DRIVER
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
3.5
3
4
3
V
T
A
= 3.3 V
= 25°C
CC
V
T
A
= 3.3 V
= 25°C
CC
2.5
2
2
1
1.5
1
0.5
0
0
−1
−4
−3
−2
0
0
2
4
6
I
− High-Level Output Current − mA
I
− Low-Level Output Current − mA
OH
OL
Figure 9.
Figure 10.
12
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SN65LVDS179, SN65LVDS180
SN65LVDS050, SN65LVDS051
www.ti.com
SLLS301O–APRIL 1998–REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
5
4
V
T
A
= 3.3 V
= 25°C
CC
V
T
A
= 3.3 V
= 25°C
CC
4
3
2
1
0
3
2
1
0
0
10
60
−80
−60
− High-Level Output Current − mA
0
20
30
40
50
−40
−20
I
− Low-Level Output Current − mA
I
OH
OL
Figure 11.
Figure 12.
DRIVER
DRIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.5
2.5
2
2
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3 V
V
CC
= 3 V
V
= 3.6 V
30
V
= 3.6 V
30
CC
CC
1.5
−50
1.5
−50
−30 −10
10
50
90
−30 −10
10
50
90
70
70
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 13.
Figure 14.
13
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SN65LVDS179, SN65LVDS180
SN65LVDS050, SN65LVDS051
www.ti.com
SLLS301O–APRIL 1998–REVISED MAY 2007
TYPICAL CHARACTERISTICS (continued)
RECEIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
4.5
V
CC
= 3.3 V
4
V
CC
= 3 V
3.5
V
CC
= 3.6 V
3
2.5
−50
−30 −10
10
50
90
30
70
T
A
− Free−Air Temperature − °C
Figure 15.
RECEIVER
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
4.5
V
CC
= 3 V
4
V
CC
= 3.3 V
3.5
V
CC
= 3.6 V
3
2.5
−50
−30 −10
10
50
90
30
70
T
A
− Free-Air Temperature − °C
Figure 16.
14
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SN65LVDS179, SN65LVDS180
SN65LVDS050, SN65LVDS051
www.ti.com
SLLS301O–APRIL 1998–REVISED MAY 2007
APPLICATION INFORMATION
Equipment
•
•
•
Hewlett Packard HP6624A DC power supply
Tektronix TDS7404 Real Time Scope
Agilent ParBERT E4832A
Hewlett Packard HP6624A
DC Power Supply
Agilent ParBERT
(E4832A)
Tektronix TDS7404
Real Time Scope
Bench Test Board
Figure 17. Equipment Setup
(a)
(b)
(c)
a. Tx + Rx running at 150 Mbps; Channel 1: R, Channel 2: Y-Z
b. Rx only running at 150 Mbps; Channel 1: R
c. Tx only running at 400 Mbps; Channel 1: Y-Z
Figure 18. Typical Eye Patterns SN65LVDS179: (T = 25°C; VCC = 3.6 V; PRBS = 223-1
)
15
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SN65LVDS179, SN65LVDS180
SN65LVDS050, SN65LVDS051
www.ti.com
SLLS301O–APRIL 1998–REVISED MAY 2007
APPLICATION INFORMATION (continued)
(a)
(b)
(c)
a. Tx + Rx running at 150 Mbps; Channel 1: R, Channel 2: Y-Z
b. Rx only running at 150 Mbps; Channel 1: R
c. Tx only running at 400 Mbps; Channel 1: Y-Z
Figure 19. Typical Eye Patterns SN65LVDS180: (T = 25°C; VCC = 3.6 V; PRBS = 223-1
)
)
)
(a)
(b)
(c)
a. All buffers running at 100 Mbps; Channel 1: R, Channel 2: 2R, Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,
b. Rx buffers only running at 100 Mbps; Channel 1: R, Channel 2: 2R
c. Tx buffers only running at 400 Mbps; Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,
Figure 20. Typical Eye Patterns SN65LVDS050: (T = 25°C; VCC = 3.6 V; PRBS = 223-1
(a)
(b)
(c)
a. All buffers running at 100 Mbps; Channel 1: R, Channel 2: 2R, Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,
b. Rx buffers only running at 100 Mbps; Channel 1: R, Channel 2: 2R
c. Tx buffers only running at 400 Mbps; Channel 3: 1Y-1Z, Channel 4: 2Y-2Z,
Figure 21. Typical Eye Patterns SN65LVDS051: (T = 25°C; VCC = 3.6 V; PRBS = 223-1
16
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SN65LVDS179, SN65LVDS180
SN65LVDS050, SN65LVDS051
www.ti.com
SLLS301O–APRIL 1998–REVISED MAY 2007
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common-mode output and balanced interface for low noise emissions.
Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL speeds without
the power and dual supply requirements.
1000
30% Jitter
100
5% Jitter
10
1
24 AWG UTP 96 Ω (PVC Dielectric)
0.1
100k
1M
10M
100M
Data Rate – Hz
Figure 22. Data Transmission Distance Versus Rate
FAIL SAFE
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that
its output logic state can be indeterminate when the differential input voltage is between -100 mV and 100 mV
and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles
the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 11. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
V
CC
300 kΩ
300 kΩ
A
R
t
100 Ω Typ
Y
B
V
IT
≈ 2.3 V
Figure 23. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
17
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2007
PACKAGING INFORMATION
Orderable Device
SN65LVDS050D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS050DG4
SN65LVDS050DR
SN65LVDS050DRG4
SN65LVDS050PW
SN65LVDS050PWG4
SN65LVDS050PWR
SN65LVDS050PWRG4
SN65LVDS051D
SOIC
SOIC
D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS051DG4
SN65LVDS051DR
SN65LVDS051DRG4
SN65LVDS051PW
SN65LVDS051PWG4
SN65LVDS051PWR
SN65LVDS051PWRG4
SN65LVDS179D
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS179DG4
SN65LVDS179DGK
SN65LVDS179DGKG4
SN65LVDS179DGKR
SN65LVDS179DGKRG4
SN65LVDS179DR
SN65LVDS179DRG4
SN65LVDS180D
SOIC
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP
MSOP
MSOP
MSOP
SOIC
DGK
DGK
DGK
DGK
D
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2007
Orderable Device
SN65LVDS180DG4
SN65LVDS180DR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS180DRG4
SN65LVDS180PW
SN65LVDS180PWG4
SN65LVDS180PWR
SN65LVDS180PWRG4
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
330
330
(mm)
16
SN65LVDS050DR
SN65LVDS050PWR
SN65LVDS051DR
SN65LVDS051PWR
SN65LVDS179DGKR
SN65LVDS179DR
SN65LVDS180DR
SN65LVDS180PWR
D
PW
D
16
16
16
16
8
SITE 60
SITE 60
SITE 60
SITE 60
SITE 35
SITE 60
SITE 60
SITE 60
6.5
6.67
6.5
10.3
5.4
10.3
5.4
3.4
5.2
9.0
5.4
2.1
1.6
2.1
1.6
1.4
2.1
2.1
1.6
8
8
8
8
8
8
8
8
16
12
16
12
12
12
16
12
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
12
16
PW
DGK
D
12
6.67
5.3
12
8
12
6.4
D
14
14
16
6.5
PW
12
6.67
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65LVDS050DR
SN65LVDS050PWR
SN65LVDS051DR
SN65LVDS051PWR
SN65LVDS179DGKR
SN65LVDS179DR
SN65LVDS180DR
SN65LVDS180PWR
D
PW
D
16
16
16
16
8
SITE 60
SITE 60
SITE 60
SITE 60
SITE 35
SITE 60
SITE 60
SITE 60
346.0
346.0
346.0
346.0
358.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
335.0
346.0
346.0
346.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
PW
DGK
D
8
D
14
14
PW
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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