SN65DSI84ZXHR [TI]
SN65DSI84 MIPI® DSI Bridge To FLATLINK⢠LVDS Single Channel DSI to Dual-Link LVDS Bridge;
| 型号： | SN65DSI84ZXHR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SN65DSI84 MIPI® DSI Bridge To FLATLINK⢠LVDS Single Channel DSI to Dual-Link LVDS Bridge |
| 文件： | 总50页 (文件大小：2302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65DSI84
SLLSEC2H – SEPTEMBER 2012 – REVISED OCTOBER 2020
SN65DSI84 MIPI® DSI Bridge To FLATLINK™ LVDS
Single Channel DSI to Dual-Link LVDS Bridge
1 Features
3 Description
•
Implements MIPI® D-PHY version 1.00.00 physical
The SN65DSI84 DSI to FlatLink™ bridge features a
layer front-end and display serial interface (DSI)
version 1.02.00
Single channel DSI receiver configurable for one,
two, three, or four D-PHY data lanes per channel
operating up to 1 Gbps per lane
Supports 18 bpp and 24-bpp DSI video packets
with RGB666 and RGB888 formats
Suitable for 60-fps WUXGA 1920 × 1200
resolution at 18-bpp and 24-bpp color, 60 fps 1366
× 768 at 18 bpp and 24 bpp
single-channel MIPI® D-PHY receiver front-end
configuration with 4 lanes per channel operating at 1
Gbps per lane; a maximum input bandwidth of 4
Gbps. The bridge decodes MIPI® DSI 18bpp RGB666
and 24 bpp RGB888 packets and converts the
•
formatted video data stream to
a
FlatLink™
•
•
compatible LVDS output operating at pixel clocks
operating from 25 MHz to 154 MHz, offering a Dual-
Link LVDS, Single-Link LVDS interface with four data
lanes per link.
•
•
•
•
FlatLink™ output configurable for single-link or
dual-link LVDS
Supports single channel DSI to dual-link LVDS
operating mode
LVDS output clock range of 25 MHz to 154 MHz in
dual-link or single-link modes
LVDS pixel clock may be sourced from free-
running continuous D-PHY clock or external
reference clock (REFCLK)
The SN65DSI84 is well suited for WUXGA 1920 x
1200 at 60 frames per second, with up to 24 bits-per-
pixel. Partial line buffering is implemented to
accommodate the data stream mismatch between the
DSI and LVDS interfaces.
Designed
with
industry
compliant
interface
technology, the SN65DSI84 is compatible with a wide
range of micro-processors, and is designed with a
range of power management features including low-
swing LVDS outputs, and the MIPI® defined ultra-low
power state (ULPS) support.
•
•
1.8-V main VCC power supply
Low power features include shutdown mode,
reduced LVDS output voltage swing, common
mode, and MIPI ultra-low power state (ULPS)
support
LVDS channel swap, LVDS PIN order reverse
feature for ease of PCB routing
ESD rating ±2 kV (HBM)
Packaged in 64-pin 5-mm × 5-mm nFBGA (ZXH)
Temperature range: –40°C to 85°C
The SN65DSI84 is implemented in a small outline
5x5mm nFBGA at 0.5 mm pitch package, and
operates across a temperature range from -40°C to
85°C.
•
Device Information (1)
•
•
•
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN65DSI84
nFBGA (64)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
PC & notebooks
Tablets
Connected peripherals & printers
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65DSI84
www.ti.com
SLLSEC2H – SEPTEMBER 2012 – REVISED OCTOBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 EDS Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Switching Characteristics............................................9
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................14
7.5 Programming............................................................ 22
7.6 Register Maps...........................................................23
8 Application and Implementation..................................33
8.1 Application Information............................................. 33
8.2 Typical Application.................................................... 33
9 Power Supply Recommendations................................40
9.1 VCC Power Supply.................................................... 40
9.2 VCORE Power Supply..............................................40
10 Layout...........................................................................41
10.1 Layout Guidelines................................................... 41
10.2 Layout Example...................................................... 42
11 Device and Documentation Support..........................43
11.1 Receiving Notification of Documentation Updates..43
11.2 Community Resources............................................43
11.3 Trademarks............................................................. 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (June 2018) to Revision H (October 2020)
Page
•
NOTE: The device in the MicroStar Jr. BGA packaging were redesigned using a laminate nFBGA package.
This nFBGA package offers datasheet-equivalent electrical performance. It is also footprint equivalent to the
MicroStar Jr. BGA. The new package designator in place of the discontinued package designator will be
updated throughout the datasheet......................................................................................................................1
Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 1
Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 4
Changed u*jr ZQE to nFBGA ZXH. Updated thermal information......................................................................6
Changed u*jr ZQE to nFBGA ZXH................................................................................................................... 41
•
•
•
•
Changes from Revision F (August 2015) to Revision G (June 2018)
Page
•
•
•
•
•
Deleted figure Shutdown and Reset Timing Definition While VCC Is High .........................................................9
Changed the paragraph following Figure 7-3 .................................................................................................. 14
Changed Recommended Initialization Sequence To: Initialization Sequence .................................................14
Changed Table 7-2 .......................................................................................................................................... 14
Changed item 3 in Video Stop and Restart Sequence From: Drive all DSI input lanes including DSI CLK lane
to LP11. To: Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS. .........................................33
Changes from Revision E (October 2013) to Revision F (August 2015)
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
Changed ULPS Itemized List, item 3 from "Wait for the PLL_LOCK bit (CSR 0x0A.7) to be set" to "Wait for a
minimum of 3 ms."............................................................................................................................................ 13
Changed Initialization Sequence Description for Init seq7 from "Wait for the PLL_LOCK bit to be set (CSR
0x0A.7)" to "Wait for a minimum of 3 ms." .......................................................................................................14
Changed Table 7-6 Address 0x0A, Bit 7 description from "PLL_LOCK" to "PLL_EN_STAT"...........................23
Changed Address 0x18, Bits 3, 2, 1, and 0 Descriptions in Table 7-8 for clarification......................................23
•
•
•
•
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SLLSEC2H – SEPTEMBER 2012 – REVISED OCTOBER 2020
•
Changed Item 1 of the Video STOP and Restart sequence from "Clear the PLL_EN bit to 0(CSR 0x0A.7)" to
"Clear the PLL_EN bit to 0 (CSR 0x0D.0)" ......................................................................................................33
Changes from Revision D (August 2013) to Revision E (October 2013)
Page
•
Added rows for Bits 7, and 6:5 to Table 7-7 CSR Bit Field Definition – DSI Registers.....................................23
Changes from Revision C (December 2012) to Revision D (August 2013)
Page
•
Aligned package description throughout datasheet............................................................................................1
Changes from Revision A (December 2012) to Revision B (December 2012)
Page
•
Changed PGBA to PBGA................................................................................................................................... 1
Changes from Revision * (August 2012) to Revision A (December 2012)
Page
•
•
•
•
•
•
•
•
•
•
•
Changed the value of VOH From: 1.3 MIN To: 1.25 MIN.....................................................................................7
Changed the ICC TYP value From: 125 To: 106 and MAX value From: 200 To: 150 .........................................7
Added a TYP value of 7.7 to IULPS .....................................................................................................................7
Changed the IRST TYP value From: 0.05 To: 0.04 and MAX value From: 0.2 To: 0.06...................................... 7
changed the values of |VOD|..............................................................................................................................7
Changed the values of VOC(SS) for test conditions CSR 0x19.6 = 0 and, or CSR 0x19.4 = 0.............................7
Changed table note 2......................................................................................................................................... 7
Added table note 3..............................................................................................................................................7
Changed the SWITCHING CHARACTERISTICS table......................................................................................9
Changed the description of CHA_LVDS_VOD_SWING................................................................................... 23
Changed the description of CHB_LVDS_VOD_SWING................................................................................... 23
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SLLSEC2H – SEPTEMBER 2012 – REVISED OCTOBER 2020
5 Pin Configuration and Functions
A
B
C
D
E
F
G
H
J
9
8
7
6
5
4
3
2
1
VCC
GND
A_Y0N
A_Y1N
A_Y2N
A_CLKN
A_Y3N
GND
IRQ
GND
B_Y3N
B_CLKN
B_Y2N
B_Y1N
B_Y0N
GND
VCC
B_Y3P
B_CLKP
B_Y2P
B_Y1P
B_Y0P
RSVD2
EN
A_Y0P
A_Y1P
A_Y2P
A_CLKP
A_Y3P
RSVD1
DA3P
DA2P
DACP
DA1P
DA0P
REFCLK
SCL
VCORE
DA3N
DA2N
DACN
DA1N
DA0N
VCC
VCC
GND
VCC
VCC
GND
VCC
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ADDR
SDA
Not to scale
To minimize the power supply noise floor, provide good decoupling near the SN65DSI84 power pins. The use of four ceramic capacitors
(2x 0.1 μF and 2x 0.01 μF) provides good performance. At the least, it is recommended to install one 0.1 μF and one 0.01 μF capacitor
near the SN65DSI84. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and device
power inputs pins must be minimized. Placing the capacitor underneath the SN65DSI84 on the bottom of the PCB is often a good
choice.
Figure 5-1. ZXH Package 64-Pin nFBGA Top View
Table 5-1. Pin Functions
PIN
DESCRIPTION
NAME
NO.
H3
J3
I/O
DA0P
DA0N
DA1P
DA1N
DA2P
DA2N
DA3P
DA3N
DACP
DACN
MIPI® D-PHY Channel A Data Lane 0; data rate up to 1 Gbps.
MIPI® D-PHY Channel A Data Lane 1; data rate up to 1 Gbps.
MIPI® D-PHY Channel A Data Lane 2; data rate up to 1 Gbps.
MIPI® D-PHY Channel A Data Lane 3; data rate up to 1 Gbps.
MIPI® D-PHY Channel A Clock Lane; operates up to 500 MHz.
H4
J4
LVDS Input (HS)
CMOS Input (LS)
(Failsafe)
H6
J6
H7
J7
H5
J5
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Table 5-1. Pin Functions (continued)
PIN
NO.
DESCRIPTION
NAME
I/O
C2, C1, D2, D1, F2,
F1, G2, G1, E2, E1
NC
No connects.
These pins should not be connected to any signal, power or ground.
FlatLink™ Channel A LVDS Data Output 0.
A_Y0P
A_Y0N
A_Y1P
A_Y1N
A_Y2P
A_Y2N
C8
C9
D8
D9
E8
E9
FlatLink™ Channel A LVDS Data Output 1.
FlatLink™ Channel A LVDS Data Output 2.
FlatLink™ Channel A LVDS Data Output 3. A_Y3P and A_Y3N shall be left NC for 18 bpp
panels.
A_Y3P
G8
A_Y3N
A_CLKP
A_CLKN
B_Y0P
B_Y0N
B_Y1P
B_Y1N
B_Y2P
B_Y2N
G9
F8
F9
B3
A3
B4
A4
B5
A5
FlatLink™ Channel A LVDS Clock
LVDS Output
FlatLink™ Channel B LVDS Data Output 0.
FlatLink™ Channel B LVDS Data Output 1.
FlatLink™ Channel B LVDS Data Output 2.
FlatLink™ Channel B LVDS Data Output 3. B_Y3P and B_Y3N shall be left NC for 18 bpp
panels.
B_Y3P
B7
B_Y3N
A7
B6
A6
B_CLKP
B_CLKN
FlatLink™ Channel B LVDS Clock.
CMOS Input/Output
with pulldown
RSVD1
RSVD2
H8
B2
Reserved. This pin should be left unconnected for normal operation.
CMOS Input with
pulldown
Reserved. This pin should be left unconnected for normal operation.
Local I2C Interface Target Address Select. See Table 7-4. In normal operation this pin is an
ADDR
EN
A1
B1
CMOS Input/Output input. When the ADDR pin is programmed high, it should be tied to the same 1.8 V power
rails where the SN65DSI84 VCC 1.8 V power rail is connected.
CMOS Input with
Chip Enable and Reset. Device is reset (shutdown) when EN is low.
pullup (Failsafe)
Optional External Reference Clock for LVDS Pixel Clock. If an External Reference Clock is
not used, this pin should be pulled to GND with an external resistor. The source of the
reference clock should be placed as close as possible with a series resistor near the
REFCLK
H2
CMOS Input
(Failsafe)
source to reduce EMI.
SCL
SDA
IRQ
H1
J1
J9
Local I2C Interface Clock.
Open Drain Input/
Local I2C Interface Bi-directional Data Signal.
Output (Failsafe)
CMOS Output
Interrupt Signal.
A2, A8, B9, D5, E4,
F4, F5, H9
GND
Reference Ground.
A9, B8, D6, E5, E6,
F6, J2
VCC
Power Supply
1.8 V Power Supply.
1.1 V Output from Voltage Regulator. This pin must have a 1 µF external capacitor to
GND.
VCORE
J8
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SLLSEC2H – SEPTEMBER 2012 – REVISED OCTOBER 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.5
–0.4
–65
MAX
2.175
2.175
1.4
UNIT
V
Supply Voltage
VCC
CMOS Input Terminals
V
Input Voltage
DSI Input Terminals (DA x P/N, DB x P/N)
V
Storage Temperature Tstg
105
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 EDS Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±200
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
165
NOM
MAX
195
0.05
85
UNIT
V
VCC
VCC Power supply
18
VPSN
TA
Supply noise on any VCC pin
Operating free-air temperature
Case temperature
f(noise) > 1MHz
–40
V
°C
TCASE
VDSI_PIN
f(I2C)
fHS_CLK
tsetup
thold
92.2
1350
400
500
°C
DSI input pin voltage range
Local I2C input frequency
–50
40
mV
kHz
MHz
DSI HS clock input frequency
DSI HS data to clock setup time
DSI HS data to clock hold time; see Figure 6-4
LVDS output differential impedance
0.15
UI(1)
Ω
0.15
90
ZL
132
(1) The unit interval (UI) is one half of the period of the HS clock; at 500 MHz the minimum setup and hold time is 150 ps.
6.4 Thermal Information
SN65DSI84
THERMAL METRIC(1)
ZXH (nFBGA)
64 PINS
55.1
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
30.6
31.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.8
ψJB
30.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
V
VIL
VIH
VOH
VOL
ILKG
IIH
Low-level control signal input voltage
High-level control signal input voltage
High-level output voltage
Low-level output voltage
0.3 x VCC
0.7 x VCC
1.25
V
IOH = –4 mA
V
IOL = 4 mA
0.4
±30
±30
±30
±10
±20
150
V
Input failsafe leakage current
High level input current
VCC = 0; VCC(PIN) = 1.8 V
Any input terminal
Any input terminal
Any output terminal
Any output driving GND short
see (2)
μA
μA
μA
μA
mA
mA
IIL
Low level input current
IOZ
IOS
ICC
High-impedance output current
Short-circuit output current
Device active current
106
7.7
All data and clock lanes are in ultra-low
power state (ULPS)
IULPS
Device standby current
10
mA
IRST
REN
Shutdown current
EN = 0
0.04
200
0.06
mA
kΩ
EN control input resistor
MIPI DSI INTERFACE
VIH-LP LP receiver input high threshold
VIL-LP
|VID
|VIDT
See Figure 6-1
See Figure 6-1
880
70
mV
mV
mV
mV
LP receiver input low threshold
HS differential input voltage
550
270
50
|
|
HS differential input voltage threshold
LP receiver input low threshold; ultra-low
power state (ULPS)
VIL-ULPS
VCM-HS
300
330
100
460
mV
mV
mV
HS common mode voltage; steady-state
70
HS common mode peak-to-peak variation
including symbol delta and interference
ΔVCM-HS
VIH-HS
VIL-HS
HS single-ended input high voltage
HS single-ended input low voltage
See Figure 6-1
See Figure 6-1
mV
mV
–40
80
HS termination enable; single-ended input Termination is switched simultaneous for
voltage (both Dp AND Dn apply to enable) Dn and Dp
VTERM-EN
RDIFF-HS
450
125
mV
Ω
HS mode differential input impedance
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UNIT
SLLSEC2H – SEPTEMBER 2012 – REVISED OCTOBER 2020
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
FLATLINK LVDS OUTPUT
CSR 0x19.3:2=00 and, or CSR
0x19.1:0=00;
100 Ω near end termination
180
215
250
290
150
200
250
300
140
168
195
226
117
156
195
234
245
293
341
389
204
271
337
402
191
229
266
303
159
211
263
314
313
372
430
488
261
346
428
511
244
290
335
381
204
270
334
CSR 0x19.3:2=01 and/or CSR
0x19.1:0=01;
100 Ω near end termination
CSR 0x19.3:2=10 and, or CSR
0x19.1:0=10;
100 Ω near end termination
CSR 0x19.3:2=11 and/or CSR
0x19.1:0=11;
100 Ω near end termination
Steady-state differential output voltage for
A_Y x P/N and B_Y x P/N
mV
CSR 0x19.3:2=00 and, or CSR
0x19.1:0=00;
200 Ω near end termination
CSR 0x19.3:2=01 and, or CSR
0x19.1:0=01;
200 Ω near end termination
CSR 0x19.3:2=10 and, or CSR
0x19.1:0=10;
200 Ω near end termination
CSR 0x19.3:2=11 and, or CSR
0x19.1:0=11;
200 Ω near end termination
|VOD
|
CSR 0x19.3:2=00 and, or CSR
0x19.1:0=00
100 Ω near end termination
CSR 0x19.3:2=01 and, or CSR
0x19.1:0=01
100 Ω near end termination
CSR 0x19.3:2=10 and, or CSR
0x19.1:0=10
100 Ω near end termination
CSR 0x19.3:2=11 and, or CSR
0x19.1:0=11
100 Ω near end termination
Steady-state differential output voltage for
A_CLKP/N and B_CLKP/N
mV
CSR 0x19.3:2=00 and, or CSR
0x19.1:0=00
200 Ω near end termination
CSR 0x19.3:2=01 and, or CSR
0x19.1:0=01
200 Ω near end termination
CSR 0x19.3:2=10 and, or CSR
0x19.1:0=10
200 Ω near end termination
CSR 0x19.3:2=11 and, or CSR
0x19.1:0=11
200 Ω near end termination
399
35
1
Change in steady-state differential output
voltage between opposite binary states
Δ|VOD
|
RL = 100 Ω
mV
V
CSR 0x19.6 = 1 and CSR 0x1B.6 = 1;
and, or CSR 0x19.4 = 1 and
0.8
0.9
Steady state common-mode output
voltage(3)
CSR 0x1B.4 = 1; see Figure 6-2
VOC(SS)
CSR 0x19.6 = 0 and, or CSR 0x19.4 = 0;
see Figure 6-2
1.15
1.25
1.35
35
Peak-to-peak common-mode output
voltage
VOC(PP)
see Figure 6-2
mV
kΩ
Pull-down resistance for disabled LVDS
outputs
RLVDS_DIS
1
(1) All typical values are at VCC = 1.8 V and TA = 25°C
(2) SN65DSI84: SINGLE Channel DSI to DUAL Channel LVDS, 1440 x 900
a. number of LVDS lanes = 2 x (3 data lanes + 1 CLK lane)
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b. number of DSI lanes = 2 data lanes + 1 CLK lane
SLLSEC2H – SEPTEMBER 2012 – REVISED OCTOBER 2020
c. LVDS CLK OUT = 53.25 M
d. DSI CLK = 500 M
e. RGB888, LVDS18bpp
Maximum values are at VCC = 1.95 V and TA = 85°C
(3) Tested at VCC = 1.8 V , TA = –40°C for MIN, TA = 25°C for TYP, TA = 85°C for MAX.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
DSI
tGS
DSI LP glitch suppression pulse width
Output clock period
300
40
ps
LVDS
tc
6.49
ns
ns
High-level output clock (CLK) pulse
duration
tw
t0
t1
t2
t3
t4
t5
t6
4/7 tc
Delay time, CLK↑ to 1st serial bit
position
-0.15
0.15
1/7 tc + 0.15
2/7 tc + 0.15
3/7 tc + 0.15
4/7 tc + 0.15
5/7 tc + 0.15
ns
ns
ns
ns
ns
ns
Delay time, CLK↑ to 2nd serial bit
position
1/7 tc – 0.15
Delay time, CLK↑ to 3rd serial bit
position
2/7 tc – 0.15
3/7 tc – 0.15
4/7 tc – 0.15
5/7 tc – 0.15
tc = 6.49ns;
Input clock jitter < 25ps
(REFCLK)
Delay time, CLK↑ to 4th serial bit
position
Delay time, CLK↑ to 5th serial bit
position
Delay time, CLK↑ to 6th serial bit
position
Delay time, CLK↑ to 7th serial bit
position
6/7 tc – 0.15
180
6/7 tc + 0.15
500
ns
ps
tr
tf
Differential output rise-time
Differential output fall-time
See Figure 6-5
tc(o) = 12.9 ns
EN, ULPS, RESET
ten
Enable time from EN or ULPS
1
ms
ms
tdis
Disable time to standby
Reset time
0.1
treset
REFCLK
10
REFCLK Freqeuncy. Supported
frequencies: 25 MHz-154 MHz
FREFCLK
25
154 MHz
tr, tf
tpj
REFCLK rise and fall time
REFCLK Peak-to-Peak Phase Jitter
REFCLK Duty Cycle
100 ps
1ns
50
s
ps
Duty
40%
50%
1%
60%
REFCLK or DSI CLK (DACP/N, DBCP/N)
SSC enabled Input CLK center spread
0.5%
30
2%
depth (2)
SSC_CLKIN
Modulation Frequency Range
60 KHz
(1) All typical values are at VCC = 1.8 V and TA = 25°C
(2) For EMI reduction purpose, SN65DSI84 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK
input. The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N and/or
B_CLKP/N.
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1.3V
LP-RX
Input HIGH
VIH-LP
VIL-LP
VIH-HS
VID
VCM-HS(MAX)
LP-RX
Input LOW
HS-RX
Common Mode
Range
VCM-HS(MIN)
VIL-HS
GND
High Speed (HS) Mode
Receiver
Low Power (LP)
Mode Receiver
Figure 6-1. DSI Receiver Voltage Definitions
49.9 ? 1% (2 PLCS)
A/B_YnP
VOD
VOC
A/B_YnN
100%
80%
VOD(H)
0 V
VOD(L)
20%
0%
tf
tr
VOC(PP)
VOC(SS)
VOC(SS)
0 V
Figure 6-2. Test Load and Voltage Definitions for Flatlink Outputs
ULPS (LP00) State
DSI lane
t
ten
dis
A_CLKP/N
(LVDS_CHA_CLK)
A. See the ULPS section of the data sheet for the ULPS entry and exit sequence.
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B. ULPS entry and exit protocol and timing requirements must be met per MIPI® DPHY specification.
Figure 6-3. ULPS Timing Definition
Figure 6-4. DSI HS Mode Receiver Timing Definitions
CLK
t6
t5
t4
t3
t2
t1
t0
Yn
VOD(H)
0.00V
VOD(L)
t0-6
Figure 6-5. SN65DSI84 Flatlink Timing Definitions
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7 Detailed Description
7.1 Overview
The SN65DSI84 DSI to FlatLink bridge features a single0channel MIPI D-PHY receiver front-end configuration
with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge
decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and converts the formatted video data stream to
a FlatLink compatible LVDS output operating at pixel clocks operating from 25 MHx to 154 MHz, offering a Dual-
Link LVDS, Single-Link LVDS interface with four data lanes per link.
7.2 Functional Block Diagram
LVDS SERIALIZER
DSI PACKET
PROCESSORS
AVCC
AGND
VCC
A_Y0P
ERR
A_Y0N
A_Y1P
PACKET
ULPS
LPRX
HEADERS
ERR
A_Y1N
A_Y2P
A_Y2N
LANE
MERGE
GND
(ODD )
18
8
DA0P
DA0N
HSRX
LONG PACKETS
A_CLKP
A_CLKN
A_Y3P
(EVEN)
18
7-BIT SHIFT
REGISTER
DATA LANE 0
EOT
SOT
DA1P
DA1N
DA2P
DA2N
DA3P
DA3N
8
8
8
DATA LANE1
(Circuit same as DATA LANE 0)
Timers
A_Y3N
32
BE
DATA LANE 2
(Circuit same as DATA LANE 0)
DE
VS
HS
B_Y0P
B_Y0N
B_Y1P
SHORT PACKETS
DATA LANE 3
(Circuit same as DATA LANE 0)
DSI CHANNEL
MERGING
CHANNEL
B_Y1N
B_Y2P
B_Y2N
B_CLKP
B_CLKN
B_Y3P
B_Y3N
FORMATTER
PARTIAL
LINE BUFFER
ULPS
LPRX
LVDSPLL
PLL
DACP
DACN
Lock
CLOCK CIRCUITS
HSRX
PIXEL CLOCK
CLK LANE
SCL
CSR
LOCAL I 2
C
SDA
IRQ
HS Clock Sourced
M /N Pixel Clock
PLL
CSR READ
CSR WRITE
ADDR
Clock Dividers
REFCLK
EN
Reset
RSVD1
RSVD2
SN65DSI84
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7.3 Feature Description
7.3.1 Clock Configurations and Multipliers
The FlatLink™ LVDS clock may be derived from the DSI channel A clock, or from an external reference clock
source. When the MIPI® D-PHY channel A HS clock is used as the LVDS clock source, the D-PHY clock lane
must operate in HS free-running (continuous) mode; this feature eliminates the need for an external reference
clock reducing system costs
The reference clock source is selected by HS_CLK_SRC (CSR 0x0A.0) programmed through the local I 2C
interface. If an external reference clock is selected, it is multiplied by the factor in REFCLK_MULTIPLIER (CSR
0x0B.1:0) to generate the FlatLink™ LVDS output clock. When an external reference clock is selected, it must be
between 25 MHz and 154 MHz. If the DSI channel A clock is selected, it is divided by the factor in
DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLink™ LVDS output clock. Additionally,
LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12) must be set to the frequency
range of the FlatLink™ LVDS output clock for and DSI Channel A input clock respectively the internal PLL to
operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) must be set to enable the
internal PLL.
7.3.2 ULPS
The SN65DSI84 supports the MIPI defined ultra-low power state (ULPS). While the device is in the ULPS, the
CSR registers are accessible via I2C interface. ULPS sequence should be issued to all active DSI CLK and/or
DSI data lanes of the enabled DSI Channels for the SN65DSI84 enter the ULPS. The Following sequence
should be followed to enter and exit the ULPS.
1. Host issues a ULPS entry sequence to all DSI CLK and data lanes enabled.
2. When host is ready to exit the ULPS mode, host issues a ULPS exit sequence to all DSI CLK and data lanes
that need to be active in normal operation.
3. Wait for a minimum of 3 ms.
4. Set the SOFT_RESET bit (CSR 0x09.0).
5. Device resumes normal operation.(i.e video streaming resumes on the panel).
7.3.3 LVDS Pattern Generation
The SN65DSI84 supports a pattern generation feature on LVDS Channels. This feature can be used to test the
LVDS output path and LVDS panels in a system platform. The pattern generation feature can be enabled by
setting the CHA_TEST_PATTERN bit at address 0x3C. No DSI data is received while the pattern generation
feature is enabled.
There are three modes available for LVDS test pattern generation. The mode of test pattern generation is
determined by register configuration as shown in Table 7-1.
Table 7-1. Video Registers
Addr. bit
0x20.7:0
0x21.3:0
0x24.7:0
0x25.3:0
0x2C.7:0
0x2D.1:0
0x30.7:0
0x31.1:0
0x34.7:0
0x36.7:0
0x38.7:0
0x3A.7:0
Register Name
CHA_ACTIVE_LINE_LENGTH_LOW
CHA_ACTIVE_LINE_LENGTH_HIGH
CHA_VERTICAL_DISPLAY_SIZE_LOW
CHA_VERTICAL_DISPLAY_SIZE_HIGH
CHA_HSYNC_PULSE_WIDTH_LOW
CHA_HSYNC_PULSE_WIDTH_HIGH
CHA_VSYNC_PULSE_WIDTH_LOW
CHA_VSYNC_PULSE_WIDTH_HIGH
CHA_HORIZONTAL_BACK_PORCH
CHA_VERTICAL_BACK_PORCH
CHA_HORIZONTAL_FRONT_PORCH
CHA_VERTICAL_FRONT_PORCH
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7.4 Device Functional Modes
7.4.1 Reset Implementation
When EN is de-asserted (low), the SN65DSI84 is in SHUTDOWN or RESET state. In this state, CMOS inputs
are ignored, the MIPI® D-PHY inputs are disabled and outputs are high impedance. It is critical to transition the
EN input from a low to a high level after the VCC supply has reached the minimum operating voltage as shown in
Figure 7-1. This is achieved by a control signal to the EN input, or by an external capacitor connected between
EN and GND.
VCC
1.65V
EN
tVCC
Figure 7-1. Cold Start VCC Ramp up to EN
ten
When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of
the VCC supply, where a slower ramp-up results in a larger value external capacitor. See the latest reference
schematic for the SN65DSI84 device and, or consider approximately 200 nF capacitor as a reasonable first
estimate for the size of the external capacitor.
Both EN implementations are shown in Figure 7-2 and Figure 7-3.
VCC
GPO
EN
EN
C
REN =200 kΩ
C
SN65DSI84
controller
SN65DSI84
Figure 7-3. EN Input From Active Controller
Figure 7-2. External Capacitor Controlled EN
7.4.2
When the SN65DSI84 is reset while VCC is high, the EN pin must be held low for at least 10 ms before being
asserted high as described in Table 7-2 to be sure that the device is properly reset. The DSI CLK lane MUST be
in HS and the DSI data lanes MUST be driven to LP11 while the device is in reset before the EN pin is asserted
per the timing described in Table 7-2.
7.4.3 Initialization Sequence
Use the following initialization sequence to setup the SN65DSI84. This sequence is required for proper operation
of the device. Steps 9 through 11 in the sequence are optional.
Also see to Figure 7-1.
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Table 7-2. Initialization Sequence
INITIALIZATION
SEQUENCE
NUMBER
INITIALIZATION SEQUENCE DESCRIPTION
Init seq 1
Power on
After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven
to LP11 state
Init seq 2
Init seq 3
Set EN pin to Low
Wait 10 ms (1)
Init seq 4
Tie EN pin to High
Wait 10 ms (1)
Init seq 5
Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI8x is not
functional until the CSR registers are initialized)
Init seq 6
Set the PLL_EN bit (CSR 0x0D.0)
Wait 10 ms (1)
Init seq 7
Set the SOFT_RESET bit (CSR 0x09.0)
Wait 10 ms (1)
Init seq 8
Change DSI data lanes to HS state and start DSI video stream
Wait 5 ms (1)
Init seq 9
Read back all resisters and confirm they were correctly written
Write 0xFF to CSR 0xE5 to clear the error registers
Init seq 10
Wait 1 ms (1)
Init seq 11
Read CSR 0xE5. If CSR 0xE5!= 0x00, then go back to step #2 and re-initialize
(1) Minimum recommended delay. It is fine to exceed these.
7.4.4 LVDS Output Formats
The SN65DSI84 processes DSI packets and produces video data driven to the FlatLink™ LVDS interface in an
industry standard format. Single-Link LVDS and Dual-Link LVDS are supported by the SN65DSI84; when the
FlatLink™ output is implemented in a Dual-Link configuration, channel A carries the odd pixel data, and channel
B carries the even pixel data. During conditions such as the default condition, and some video synchronization
periods, where no video stream data is passing from the DSI input to the LVDS output, the SN65DSI84 transmits
zero value pixel data on the LVDS outputs while maintaining transmission of the vertical sync and horizontal
sync status.
Figure 7-4 illustrates a Single-Link LVDS 18bpp application.
Figure 7-5 illustrates a Dual-Link 24 bpp application using Format 2, controlled by CHA_24BPP_FORMAT1
(CSR 0x18.1) and CHB_24BPP_FORMAT1 (CSR 0x18.0). In data Format 2, the two MSB per color are
transferred on the Y3P/N LVDS lane.
Figure 7-6 illustrates a 24 bpp Single-Link application using Format 1. In data Format 1, the two LSB per color
are transferred on the Y3P/N LVDS lane.
Figure 7-7 illustrates a Single-Link LVDS application where 24 bpp data is received from DSI and converted to
18 bpp data for transmission to an 18 bpp panel. This application is configured by setting
CHA_24BPP_FORMAT1 (CSR 0x18.1) to ‘1’ and CHA_24BPP_MODE (CSR 0x18.3) to ‘0’. In this configuration,
the SN65DSI84 will not transmit the 2 LSB per color since the Y3P/N LVDS lane is disabled.
Note
Note: Figure 7-4, Figure 7-5, Figure 7-6, and Figure 7-7 only illustrate a few example applications for
the SN65DSI84. Other applications are also supported.
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A_CLKP/N
B_CLKP/N
cycle ‘n-1’
cycle ‘n’
G0
B1
DE
R5
B0
VS
R4
G5
HS
R3
R2
G3
B4
R1
G2
B3
R0
G1
B2
A_Y0P/N
A_Y1P/N
A_Y2P/N
A_Y3P/N
G4
B5
B_YxP/N
DE = Data Enable; Channel B Clock, Channel B Data, and A_Y3P/N are Output Low
Figure 7-4. Flatlink Output Data; Single-Link 18 Bpp
A_CLKP/N
B_CLKP/N
cycle ‘n-1’
cycle ‘n’
G0
(o)
R5
(o)
R4
(o)
R3
(o)
R2
(o)
R1
(o)
R0
(o)
A_Y0P/N
A_Y1P/N
A_Y2P/N
A_Y3P/N
B1
(o)
B0
(o)
G5
(o)
G4
(o)
G3
(o)
G2
(o)
G1
(o)
DE
(o)
VS
(o)
HS
(o)
B5
(o)
B4
(o)
B3
(o)
B2
(o)
0
(o)
B7
(o)
B6
(o)
G7
(o)
G6
(o)
R7
(o)
R6
(o)
G0
(e)
R5
(e)
R4
(e)
R3
(e)
R2
(e)
R1
(e)
R0
(e)
B_Y0P/N
B_Y1P/N
B_Y2P/N
B_Y3P/N
B1
(e)
B0
(e)
G5
(e)
G4
(e)
G3
(e)
G2
(e)
G1
(e)
DE
(e)
VS
(e)
HS
(e)
B5
(e)
B4
(e)
B3
(e)
B2
(e)
0
(e)
B7
(e)
B6
(e)
G7
(e)
G6
(e)
R7
(e)
R6
(e)
DE = Data Enable; (o) = Odd Pixels; (e) = Even Pixels
Figure 7-5. Flatlink Output Data (Format 2); Dual-Link 24 Bpp
A_CLKP/N
B_CLKP/N
cycle ‘n-1’
cycle ‘n’
G2
B3
DE
R7
B2
VS
R6
G7
HS
R5
R4
G5
B6
R3
G4
B5
R2
G3
B4
A_Y0P/N
A_Y1P/N
A_Y2P/N
A_Y3P/N
G6
B7
0
B1
B0
G1
G0
R1
R0
B_YxP/N
DE = Data Enable; Channel B Clock and Data are Output Low
Figure 7-6. Flatlink Output Data (Format 1); Single-Link 24 Bpp
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A_CLKP/N
B_CLKP/N
cycle ‘n-1’
cycle ‘n’
G2
B3
DE
R7
B2
VS
R6
G7
HS
R5
G6
B7
R4
G5
B6
R3
G4
B5
R2
G3
B4
A_Y0P/N
A_Y1P/N
A_Y2P/N
A_Y3P/N
B_YxP/N
DE = Data Enable; Channel B Clock, Channel B Data, and A_Y3P/N a re Output Low; Channel B Clock, Channel B Data, and A_Y3P/N
are Output Low
Figure 7-7. Flatlink Output Data (Format 1); 24-Bpp to Single-Link 18-Bpp Conversion
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7.4.5 DSI Lane Merging
The SN65DSI84 supports four DSI data lanes per input channel, and may be configured to support one, two, or
three DSI data lanes per channel. Unused DSI input pins on the SN65DSI84 should be left unconnected or
driven to LP11 state. The bytes received from the data lanes are merged in HS mode to form packets that carry
the video stream. DSI data lanes are bit and byte aligned.
Figure 7-8 illustrates the lane merging function for each channel; 4-Lane, 3-Lane, and 2-Lane modes are
illustrated
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 4
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 3
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-4
BYTE n-3
BYTE n-2
BYTE n-1
EOT
EOT
EOT
EOT
SOT
SOT
SOT
BYTE0
BYTE 1
BYTE2
BYTE3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE8
BYTE n-3
BYTE n-2
BYTE n-1
EOT
EOT
EOT
LANE 0
LANE 1
LANE 2
BYTE 10
BYTE 11
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 3
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 4
SOT
SOT
SOT
BYTE0
BYTE 1
BYTE2
BYTE3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE8
BYTE n-2
BYTE n-1
EOT
EOT
EOT
LANE 0
LANE 1
LANE 2
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-3
BYTE n-2
BYTE n-1
EOT
EOT
EOT
EOT
BYTE 10
BYTE 11
HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 3
SOT
SOT
SOT
BYTE0
BYTE 1
BYTE2
BYTE3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE8
BYTE n-1
EOT
EOT
LANE 0
LANE 1
LANE 2
HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 4
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-2
BYTE n-1
EOT
EOT
EOT
EOT
BYTE 10
BYTE 11
3 DSI Data Lane Configuration
EOT
HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 2
HS BYTES TRANSMITTED (n) IS 3 LESS THAN INTEGER MULTIPLE OF 4
LANE 0
LANE 1
LANE 2
LANE 3
SOT
SOT
SOT
SOT
BYTE 0
BYTE1
BYTE2
BYTE 3
BYTE 4
BYTE5
BYTE6
BYTE 7
BYTE 8
BYTE9
BYTE n-1
EOT
EOT
LANE 0
LANE 1
SOT
SOT
BYTE 0
BYTE1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE n-2
BYTE n-1
EOT
EOT
BYTE 10
BYTE 11
EOT
HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 2
EOT
LANE 0
LANE 1
SOT
SOT
BYTE 0
BYTE1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE n-1
EOT
EOT
4 DSI Data Lane Configuration (default)
2 DSI Data Lane Configuration
Figure 7-8. SN65DSI84 DSI Lane Merging Illustration
7.4.6 DSI Pixel Stream Packets
The SN65DSI84 processes 18bpp (RGB666) and 24 bpp (RGB888) DSI packets on each channel as shown in
Figure 7-9, Figure 7-10, andFigure 7-11.
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1 Byte
2 Bytes
1 Byte
WORD COUNT Bytes
2 Bytes
18 bpp Loosely Packed Pixel Stream
(Variable Size Payload)
WORD COUNT
ECC
CRC CHECKSUM
Packet Payload
Packet Footer
Packet Header
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
0 1
2
7
2
7
2
7
2
7
2
7
2
7
2
7
2
7
2
7
R0
R5
G0
G5
B0
B5
R0
R5
G0
G5
B0
B5
R0
R5
G0
G5
B0
B5
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
6-bits
BLUE
First Pixel in Packet
Second Pixel in Packet
Third Pixel in Packet
Variable Size Payload (Three Pixels Per Nine Bytes of Payload)
Figure 7-9. 18 Bpp (Loosely Packed) DSI Packet Structure
1 Byte
2 Bytes
1 Byte
WORD COUNT Bytes
2 Bytes
18 bpp Packed Pixel Stream
(Variable Size Payload)
WORD COUNT
ECC
CRC CHECKSUM
Packet Payload
Packet Footer
Packet Header
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
0
5
6
7
0
3
4
7
0 1
2
7
0
5
6
7
0
3
4
7
0 1
2
7
0
5
6
7
0
3
4
7
0 1
2
7
R0
R5 G0
G5 B0
B5 R0
R5 G0
G5 B0
B5 R0
R5 G0
G5 B0
B5 R0
R5 G0
G5 B0
B5
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
6-bits
BLUE
6-bits
RED
6-bits
GREEN
6-bits
BLUE
First Pixel in Packet
Second Pixel in Packet
Third Pixel in Packet
Fourth Pixel in Packet
Variable Size Payload (Four Pixels Per Nine Bytes of Payload)
Figure 7-10. 18-Bpp (Tightly Packed) DSI Packet Structure
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1 Byte
2 Bytes
1 Byte
WORD COUNT Bytes
2 Bytes
24 bpp Packed Pixel Stream
(Variable Size Payload)
WORD COUNT
ECC
CRC CHECKSUM
Packet Payload
Packet Footer
Packet Header
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
0
7
R0
R7 G0
G 7 B0
B7 R0
R7 G0
G 7 B0
B7 R0
R7 G0
G7 B0
B7
8-bits
RED
8-bits
GREEN
8-bits
BLUE
8-bits
RED
8-bits
GREEN
8-bits
BLUE
8-bits
RED
8-bits
GREEN
8-bits
BLUE
First Pixel in Packet
Second Pixel in Packet
Third Pixel in Packet
Variable Size Payload (Three Pixels Per Nine Bytes of Payload)
Figure 7-11. 24-Bpp DSI Packet Structure
7.4.7 DSI Video Transmission Specifications
The SN65DSI84 supports burst video mode and non-burst video mode with sync events or with sync pulses
packet transmission as described in the DSI specification. The burst mode supports time-compressed pixel
stream packets that leave added time per scan line for power savings LP mode. The SN65DSI84 requires a
transition to LP mode once per frame to enable PHY synchronization with the DSI host processor; however, for a
robust and low-power implementation, the transition to LP mode is recommended on every video line.
Figure 7-12 illustrates the DSI video transmission applied to SN65DSI84 applications. In all applications, the
LVDS output rate must be less than or equal to the DSI input rate. The first line of a video frame shall start with a
VSS packet, and all other lines start with VSE or HSS. The position of the synchronization packets in time is of
utmost importance since this has a direct impact on the visual performance of the display panel; that is, these
packets generate the HS and VS (horizontal and vertical sync) signals on the LVDS interface after the delay
programmed into CHA_SYNC_DELAY_LOW/HIGH (CSR 0x28.7:0 and 0x29.3:0).
As required in the DSI specification, the SN65DSI84 requires that pixel stream packets contain an integer
number of pixels (i.e. end on a pixel boundary); it is recommended to transmit an entire scan line on one pixel
stream packet. When a scan line is broken in to multiple packets, inter-packet latency shall be considered such
that the video pipeline (ie. pixel queue or partial line buffer) does not run empty (i.e. under-run); during scan line
processing, if the pixel queue runs empty, the SN65DSI84 transmits zero data (18’b0 or 24’b0) on the LVDS
interface.
Note
When the HS clock is used as a source for the LVDS pixel clock, the LP mode transitions apply only to
the data lanes, and the DSI clock lane remains in the HS mode during the entire video transmission.
The DSI84 does not support the DSI Virtual Channel capability or reverse direction (peripheral to
processor) transmissions.
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One Video Frame
t LINE
t LINE
t LINE
t LINE
t LINE
t LINE
t LINE
DSI
Channel A
NOP/
LP
NOP/
LP
NOP/
LP
NOP/
RGB
NOP/
LP
NOP/
LP
NOP/
LP
...
...
...
RGB
LP
Vertical sync / blanking
Active Lines
Vertical sync / blanking
* VSS and HSS packets are required for DSI Channel B, although LVDS video sync signals are derived from DSI Channel A VSS and HSS packets
Vertical Blanking Period LVDS Transfer Function
Active Video Line LVDS Transfer Function
t LINE
t LINE
tLINE
DSI
DSI
DSI
NOP/
LP
NOP/
LP
NOP/
LP
...
RGB
Channel A
Channel A
Channel(s)
tW (HS )
t W(HS)
HS (1)
HS(1)
HS (1)
t PD
tPD
VS (2)
DE (3)
DATA
VS (2)
DE(3)
DATA
VS (2)
DE (3)
DATA
0x000
0x000
0x000
PixelStream Data
0x000 (4)
LEGEND
VSS
(1) The assertion of HS is delayed (tPD) by a programmable number of pixel clocks from the
last bit of VSS/HSS packet received on DSI. The HS pulse width (tW(HS)) is also programmable.
The illustration shows HS active low.
DSI Sync Event Packet: V Sync Start
DSI Sync Event Packet: H Sync Start
(2) VS is signaled for a programmable number of lines (tLINE ) and is asserted when HS is
asserted for the first line of the frame . VS is de -asserted when HS is asserted after the
number of lines programmed has been reached. The illustration shows VS active low
HSS
RGB
A sequence of DSI Pixel Stream Packets
and Null Packets
(3) DE is asserted when active pixel data is transmitted on LVDS , and polarity is set
independent to HS/VS. The illustration shows DE active high
NOP/LP
DSI Null Packet , Blanking Packet , or a
transition to LP Mode
(4) After the last pixel in an active line is output to LVDS, the LVDS data is output zero
Figure 7-12. DSI Channel Transmission and Transfer Function
7.4.8 Operating Modes
The SN65DSI84 can be configured for several different operating modes via LVDS_LINK_CFG (CSR 0x18.4),
LEFT_RIGHT_PIXELS (CSR 0x10.7), and DSI_CHANNEL_MODE (CSR 0x10.6:5). These modes are
summarized in Table 7-3. In each of the modes, video data can be 18 bpp or 24 bpp.
Table 7-3. SN65DSI84 Operating Modes
CSR 0x18.4
MODE
DESCRIPTION
LVDS_LINK_CFG
Single DSI Input to Single-Link LVDS
Single DSI Input to Dual-Link LVDS
1
Single DSI Input on Channel A to Single-Link LVDS output on Channel A.
Single DSI Input on Channel A to Dual-Link LVDS output with Odd pixels on
Channel A and Even pixels on Channel B.
0
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7.5 Programming
7.5.1 Local I2C Interface Overview
The SN65DSI84 local I2C interface is enabled when EN is input high, access to the CSR registers is supported
during ultra-low power state (ULPS). The SCL and SDA terminals are used for I 2C clock and I 2C data
respectively. The SN65DSI84 I2C interface conforms to the two-wire serial interface defined by the I2C Bus
Specification, Version 2.1 (January 2000), and supports fast mode transfers up to 400 kbps.
The device address byte is the first byte received following the START condition from the master device. The 7
bit device address for SN65DSI84 is factory preset to 010110X with the least significant bit being determined by
the ADDR control input. Table 7-4 clarifies the SN65DSI84 target address.
Table 7-4. SN65DSI84 I2C Target Address Description (1) (2)
SN65DSI84 I2C TARGET ADDRESS
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
ADDR
BIT 0 (W/R)
0
1
0
1
1
0
0/1
(1) When ADDR=1, Address Cycle is 0x5A (Write) and 0x5B (Read)
(2) When ADDR=0, Address Cycle is 0x58 (Write) and 0x59 (Read)
The following procedure is followed to write to the SN65DSI84 I2C registers.
1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI84 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The SN65DSI84 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within SN65DSI84) to be written, consisting of one byte of
data, MSB-first.
4. The SN65DSI84 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The SN65DSI84 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the SN65DSI84.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure is followed to read the SN65DSI84 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the SN65DSI84 7-bit
address and a one-value “W/R” bit to indicate a read cycle.
2. The SN65DSI84 acknowledges the address cycle.
3. The SN65DSI84 transmit the contents of the memory registers MSB-first starting at register 00h. If a write to
the SN65DSI84 I2C register occurred prior to the read, then the SN65DSI84 will start at the sub-address
specified in the write.
4. The SN65DSI84 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master
after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the SN65DSI84 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure is followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI84 7-bit
address and a zero-value “W/R” bit to indicate a write cycle
2. The SN65DSI84 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within SN65DSI84) to be written, consisting of one byte of
data, MSB-first.
4. The SN65DSI84 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
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7.6 Register Maps
7.6.1 Control and Status Registers Overview
Many of the SN65DSI84 functions are controlled by the Control and Status Registers (CSR). All CSR registers
are accessible through the local I2C interface.
See the following tables for the SN65DSI84 CSR descriptions. Reserved or undefined bit fields should not be
modified. Otherwise, the device may operate incorrectly.
Table 7-5. CSR Bit Field Definitions – ID Registers
ADDRESS
BIT(S)
DESCRIPTION
DEFAULT
ACCESS(1)
Reserved
0x00 – 0x08
7:0
Addresses 0x08 - 0x00 = {0x01, 0x20, 0x20, 0x20, 0x44, 0x53, 0x49, 0x38,
0x35}
Reserved
RO
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)
Table 7-6. CSR Bit Field Definitions – Reset and Clock Registers
ADDRESS
BIT(S)
DESCRIPTION
DEFAULT
ACCESS (1)
SOFT_RESET
This bit automatically clears when set to ‘1’ and returns zeros when read.
This bit must be set after the CSR’s are updated. This bit must also be set
after making any changes to the DIS clock rate or after changing between
DSI burst and non-burst modes.
0x09
0
0
WO
0 – No action (default)
1 – Reset device to default condition excluding the CSR bits.
PLL_EN_STAT
0 – PLL not enabled (default)
1 – PLL enabled
Note: After PLL_EN_STAT = 1, wait at least 3ms for PLL to lock.
7
3:1
0
0
101
0
RO
RW
RW
LVDS_CLK_RANGE
This field selects the frequency range of the LVDS output clock.
000 – 25 MHz ≤ LVDS_CLK < 37.5 MHz
001 – 37.5 MHz ≤ LVDS_CLK < 62.5 MHz
010 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz
011 – 87.5 MHz ≤ LVDS_CLK < 112.5 MHz
100 – 112.5 MHz ≤ LVDS_CLK < 137.5 MHz
101 – 137.5 MHz ≤ LVDS_CLK ≤ 154 MHz (default)
110 – Reserved
0x0A
111 – Reserved
HS_CLK_SRC
0 – LVDS pixel clock derived from input REFCLK (default)
1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous
clock
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Table 7-6. CSR Bit Field Definitions – Reset and Clock Registers (continued)
BIT(S)
ADDRESS
DESCRIPTION
DEFAULT
DSI_CLK_DIVIDER
When CSR 0x0A.0 = ‘1’, this field controls the divider used to generate the
LVDS output clock from the MIPI D-PHY Channel A HS continuous clock.
When CSR 0x0A.0 = ‘0’, this field must be programmed to 00000.
00000 – LVDS clock = source clock (default)
00001 – Divide by 2
00010 – Divide by 3
00011 – Divide by 4
7:3
00000
RW
•
•
•
0x0B
10111 – Divide by 24
11000 – Divide by 25
11001 through 11111 – Reserved
REFCLK_MULTIPLIER
When CSR 0x0A.0 = ‘0’, this field controls the multiplier used to generate the
LVDS output clock from the input REFCLK. When CSR 0x0A.0 = ‘1’, this field
must be programmed to 00.
00 – LVDS clock = source clock (default)
01 – Multiply by 2
1:0
00
RW
RW
10 – Multiply by 3
11 – Multiply by 4
PLL_EN
When this bit is set, the PLL is enabled with the settings programmed into
CSR 0x0A and CSR 0x0B. The PLL should be disabled before changing any
of the settings in CSR 0x0A and CSR 0x0B. The input clock source must be
active and stable before the PLL is enabled.
0 – PLL disabled (default)
0x0D
0
0
1 – PLL enabled
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)
Table 7-7. CSR Bit Field Definitions – DSI Registers
ADDRESS
BIT(S)
7
DESCRIPTION
DEFAULT
ACCESS (1)
RW
Reserved - Do not write to this field. Must remain at default.
Reserved - Do not write to this field. Must remain at default.
0
6:5
01
RW
CHA_DSI_LANES
This field controls the number of lanes that are enabled for DSI Channel A.
00 – Four lanes are enabled
4:3
01 – Three lanes are enabled
10 – Two lanes are enabled
11
RW
0x10
11 – One lane is enabled (default)
Note: Unused DSI input pins on the SN65DSI84 should be left unconnected.
SOT_ERR_TOL_DIS
0 – Single bit errors are tolerated for the start of transaction SoT leader
sequence (default)
1 – No SoT bit errors are tolerated
0
0
RW
RW
CHA_DSI_DATA_EQ
This field controls the equalization for the DSI Channel A Data Lanes
00 – No equalization (default)
01 – 1 dB equalization
7:6
00
10 – Reserved
11 – 2 dB equalization
0x11
CHA_DSI_CLK_EQ
This field controls the equalization for the DSI Channel A Clock
00 – No equalization (default)
01 – 1 dB equalization
3:2
00
RW
10 – Reserved
11 – 2 dB equalization
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Table 7-7. CSR Bit Field Definitions – DSI Registers (continued)
BIT(S)
DESCRIPTION
DEFAULT
ACCESS (1)
CHA_DSI_CLK_RANGE
This field specifies the DSI Clock frequency range in 5 MHz increments for
the DSI Channel A Clock
0x00 through 0x07 – Reserved
0x08 – 40 ≤ frequency < 45 MHz
0x09 – 45 ≤ frequency < 50 MHz
•
0x12
7:0
0
RW
•
•
0x63 – 495 ≤ frequency < 500 MHz
0x64 – 500 MHz
0x65 through 0xFF – Reserved
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)
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Table 7-8. CSR Bit Field Definitions – LVDS Registers
ADDRESS
BIT(S)
DESCRIPTION
DEFAULT
DE_NEG_POLARITY
0 – DE is positive polarity driven ‘1’ during active pixel transmission on LVDS
7
(default)
0
RW
1 – DE is negative polarity driven ‘0’ during active pixel transmission on
LVDS
HS_NEG_POLARITY
6
5
0 – HS is positive polarity driven ‘1’ during corresponding sync conditions
1 – HS is negative polarity driven ‘0’ during corresponding sync (default)
1
1
RW
RW
VS_NEG_POLARITY
0 – VS is positive polarity driven ‘1’ during corresponding sync conditions
1 – VS is negative polarity driven ‘0’ during corresponding sync (default)
LVDS_LINK_CFG
0 – LVDS Channel A and Channel B outputs enabled
When CSR 0x10.6:5 = ’00’ or ‘01’, the LVDS is in Dual-Link
configuration
4
1
RW
When CSR 0x10.6:5 = ‘10’, the LVDS is in two Single-Link
configuration
1 – LVDS Single-Link configuration; Channel A output enabled and Channel
B output disabled (default)
CHA_24BPP_MODE
3
2
0 – Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled (default)
1 – Force 24bpp; LVDS channel A lane 4 (B_Y3P/N) is enabled
0
0
RW
RW
0x18
CHB_24BPP_MODE
0 – Force 18bpp; LVDS channel B lane 4 (A_Y3P/N) is disabled (default)
1 – Force 24bpp; LVDS channel B lane 4 (B_Y3P/N) is enabled
CHA_24BPP_FORMAT1
This field selects the 24bpp data format
0 – LVDS channel A lane A_Y3P/N transmits the 2 most significant bits
(MSB) per color; Format 2 (default)
1 – LVDS channel B lane A_Y3P/N transmits the 2 least significant bits
(LSB) per color; Format 1
1
0
RW
Note1: This field must be ‘0’ when 18bpp data is received from DSI.
Note2: If this field is set to ‘1’ and CHA_24BPP_MODE is ‘0’, the SN65DSI84
will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In
this configuration, the SN65DSI84 will not transmit the 2 LSB per color on
LVDS channel A, since LVDS channel A lane A_Y3P/N is disabled.
CHB_24BPP_FORMAT1
This field selects the 24bpp data format
0 – LVDS channel B lane B_Y3P/N transmits the 2 most significant bits
(MSB) per color; Format 2 (default)
1 – LVDS channel B lane B_Y3P/N transmits the 2 least significant bits
(LSB) per color; Format 1
0
0
RW
Note1: This field must be ‘0’ when 18bpp data is received from DSI.
Note2: If this field is set to ‘1’ and CHB_24BPP_MODE is ‘0’, the SN65DSI84
will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In
this configuration, the SN65DSI84 will not transmit the 2 LSB per color on
LVDS channel B, since LVDS channel B lane B_Y3P/Nis disabled.
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Table 7-8. CSR Bit Field Definitions – LVDS Registers (continued)
BIT(S)
DESCRIPTION
DEFAULT
ACCESS (1)
CHA_LVDS_VOCM
This field controls the common mode output voltage for LVDS Channel A
0 – 1.2V (default)
6
0
RW
1 – 0.9V (CSR 0x1B.5:4 CHA_LVDS_CM_ADJUST must be set to ‘01b’)
CHB_LVDS_VOCM
This field controls the common mode output voltage for LVDS Channel B
0 – 1.2V (default)
1 – 0.9V (CSR 0x1B.1:0 CHB_LVDS_CM_ADJUST must be set to ‘01b’)
4
0
RW
RW
RW
0x19
CHA_LVDS_VOD_SWING
This field controls the differential output voltage for LVDS Channel A. See
the Electrical Characteristics table for |VOD| for each setting:
00, 01 (default), 10, 11.
3:2
1:0
01
01
CHB_LVDS_VOD_SWING
This field controls the differential output voltage for LVDS Channel B. See
the Electrical Characteristics table for |VOD| for each setting:
00, 01 (default), 10, 11.
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Table 7-8. CSR Bit Field Definitions – LVDS Registers (continued)
ADDRESS
BIT(S)
DESCRIPTION
DEFAULT
EVEN_ODD_SWAP
0 – Odd pixels routed to LVDS Channel A and Even pixels routed to LVDS
Channel B (default)
1 – Odd pixels routed to LVDS Channel B and Even pixels routed to LVDS
Channel A
6
0
RW
Note: When the SN65DSI84 is in two stream mode (CSR 0x10.6:5 = ‘10’),
setting this bit to ‘1’ will cause the video stream from DSI Channel A to be
routed to LVDS Channel B and the video stream from DSI Channel B to be
routed to LVDS Channel A.
CHA_REVERSE_LVDS
This bit controls the order of the LVDS pins for Channel A.
0 – Normal LVDS Channel A pin order. LVDS Channel A pin order is the
same as listed in the Terminal Assignments Section. (default)
1 – Reversed LVDS Channel A pin order. LVDS Channel A
pin order is remapped as follows:
•
•
•
•
•
•
•
•
•
•
A_Y0P → A_Y3P
A_Y0N → A_Y3N
A_Y1P → A_CLKP
A_Y1N → A_CLKN
A_Y2P → A_Y2P
A_Y2N → A_Y2N
A_CLKP → A_Y1P
A_CLKN → A_Y1N
A_Y3P → A_Y0P
A_Y3N → A_Y0N
5
0
RW
CHB_REVERSE_LVDS
0x1A
This bit controls the order of the LVDS pins for Channel B.
0 – Normal LVDS Channel B pin order. LVDS Channel B pin order is the
same as listed in the Terminal Assignments Section. (default)
1 – Reversed LVDS Channel B pin order. LVDS Channel B
pin order is remapped as follows:
•
•
B_Y0P → B_Y3P
B_Y0N → B_Y3N
4
0
RW
•
•
•
•
•
•
•
•
B_Y1P → B_CLKP
B_Y1N → B_CLKN
B_Y2P → B_Y2P
B_Y2N → B_Y2N
B_CLKP → B_Y1P
B_CLKN → B_Y1N
B_Y3P → B_Y0P
B_Y3N → B_Y0N
CHA_LVDS_TERM
This bit controls the near end differential termination for LVDS Channel A.
This bit also affects the output voltage for LVDS Channel A.
0 – 100Ω differential termination
1
0
1
1
RW
RW
1 – 200Ω differential termination (default)
CHB_LVDS_TERM
This bit controls the near end differential termination for LVDS Channel B.
This bit also affects the output voltage for LVDS Channel B.
0 – 100Ω differential termination
1 – 200Ω differential termination (default)
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Table 7-8. CSR Bit Field Definitions – LVDS Registers (continued)
BIT(S)
DESCRIPTION
DEFAULT
ACCESS (1)
CHA_LVDS_CM_ADJUST
This field can be used to adjust the common mode output voltage for LVDS
Channel A.
5:4
00 – No change to common mode voltage (default)
01 – Adjust common mode voltage down 3%
10 – Adjust common mode voltage up 3%
11 – Adjust common mode voltage up 6%
00
RW
0x1B
CHB_LVDS_CM_ADJUST
This field can be used to adjust the common mode output voltage for LVDS
Channel B.
1:0
00 – No change to common mode voltage (default)
01 – Adjust common mode voltage down 3%
10 – Adjust common mode voltage up 3%
11 – Adjust common mode voltage up 6%
00
RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)
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Note for all video registers:
1. TEST PATTERN GENERATION PURPOSE ONLY registers are for test pattern generation use only. Others
are for normal operation unless the test pattern generation feature is enabled.
Table 7-9. CSR Bit Field Definitions – Video Registers
DESCRIPTION
ADDRESS
BIT(S)
DEFAULT
ACCESS(1)
CHA_ACTIVE_LINE_LENGTH_LOW
This field controls the length in pixels of the active horizontal line line that are
received on DSI Channel A and output to LVDS Channel A in single LVDS
Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel
mode(CSR 0x18.4=0). The value in this field is the lower 8 bits of the 12-bit
value for the horizontal line length.
0x20
7:0
0
RW
CHA_ACTIVE_LINE_LENGTH_HIGH
This field controls the length in pixels of the active horizontal line that are
received on DSI Channel A and output to LVDS Channel A in single LVDS
Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel
mode(CSR 0x18.4=0). The value in this field is the upper 4 bits of the 12-bit
value for the horizontal line length.
0x21
0x24
0x25
3:0
7:0
3:0
0
0
0
RW
RW
RW
CHA_VERTICAL_DISPLAY_SIZE_LOW
TEST PATTERN GENERATION PURPOSE ONLY. This field controls the
vertical display size in lines for LVDS Channel A in single LVDS Channel
mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR
0x18.4=0. The value in this field is the lower 8 bits of the 12-bit value for the
vertical display size.
CHA_VERTICAL_DISPLAY_SIZE_HIGH
TEST PATTERN GENERATION PURPOSE ONLY. This field controls the
vertical display size in lines for LVDS Channel A in single LVDS Channel
mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR
0x18.4=0). The value in this field is the upper 4 bits of the 12-bit value for the
vertical display size
CHA_SYNC_DELAY_LOW
This field controls the delay in pixel clocks from when an HSync or VSync is
received on the DSI to when it is transmitted on the LVDS interface for
Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B
in dual LVDS Channel mode(CSR 0x18.4=0). The delay specified by this
field is in addition to the pipeline and synchronization delays in the
SN65DSI84. The additional delay is approximately 10 pixel clocks. The Sync
delay must be programmed to at least 32 pixel clocks to ensure proper
operation. The value in this field is the lower 8 bits of the 12-bit value for the
Sync delay.
0x28
7:0
0
RW
CHA_SYNC_DELAY_HIGH
This field controls the delay in pixel clocks from when an HSync or VSync is
received on the DSI to when it is transmitted on the LVDS interface for
Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B
in dual LVDS Channel mode(CSR 0x18.4=0). The delay specified by this
field is in addition to the pipeline and synchronization delays in the
SN65DSI84. The additional delay is approximately 10 pixel clocks. The Sync
delay must be programmed to at least 32 pixel clocks to ensure proper
operation. The value in this field is the upper 4 bits of the 12-bit value for the
Sync delay.
0x29
3:0
0
RW
CHA_HSYNC_PULSE_WIDTH_LOW
This field controls the width in pixel clocks of the HSync Pulse Width for
LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A
and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is
the lower 8 bits of the 10-bit value for the HSync Pulse Width.
0x2C
0x2D
7:0
1:0
0
0
RW
RW
CHA_HSYNC_PULSE_WIDTH_HIGH
This field controls the width in pixel clocks of the HSync Pulse Width for
LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A
and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is
the upper 2 bits of the 10-bit value for the HSync Pulse Width.
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Table 7-9. CSR Bit Field Definitions – Video Registers (continued)
BIT(S)
DESCRIPTION
DEFAULT
ACCESS(1)
CHA_VSYNC_PULSE_WIDTH_LOW
This field controls the length in lines of the VSync Pulse Width for LVDS
Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B
in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the
lower 8 bits of the 10-bit value for the VSync Pulse Width.
0x30
0x31
0x34
0x36
0x38
0x3A
7:0
0
RW
CHA_VSYNC_PULSE_WIDTH_HIGH
This field controls the length in lines of the VSync Pulse Width for LVDS
Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B
in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the
upper 2 bits of the 10-bit value for the VSync Pulse Width.
1:0
7:0
7:0
7:0
7:0
0
0
0
0
0
RW
RW
RW
RW
RW
CHA_HORIZONTAL_BACK_PORCH
This field controls the time in pixel clocks between the end of the HSync
Pulse and the start of the active video data for LVDS Channel A in single
LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS
Channel mode(CSR 0x18.4=0).
CHA_VERTICAL_BACK_PORCH
TEST PATTERN GENERATION PURPOSE ONLY. This field controls the
number of lines between the end of the VSync Pulse and the start of the
active video data for LVDS Channel A in single LVDS Channel mode(CSR
0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).
CHA_HORIZONTAL_FRONT_PORCH
TEST PATTERN GENERATION PURPOSE ONLY. This field controls the
time in pixel clocks between the end of the active video data and the start of
the HSync Pulse for LVDS Channel A in single LVDS Channel mode(CSR
0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).
CHA_VERTICAL_FRONT_PORCH
TEST PATTERN GENERATION PURPOSE ONLY. This field controls the
number of lines between the end of the active video data and the start of the
VSync Pulse for LVDS Channel A in single LVDS Channel mode(CSR
0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0).
CHA_TEST_PATTERN
TEST PATTERN GENERATION PURPOSE ONLY. When this bit is set, the
SN65DSI84 will generate a video test pattern based on the values
programmed into the Video Registers for LDS Channel A in single LVDS
Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel
mode(CSR 0x18.4=0).
0x3C
4
0
RW
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)
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Table 7-10. CSR Bit Field Definitions – IRQ Registers
ADDRESS
BIT(S)
DESCRIPTION
DEFAULT
IRQ_EN
When enabled by this field, the IRQ output is driven high to communicate
IRQ events.
0 – IRQ output is high-impedance (default)
0xE0
0
0
RW
1 – IRQ output is driven high when a bit is set in registers 0xE5 that also has
the corresponding IRQ_EN bit set to enable the interrupt condition
CHA_SYNCH_ERR_EN
7
6
5
4
3
2
0
0 – CHA_SYNCH_ERR is masked
1 – CHA_SYNCH_ERR is enabled to generate IRQ events
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
CHA_CRC_ERR_EN
0 – CHA_CRC_ERR is masked
1 – CHA_CRC_ERR is enabled to generate IRQ events
CHA_UNC_ECC_ERR_EN
0 – CHA_UNC_ECC_ERR is masked
1 – CHA_UNC_ECC_ERR is enabled to generate IRQ events
CHA_COR_ECC_ERR_EN
0 – CHA_COR_ECC_ERR is masked
1 – CHA_COR_ECC_ERR is enabled to generate IRQ events
0xE1
CHA_LLP_ERR_EN
0 – CHA_LLP_ERR is masked
1 – CHA_ LLP_ERR is enabled to generate IRQ events
CHA_SOT_BIT_ERR_EN
0 – CHA_SOT_BIT_ERR is masked
1 – CHA_SOT_BIT_ERR is enabled to generate IRQ events
PLL_UNLOCK_EN
0 – PLL_UNLOCK is masked
1 – PLL_UNLOCK is enabled to generate IRQ events
CHA_SYNCH_ERR
When the DSI channel A packet processor detects an HS or VS
synchronization error, that is, an unexpected sync packet; this bit is set; this
bit is cleared by writing a ‘1’ value.
7
0
RW1C
CHA_CRC_ERR
6
5
4
When the DSI channel A packet processor detects a data stream CRC error,
this bit is set; this bit is cleared by writing a ‘1’ value.
0
0
0
RW1C
RW1C
RW1C
CHA_UNC_ECC_ERR
When the DSI channel A packet processor detects an uncorrectable ECC
error, this bit is set; this bit is cleared by writing a ‘1’ value.
CHA_COR_ECC_ERR
When the DSI channel A packet processor detects a correctable ECC error,
this bit is set; this bit is cleared by writing a ‘1’ value.
0xE5
CHA_LLP_ERR
When the DSI channel A packet processor detects a low level protocol error,
this bit is set; this bit is cleared by writing a ‘1’ value.
Low level protocol errors include SoT and EoT sync errors, Escape Mode
entry command errors, LP transmission sync errors, and false control errors.
Lane merge errors are reported by this status condition.
3
0
RW1C
CHA_SOT_BIT_ERR
2
0
When the DSI channel A packet processor detects an SoT leader sequence
bit error, this bit is set; this bit is cleared by writing a ‘1’ value.
0
1
RW1C
RW1C
PLL_UNLOCK
This bit is set whenever the PLL Lock status transitions from LOCK to
UNLOCK.
(1) RO = Read Only; RW = Read/Write; RW1C = Read/Write ‘1’ to Clear; WO = Write Only (reads return undetermined values)
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The SN65DSI84 device is primarily targeted for portable applications such as tablets and smart phones that
utilize the MIPI DSI video format. The SN65DSI84 device can be used between a GPU with DSI output and a
video panel with LVDS inputs
8.1.1 Video Stop and Restart Sequence
When the system requires to stop outputting video to the display, it is recommended to use the following
sequence for the SN65DSI84:
1. Clear the PLL_EN bit to 0 (CSR 0x0D.0)
2. Stop video streaming on DSI inputs
3. Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS.
When the system is ready to restart the video streaming.
1. Start video streaming on DSI inputs.
2. Set the PLL_EN bit to 1(CSR 0x0D.0).
3. Wait for a minimum of 3 ms.
4. Set the SOFT_RESET bit(0x09.0).
8.1.2 Reverse LVDS Pin Order Option
For ease of PCB routing, the SN65DSI84 supports swapping/reversing the channel or pin order via configuration
register programming. The order of the LVDS pin for LVDS Channel A or Channel B can be reversed by setting
the address 0x1A bit 5 CHA_REVERSE_LVDS or bit 4 CHB_REVERSE_LVDS. The LVDS Channel A and
Channel B can be swapped by setting the 0x1A.6 EVEN_ODD_SWAP bit. See the corresponding register bit
definition for details.
8.1.3 IRQ Usage
The SN65DSI84 provides an IRQ pin that can be used to indicate when certain errors occur on DSI. The IRQ
output is enabled through the IRQ_EN bit (CSR 0xE0.0). The IRQ pin will be asserted when an error occurs on
DSI, the corresponding error enable bit is set, and the IRQ_EN bit is set. An error is cleared by writing a ‘1’ to the
corresponding error status bit.
Note
If the SOFT_RESET bit is set while the DSI video stream is active, some of the error status bits may
be set.
If the DSI video stream is stopped, some of the error status bits may be set. These error status bits
should be cleared before restarting the video stream.
If the DSI video stream starts before the device is configured, some of the error status bits may be set.
It is recommended to start streaming after the device is correctly configured as recommended in the
initialization sequence in the Section 7.4.3 section.
8.2 Typical Application
Figure 8-1 illustrates a typical application using the SN65DSI84 for a single channel DSI receiver to interface a
single-channel DSI application processor to an LVDS Dual-Link 18 bit-per-pixel panel supporting 1920 x 1200
WUXGA resolutions at 60 frames per second.
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SN65DSI84
A_Y0N
A_Y0P
100Ω
100Ω
100Ω
100Ω
DA0P
A_Y1N
A_Y1P
Application
Processor
DA0N
to odd pixel
row and column
drivers
DA1P
DA1N
A_Y2N
A_Y2P
DA2P
DA2N
A_CLKN
A_CLKP
DA3P
DA3N
A_Y3N
A_Y3P
DACP
DACN
B_Y0N
B_Y0P
SCL
SDA
100Ω
100Ω
100Ω
100Ω
IRQ
EN
B_Y1N
B_Y1P
to even pixel
row and column
drivers
ADDR
REFCLK
GND
B_Y2N
B_Y2P
B_CLKN
B_CLKP
1.8V
B_Y3N
B_Y3P
VCC
C1
Figure 8-1. Typical 1920 x 1200 WUXGA 18-bpp Panel Application
8.2.1 Design Requirements
For the 1920 x 1200 WUXGA 18-bpp Panel typical application design parameters, see Table 8-1.
Table 8-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
1.8V (±5%)
DSIA_CLK
N/A
VCC
CLOCK
REFCKL Frequency
DSIA Clock Frequency
PANEL INFORMATION
490 MHz
LVDS Output Clock Frequency
Resolution
81 MHz
1920 x 1200
Horizontal Active (pixels)
Horizontal Blanking (pixels)
Vertical Active (lines)
960
144
1200
Vertical Blanking (lines)
20
Horizontal Sync Offset (pixels)
Horizontal Sync Pulse Width (pixels)
Vertical Sync Offset (lines)
Vertical Sync Pulse Width (lines)
Horizontal Sync Pulse Polarity
Vertical Sync Pulse Polarity
Color Bit Depth (6bpc or 8bpc)
Number of LVDS Lanes
50
50
1
5
Negative
Negative
6-bit
2 X [3 Data Lanes + 1 Clock Lane]
DSI INFORMATION
Number of DSI Lanes
1 X [4 Data Lanes + 1 Clock Lane]
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Table 8-1. Design Parameters (continued)
DESIGN PARAMETER
EXAMPLE VALUE
490MHz
DSI Input Clock Frequency
Dual DSI Configuration(Odd/Even or Left/Right)
N/A
8.2.2 Detailed Design Procedure
The video resolution parameters required by the panel need to be programmed into the SN65DSI84. For this
example, the parameters programmed would be the following:
Horizontal active = 1920 or 0x780
CHA_ACTIVE_LINE_LENGTH_LOW = 0X80
CHA_ACTIVE_LINE_LENGTH_HIGH = 0x07
Horizontal pulse Width = 50 or 0x32
CHA_HSYNC_PULSE_WIDTH_LOW = 0x32
CHA_HSYNC_PULSE_WIDTH_HIGH= 0x00
Horizontal back porch = Horizontal blanking – (Horizontal sync offset + Horizontal sync pulse width)
Horizontal back porch = 144– (50 + 50)
Horizontal back porch = 44 or 0x2C
CHA_HORIZONTAL_BACK_PORCH = 0x2C
Vertical pulse width = 5
CHA_VSYNC_PULSE_WIDTH_LOW = 0x05
CHA_VSYNC_PULSE_WIDTH_HIGH= 0x00
The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0x3C and
configuring the following TEST PATTERN GENERATION PURPOSE ONLY registers.
Vertical active = 1200 or 0x4B0
CHA_VERTICAL_DISPLAY_SIZE_LOW = 0xB0
CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0x04
Vertical back porch = Vertical blanking – (Vertical sync offset +Vertical sync pulse width)
Vertical back porch = 20 – (1 + 5)
Vertical back porch = 14 or 0x0E
CHA_VERTICAL_BACK_PORCH = 0x0E
Horizontal front porch = Horizontal sync offset
Horizontal front porch = 50 or 0x32
CHA_HORIZONTAL_FRONT_PORCH = 0x32
Vertical front porch = Vertical sync offset
Vertical front porch =1
CHA_VERTICAL_FRONT_PORCH = 0x01
In this example, the clock source for the SN65DSI84 is the DSI clock. When the MIPI D-PHY clock is used as
the LVDS clock source, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLink
LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0x0A.3:1) and CH_DSI_CLK_RANGE(CSR 0x12)
must be set to the frequency range of the FlatLink LVDS output clock and DSI Channel A input clock respectively
for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0x0D.0) should be
set to enable the internal PLL.
LVDS_CLK_RANGE = 010b-62.5 MHz ≤ LVDS_CLK < 87.5 MHz
HS_CLK_SRC = 1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock
DSI_CLK_DIVIDER = 0010b – Divide by 6
CHA_DSI_LANES = 00 – Four lanes are enabled
CHA_DSI_CLK_RANGE = 0x62 – 490 MHz ≤ frequency < 495 MHz
8.2.2.1 Example Script
This example configures the SN65DSI84 for the following configuration:
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<aardvark>
<configure i2c="1" spi="1" gpio="0" tpower="1" pullups="1"/>
<i2c_bitrate khz="100"/>
=====SOFTRESET=======
<i2c_write addr="0x2D" count="1" radix="16"glt;09 01</i2c_writeglt;
<sleep ms="10"/>
======ADDR 0D=======
======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured======
<i2c_write addr="0x2D" count="1" radix="16"glt;0D 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 0A=======
======HS_CLK_SRC bit0===
======LVDS_CLK_Range bit 3:1======
<i2c_write addr="0x2D" count="1" radix="16"glt;0A 05</i2c_writeglt;
<sleep ms="10"/>
======ADDR 0B=======
======DSI_CLK_DIVIDER bit7:3=====
======RefCLK multiplier(bit1:0)====== ======00 - LVDSclk=source clk, 01 - x2, 10 -x3, 11 - x4======
<i2c_write addr="0x2D" count="1" radix="16"glt;0B 28</i2c_writeglt;
<sleep ms="10"/>
======ADDR 10=======
======DSI Ch Confg Left_Right Pixels(bit7 - 0 for A ODD, B EVEN, 1 for the other config)======
======DSI Ch Mode(bit6:5) 00 - Dual, 01 - single, 10 - two single =======
======CHA_DSI_Lanes(bit4:3), CHB_DSI_Lanes(bit2:1), 00 - 4, 01 - 3, 10 - 2, 11 - 1
======SOT_ERR_TOL_DIS(bit0)=======
<i2c_write addr="0x2D" count="1" radix="16"glt;10 26</i2c_writeglt;
<sleep ms="10"/>
======ADDR 12=======
<i2c_write addr="0x2D" count="1" radix="16"glt;12 62</i2c_writeglt;
<sleep ms="10"/>
======ADDR 18=======
======bit7: DE_Pol, bit6:HS_Pol, bit5:VS_Pol, bit4: LVDS Link Cfg, bit3:CHA 24bpp, bit2: CHB 24bpp,
bit1: CHA 24bpp fmt1, bit0: CHB 24bpp fmt1======
<i2c_write addr="0x2D" count="1" radix="16"glt;18 63</i2c_writeglt;
<sleep ms="10"/>
======ADDR 19=======
<i2c_write addr="0x2D" count="1" radix="16"glt;19 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 1A=======
<i2c_write addr="0x2D" count="1" radix="16"glt;1A 03</i2c_writeglt;
<sleep ms="10"/>
======ADDR 20=======
======CHA_LINE_LENGTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;20 80</i2c_writeglt;
<sleep ms="10"/>
======ADDR 21=======
======CHA_LINE_LENGTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;21 07</i2c_writeglt;
<sleep ms="10"/>
======ADDR 22=======
======CHB_LINE_LENGTH_LOW========
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<i2c_write addr="0x2D" count="1" radix="16"glt;22 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 23=======
======CHB_LINE_LENGTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;23 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 24=======
======CHA_VERTICAL_DISPLAY_SIZE_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;24 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 25=======
======CHA_VERTICAL_DISPLAY_SIZE_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;25 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 26=======
======CHB_VERTICAL_DISPLAY_SIZE_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;26 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 27=======
======CHB_VERTICAL_DISPLAY_SIZE_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;27 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 28=======
======CHA_SYNC_DELAY_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;28 20</i2c_writeglt;
<sleep ms="10"/>
======ADDR 29=======
======CHA_SYNC_DELAY_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;29 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2A=======
======CHB_SYNC_DELAY_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;2A 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2B=======
======CHB_SYNC_DELAY_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;2B 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2C=======
======CHA_HSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;2C 32</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2D=======
======CHA_HSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;2D 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2E=======
======CHB_HSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;2E 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 2F=======
======CHB_HSYNC_PULSE_WIDTH_HIGH========
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<i2c_write addr="0x2D" count="1" radix="16"glt;2F 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 30=======
======CHA_VSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;30 05</i2c_writeglt;
<sleep ms="10"/>
======ADDR 31=======
======CHA_VSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;31 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 32=======
======CHB_VSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16"glt;32 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 33=======
======CHB_VSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16"glt;33 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 34=======
======CHA_HOR_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;34 2C</i2c_writeglt;
<sleep ms="10"/>
======ADDR 35=======
======CHB_HOR_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;35 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 36=======
======CHA_VER_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;36 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 37=======
======CHB_VER_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;37 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 38=======
======CHA_HOR_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;38 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 39=======
======CHB_HOR_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;39 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 3A=======
======CHA_VER_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;3A 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 3B=======
======CHB_VER_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16"glt;3B 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 3C=======
======CHA/CHB TEST PATTERN(bit4 CHA, bit0 CHB)========
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<i2c_write addr="0x2D" count="1" radix="16"glt;3C 00</i2c_writeglt;
<sleep ms="10"/>
======ADDR 0D=======
======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured======
<i2c_write addr="0x2D" count="1" radix="16"glt;0D 01</i2c_writeglt;
<sleep ms="10"/>
=====SOFTRESET=======
<i2c_write addr="0x2D" count="1" radix="16"glt;09 00</i2c_writeglt;
<sleep ms="10"/>
======write======
<i2c_write addr="0x2D" count="196" radix="16"glt;00</i2c_writeglt;
<sleep ms="10"/>
======Read======
<i2c_read addr="0x2D" count="256" radix="16"glt;00</i2c_readglt;
<sleep ms="10"/>
</aardvark>
8.2.3 Application Curve
SN65DSI84: SINGLE Channel DSI to DUAL Channel LVDS, 1440 x 900
111.0
Unit 1
110.0
Unit 2
109.0
Unit 3
108.0
107.0
106.0
105.0
104.0
103.0
102.0
0.0
20.0
40.0
60.0
80.0
œ40.0
œ20.0
Temperature (°C)
C001
Figure 8-2. Supply Current vs Temperature
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9 Power Supply Recommendations
9.1 VCC Power Supply
Each VCC power supply pin must have a 100-nF capacitor to ground connected as close as possible to the
SN65DSI83 device. It is recommended to have one bulk capacitor (1 µF to 10 µF) on it. It is also recommended
to have the pins connected to a solid power plane.
9.2 VCORE Power Supply
This pin must have a 100-nF capacitor to ground connected as close as possible to the SN65DSI83 device. It is
recommended to have one bulk capacitor (1 µF to 10 µF) on it. It is also recommended to have the pins
connected to a solid power plane.
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10 Layout
10.1 Layout Guidelines
10.1.1 Package Specific
For the ZXH package, to minimize the power supply noise floor, provide good decoupling near the SN65DSI83
device power pins. The use of four ceramic capacitors (2 × 0.1 μF and 2 × 0.01 μF) provides good performance.
At the least, TI recommends to install one 0.1-μF and one 0.01-μF capacitor near the SN65DSI83 device. To
avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power
inputs pins must be minimized. Placing the capacitor underneath the SN65DSI83 device on the bottom of the
PCB is often a good choice.
10.1.2 Differential Pairs
•
Differential pairs must be routed with controlled 100-Ω differential impedance (± 20%) or 50-Ω single-ended
impedance (±15%).
•
•
•
•
•
Keep away from other high speed signals
Keep lengths to within 5 mils of each other.
Length matching must be near the location of mismatch.
Each pair must be separated at least by 3 times the signal trace width.
The use of bends in differential traces must be kept to a minimum. When bends are used, the number of left
and right bends must be as equal as possible and the angle of the bend must be ≥ 135 degrees. This
arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that
bends have on EMI.
•
•
•
•
•
Route all differential pairs on the same of layer.
The number of vias must be kept to a minimum. It is recommended to keep the via count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do NOT route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity and will therefore negatively impact signal
performance. If test points are used, they must be placed in series and symmetrically. They must not be
placed in a manner that causes a stub on the differential pair.
10.1.3 Ground
TI recommends that only one board ground plane be used in the design. This provides the best image plane for
signal traces running above the plane. The thermal pad of the SN65DSI83 must be connected to this plane with
vias.
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10.2 Layout Example
Purple traces on
this side are LVDS
ChB signals.
Purple traces on
this side are DSI
ChA signals.
Green traces on
this side are LVDS
ChA signals.
Green traces on
this side are LVDS
ChB signals.
Figure 10-1. SN65DSI8x Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
11.3 Trademarks
FlatLink™ is a trademark of Texas Instruments.
MIPI® is a registered trademark of Arasan Chip Systems, Inc.
All trademarks are the property of their respective owners.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2020
PACKAGING INFORMATION
Orderable Device
SN65DSI84ZQER
SN65DSI84ZXHR
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
64
64
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
DSI84
DSI84
ACTIVE
NFBGA
ZXH
2500
Green (RoHS
& no Sb/Br)
SNAGCU
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65DSI84 :
Automotive: SN65DSI84-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE OUTLINE
ZXH0064A
NFBGA - 1 mm max height
SCALE 2.500
PLASTIC BALL GRID ARRAY
5.1
4.9
B
A
BALL A1 CORNER
INDEX AREA
5.1
4.9
(0.65)
1 MAX
C
SEATING PLANE
0.08 C
0.25
TYP
0.15
BALL TYP
4 TYP
SYMM
(0.5) TYP
J
H
G
F
(0.5) TYP
SYMM
64X
4
E
D
C
TYP
0.35
0.25
0.15
0.05
B
A
C A
C
B
0.5 TYP
1
2
3
4
5
6
7
8
9
0.5 TYP
4222101/A 06/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
ZXH0064A
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
64X ( 0.25)
(0.5) TYP
3
4
5
6
7
8
9
1
2
A
B
C
(0.5) TYP
D
E
F
G
H
J
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
(
0.25)
METAL
SOLDER MASK
OPENING
(
0.25)
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222101/A 06/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZXH0064A
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
64X ( 0.25)
(R0.05) TYP
(0.5) TYP
1
2
4
5
6
8
9
3
7
A
(0.5) TYP
B
C
D
E
F
G
H
J
METAL
TYP
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:20X
4222101/A 06/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
相关型号：
SN65DSI84_V01
SN65DSI84 MIPI® DSI Bridge To FLATLINK⢠LVDS Single Channel DSI to Dual-Link LVDS Bridge
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