SN65DP141 [TI]
12Gbps DP 1.4/eDP1.4 线性转接驱动器;
| 型号： | SN65DP141 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12Gbps DP 1.4/eDP1.4 线性转接驱动器 驱动 驱动器 |
| 文件： | 总35页 (文件大小：1681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65DP141
ZHCSEQ7C –FEBRUARY 2016 –REVISED DECEMBER 2021
SN65DP141 DisplayPort 线性转接驱动器
1 特性
3 说明
• 支持VESA DisplayPort 1.4a、
2.0 和eDP 1.4
• 四通道线性转接驱动器，支持高达12Gbps 的数据
速率，包括DisplayPort RBR、HBR、HBR2、
HBR3 和UHBR10
• 与协议无关
• 透明呈现DP 链路训练
• 与在链路上的位置无关，适用于源端、接收端和电
缆应用
• 6GHz 时模拟均衡为15dB
• 输出线性动态范围：1200mV
• 带宽：>20 GHz
• 6GHz 时的回波损耗优于16dB
• 2.5V 或3.3V ±5% 单电源选项
• 低功耗，2.5V VCC 时每通道80mW
• GPIO 或I2C 控制
SN65DP141 是一款与协议无关的异步、低延迟、四通
道线性均衡器，该器件经过优化适用于高达 12Gbps
的数据速率并且可对电路板走线和电缆所产生的损耗进
行补偿。
该器件透明呈现 DisplayPort (DP) 链路训练，这使得
DP 发送设备和接收设备能够执行有效的链路训练，克
服了传统 aux snooping 转接驱动器的缺点。此外，该
器件与位置无关。它可置于源设备、电缆或接收设备
内，从而为总体链路预算有效提供负损耗 分量。
SN65DP141 内的线性均衡在与接收器搭配使用时还可
提高链路裕度，从而实现判决反馈均衡(DFE)。
SN65DP141 支持采用 I2C 和 GPIO 配置对均衡、增
益、动态范围进行独立通道控制。
器件信息(1)
封装尺寸（标称值）
器件型号
SN65DP141
封装
WQFN (38)
7.00mm × 5.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 平板电脑
• 笔记本电脑
• 台式机
.
.
• 扩展坞
DP141
DP0
OUTP0
OUTP1
ML0
ML1
DP1
DP2
OUTP2
OUTP3
x
ML2
GPU
x
x
DP3
ML3
DP141
AUXp
AUXn
GPU
DP141
AUXp
AUXn
HPD
HPD
Copyright © 2016, Texas Instruments Incorporated
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSES6
SN65DP141
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ZHCSEQ7C –FEBRUARY 2016 –REVISED DECEMBER 2021
Table of Contents
8.3 Feature Description...................................................16
8.4 Device Functional Modes..........................................17
8.5 Register Maps...........................................................18
9 Application and Implementation..................................24
9.1 Application Information............................................. 24
9.2 Typical Application.................................................... 24
10 Power Supply Recommendations..............................26
11 Layout...........................................................................27
11.1 Layout Guidelines................................................... 27
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................29
12.1 接收文档更新通知................................................... 29
12.2 支持资源..................................................................29
12.3 Trademarks.............................................................29
12.4 Electrostatic Discharge Caution..............................29
12.5 术语表..................................................................... 29
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................8
6.7 Switching Characteristics, I2C Interface......................9
6.8 Typical Characteristics..............................................10
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................15
8.1 Overview...................................................................15
8.2 Functional Block Diagram.........................................15
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (September 2021) to Revision C (December 2021)
Page
• Changed the I2C_EN pin Type from internal pull-up to internal pull-down ........................................................3
Changes from Revision A (October 2016) to Revision B (September 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 将特性从：“支持VESA DisplayPort 1.3 和eDP 1.4”更新为：“支持VESA DisplayPort 1.4a、2.0 和eDP
1.4”................................................................................................................................................................... 1
• 将特性从“包括DisplayPort RBR、HBR、HBR2 和HBR3”更新为“包括DisplayPort RBR、HBR、HBR2、
HBR3 和UHBR10”...........................................................................................................................................1
• Updated the DP bit rates from: RBR to HBR3 (1.6 Gbps, 2.7 Gbps, 5.4 Gbps and 8.1 Gbps ... to: RBR to
UHBR10 (1.6 Gbps, 2.7 Gbps, 5.4 Gbps, 8.1 Gbps and 10.0 Gbps …in the Overview section......................15
• Updated Operating data rate from HBR3 (8.1 Gbps) to UHBR10 (10 Gbps)................................................... 24
Changes from Revision * (February 2016) to Revision A (October 2016)
Page
• Replaced 图9-2 ...............................................................................................................................................25
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5 Pin Configuration and Functions
38
37
36
35
34
33
32
OUT0_P
OUT0_N
VCC
IN0_P
1
31
30
29
28
27
IN0_N
2
VCC
IN1_P
IN1_N
3
OUT1_P
4
5
OUT1_N
VCC
6
VCC
VCC
26
25
24
Thermal
Pad
7
VCC
OUT2_P
IN2_P
IN2_N
8
23
22
21
20
OUT2_N
9
10
11
12
VCC
VCC
OUT3_P
IN3_P
IN3_N
OUT3_N
13
14
15
16
17
18
19
It is required for the thermal pad to be soldered to ground for better thermal performance.
图5-1. RLJ Package 38 Pins (WQFN) Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
DIFFERENTIAL HIGH-SPEED I/O
IN0_P
1
2
I
I
Differential input, lane 0 (with 50 Ωtermination to input common mode)
Differential input, lane 1 (with 50 Ωtermination to input common mode)
Differential input, lane 2 (with 50 Ωtermination to input common mode)
Differential input, lane 3 (with 50 Ωtermination to input common mode)
Differential output, lane 0
IN0_N
IN1_P
4
I
IN1_N
5
I
IN2_P
8
I
IN2_N
9
I
IN3_P
11
12
31
30
28
27
24
23
21
20
I
IN3_N
I
OUT0_P
OUT0_N
OUT1_P
OUT1_N
OUT2_P
OUT2_N
OUT3_P
OUT3_N
O
O
O
O
O
O
O
O
Differential output, lane 1
Differential output, lane 2
Differential output, lane 3
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表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
15
CONTROL SIGNALS
I
I2C mode:
GPIO mode:
HIGH: disable Driver peaking
LOW: enables Driver 6-dB AC peaking
(with 200-kΩ internal
pull-up)
I2C CLK. Connect a 10-kΩpull-up resistor
DRV_PK#/SCL
externally.
I2C mode:
ADD2 along with pins ADD1 and ADD0
comprise the three bits of I2C slave
address. ADD2:ADD1:ADD0:XXX
I
GPIO mode:
HIGH: Trace mode
LOW: Cable mode
(with 200-kΩ Internal
pull-down, 2.5 V/3.3
V CMOS )
EQ_MODE/ ADD2
EQ0/ADD0
35
I2C mode:
ADD0 along with pins ADD1 and ADD2
comprise the three bits of I2C slave
address. ADD2:ADD1:ADD0:XXX
I
GPIO mode:
33
(2.5 V/3.3 V CMOS - Working with RX_GAIN and EQ1 to determine the
3-state)
receiver DC and AC gain.
I2C mode:
I
GPIO mode:
ADD1 along with pins ADD0 and ADD2
comprise the three bits of I2C slave
address ADD2:ADD1:ADD0:XXX
EQ1/ADD1
I2C_EN
PWD#
34
16
37
(2.5 V/3.3 V CMOS - Working with RX_GAIN and EQ0 to determine the
3-state)
receiver DC and AC gain.
Configures the device operation for I2C or GPIO mode:
HIGH: enables I2C mode
I
(with 200-kΩ internal
pull-down)
LOW: enables GPIO mode
I
HIGH: Normal Operation
(with 200-kΩ Internal
pull-up, 2.5 V/3.3 V
CMOS)
LOW: Power downs the device, inputs off and outputs disabled, resets I2C
REXT
18
36
I (analog)
External Bias Resistor: 1,200 Ωto GND
I
GPIO mode:
I2C mode:
RX_GAIN
(2.5 V/3.3 V CMOS - Working with EQ0 and EQ1 to determine the
No action needed
3-state)
receiver DC and AC gain.
I2C mode:
GPIO mode:
No action needed.
I2C data. Connect a 10-kΩpull-up resistor
SDA
14
17
I/O (open drain)
externally.
I
GPIO mode:
I2C mode:
(with 200-kΩ Internal
pull-down, 2.5 V/3.3
V CMOS)
TX_DC_GAIN/CS
HIGH: 6 dB DC gain for transmitter
LOW: 0 dB DC gain for transmitter
HIGH: acts as Chip Select
LOW: disables I2C interface
POWER SUPPLY
The ground center pad is the metal contact at the bottom of the package. This pad must be
connected to the GND plane. At least 15 PCB vias are recommended to minimize inductance
and provide a solid ground. Refer to the package drawing (RLJ-package) for the via placement.
GND Center Pad
Ground
Power
3, 6, 7, 10, 13,
19, 22, 25, 26,
29, 32, 38
VCC
Power supply 2.5 V ±5%, 3.3 V ±5%
(1) I = input, O = output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
4
UNIT
Supply voltage range
VCC
V
V
V
V
–0.3
–2.5
–0.5
–0.5
Differential voltage between INx_P and INx_N
Voltage at INx_P and INx_N,
Voltage on control IO pins,VIO
VIN, DIFF
VIN+, IN–
2.5
VCC + 0.5
VCC + 0.5
Continuous current at high speed differential data
inputs(differential)
25
25
mA
mA
IN+, IN–
–25
–25
Continuous current at high speed differential data
outputs
IOUT+, IOUT–
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
12
UNIT
Gbps
V
DR
VCC
TC
Operating data rate
Supply voltage
2.375
–10
–40
2.5/3.3
3.465
125
85
Junction temperature
Operating free-air temperature
°C
TA
°C
CMOS DC SPECIFICATIONS
VIH
Input high voltage
Input middle voltage
Input low voltage
0.8 x VCC
VCC x 0.4
–0.5
V
V
V
V(MID)
VIL
VCC x 0.6
0.2 x VCC
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6.4 Thermal Information
SN65DP141
RLJ (WQFN)
38 PINS
36.9
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
22.3
10.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJT
10.6
ψJB
RθJC(bot)
1.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER CONSUMPTION
PDL
Device Power dissipation
Device Power dissipation
VOD = Low, VCC = 3.3 V and all 4 channels
active
450
317
697
485
10
625
475
925
675
mW
mW
mW
mW
mW
VOD = Low, VCC = 2.5 V and all 4 channels
active
PDH
VOD = High, VCC = 3.3 V and all 4 channels
active
VOD = High, VCC = 2.5 V and all 4 channels
active
PDOFF
Device power with all 4 channels Refer to I2C section for device configuration
switched off
CMOS DC SPECIFICATIONS
IIH
IIL
High level input current
Low level input current
VIN = 0.9 × VCC
VIN = 0.1 × VCC
-40
-40
17
17
40
40
µA
µA
CML INPUTS (IN[3:0]_P, IN[3:0]_N)
RIN
Differential input resistance
Input linear dynamic range
Input common mode voltage
INx_P to INx_N
Gain = 0.5
100
Ω
mVpp
V
VIN
1200
VICM
Internally biased
VCC
–
0.8
SCD11
SDD11
Input differential to common
mode conversion
100 MHz to 6 GHz
100 MHz to 6 GHz
-20
dB
dB
Differential input return loss
-15
CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N)
VOD
Output linear dynamic range
1200
600
10
mVpp
mVpp
mVpp
V
RL = 100 Ω, VOD = HIGH
RL = 100 Ω, VOD = LOW
VOS
Output offset voltage
RL = 100 Ω, 0 V applied at inputs
VOCM
Output common mode voltage
VCC
–
0.4
VCM(RIP)
VOD(RIP)
Common mode output ripple
Differential path output ripple
K28.5 pattern at 12 Gbps on all 4 channels,
No interconnect loss, VOD = HIGH
10
20 mVRMS
20 mVpp
K28.5 pattern at 12 Gbps on all channels, No
interconnect loss, VIN = 1200 mVpp.
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6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOC(SS)
Change in steady-state common
mode output voltage between
logic states
±10
mV
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6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N)
tR
Rise time (1)
Input signal with 30 ps rise time, 20% to 80%,
See 图7-3
31
32
ps
ps
tF
Fall time (1)
Input signal with 30 ps fall time, 20% to 80%,
See 图7-3
SDD22
Differential output return loss
6 GHz (12 Gbps)
-14
–9.33
–6.35
–3.5
65
dB
dB
dB
dB
ps
ps
ps
4.05 GHz (HBR3, 8.1 Gbps)
4.05 GHz (HBR3, 8.1 Gbps)
1.35 GHz (HBR, 2.7Gbps)
tPLH
Low-to-high propagation delay
High-to-low propagation delay
Inter-Pair (lane to lane) output skew (2)
See 图7-2
tPHL
65
tSK(O)
8
All outputs terminated with 100 Ω,
See 图7-4
tSK(PP)
rOT
Part-to-part skew (3)
50
ps
All outputs terminated with 100 Ω
Single ended output resistance
Single ended on-chip termination to VCC
,
50
Ω
Outputs are AC coupled
rOM
Output termination mismatch at 1 MHz
5%
≈
∆
«
’
÷
◊
rp - rn
Dr
= 2 x
x 100
OM
rn + rp
Channel-to-channel isolation
Output referred noise(4)
Frequency at 6 GHz
35
45
dB
10 MHz to 6 GHz, No other noise source present,
VOD = LOW
400
µVRMS
10 MHz to 6 GHz, No other noise source present,
VOD = HIGH
500
µVRMS
EQUALIZATION
G
At 6 GHz input signal
Equalization Gain, EQ = MAX
15
dB
dB
V(pre)
Output pre-cursor pre-emphasis
Output post-cursor pre-emphasis
Input signal with 3.75 pre-cursor and measure it on
the output signal,
See 图7-5
3.75
V(pst)
Input signal with 12 dB post-cursor and measure it
on the output signal,
12
dB
See 图7-5
(1) Rise and Fall measurements include board and channel effects of the test environment, refer to 图7-1 and 图7-3.
(2) tSK(O) is the magnitude of the time difference between the channels.
(3) tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same
(4) All noise sources added.
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6.7 Switching Characteristics, I2C Interface
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
KHz
µs
fSCL
SCL clock frequency
400
tBUF
Bus free time between START and STOP conditions
1.3
0.6
tHDSTA
"Hold time after repeated START condition.
µs
After this period, the first clock pulse is generated
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data HOLD time
1.3
0.6
0.6
0
µs
µs
µs
µs
µs
µs
µs
µs
Data setup time
100
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
300
300
tF
tSUSTO
0.6
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6.8 Typical Characteristics
0
0
−10
−20
−30
−40
−50
−60
−70
−5
−10
−15
−20
−25
−30
−35
−40
−45
0
2
4
6
Frequency (GHz)
8
10
12
14
0
2
4
6
Frequency (GHz)
8
10
12
14
G002
G003
图6-1. Differential Input Return Loss
图6-2. Differential to Common Mode Conversion
0
0
−5
−5
−10
−15
−20
−25
−30
−35
−40
−10
−15
−20
−25
−30
−35
−40
−45
0
2
4
6
Frequency (GHz)
8
10
12
14
0
2
4
6
Frequency (GHz)
8
10
12
14
G004
G005
图6-3. Differential Output Return Loss
图6-4. Common Mode Output Return Loss
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7 Parameter Measurement Information
50ꢀ
50ꢀ
OUT+
VOCM
OUT-
1pF
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图7-1. Common Mode Output Voltage Test Circuit
SPACE
V
= 0 V
IN
ID
t
t
PHL
PLH
V
= 0 V
OUT
OD
图7-2. Propagation Delay Input to Output
SPACE
80%
80%
VOD
20%
20%
tr
tf
图7-3. Output Rise and Fall Times
SPACE
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OUTx
t
SK(0)
OUTy
图7-4. Output Inter-Pair Skew
SPACE
V
1
V
3
V
2
0V
V
5
Not drawn to scale
V
6
V
4
图7-5. V(pre) and V(post) (test pattern is 1111111100000000 (8-1s, 8-0s))
SPACE
CHARACTERIZATION
TEST CHANNEL
BOARD
SN65DP141
PATTERN
GENERATOR
OSCILLOSCOPE
L= 2"
RX+EQ
OUT
L= 2"
图7-6. Receive Side Performance Test Circuit
SPACE
CHARACTERIZATION BOARD
TEST CHANNEL
SN65DP141
PATTERN
GENERATOR
OSCILLOSCOPE
L= 2"
L= 2"
OUT
图7-7. Transmit Side Performance Test Circuit
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VCC
IN+
R = 50ꢀ
T(SE)
Gain
Stage
+EQ
VCC
RBBDC
VBB
R = 50ꢀ
T(SE)
IN-
Line End Termination
ESD
Self-Biasing Network
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图7-8. Equivalent Input Circuit
SPACE
VCC
VCC
48 kꢀ
ESD
IN
ESD
48 kꢀ
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图7-9. 3-Level Input Biasing Network
图7-10. Two –Wire Serial Interface Data Transfer
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图7-11. Two –Wire Serial Interface Timing Diagram
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8 Detailed Description
8.1 Overview
The SN65DP141 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for
use up to 12 Gbps. The characteristics of this device make it transparent to DisplayPort (DP) link training. It
supports all the available DP bit rates from RBR to UHBR10 (1.6 Gbps, 2.7 Gbps, 5.4 Gbps, 8.1 Gbps, and 10.0
Gbps respectively). Additionally, the SN65DP141 is configurable to a trace or cable mode, and hence improves
its performance depending on the type of channel it is being used. Its transparency to the DP link training makes
the SN65DP141 a position independent device, suitable for source/sink or cable applications, effectively
providing a negative loss component to the overall link budget, in order to compensate the signal degradation
over the channel.
The SN65DP141 is configurable by means of I2C and GPIOs, allowing independent channel control for
activation, equalization, gain, and dynamic range.
8.2 Functional Block Diagram
VCC
GND
VBB
VCC
Input Buffer with
Selectable Equalizer
50 ꢀ
50 ꢀ
50 ꢀ
50 ꢀ
Output Driver
IN[3:0]_P
IN[3:0]_N
OUT[3:0]_P
OUT[3:0]_P
Band-Gap Voltage
Reference and Bias
Current Generation
Power-OnReset
Power-On
Reset
1.2Kꢀ
200Kꢀ
200Kꢀ
6 Bit Register
General Setting
DRV_PK#/SCL
DRV_PK#/SCL
EQ Control
3 Bit Register
4 Bit Register
1 Bit Register
1 Bit Register
Channel Enable
VOD Swing
DC Gain
SDA
2 Bit Register
AC Gain
SDA
I2C_EN
I2C_EN
PWD#
EQ0/ADD0
PWD#
EQ0/ADD0
EQ1/ADD1
VOD/CS
GAIN
VOD/CS
GAIN
EQ1/ADD1
EQ_MODE/ADD2
2-Wire Interface and Control Logic
EQ_MODE/ADD2
200Kꢀ
200Kꢀ
200Kꢀ
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8.3 Feature Description
8.3.1 DC and AC Independent Gain Control
Besides the functional block diagram, the behavior of the SN65DP141 can be described as it is shown in 图 8-1;
where the input stage first applies a DC gain (0 dB or –6 dB) and then equalizes the signal, which is driven to
the output stage where the SN65DP141 applies an output DC gain (0 dB or 6 dB).
RX_GAIN(EQ_DC_GAIN)
TX_GAIN(TX_DC_GAIN)
EQUALIZATION(EQ_AC_GAIN)
INx_P
INx_N
OUTx_P
OUTx_N
Up to 15dB
0dB or -6dB
0dB or 6dB
图8-1. DP141 Signal Chain Gain Control
8.3.2 Two-Wire Serial Interface and Control Logic
The SN65DP141 uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCL, are
driven, respectively, by the serial data and serial clock from a microcontroller, for example. The SDA and SCK
pins require external 10 kΩ pull-ups to VCC.
The 2-wire interface allows write access to the internal memory map to modify control registers and read access
to read out control and status signals. The SN65DP141 is a slave device only which means that it cannot initiate
a transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The
master device provides the clock signal as well as the START and STOP commands. The protocol for a data
transmission is as follows:
1. START command
2. 7 bit slave address (0000ADD [2:0]) followed by an eighth bit which is the data direction bit (R/W). A zero
indicates a WRITE and a 1 indicates a READ. The ADD [2:0] address bits change with the status of the
ADD2, ADD1, and ADD0 device pins, respectively. If the pins are left floating or pulled down, the 7 bit slave
address is 0000000.
3. 8-bit register address
4. 8-bit register data word
5. STOP command
Regarding timing, the SN65DP141 is I2C compatible. The typical timing is shown in 图 7-11 and a complete data
transfer is shown in 图 7-10. Parameters for these figures are defined in the I2C Interface section of the
Switching Characteristics.
8.3.3 Bus Idle
Both SDA and SCL lines remain HIGH
8.3.4 Start Data Transfer
A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START
condition (S). Each data transfer is initiated with a START condition.
8.3.5 Stop Data Transfer
A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition
(P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate
on the bus, it can generate a repeated START condition and address another slave without first generating a
STOP condition.
8.3.6 Data Transfer
The number of data bytes transferred between a START and a STOP condition is not limited and is determined
by the master device. The receiver acknowledges the transfer of data.
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8.3.7 Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the
SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and
hold times must be taken into account. When a slave-receiver doesn’t acknowledge the slave address, the
data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If
the slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any
more data bytes, the master must abort the transfer. This is indicated by the slave generating the not
acknowledge on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP
condition.
8.4 Device Functional Modes
8.4.1 TRACE and CABLE Equalization Modes
The SN65DP141 is optimized for both trace and cable application at its input. The device pin EQ_MODE sets
the EQ gain curve profile suitable for these two use cases.
8.4.2 Control Modes
The SN65DP141 features two control modes: GPIO and I2C, and the selection between these two modes is by
means of the I2C_EN terminal, which activates the GPIO when tied to LOW; otherwise, the I2C mode is active
due to its internal pull-up resistance.
8.4.3 GPIO MODE
Device Pins RX_GAIN, EQ1 and EQ0 determines receiver DC and AC gain as shown in 表8-1 and 表8-2.
表8-1. EQ Pin Settings
EQ1
GND
GND
GND
HiZ
EQ0
GND
HiZ
EQ Setting
000
000
VCC
GND
HiZ
001
010
HiZ
011
HiZ
VCC
GND
HiZ
100
VCC
VCC
VCC
101
110
VCC
111
表8-2. RX DC and AC GAIN Settings
EQ Configuration
EQ Gain
EQ Setting
000 - 111
000 - 111
000 - 111
RX_GAIN
LOW
EQ_DC_GAIN (dB)
EQ_AC_GAIN (dB)
1 - 9
7 - 17
1 - 9
–6
–6
0
HiZ
HIGH
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8.4.4 I2C Mode
表8-3. I2C Control Settings Description for RX DC and AC GAIN
EQ_MODE
EQ_DC GAIN
RX_GAIN<1:0>
EQ_Setting<2:0>
000 to 111
000 to 111
000 to 111
000 to 111
000 to 111
000 to 111
000 to 111
000 to 111
DC GAIN (dB)
AC GAIN (dB)
APPLICATION
00
11
01
11
00
11
01
11
1 to 9
Short Input Cable; Large Input Swing
Long Input Cable; Large Input Swing
Short Input Cable; Small Input Swing
Short Input Cable, Small Input Swing
Short Input Trace; Large Input Swing
Long Input Trace; Large Input Swing
Short Input Trace; Small Input Swing
Short Input Trace, Small Input Swing
–6
–6
0
0
7 to 17
1 to 9
0
1
0
1
0
2 to 10
1 to 9
–6
–6
0
7 to 17
1 to 9
1
0
2 to 10
8.5 Register Maps
8.5.1 Register 0x00 (General Device Settings) (offset = 00000000) [reset = 00000000]
图8-2. Register 0x00 (General Device Settings)
7
6
5
4
3
2
1
0
SW_GPIO
R/W
PWRDOWN
R/W
SYNC_01
R/W
SYNC_23
R/W
SYNC_ALL
R/W
EQ_MODE
R/W
RSVD
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-4. Register 0x00 (General Device Settings)
Bit
7
Field
Type
Reset
Description
SW_GPIO
R/W
0
Switching logic is controlled by GPIO or I2C:
0 = I2C control
1 = GPIO control
6
PWRDOWN
SYNC_01
R/W
R/W
R/W
R/W
0
0
0
0
Power down the device:
0 = Normal operation
1 = Powerdown
5
4
3
All settings from channel 1 will be used for channel 0 and 1:
0 = Channel 0 tracking channel 1 settings
1 = No tracking tracking
SYNC_ 23
SYNC_ALL
All settings from channel 2 will be used for channel 2 and 3:
0 = Channel 3 tracking channel 2 settings
1 = No channel tracking
All settings from channel 1 will be used on all channels:
0 = All channels tracking channel 1
1 = No channel tracking
Overwrites SYNC_01 and SYNC_23
2
EQ_MODE
RSVD
R/W
0
Set EQ mode:
0 = Cable mode
1 = Trace mode
1
0
R/W
R/W
0
0
For TI use only
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8.5.2 Register 0x01 (Channel Enable) (offset = 00000000) [reset = 00000000]
图8-3. Register 0x01 (Channel Enable)
7
6
5
4
3
2
1
0
LN_EN_CH3
R/W
LN_EN_CH2
R/W
LN_EN_CH1
R/W
LN_EN_CH0
R/W
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-5. Register 0x01 (Channel Enable)
Bit
7
Field
Type
Reset
Description
R
0
0
0
0
0
6
R
5
R
4
R
3
LN_EN_CH3
LN_EN_CH2
LN_EN_CH1
LN_EN_CH0
R/W
Channel 3 enable:
0 = Enable
1 = Disable
2
1
0
R/W
R/W
R/W
0
0
0
Channel 3 enable:
0 = Enable
1 = Disable
Channel 1 enable:
0 = Enable
1 = Disable
Channel 0 enable:
0 = Enable
1 = Disable
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8.5.3 Register 0x02 (Channel 0 Control Settings) (offset = 00000000) [reset = 00000000]
图8-4. Register 0x02 (Channel 0 Control Settings)
7
6
5
4
3
2
1
0
RSVD
R/W
EQ Setting<2> EQ Setting<1> EQ Setting<0>
R/W R/W R/W
TX_GAIN
R/W
EQ_DC_GAIN
R/W
RX_GAIN<1>
R/W
RX_GAIN<0>
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-6. Register 0x02 (Channel 0 Control Settings)
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
Reset
Description
RSVD
0
0
0
0
0
6
EQ Setting<2>
EQ Setting<1>
EQ Setting<0>
TX GAIN
Equalizer adjustment setting:
000 = Minimum equalization setting
111 = Maximum equalization setting
5
4
3
Channel [0] TX_DC_GAIN control:
0 = Set 0 dB DC gain for transmitter
1 = Set 6 dB DC gain for transmitter
2
EQ_DC_GAIN
R/W
0
Channel [0] EQ DC gain:
0 = Set EQ DC gain to -6 dB
1 = Set EQ DC gain to -0 dB
1
0
RX_GAIN<1>
RX_GAIN<0>
R/W
R/W
0
0
Equivalent to RX_GAIN control pin for channel [0].
00: RX_GAIN = Low
01: RX_GAIN = HiZ
11: RX_GAIN = High
8.5.4 Register 0x03 (Channel 0 Enable Settings) (offset = 00000000) [reset = 00000000]
图8-5. Register 0x03 (Channel 0 Enable Settings)
7
6
5
4
3
2
1
0
DRV_PEAK
R/W
EQ_EN
R/W
DRV_EN
R/W
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-7. Register 0x03 (Channel 0 Enable Settings)
Bit
7
Field
Type
Reset
Description
R
0
0
0
0
0
0
6
R
5
R
4
R
3
R
2
DRV_PEAK
EQ_EN
R/W
Channel [0] driver peaking:
0 = Disables driver Peaking
1 = Enables driver 6 db AC Peaking"
1
0
R/W
R/W
0
0
Channel [0] EQ stage enable:
0 = Enable
1 = Disable
RSVDRV_EN
Channel [0] driver stage enable:
0 = Enable
1 = Disable
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8.5.5 Register 0x05 (Channel 1 Control Settings) (offset = 00000000) [reset = 00000000]
图8-6. Register 0x05 (Channel 1 Control Settings)
7
6
5
4
3
2
1
0
RSVD
R/W
EQ Setting<2> EQ Setting<1> EQ Setting<0>
R/W R/W R/W
TX_GAIN
R/W
EQ_DC_GAIN
R/W
RX_GAIN<1>
R/W
RX_GAIN<0>
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-8. Register 0x05 (Channel 1 Control Settings)
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
Reset
Description
RSVD
0
0
0
0
0
6
EQ Setting<2>
EQ Setting<1>
EQ Setting<0>
TX_GAIN
Equalizer adjustment setting:
000 = Minimum equalization setting
111 = Maximum equalization setting
5
4
3
Channel [1] TX_DC_GAIN control:
0 = Set 0 dB DC gain for transmitter
1 = Set 6 dB DC gain for transmitter
2
EQ_DC_GAIN
R/W
0
Channel [1] EQ DC gain:
0 = Set EQ DC gain to -6 dB
1 = Set EQ DC gain to -0 dB
1
0
RX_GAIN<1>
RX_GAIN<0>
R/W
R/W
0
0
Equivalent to RX_GAIN control pin for channel [1].
00: RX_GAIN = Low
01: RX_GAIN = HiZ
11: RX_GAIN = High
8.5.6 Register 0x06 (Channel 1 Enable Settings) (offset = 00000000) [reset = 00000000]
图8-7. Register 0x06 (Channel 1 Enable Settings)
7
6
5
4
3
2
1
0
DRV_PEAK
R/W
EQ_EN
R/W
DRV_EN
R/W
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-9. Register 0x06 (Channel 1 Enable Settings)
Bit
7
Field
Type
Reset
Description
R
0
0
0
0
0
0
6
R
5
R
4
R
3
R
2
DRV_PEAK
EQ_EN
R/W
Channel [1] driver peaking:
0 = Disables driver Peaking
1 = Enables driver 6 db AC Peaking
1
0
R/W
R/W
0
0
Channel [1] EQ stage enable:
0 = Enable
1 = Disable
DRV_EN
Channel [1] driver stage enable:
0 = Enable
1 = Disable
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8.5.7 Register 0x08 (Channel 2 Control Settings) (offset = 00000000) [reset = 00000000]
图8-8. Register 0x08 (Channel 2 Control Settings)
7
6
5
4
3
2
1
0
RSVD
R/W
EQ Setting<2> EQ Setting<1> EQ Setting<0>
R/W R/W R/W
TX_GAIN
R/W
EQ_DC_GAIN
R/W
RX_GAIN<1>
R/W
RX_GAIN<0>
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-10. Register 0x08 (Channel 2 Control Settings)
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
Reset
Description
RSVD
0
0
0
0
0
6
EQ Setting<2>
EQ Setting<1>
EQ Setting<0>
TX_GAIN
Equalizer adjustment setting:
000 = Minimum equalization setting
111 = Maximum equalization setting
5
4
3
Channel [2] TX_DC_GAIN control:
0 = Set 0 dB DC gain for transmitter
1 = Set 6 dB DC gain for transmitter
2
EQ_DC_GAIN
R/W
0
Channel [2] EQ DC gain:
0 = Set EQ DC gain to -6 dB
1 = Set EQ DC gain to -0 dB
1
0
RX_GAIN<1>
RX_GAIN<0>
R/W
R/W
0
0
Equivalent to RX_GAIN control pin for channel [2].
00: RX_GAIN = Low
01: RX_GAIN = HiZ
11: RX_GAIN = High
8.5.8 Register 0x09 (Channel 2 Enable Settings) (offset = 00000000) [reset = 00000000]
图8-9. Register 0x09 (Channel 2 Enable Settings)
7
6
5
4
3
2
1
0
DRV_PEAK
R/W
EQ_EN
R/W
DRV_EN
R/W
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-11. Register 0x09 (Channel 2 Enable Settings)
Bit
7
Field
Type
Reset
Description
R
0
0
0
0
0
0
6
R
5
R
4
R
3
R
2
DRV_PEAK
EQ_EN
R/W
Channel [2] driver peaking:
0 = Disables driver Peaking
1 = Enables driver 6 db AC Peaking
1
0
R/W
R/W
0
0
Channel [2] driver stage enable:
0 = Enable
1 = Disable
DRV_EN
Channel [2] driver stage enable:
0 = Enable
1 = Disable
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8.5.9 Register 0x0B (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
图8-10. Register 0x0B (Channel 3 Control Settings)
7
6
5
4
3
2
1
0
RSVD
R/W
EQ Setting<2> EQ Setting<1> EQ Setting<0>
R/W R/W R/W
TX_GAIN
R/W
EQ_DC_GAIN
R/W
RX_GAIN<1>
R/W
RX_GAIN<0>
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-12. Register 0x0B (Channel 3 Control Settings)
Bit
7
Field
Type
R/W
R/W
R/W
R/W
R/W
Reset
Description
RSVD
0
0
0
0
0
6
EQ Setting<2>
EQ Setting<1>
EQ Setting<0>
TX_GAIN
Equalizer adjustment setting:
000 = Minimum equalization setting
111 = Maximum equalization setting
5
4
3
Channel [3] TX_DC_GAIN control:
0 = Set 0 dB DC gain for transmitter
1 = Set 6 dB DC gain for transmitter
2
EQ_DC_GAIN
R/W
0
Channel [3] EQ DC gain:
0 = Set EQ DC gain to -6 dB
1 = Set EQ DC gain to -0 dB
1
0
RX_GAIN<1>
RX_GAIN<0>
R/W
R/W
0
0
Equivalent to RX_GAIN control pin for channel [3].
00: RX_GAIN = Low
01: RX_GAIN = HiZ
11: RX_GAIN = High
8.5.10 Register 0x0C (Channel 3 Control Settings) (offset = 00000000) [reset = 00000000]
图8-11. Register 0x0C (Channel 3 Enable Settings)
7
6
5
4
3
2
1
0
DRV_PEAK
R/W
EQ_EN
R/W
DRV_EN
R/W
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表8-13. Register 0x0C (Channel 3 Enable Settings)
Bit
7
Field
Type
Reset
Description
R
0
0
0
0
0
0
6
R
5
R
4
R
3
R
2
DRV_PEAK
EQ_EN
R/W
Channel [3] driver peaking:
0 = Disables driver Peaking
1 = Enables driver 6db AC Peaking
1
0
R/W
R/W
0
0
Channel [3] EQ stage enable:
0 = Enable
1 = Disable
RSVDRV_EN
Channel [3] driver stage enable:
0 = Enable
1 = Disable
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The SN65DP141 can be used in Source, Sink, cable, and dongle applications, where the device is transparent
to the DisplayPort link layer. For illustrating purposes, this section shows the implementation of a DisplayPort
dongle, 图 9-1 shows an example of the SN65DP141 on a dongle board, where the AUX channel is directly
connected from source to sink, meanwhile the power can be provided either way from the DP source or an
external power source.
9.2 Typical Application
3P3V
POWER SOURCE
DP SOURCE
DP SINK
ML0_IN
ML1_IN
ML2_IN
ML3_IN
ML0_OUT
ML1_OUT
ML2_OUT
ML3_OUT
DP141
3P3V
AUX
HPD
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图9-1. SN65DP141 Application Diagram
9.2.1 Design Requirements
The SN65DP141 can be designed into many types of applications. All applications have certain requirements for
the system to work properly. The voltage rails are required to support the lowest possible power consumption.
Configure the device by using I2C. The GPIO configuration is provided as I2C is not available in all cases.
Because sources may have different naming conventions, confirm the link between source and sink is correctly
mapped through the SN65DP141.
表9-1. Design Parameters
PARAMETER
Operating data rate
Supply voltage
VALUE
UHBR10 (10 Gbps)
3.3 V
Main link input voltage
Control pin Low
VID = 75 mVpp to 1.2 Vpp
1 KΩ pulled to GND
No Connect
Control pin Mid
Control pin Low
1 KΩ pulled to High
75 to 200 nF, recommend 100 nF
Main link AC decoupling capacitor
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First approach for GAIN configuration: It is highly recommend that DC GAIN be set to 1, this leads the output to
preserve the input amplitude (GAIN = 1):
• For GPIO implementation: Use a pull-up resistor on the GAIN terminal (pin 36), refer to the schematic in 图
9-2.
• For I2C implementation: write a 1 to the bit 2 of the registers 0x02, 0x05, 0x08 and 0x0B. Refer to 节8.3.2 for
a detailed description of the I2C interface
9.2.2 Detailed Design Procedure
Designing in the SN65DP141 requires the following:
• Determine the loss profile on the DP input and output channels and cables.
• Based upon the loss profile and signal swing, determine the optimal configuration for the SN65DP141, to
pass electrical compliance (Equalization mode, EQ Gain, DC gain, and AC Gain).
• See 图9-2 for information on using the AC coupling capacitors and control pin resistors, as well as for
recommended decouple capacitors from VCC pins to ground.
• Configure the TheSN65DP141 using the GPIO terminals or the I2C interface:
– GPIO –Using the terminals EQ_MODE, EQ1, EQ1, and gain.
– I2C –Refer to the I2C Register Maps and the Two-Wire Serial Interface and Control Logic sections for a
detailed configuration procedures.
• The thermal pad must be connected to ground.
3P3V
Place near DP141
C1
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
C8
0.1uF
C9
0.1uF
C10
0.1uF
C11
0.1uF
BOARD_3P3V
10uF
0.1uF
3P3V
LP1
LP2
FB1
220
@
100MHZ
Connecting to DP Receiver
U1
0201
0.1uF
0201
0.1uF
SNK_DP_ML0P
SNK_DP_ML0N
C12
C14
C13
C16
SRC_DP_ML0P
SRC_DP_ML0N
SNK_DP_ML0P
SNK_DP_ML0N
141_DP_IN0P
141_DP_IN0N
141_DP_OUT0P
141_DP_OUT0N
0.1uF
0201
0201
0.1uF
1
2
31
30
0.1uF
0201
0201
0.1uF
IN0_P
IN0_N
OUT0_P
OUT0_N
141_DP_IN1P
141_DP_IN1N
141_DP_OUT1P
141_DP_OUT1N
SNK_DP_ML1P
SNK_DP_ML1N
C15
C18
4
5
28
27
C17
C19
SRC_DP_ML1P
SRC_DP_ML1N
SNK_DP_ML1P
SNK_DP_ML1N
IN1_P
IN1_N
OUT1_P
OUT1_N
0.1uF
0201
0201
0.1uF
0.1uF
0201
0201
0.1uF
141_DP_IN2P
141_DP_IN2N
141_DP_OUT2P
141_DP_OUT2N
8
9
24
23
IN2_P
IN2_N
OUT2_P
OUT2_N
SNK_DP_ML2P
SNK_DP_ML2N
C20
C22
C21
C23
SRC_DP_ML2P
SRC_DP_ML2N
SNK_DP_ML2P
SNK_DP_ML2N
141_DP_IN3P
141_DP_IN3N
141_DP_OUT3P
141_DP_OUT3N
11
12
21
20
IN3_P
IN3_N
OUT3_P
OUT3_N
0.1uF
0201
0201
0.1uF
0.1uF
0201
0201
0.1uF
SDA
14
15
16
17
BOARD_3P3V
SDA
DRV_PK#/SCL
I2C_EN
VOD/CS
SNK_DP_ML3P
SNK_DP_ML3N
C24
C26
C25
C27
SRC_DP_ML3P
SRC_DP_ML3N
SNK_DP_ML3P
SNK_DP_ML3N
DRV_PK#/SCL
I2C_EN
VOD/CS
18
REXT
0.1uF
0201
0.1uF
0201
R1
R10
1K
EQ0/ADD0
EQ1/ADD1
EQ_MODE/ADD2
33
34
35
36
EQ0/ADD0
EQ1/ADD1
EQ_MODE/ADD2
GAIN
37
39
PWD#
1.2K
PWD#
PwPd
NOTE: ALL DIFF PAIRS ARE
ROUTEDTO 90 OHMS
DIFFERENTIAL AND 50 OHMS
COMMON MODE. ALL OTHER
TRACES ARE 50 OHM.
NOTE:Min of 15 Vias
recommended for GND Pad
connection
DP141
3P3V
3P3V
BOARD_3P3V
BOARD_3P3V
BOARD_3P3V
BOARD_3P3V
BOARD_3P3V
BOARD_3P3V
R3
1K
R4
DNI, 1K
R5
DNI, 1K
R6
DNI, 1K
R7
DNI, 1K
R8
DNI, 1K
R9
DNI, 1K
R2
1K
SILKSCREEN:
J0
J1
J2
1
2
3
J3
J4
1
2
3
J5
1
2
3
J6
1
2
3
1
2
3
1
2
3
1
2
3
EN
SDA
DRV_PK#/SCL
I2C_EN
EQ_MODE/ADD2
VOD/CS
EQ0/ADD0
EQ1/ADD1
PWD#
1
4
3
Device disable/I2C Reset if asserted low
HDR3X1
M
.1
HDR3X1
R11
DNI, 1K
M
.1
HDR3X1
M
.1
HDR3X1
R13
DNI, 1K
M
.1
HDR3X1
R14
DNI, 1K
M
.1
HDR3X1
R15
DNI, 1K
M
.1
HDR3X1
R16
DNI, 1K
M .1
SW1
B3SN-3012
R12
DNI, 1K
2
C28
1uF
BOARD_3P3V
R18
0R
Value of the cap to vary
depending on power rail
ramp-up time
5V
R28
175K
BOARD_3P3V
5V
J13
VBUS Shield1
1
2
3
4
5
6
7
8
9
10
11
L1
U2
J8
D-
D+
ID
Shield2
Shield3
Shield4
8
1
3
2
7
VIN
SW
DRV_PK#/SCL
SDA
1
3
5
7
9
2
4
6
8
10
1uH
GND Shield5
Shield6
EN
J12
C29
1
2
3
5
4
MODE
GND
VOS
FB
USB2_micAB_Recept
DP_PWR
DP_PWR_SRC
10uF
C30
22uF
HDR3X1
M .1
Header 5x2 0.1" Shroud RA thru-hole
TPS62082DSGT
图9-2. SN65DP141 Application Schematic
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9.2.3 Application Curves
0.25
0
−5
3 meter
6 meter
6 meter (See Note A)
3 meter
6 meter
6 meter (See Note A)
0.2
0.15
0.1
−10
−15
−20
−25
−30
−35
−40
−45
0.05
0
0
200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
Time (ps)
0
2
4 6
Frequency (GHz)
8
10
G006
G007
With SN65DP141 -> EQ = 4, VOD = High, ACGain = HiZ,
DCGain = Low
With SN65DP141 -> EQ = 4, VOD = High, ACGain = HiZ,
DCGain = Low
图9-3. Cable Mode –Symbol Response
图9-4. Cable Mode –Frequency Domain
0.35
0
3 meter
6 meter
3 meter
6 meter
6 meter (See Note A)
−5
−10
6 meter (See Note A)
0.3
0.25
0.2
0.15
0.1
0.05
0
−15
−20
−25
−30
−35
−40
−45
−50
0
200 400 600 800 1k
Time (ps)
1k
1k
2k
2k
2k
0
2
4
Frequency (GHz)
6
8
10
G008
G009
With SN65DP141 -> EQ = 7, VOD = High, ACGain = High,
DCGain = Low
With SN65DP141 -> EQ = 7, VOD = High, ACGain = High,
DCGain = Low
图9-5. Trace Mode –Symbol Response
图9-6. Trace Mode –Frequency Domain
10 Power Supply Recommendations
To minimize the power supply noise floor, provide good decoupling near the SN65DP141 power pins. It is
recommended to place one 0.01-μF ceramic capacitor at each power pin, and two 0.1-μF ceramic capacitors
on each power node. The distance between the SN65DP141 and capacitors should be minimized to reduce loop
inductance and provide optimal noise filtering. Placing the capacitor underneath the SN65DP141 on the bottom
of the PCB is often a good choice. A 100-pF ceramic capacitor can be put at each power pin to optimize the EMI
performance.
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11 Layout
11.1 Layout Guidelines
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
• If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also
the power and ground plane of each power system can be placed closer together, thus increasing the high
frequency bypass capacitance significantly.
• The control pin pull-up and pull-down resistors are shown in application section for reference. If a high level is
needed then only uses the pull up. If a low level is needed only use the pull down.
• Place passive components within the signal path, such as source-matching resistors or ac-coupling
capacitors, next to each other. Routing as in case a) creates wider trace spacing than in b); the resulting
discontinuity, however, is limited to a far narrower area.
• When routing traces next to a via or between an array of vias, make sure that the via clearance section does
not interrupt the path of the return current on the ground plane below.
• Avoid metal layers and traces underneath or between the pads off the DisplayPort connectors for better
impedance matching. Otherwise they will cause the differential impedance to drop below 75 Ω and fail the
board during TDR testing.
• Use solid power and ground planes for 100 Ω impedance control and minimum power noise.
• For a multi-layer PCB, it is recommended to keep one common GND layer underneath the device and
connect all ground terminals directly to this plane. For 100 Ω differential impedance, use the smallest trace
spacing possible, which is usually specified by the PCB vendor.
• Keep the trace length as short as possible to minimize attenuation.
• Place bulk capacitors (that is, 10 μF) close to power sources, such as voltage regulators or where the power
is supplied to the PCB.
Layer 1:DP Signal layer
5 to 10 mils
Layer 2: Ground plane
20 to 40 mils
Layer 3: Power plane
5 to 10 mils
Layer 4: Control signal layer
图11-1. PCB Stack
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11.2 Layout Example
图11-2. Example Layout (Top)
图11-3. Example Layout (Top)
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65DP141RLJR
SN65DP141RLJT
ACTIVE
ACTIVE
WQFN
WQFN
RLJ
RLJ
38
38
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
DP141
DP141
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65DP141RLJR
SN65DP141RLJT
WQFN
WQFN
RLJ
RLJ
38
38
3000
250
330.0
330.0
16.4
16.4
5.25
5.25
7.25
7.25
1.45
1.45
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65DP141RLJR
SN65DP141RLJT
WQFN
WQFN
RLJ
RLJ
38
38
3000
250
367.0
367.0
367.0
367.0
38.0
38.0
Pack Materials-Page 2
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