SN6505BDBVT [TI]
适用于隔离电源的低噪声、1A、420kHz 变压器驱动器 | DBV | 6 | -55 to 125;
| 型号： | SN6505BDBVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于隔离电源的低噪声、1A、420kHz 变压器驱动器 | DBV | 6 | -55 to 125 变压器 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总38页 (文件大小：1359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN6505A, SN6505B
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
适用于隔离式电源的 SN6505 低噪声 1A 变压器驱动器
1 特性
3 说明
1
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用于变压器的推挽式驱动器
SN6505 是一款低噪声、低 EMI、推挽式变压器驱动
器，专为小型隔离式电源而设计。该器件通过 2.25V
至 5V 的直流电源来驱动薄型、中间抽头的变压器。
通过输出开关电压的转换速率控制和扩频时钟 (SSC)
可实现超低噪声和 EMI。SN6505 包含一个振荡器，之
后是一个栅极驱动器电路，此电路提供补偿输出信号以
驱动接地参考 N 通道电源开关。该器件包含两个 1A
电源 MOSFET 开关，确保在重负载条件下正常启动。
开关时钟也可由外部提供，这样可确保准确定位开关谐
波或者与多个互感器驱动器搭配使用。内部保护 功能
包括一个 1.7A 的电流限制、欠压锁定、热关断且先断
后通型电路。SN6505 具有软启动特性，可防止大负载
电容器在上电过程中出现高浪涌电流。SN6505 可采用
小型 6 引脚 SOT23/DBV 封装。该器件的运行温度范
围为 –55°C 至 125°C。
宽输入电压范围：2.25V 至 5.5V
高输出驱动：5V 电源时为 1A
低 RON，4.5V 电源时的最大值为 0.25Ω
超低 EMI
扩频时钟
精密内部振荡器选项：160kHz (SN6505A) 和
420kHz（SN6505B）
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通过外部时钟输入同步多个器件
转换率控制
1.7A 限流
低关断电流：< 1μA
热关断
宽温度范围：–55°C 至 125°C
小型 6 引脚 SOT23 (DBV) 封装
具有软启动，可减小浪涌电流
器件信息(1)
器件型号
SN6505A
SN6505B
封装
封装尺寸（标称值）
2 应用
•
用于控制器局域网 (CAN)、RS-485、RS-422、
SOT23（6 引脚）
2.90mm × 1.60mm
RS-232、串行外设接口 (SPI)、I2C、低功耗局域
网 (LAN) 的隔离电源
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
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低噪声隔离式 USB 电源
过程控制
电信电源
无线电电源
分布式电源
医疗仪器
精密仪器
低噪声灯丝电源
简化原理图
SN6505
GND
VOUT
4
3
2
1
D2
VCC
Enable
5
6
EN
V
CC
Ext Clock
CLK
D1
10µF 0.1µF
10µF
Copyright © 2016, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEP9
SN6505A, SN6505B
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 18
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application .................................................. 20
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 7
6.7 Typical Characteristics, SN6505A ............................ 8
6.8 Typical Characteristics, SN6505B .......................... 10
Parameter Measurement Information ................ 14
Detailed Description ............................................ 16
8.1 Overview ................................................................. 16
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
9
10 Power Supply Recommendations ..................... 28
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
12 器件和文档支持 ..................................................... 29
12.1 器件支持................................................................ 29
12.2 文档支持................................................................ 29
12.3 相关链接................................................................ 29
12.4 接收文档更新通知 ................................................. 29
12.5 社区资源................................................................ 29
12.6 商标....................................................................... 29
12.7 静电放电警告......................................................... 29
12.8 术语表 ................................................................... 29
13 机械、封装和可订购信息....................................... 30
7
8
4 修订历史记录
Changes from Revision F (September 2016) to Revision G
Page
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•
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通篇进行了编辑性更正和修改 ................................................................................................................................................ 1
Added Soft-Start description in Device Functional Modes section ...................................................................................... 18
Changed 3 V to 2.25 V in the description of Drive Capability section ................................................................................. 20
Changed Schottky diode RB168M-40 to RB168MM-40 in Diode Selection section ............................................................ 21
Changed fmin to 138 kHz for SN6505A and 363 kHz for SN6505B in V-t Product Calculation section and updated
Equation 4............................................................................................................................................................................. 22
•
Changed load current, VDO-max, VO-max, RDS-max and ID-max values and updated Equation 11 in Turns Ratio Estimate
Example ............................................................................................................................................................................... 23
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•
•
Changed LDO from 'No' to 'Yes' for transformer ORDER NO. 750313638 and 750313626 in Table 3 .............................. 25
Updated Figure 48................................................................................................................................................................ 26
已更改 静电放电注意事项声明.............................................................................................................................................. 29
Changes from Revision E (August 2016) to Revision F
Page
•
Changed text From: "connected as possible" To: "connected as close as possible" in Power Supply Recommendations 28
Changes from Revision D (August 2016) to Revision E
Page
•
Changed Table 3, and added Note 1 ................................................................................................................................... 25
Changes from Revision C (August 2016) to Revision D
Page
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•
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•
Typical Characteristics, SN6505A, added Figure 1 and Figure 2 back into the datasheet ................................................... 8
Typical Characteristics, SN6505A, added Figure 9 to Figure 33 back into the datasheet .................................................... 8
Typical Characteristics, SN6505B, added Figure 11 and Figure 12 back into the datasheet ............................................. 10
Typical Characteristics, SN6505B, added Figure 31 and Figure 32 back into the datasheet ............................................. 12
2
版权 © 2015–2018, Texas Instruments Incorporated
SN6505A, SN6505B
www.ti.com.cn
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
•
Changed Table 3 .................................................................................................................................................................. 25
Changes from Revision B (February 2016) to Revision C
Page
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•
•
Changed the Typical Characteristics, SN6505A section........................................................................................................ 8
Added the Typical Characteristics, SN6505B section .......................................................................................................... 10
Changed Table 3 .................................................................................................................................................................. 25
Changes from Revision A (October 2015) to Revision B
Page
•
Changed the Thermal Information table From: 16 Pin DW (SOIC) To: 6 Pin DBV (SOT-23) ............................................... 5
Changes from Original (September 2015) to Revision A
Page
•
量产发布 ................................................................................................................................................................................. 1
Copyright © 2015–2018, Texas Instruments Incorporated
3
SN6505A, SN6505B
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
5 Pin Configuration and Functions
DBV Package
SOT-23 (6 Pin)
Top View
6
D1
CLK
EN
1
VCC
5
4
2
3
GND
D2
Pin Functions
PIN
DESCRIPTION
NAME
NO.
TYPE
Open drain output of the first power MOSFETs. Typically connected to the outer terminals of the
center tap transformer. Because large currents flow through these pins, their external traces
should be kept short.
D1
1
O
This is the device supply pin. It should be bypassed with a 4.7 μF or greater, low ESR capacitor.
When VCC ≤ 2.25 V, an internal undervoltage lockout circuit trips and turns both outputs off.
VCC
D2
2
3
P
Open drain output of the second power MOSFETs. Typically connected to the outer terminals of
the center tap transformer. Because large currents flow through these pins, their external traces
should be kept short.
O
GND is connected to the source of the power MOSFET switches via an internal sense circuit.
Because large currents flow through it, the GND terminals must be connected to a low-inductance
quality ground plane.
GND
4
P
The EN pin turns the device on or off. Grounding or leaving this pin floating disables all internal
EN
5
6
I
I
circuitry. If unused this pin should be tied directly to VCC
.
This pin is used to run the device with external clock. Internally it is pulled down to GND. If valid
clock is not detected on this pin, the device shifts automatically to internal clock.
CLK
4
Copyright © 2015–2018, Texas Instruments Incorporated
SN6505A, SN6505B
www.ti.com.cn
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1). All typical values are at TA = 25°C, VCC = 5 V.
MIN
–0.5
–0.5
MAX
UNIT
(2)
Supply voltage
Voltage
VCC
6
VCC + 0.5(3)
16
V
EN, CLK
D1, D2
Output switch voltage
V
A
Peak output switch current I(D1)Pk, I(D2)Pk
Junction temperature, TJ
2.4
-55
150
°C
°C
Storage temperature range, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND) and are peak voltage values.
(3) Maximum voltage of 6V.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±6000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
TYP
MAX
5.5
UNIT
VCC
Supply voltage
2.25
V
2.25 V < VCC < 2.8 V
2.8 V < VCC < 5.5 V
0.75
1
ID1, ID2
TA
Output switch current - Primary side
Ambient temperature
A
–55
125
°C
6.4 Thermal Information
SN6505
DBV (SOT-23)
6 PINS
137.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
57.7
46.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
13.4
ψJB
44.9
RθJC(bottom)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2015–2018, Texas Instruments Incorporated
5
SN6505A, SN6505B
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
6.5 Electrical Characteristics
over full-range of recommended operating conditions, unless otherwise noted. All typical values are at TA = 25°C, VCC = 5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOLTAGE SUPPLY
Supply Current (2.8 V < VCC < 5.5)
(SN6505A)
RL = 50 Ω
1
1.4
mA
mA
I(Vcc)
Supply Current (2.8 V < VCC < 5.5)
(SN6505B)
RL = 50 Ω
1.56
2.3
20
IIH
Leakage Current on EN and CLK pin
VCC current for EN = 0
EN / CLK = VCC
10
µA
µA
IDIS
0.1
ILKG(D1)
ILKG(D2)
Leakage Current on D1,D2 for EN=0
Voltage of D1,D2 = VCC
0.1
µA
VCC+ (UVLO) Positive-going UVLO threshold
VCC- (UVLO) Negative-going UVLO threshold
VHYS (UVLO1) UVLO threshold hysteresis
2.25
0.7
V
V
1.7
0.3
0.3
0.2
V
VIN(ON)
VIN(OFF)
VIN(HYS)
CLK
EN, CLK pin logic high threshold
EN, CLK pin logic low threshold
EN, CLK pin threshold hysteresis
VCC
VCC
VCC
D1, D2 average switching Frequency
(SN6505A)
RL = 50 Ω to VCC; Refer to Figure 36
RL = 50 Ω to VCC; Refer to Figure 36.
138
363
100
100
160
424
203
517
Khz
kHz
kHz
kHz
FSW
D1, D2 average switching Frequency
(SN6505B)
External clock frequency on CLK pin
(SN6505A)
600
F(EXT)
External clock frequency on CLK pin
(SN6505B)
1600
OUTPUT STAGE
Average ON time mismatch between D1
and D2
DMM
RL = 50 Ω
0%
VCC = 4.5 V, ID1,ID2 = 1 A
VCC = 2.8 V, ID1,ID2 = 1 A
VCC = 2.25 V, ID1,ID2 = 0.5 A
0.16
0.19
0.21
0.25
0.31
0.45
Ω
Ω
Ω
R(ON)
Output switch on resistance
Voltage slew rates on D1 and D2 for
SN6505A
V(SLEW)
I(SLEW)
V(SLEWHF)
I(SLEWHF)
RL = 50 Ω to VCC; Refer to Figure 36
48
11
V/µs
A/µs
V/µs
A/µs
Current slew rates at D1 and D2 for
SN6505A
RL = 5 Ω through transformer;
Refer to Figure 37
Voltage slew rates on D1 and D2 for
SN6505B
RL = 50 Ω to VCC; Refer to Figure 36
152
Current slew rates at D1 and D2 for
SN6505B
RL = 5 Ω through transformer;
Refer to Figure 37
41
Current clamp limit (2.8 V < VCC < 5.5V )
Current clamp limit (2.25 V < VCC < 2.8 V)
1.42
0.65
1.75
2.15
1.85
A
A
ILIM
THERMAL SHUT DOWN
TSD+
TSD-
TSD-
TSD turn on temperature
154
135
13
168
150
17
181
166
°C
°C
°C
TSD turn off temperature
TSD hysteresis
6
Copyright © 2015–2018, Texas Instruments Incorporated
SN6505A, SN6505B
www.ti.com.cn
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
CLK
Duration after which device switches to internal clock in case of invalid external
clock
10
25
µs
tCLKTIMER
OUTPUT STAGE
Break-before-make time
Measured as voltage with RL = 50 Ω to VCC
Refer to Figure 36
,
115
90
ns
ns
(SN6505A)
tBBM
Break-before-make time
(SN6505B)
Measured as voltage with RL = 50 Ω to VCC
,
Refer to Figure 36
SOFT-START
10% to 90% transition time on VOUT With
transformer CLOAD = 40 µF
RL = 5 Ω
tSS
Soft-start time
1
4.25
8.5
8
ms
ms
From power up to 90% transition time on
VOUT With transformer CLOAD = 40 µF
RL = 5 Ω
tSSdelay
Soft-start time delay
3.5
18
Copyright © 2015–2018, Texas Instruments Incorporated
7
SN6505A, SN6505B
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
6.7 Typical Characteristics, SN6505A
6
100
90
80
70
60
50
40
30
20
10
0
5
4
3
2
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
1
25
125 225 325 425 525 625 725 825 925
Load Current (mA)
25
125 225 325 425 525 625 725 825 925
Load Current (mA)
D006
SN6505A + Wurth 750315240
SN6505A + Wurth 750315240
Figure 1. Output Voltage vs Load Current
Figure 2. Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
D028
D029
Load Current (mA)
Load Current (mA)
SN6505A + Wurth 750316031
VCC = 3.3 V
SN6505A + Wurth 750316031
VCC = 3.3 V
Figure 3. Output Voltage vs Load Current
Figure 4. Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
D030
D031
Load Current (mA)
Load Current (mA)
SN6505A + Wurth 750316032
VCC = 3.3 V
SN6505A + Wurth 750316032
VCC = 3.3 V
Figure 5. Output Voltage vs Load Current
Figure 6. Efficiency vs Load Current
8
Copyright © 2015–2018, Texas Instruments Incorporated
SN6505A, SN6505B
www.ti.com.cn
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
Typical Characteristics, SN6505A (continued)
100
90
80
70
60
50
40
30
20
10
0
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
D032
D033
Load Current (mA)
Load Current (mA)
SN6505A + Wurth 750316033
VCC = 5 V
SN6505A + Wurth 750316033
VCC = 5 V
Figure 7. Output Voltage vs Load Current
Figure 8. Efficiency vs Load Current
170
165
160
155
150
1.6
1.4
1.2
1
VCC = 2.25 V
VCC = 5.5 V
VCC = 2.25 V
VCC = 5.5 V
0.8
0.6
0.4
0.2
0
-75
-25
25
75
125
100
200
300
400
500
600
Temperature (èC)
External Frequency (kHz)
D003
D001
Figure 9. Frequency vs Free-Air Temperature
Figure 10. Current vs External Frequency
Copyright © 2015–2018, Texas Instruments Incorporated
9
SN6505A, SN6505B
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
6.8 Typical Characteristics, SN6505B
100
90
80
70
60
50
40
30
20
10
0
6
5
4
3
2
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
1
25
125 225 325 425 525 625 725 825 925
Load Current (mA)
25
125 225 325 425 525 625 725 825 925
Load Current (mA)
D007
D008
SN6505B + Wurth 750315371
SN6505B + Wurth 750315371
Figure 11. Output Voltage vs Load Current
Figure 12. Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
4
3.5
3
2.5
2
1.5
1
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
D010
D011
SN6505B + Wurth 760390011
VCC = 3.3 V
SN6505B + Wurth 760390011
VCC = 3.3 V
Figure 13. Output Voltage vs Load Current
Figure 14. Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
D012
D013
SN6505B + Wurth 760390012
VCC = 5 V
SN6505B + Wurth 760390012
VCC = 5 V
Figure 15. Output Voltage vs Load Current
Figure 16. Efficiency vs Load Current
10
Copyright © 2015–2018, Texas Instruments Incorporated
SN6505A, SN6505B
www.ti.com.cn
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
Typical Characteristics, SN6505B (continued)
100
90
80
70
60
50
40
30
20
10
0
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0
0
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
0
0
0
20
20
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
D014
D013
SN6505B + Wurth 760390013
VCC = 3.3 V
SN6505B + Wurth 760390013
VCC = 3.3 V
Figure 17. Output Voltage vs Load Current
Figure 18. Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
5
4.5
4
3.5
3
2.5
2
1.5
1
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
40
60
80 100 120 140 160 180 200
Load Current (mA)
D016
D017
SN6505B + Wurth 760390014
VCC = 3.3 V
SN6505B + Wurth 760390014
VCC = 3.3 V
Figure 19. Output Voltage vs Load Current
Figure 20. Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
40
60
80 100 120 140 160 180 200
Load Current (mA)
D018
D019
SN6505B + Wurth 760390014
VCC = 5 V
SN6505B + Wurth 760390014
VCC = 5 V
Figure 21. Output Voltage vs Load Current
Figure 22. Efficiency vs Load Current
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Typical Characteristics, SN6505B (continued)
100
90
80
70
60
50
40
30
20
10
0
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Load Current (mA)
D020
D021
SN6505B + Wurth 760390015
VCC = 3.3 V
SN6505B + Wurth 760390015
VCC = 3.3 V
Figure 23. Output Voltage vs Load Current
Figure 24. Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
D022
D021
Load Current (mA)
Load Current (mA)
SN6505B + Wurth 750316028
VCC = 3.3 V
SN6505B + Wurth 750316028
VCC = 3.3 V
Figure 25. Output Voltage vs Load Current
Figure 26. Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0
100 200 300 400 500 600 700 800 900
Load Current (mA)
0
100 200 300 400 500 600 700 800 900
Load Current (mA)
D024
D025
SN6505B + Wurth 750316029
VCC = 3.3 V
SN6505B + Wurth 750316029
VCC = 3.3 V
Figure 27. Output Voltage vs Load Current
Figure 28. Efficiency vs Load Current
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Typical Characteristics, SN6505B (continued)
100
90
80
70
60
50
40
30
20
10
0
4.5
4
3.5
3
2.5
2
1.5
1
D026
D027
Load Current (mA)
Load Current (mA)
SN6505B + Wurth 7503160030
VCC = 5 V
SN6505B + Wurth 7503160030
VCC = 5 V
Figure 29. Output Voltage vs Load Current
Figure 30. Efficiency vs Load Current
450
440
430
420
410
400
3
2.5
2
VCC = 2.25 V
VCC = 5.5 V
VCC = 2.25 V
VCC = 5.5 V
1.5
1
0.5
0
-75
-25
25
75
125
100
400
700
1000
1300
1600
Temperature (èC)
External Frequency (kHz)
D004
D002
Figure 31. Frequency vs Free-Air Temperature
Figure 32. Current vs External Frequency
Time 2.5 ms/div
Figure 33. Scope Capture of SN6505 Switching from External to Internal Clock
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7 Parameter Measurement Information
SN6505
VOUT
4
3
2
1
GND
EN
D2
VCC
Enable
5
6
V
CC
Ext Clock
CLK
D1
10µF 0.1µF
10µF
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Measurement Circuit for Unregulated Output (TP1)
Figure 35. Timing Diagram
VCC
SN6505
50ꢀ
4
3
2
1
GND
EN
D2
Enable
5
6
V
CC
50ꢀ
Ext Clock
CLK
D1
10µF
Copyright © 2016, Texas Instruments Incorporated
Figure 36. Test Circuit for FSW, V(slew), tBBM
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Parameter Measurement Information (continued)
VCC
C1
V
(Current)
SN6505
VCC
4
5
6
3
2
1
GND
D 2
Vcc
D 1
EN
CLK
Copyright © 2016, Texas Instruments Incorporated
Figure 37. I(slew) Test Setup
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8 Detailed Description
8.1 Overview
The SN6505 is a transformer driver designed for low-cost, small form-factor, isolated DC/DC converters utilizing
the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
The output frequency of the oscillator is divided down by two . A subsequent break-before-make logic inserts a
dead-time between the high-pulses of the two signals. Before either one of the gates can assume logic high, the
BBM logic ensures a short time period during which both signals are low and both transistors are high-
impedance. This short period, is required to avoid shorting out both ends of the primary. The resulting output
signals, present the gate-drive signals for the output transistors.
8.2 Functional Block Diagram
EN
D2 D1
V
CC
UVLO
TEMP
SSC
OSC
÷ 2
MOSFET
Driver
CLK
I-LIM
Ext CLK
Detect
GND GND
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Push-Pull Converter
Push-pull converters require transformers with center-taps to transfer power from the primary to the secondary
(see Figure 38).
CR
CR
1
1
V
V
OUT
OUT
C
C
R
R
L
L
V
V
IN
IN
CR
CR
2
2
Q
Q
Q
Q
1
2
1
2
Figure 38. Switching Cycles of a Push-Pull Converter
When Q1 conducts, VIN drives a current through the lower half of the primary to ground, thus creating a negative
voltage potential at the lower primary end with regards to the VIN potential at the center-tap.
At the same time the voltage across the upper half of the primary is such that the upper primary end is positive
with regards to the center-tap in order to maintain the previously established current flow through Q2, which now
has turned high-impedance. The two voltage sources, each of which equaling VIN, appear in series and cause a
voltage potential at the open end of the primary of 2×VIN with regards to ground.
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Feature Description (continued)
Per dot convention the same voltage polarities that occur at the primary also occur at the secondary. The
positive potential of the upper secondary end therefore forward biases diode CR1. The secondary current starting
from the upper secondary end flows through CR1, charges capacitor C, and returns through the load impedance
RL back to the center-tap.
When Q2 conducts, Q1 goes high-impedance and the voltage polarities at the primary and secondary reverse.
Now the lower end of the primary presents the open end with a 2×VIN potential against ground. In this case CR2
is forward biased while CR1 is reverse biased and current flows from the lower secondary end through CR2,
charging the capacitor and returning through the load to the center-tap.
8.3.2 Core Magnetization
Figure 39 shows the ideal magnetizing curve for a push-pull converter with B as the magnetic flux density and H
as the magnetic field strength. When Q1 conducts the magnetic flux is pushed from A to A’, and when Q2
conducts the flux is pulled back from A’ to A. The difference in flux and thus in flux density is proportional to the
product of the primary voltage, VP, and the time, tON, it is applied to the primary: B ≈ VP × tON
.
B
V
V
P
IN
A’
H
R
V
DS
DS
A
V
= V +V
P DS
IN
Figure 39. Core Magnetization and Self-Regulation Through Positive Temperature Coefficient of RDS(on)
This volt-seconds (V-t) product is important as it determines the core magnetization during each switching cycle.
If the V-t products of both phases are not identical, an imbalance in flux density swing results with an offset from
the origin of the B-H curve. If balance is not restored, the offset increases with each following cycle and the
transformer slowly creeps toward the saturation region.
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8.4 Device Functional Modes
The functional modes of the device are divided into start-up, operating, and off-mode.
8.4.1 Start-Up Mode
When the supply voltage at VCC ramps up to 2.25 V , the internal oscillator starts operating . The output stage
begins switching but the amplitude of the drain signals at D1 and D2 has not reached its full maximum yet.
8.4.1.1 Soft-Start
SN6505A and SN6505B devices support soft-start feature. Upon power up or when EN pin transitions from Low
to High, the gate drive of the output power-MOSFET is gradually increased over a period of time from 0 V to VCC
.
Soft-start prevents high inrush current from VCC while charging large secondary side decoupling capacitors, and
also prevents overshoot in secondary voltage during power-up.
8.4.2 Operating Mode
When the device supply has reached its nominal value ±10% the oscillator is fully operating. However variations
over supply voltage and operating temperature can vary the switching frequencies at D1 and D2.
8.4.3 Shutdown-Mode
The device has a dedicated enable pin to put the device in very low power mode to save power when not in use.
Enable pin has an internal pull down resistor which keeps device disabled when not driven. When disabled or
when VCC is < 1.7 V , both drain outputs, D1 and D2, are tri-stated.
8.4.4 Spread Spectrum Clocking
Radiated emissions is an important concern in high current switching power supplies. SN6505 addresses this by
modulating its internal clock in such a way that the emitting energy is spread over multiple frequency bins. This
Spread Spectrum clocking feature greatly improves the emissions performance of the entire power supply block
and hence relieves the system designer from one major concern in isolated power supply design.
8.4.5 External Clock Mode
The SN6505 has a CLK pin which can be used to synchronize the device with system clock and in turn with
other SN6505 devices so that the system can control the exact switching frequency of the device. The Rising
edge of the CLK is used to divide a clock by two and used to drive the gates. Figure 41 shows the timing
diagram for the same. The device also has external clock fail safe feature which automatically switches the
device to the internal clock if a valid input clock is not present for long (tCLKTIMER). The in-built emissions
reduction scheme of Spread Spectrum clocking is disabled when external clock is present.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN6505 is a transformer driver designed for low-cost, small form-factor, isolated DC/DC converters using
the push-pull topology. The device includes an oscillator that feeds a gate-drive circuit. The gate-drive,
comprising a frequency divider and a break-before-make (BBM) logic, provides two complementary output
signals which alternately turn the two output transistors on and off.
Vcc
SN6505
Q off
2
Q off
1
D2
D1
S
S
G
G
2
Q
2
Freq.
Divider
BBM
Logic
fOSC
OSC
1
Q
1
Q on
1
Q on
2
tBBM
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 40. Block Diagram and Output Timing With Break-Before-Make Action
The output frequency of the oscillator is divided down by an asynchronous divider that provides two
complementary output signals, S and S, with a 50% duty cycle. A subsequent break-before-make logic inserts a
dead-time between the high-pulses of the two signals. The resulting output signals, G1 and G2, present the gate-
drive signals for the output transistors Q1 and Q2. As shown in Figure 41, before either one of the gates can
assume logic high, there must be a short time period during which both signals are low and both transistors are
high-impedance. This short period, known as break-before-make time, is required to avoid shorting out both ends
of the primary.
Figure 41. Detailed Output Signal Waveforms
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9.2 Typical Application
VIN = 3.3V
10µF
SN6505
TPS76350
MBR0520L
VOUT
1:2.2
VOUT-REG = 5V
4
5
6
3
2
1
1
2
3
5
4
GND
EN
D2
Vcc
D1
IN
OUT
GND
EN
ENABLE
CLOCK
10µF 0.1µF
10µF
NC
CLK
MBR0520L
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as design parameters.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE VALUE
3.3 V ± 3%
5 V
Maximum load current
100 mA
9.2.2 Detailed Design Procedure
The following recommendations on components selection focus on the design of an efficient push-pull converter
with high current drive capability. Contrary to popular belief, the output voltage of the unregulated converter
output drops significantly over a wide range in load current. The characteristic curve in Figure 1 and Figure 11 for
example, shows that the difference between VOUT at minimum load and VOUT at maximum load exceeds a
transceiver’s supply range. Therefore, in order to provide a stable, load independent supply while maintaining
maximum possible efficiency the implementation of a low dropout regulator (LDO) is strongly advised.
The final converter circuit is shown in Figure 47. The measured VOUT and efficiency characteristics for the
regulated and unregulated outputs are shown in Figure 2 and Figure 12.
9.2.2.1 Drive Capability
The transformer driver is designed for low-power push-pull converters with input and output voltages in the range
of 2.25 V to 5.5 V. While converter designs with higher output voltages are possible, care must be taken that
higher turns ratios don’t lead to primary currents that exceed the specified current limits of the device.
9.2.2.2 LDO Selection
The minimum requirements for a suitable low dropout regulator are:
•
•
•
Its current drive capability should slightly exceed the specified load current of the application to prevent the
LDO from dropping out of regulation. Therefore, for a load current of 600 mA, choose a 600 mA to 750 mA
LDO. While regulators with higher drive capabilities are acceptable, they also usually possess higher dropout
voltages that will reduce overall converter efficiency.
The internal dropout voltage, VDO, at the specified load current should be as low as possible to maintain
efficiency. For a low-cost 750 mA LDO, a VDO of 600 mV at 750 mA is common. Be aware; however, that this
lower value is usually specified at room temperature and can increase by a factor of 2 over temperature,
which in turn will raise the required minimum input voltage.
The required minimum input voltage preventing the regulator from dropping out of line regulation is given with:
VI-min = VDO-max + VO-max
(1)
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This means in order to determine VI for worst-case condition, the user must take the maximum values for VDO and VO
specified in the LDO data sheet for rated output current (that is, 600 mA) and add them together. Also specify that the
output voltage of the push-pull rectifier at the specified load current is equal or higher than VI-min. If it is not, the LDO will
lose line-regulation and any variations at the input passes straight through to the output. Hence, below VI-min the output
voltage follows the input and the regulator behaves like a simple conductor.
•
The maximum regulator input voltage must be higher than the rectifier output under no-load. Under this
condition there is no secondary current reflected back to the primary, thus making the voltage drop across
RDS-on negligible and allowing the entire converter input voltage to drop across the primary. At this point, the
secondary reaches its maximum voltage of
VS-max = VIN-max × n
(2)
with VIN-max as the maximum converter input voltage and n as the transformer turns ratio. Thus to prevent the
LDO from damage the maximum regulator input voltage must be higher than VS-max. Table 2 lists the maximum
secondary voltages for various turns ratios commonly applied in push-pull converters.
Table 2. Required Maximum LDO Input Voltages for Various Push-Pull Configurations
PUSH-PULL CONVERTER
LDO
VI-max [V]
6 to 10
10
CONFIGURATION
3.3 VIN to 3.3 VOUT
3.3 VIN to 5 VOUT
5 VIN to 5 VOUT
VIN-max [V]
TURNS-RATIO
1.5 ± 3%
VS-max [V]
5.6
3.6
3.6
5.5
2.2 ± 3%
8.2
1.5 ± 3%
8.5
10
9.2.2.3 Diode Selection
A rectifier diode should always possess low-forward voltage to provide as much voltage to the converter output
as possible. When used in high-frequency switching applications, such as the SN6505 however, the diode must
also possess a short recovery time. Schottky diodes meet both requirements and are therefore strongly
recommended in push-pull converter designs. A good choice for low-volt applications and ambient temperatures
of up to 85°C is the low-cost Schottky rectifier MBR0520L with a typical forward voltage of 275 mV at 100-mA
forward current. For higher output voltages such as ±10 V and above use the MBR0530 which provides a higher
DC blocking voltage of 30 V.
Lab measurements have shown that at temperatures higher than 100°C the leakage currents of the above
Schottky diodes increase significantly. This can cause thermal runaway leading to the collapse of the rectifier
output voltage. Therefore, for ambient temperatures higher than 85°C use low-leakage Schottky diodes, such as
RB168MM-40.
1
1
TJ = 125°C
25°C
0°C
-40°C
75°C
-25°C
TJ = 100°C
25°C
75°C
0.1
0.1
0.01
0.01
0.2
0.3
0.4
0.5
0.1
0.2
0.3
0.4
0.5
Forward Voltage, VF - V
Forward Voltage, VF - V
Figure 44. Diode Forward Characteristics MBR0530
Figure 43. Diode Forward Characteristics for MBR0520L
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9.2.2.4 Capacitor Selection
The capacitors in the converter circuit in Figure 47 are multi-layer ceramic chip (MLCC) capacitors.
As with all high speed CMOS ICs, the device requires a bypass capacitor in the range of 10 nF to 100 nF.
The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fast
switching transients. For minimum ripple make this capacitor 1 μF to 10 μF. In a 2-layer PCB design with a
dedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4-
layer board design with low-inductance reference planes for ground and VIN, the capacitor can be placed at the
supply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to a
reference plane or to the primary center-tap.
The bulk capacitor at the rectifier output smooths the output voltage. Make this capacitor 1 μF to 10 μF.
The small capacitor at the regulator input is not necessarily required. However, good analog design practice
suggests, using a small value of 47 nF to 100 nF improves the regulator’s transient response and noise rejection.
The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. The
choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, in
most cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements.
9.2.2.5 Transformer Selection
9.2.2.5.1 V-t Product Calculation
To prevent a transformer from saturation its V-t product must be greater than the maximum V-t product applied
by the device. The maximum voltage delivered by the device is the nominal converter input plus 10%. The
maximum time this voltage is applied to the primary is half the period of the lowest frequency at the specified
input voltage. Therefore, the transformer’s minimum V-t product is determined through:
T
V
max
IN-max
Vt
³ V
´
=
min
IN-max
2
2 ´ f
min
(3)
Taking an example of fmin as 138 kHz for SN6505A and 363 kHZ for SN6505B with a 5 V supply, Equation 3
yields the minimum V-t products of:
5.5 V
Vtmin
³
= 20 Vμs
for SN6505A, and
2 ´ 138 kHz
5.5 V
Vtmin
³
= 7.6 Vμs for SN6505B applications.
2 ´ 363 kHz
(4)
Common V-t values for low-power center-tapped transformers range from 22 Vμs to 150 Vμs with typical
footprints of 10 mm x 12 mm. However, transformers specifically designed for PCMCIA applications provide as
little as 11 Vμs and come with a significantly reduced footprint of 6 mm x 6 mm only.
While Vt-wise all of these transformers can be driven by the device, other important factors such as isolation
voltage, transformer wattage, and turns ratio must be considered before making the final decision.
9.2.2.5.2 Turns Ratio Estimate
Assume the rectifier diodes and linear regulator has been selected. Also, it has been determined that the
transformer chosen must have a V-t product of at least 11 Vμs. However, before searching the manufacturer web
sites for a suitable transformer, the user still needs to know its minimum turns ratio that allows the push-pull
converter to operate flawlessly over the specified current and temperature range. This minimum transformation
ratio is expressed through the ratio of minimum secondary to minimum primary voltage multiplied by a correction
factor that takes the transformer’s typical efficiency of 97% into account:
VP-min = VIN-min - VDS-max
(5)
VS-min must be large enough to allow for a maximum voltage drop, VF-max, across the rectifier diode and still
provide sufficient input voltage for the regulator to remain in regulation. From the LDO Selection section, this
minimum input voltage is known and by adding VF-max gives the minimum secondary voltage with:
VS-min = VF-max + VDO-max + VO-max
(6)
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V
F
V
DO
V
V
I
O
V
R
L
S
V
V
IN
P
V
DS
R
Q
DS
Figure 45. Establishing the Required Minimum Turns Ratio Through Nmin = 1.031 × VS-min / VP-min
Then calculating the available minimum primary voltage, VP-min, involves subtracting the maximum possible drain-
source voltage of the device, VDS-max, from the minimum converter input voltage VIN-min
:
VP-min = VIN-min – VDS-max
(7)
VDS-max however, is the product of the maximum RDS(on) and ID values for a given supply specified in the data
sheet:
VDS-max = RDS-max × IDmax
(8)
Then inserting Equation 8 into Equation 7 yields:
VP-min = VIN-min - RDS-max x IDmax
(9)
and inserting Equation 9 and Equation 6 into Equation 5 provides the minimum turns ration with:
VF-max + VDO-max + VO-max
nmin = 1.031 ´
VIN-min - RDS-max ´ ID-max
(10)
Example:
For a 3.3 VIN to 5 VOUT converter using the rectifier diode MBR0520L and the 5 V LDO, the data sheet values
taken for a load current of 600 mA and a maximum temperature of 85°C are VF-max = 0.2 V,
VDO-max = 0.5 V, and VO-max = 5.1 V.
Then assuming that the converter input voltage is taken from a 3.3 V controller supply with a maximum ±2%
accuracy makes VIN-min = 3.234 V. Finally the maximum values for drain-source resistance and drain current at
3.3 V are taken from the data sheet with RDS-max = 0.31 Ω and ID-max = 1 A.
Inserting the values above into Equation 10 yields a minimum turns ratio of:
0.2 V + 0.5 V + 5.1V
nmin = 1.031 ´
= 2.05
3.234 V - 0.31 Ω ´ 1 A
(11)
Most commercially available transformers for 3-to-5 V push-pull converters offer turns ratios between 2.0 and 2.3
with a common tolerance of ±3%.
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9.2.2.5.3 Recommended Transformers
Depending on the application, use the minimum configuration in Figure 46 or standard configuration in Figure 47.
Figure 46. Unregulated Output for Low-Current Loads With Wide Supply Range
Figure 47. Regulated Output for Stable Supplies and High Current Loads
The Wurth Electronics Midcom isolation transformers in Table 3 are optimized designs for the device, providing
high efficiency and small form factor at low-cost.
The 1:1.1 and 1:1.7 turns-ratios are designed for logic applications with wide supply rails and low load currents.
These applications operate without LDO, thus achieving further cost-reduction.
24
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Table 3. Recommended Isolation Transformers Optimized for the Device
TURNS
RATIO
V × T
(Vμs)
ISOLATION
(VRMS
DIMENSIONS
(mm)
APPLICATION
LDO(1)
ORDER NO.
760390011
760390012
760390013
760390014
760390014
MANUFACTURER
)
3.3 V → 3.3 V, 100mA, SN6505B
Refer to Figure 13 and Figure 14
1:1.1 ±2%
1:1.1 ±2%
1:1.7 ±2%
1:1.3 ±2%
1:1.3 ±2%
7
5 V → 5 V, 100mA, SN6505B
Refer to Figure 15 and Figure 16
No
3.3 V → 5 V, 100mA, SN6505B
Refer to Figure 17 and Figure 18
6.73 x 10.05 x 4.19
3.3 V → 3.3 V, 100mA, SN6505B
Refer to Figure 19 and Figure 20
11
5 V → 5 V, 100mA, SN6505B
Refer to Figure 21 and Figure 22
3.3 V → 5 V, 100mA, SN6505B
Refer to Figure 23 and Figure 24
Yes
1:2.1 ±2%
1.23:1 ±2%
1:1.7 ±2%
2500
760390015
750313710
750316028
5 V → 3.3 V, 100mA, SN6505B
3.3 V → 3.3 V, 1A, SN6505B
Refer to Figure 25 and Figure 26
8.9
3.3 V → 5 V, 1A, SN6505B
Refer to Figure 27 and Figure 28
1:2.1 ±2%
1.3:1 ±2%
750316029
750316030
8.3 x 12.6 x 4.1
5 V → 3.3 V, 1A, SN6505B
Refer to Figure 29 and Figure 30
10.8
8.6
Wurth Electronics /
Midcom
3.3 V → 3.3 V , 1A , SN6505B
5 V → 5 V , 1A , SN6505B
No
1:1.1 ±2%
750315371
Refer to Figure 11 and Figure 12
1:1.1 ±2%
1:1.1 ±2%
1:1.7 ±2%
3.3 V → 3.3 V, 100mA, SN6505B
5 V → 5 V, 100mA, SN6505B
3.3 V → 5 V, 100mA, SN6505B
750313734
750313734
750313769
11
9.14 x 12.7 x 7.37
3.3 V → 3.3 V, 100mA, SN6505B
5 V → 5 V, 100mA, SN6505B
1:1.3 ±2%
750313638
Yes
1:2.1 ±2%
1.3:1 ±2%
3.3 V → 5 V, 100mA, SN6505B
5 V → 3.3 V, 100mA , SN6505B
750313626
750313638
No
5000
3.3 V → 3.3 V, 1A, SN6505A
Refer to Figure 3 and Figure 4
1:1.75 ±2%
1:2 ±2%
Yes
750316031
750316032
750316033
41
3.3 V → 5 V, 1A, SN6505A
Refer to Figure 5 and Figure 6
12.32 x 15.41 x 11.05
14.88 x 12.32 x 11.05
5.0 V → 3.3 V, 1A, SN6505A
Refer to Figure 7 and Figure 8
1.3:1 ±2%
42
23
No
3.3 V → 3.3 V, 1A, SN6505A
5 V → 5 V, 1A , SN6505A
1:1.1 ±2%
750315240
Refer to Figure 1 and Figure 2
(1) For configurations with LDO, a higher voltage than the required output voltage is generated, to allow for LDO drop-out. Figures show the
voltage and efficiency at the LDO input.
9.2.3 Application Curves
See theTypical Characteristics, SN6505A and Typical Characteristics, SN6505B for application curves with
transformers optimized for the device, providing high efficiency and small form factor at low-cost.
Copyright © 2015–2018, Texas Instruments Incorporated
25
SN6505A, SN6505B
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
9.2.4 System Examples
9.2.4.1 Higher Output Voltage Designs
The device can drive push-pull converters that provide high output voltages of up to 30 V, or bipolar outputs of
up to ±15 V. Using commercially available center-tapped transformers, with their rather low turns ratios of 0.8 to
5, requires different rectifier topologies to achieve high output voltages. Figure 48 to Figure 50 show some of
these topologies together with their respective open-circuit output voltages.
n
n
V
VOUT = +n·VIN
V =2n·V
OUT IN
V
IN
IN
VOUT = -n·VIN
Figure 48. Bridge Rectifier With Center-Tapped
Secondary Enables Bipolar Outputs
Figure 49. Bridge Rectifier Without Center-Tapped
Secondary Performs Voltage Doubling
V
=4n·V
IN
OUT
n
V
IN
Figure 50. Half-Wave Rectifier Without Centered Ground and Center-Tapped Secondary Performs Voltage
Doubling Twice, Hence Quadrupling VIN
9.2.4.2 Application Circuits
The following application circuits are shown for a 3.3 V input supply commonly taken from the local, regulated
microcontroller supply. For 5 V input voltages requiring different turn ratios refer to the transformer manufacturers
and their web sites listed in Table 4.
Table 4. Transformer Manufacturers
MANUFACTURER
MORE INFORMATION
Coilcraft Inc.
http://www.coilcraft.com
Halo-Electronics Inc.
Murata Power Solutions
Wurth Electronics Midcom Inc
http://www.haloelectronics.com
http://www.murata-ps.com
http://www.midcom-inc.com
26
Copyright © 2015–2018, Texas Instruments Incorporated
SN6505A, SN6505B
www.ti.com.cn
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
VIN
0.1ꢀF
3.3V
2, 5
Vcc
MBR0520L
MBR0520L
1:2.2
5VISO
3
1
1
3
5
2
D2
IN
OUT
GND
TPS76350
SN6505
10ꢀF 0.1ꢀF
10ꢀF
EN
D1
GND
4,6
10ꢀF
Isolation Barrier
0.1ꢀF
0.1ꢀF
0.1ꢀF
1
16
2
VCC1
R
VCC2
3
DVcc
16
UCA0RXD
P3.0
10ꢁ MELF
10ꢁ MELF
5
6
13
B
XOUT
XIN
11
12
12
4
5
6
RE
DE
D
ISO3082
ISO3088
MSP430F2132
12
P3.1
UCA0TXD
A
DVss
4
SM712
GND1
2,7,8
GND2
9,10,15
4.7nF/2kV
Figure 51. Isolated RS-485 Interface
Copyright © 2015–2018, Texas Instruments Incorporated
27
SN6505A, SN6505B
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 5 V nominal. This input
supply must be regulated within ±10%. If the input supply is located more than a few inches from the device, a
0.1 μF by-pass capacitor should be connected as close as possible to the device VCC pin and a 10 μF capacitor
should be connected close to the transformer center-tap pin.
11 Layout
11.1 Layout Guidelines
•
•
•
•
The VIN pin must be buffered to ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1 μF to 10 μF. The capacitor must have a voltage rating of 10 V minimum and
a X5R or X7R dielectric.
The optimum placement is closest to the VIN and GND pins at the board entrance to minimize the loop area
formed by the bypass-capacitor connection, the VIN terminal, and the GND pin. See Figure 52 for a PCB
layout example.
The connections between the device D1 and D2 pins and the transformer primary endings, and the
connection of the device VCC pin and the transformer center-tap must be as close as possible for minimum
trace inductance.
The connection of the device VCC pin and the transformer center-tap must be buffered to ground with a low-
ESR ceramic bypass-capacitor. The recommended capacitor value can range from 1μF to 10 μF. The
capacitor must have a voltage rating of 16 V minimum and a X5R or X7R dielectric.
•
•
•
The device GND pins must be tied to the PCB ground plane using two vias for minimum inductance.
The ground connections of the capacitors and the ground plane should use two vias for minimum inductance.
The rectifier diodes should be Schottky diodes with low forward voltage in the 10 mA to 100 mA current range
to maximize efficiency.
•
The VOUT pin must be buffered to ISO-Ground with a low-ESR ceramic bypass-capacitor. The recommended
capacitor value can range from 1μF to 10 μF. The capacitor must have a voltage rating of 16 V minimum and
a X5R or X7R dielectric.
11.2 Layout Example
Figure 52. Layout Example of a 2-Layer Board
28
版权 © 2015–2018, Texas Instruments Incorporated
SN6505A, SN6505B
www.ti.com.cn
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
德州仪器 (TI)，《数字隔离器设计指南》
德州仪器 (TI)，《隔离相关术语》
德州仪器 (TI)，如何在隔离式 CAN 系统中隔离信号和电源 TI 技术手册
德州仪器 (TI)，《适用于三相逆变器的小型增强型隔离式 IGBT 栅极驱动参考设计》TI 设计
12.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 5. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
SN6505A
SN6505B
12.4 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.6 商标
E2E is a trademark of Texas Instruments.
12.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
版权 © 2015–2018, Texas Instruments Incorporated
29
SN6505A, SN6505B
ZHCSE71G –SEPTEMBER 2015–REVISED NOVEMBER 2018
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
30
版权 © 2015–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
17-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN6505ADBVR
SN6505ADBVT
SN6505BDBVR
SN6505BDBVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
(650A, 65AQ)
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
(650A, 65AQ)
(650B, 65BQ)
(650B, 65BQ)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Feb-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN6505A, SN6505B :
Automotive : SN6505A-Q1, SN6505B-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN6505ADBVR
SN6505ADBVR
SN6505ADBVT
SN6505BDBVR
SN6505BDBVT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
3000
3000
250
180.0
178.0
180.0
180.0
178.0
8.4
9.0
8.4
8.4
9.0
3.2
3.23
3.2
3.2
3.17
3.2
1.4
1.37
1.4
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
3000
250
3.2
3.2
1.4
3.23
3.17
1.37
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN6505ADBVR
SN6505ADBVR
SN6505ADBVT
SN6505BDBVR
SN6505BDBVT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
3000
3000
250
210.0
180.0
210.0
210.0
180.0
185.0
180.0
185.0
185.0
180.0
35.0
18.0
35.0
35.0
18.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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保。
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
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