SN54HCT74FK-00 [TI]
HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20;
| 型号： | SN54HCT74FK-00 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20 输出元件 逻辑集成电路 触发器 |
| 文件： | 总20页 (文件大小：949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢈ ꢀꢁꢇ ꢃꢄ ꢅꢆ ꢇꢃ
ꢉꢊꢋ ꢌ ꢉꢍꢆ ꢎꢏ ꢐ ꢏꢑ ꢀꢒ ꢆ ꢒꢓꢐ ꢍꢐꢉꢔ ꢐꢍꢆ ꢕꢒ ꢔ ꢔꢐ ꢕꢐꢉ ꢖ ꢌꢒ ꢏ ꢍꢖ ꢌꢑ ꢏꢀ
ꢗ ꢒꢆ ꢄ ꢅꢌ ꢐꢋꢕ ꢋꢁꢉ ꢏ ꢕꢐ ꢀ ꢐꢆ
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
SN54HCT74 . . . J OR W PACKAGE
SN74HCT74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 40-µA Max I
CC
1
2
3
4
5
6
7
1CLR
1D
V
CC
13 2CLR
14
Typical t = 17 ns
pd
4-mA Output Drive at 5 V
12
11
10
9
1CLK
1PRE
1Q
2D
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
2CLK
2PRE
2Q
1Q
description/ordering information
8
GND
2Q
The ’HCT74 devices contain two independent
D-type positive-edge-triggered flip-flops. A low
level at the preset (PRE) or clear (CLR) inputs sets
or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK)
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of CLK.
Following the hold-time interval, data at the
D input may be changed without affecting the
levels at the outputs.
SN54HCT74 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
2D
1CLK
NC
4
5
6
7
8
NC
17
16
2CLK
1PRE
NC
15 NC
14
9 10 11 12 13
2PRE
1Q
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HCT74N
SN74HCT74N
SN74HCT74D
SN74HCT74DR
SN74HCT74DT
SN74HCT74NSR
SN74HCT74DBR
SN74HCT74PW
SN74HCT74PWR
SN74HCT74PWT
SNJ54HCT74J
HCT74
SOP − NS
HCT74
HT74
−40°C to 85°C
SSOP − DB
TSSOP − PW
HT74
CDIP − J
CFP − W
LCCC − FK
SNJ54HCT74J
SNJ54HCT74W
SNJ54HCT74FK
−55°C to 125°C
SNJ54HCT74W
SNJ54HCT74FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
ꢊ ꢁ ꢌꢐꢀꢀ ꢑ ꢆꢄ ꢐꢕꢗ ꢒꢀ ꢐ ꢁ ꢑꢆꢐꢉ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢏꢕ ꢑ ꢉ ꢊ ꢅꢆ ꢒꢑ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢃ ꢈ ꢀꢁꢇ ꢃ ꢄꢅ ꢆꢇ ꢃ
ꢉ ꢊꢋꢌ ꢉ ꢍꢆ ꢎꢏꢐ ꢏꢑ ꢀꢒ ꢆ ꢒ ꢓꢐ ꢍꢐ ꢉꢔ ꢐꢍꢆ ꢕꢒ ꢔ ꢔꢐ ꢕꢐꢉ ꢖ ꢌꢒ ꢏꢍꢖ ꢌ ꢑ ꢏꢀ
ꢗꢒ ꢆ ꢄ ꢅ ꢌ ꢐꢋ ꢕ ꢋꢁ ꢉ ꢏ ꢕꢐ ꢀꢐ ꢆ
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
FUNCTION TABLE
INPUTS
OUTPUT
PRE
CLR
H
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
L
L
X
H
†
†
H
L
X
H
H
H
H
H
°
H
L
L
H
°
H
H
L
X
Q
Q
0
0
†
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram (positive logic)
PRE
C
CLK
C
C
Q
TG
C
TG
C
C
C
C
D
TG
C
TG
C
Q
CLR
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢈ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢃ
ꢉꢊꢋ ꢌ ꢉꢍꢆ ꢎꢏ ꢐ ꢏꢑ ꢀꢒ ꢆ ꢒꢓꢐ ꢍꢐꢉꢔ ꢐꢍꢆ ꢕꢒ ꢔ ꢔꢐ ꢕꢐꢉ ꢖ ꢌ ꢒꢏ ꢍ ꢖꢌꢑ ꢏ ꢀ
ꢗ ꢒꢆ ꢄ ꢅꢌ ꢐꢋꢕ ꢋꢁꢉ ꢏ ꢕꢐ ꢀ ꢐꢆ
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
recommended operating conditions (see Note 3)
SN54HCT74
MIN NOM
SN74HCT74
MIN NOM
UNIT
MAX
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0.8
0.8
V
CC
0
0
V
V
0
0
V
V
V
CC
CC
Output voltage
V
O
CC
CC
∆t/∆v
Input transition rise/fall time
Operating free-air temperature
500
125
500
85
ns
°C
T
A
−55
−40
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT74
SN74HCT74
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= −20 µA
= −4 mA
= 20 µA
= 4 mA
4.4 4.499
OH
OH
OL
OL
V
V = V or V
IH
4.5 V
4.5 V
OH
OL
I
IL
3.98
4.3
0.001
0.17
0.1
3.7
3.84
0.1
0.26
100
4
0.1
0.4
0.1
0.33
1000
40
V
V = V or V
V
I
IH
IL
I
I
V = V
I
or 0
5.5 V
5.5 V
1000
80
nA
I
CC
V = V
I
or 0,
I
O
= 0
µA
CC
CC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
†
5.5 V
1.4
3
2.4
10
3
2.9
10
mA
pF
∆I
CC
CC
4.5 V
to 5.5 V
C
10
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
.
CC
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HCT74
SN74HCT74
A
V
UNIT
CC
MIN
MAX
27
MIN
MAX
18
MIN
MAX
22
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
t
Clock frequency
Pulse duration
MHz
clock
30
20
24
16
14
18
16
12
11
0
24
21
27
24
18
16
0
20
18
23
21
15
14
0
PRE or CLR low
CLK high or low
Data
ns
w
t
t
Setup time before CLK↑
ns
ns
su
PRE or CLR inactive
0
0
0
0
0
0
Hold time, data after CLK↑
h
0
0
0
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢃ ꢈ ꢀꢁꢇ ꢃ ꢄꢅ ꢆꢇ ꢃ
ꢉ ꢊꢋꢌ ꢉ ꢍꢆ ꢎꢏꢐ ꢏꢑ ꢀꢒ ꢆ ꢒ ꢓꢐ ꢍꢐ ꢉꢔ ꢐꢍꢆ ꢕꢒ ꢔ ꢔꢐ ꢕꢐꢉ ꢖ ꢌꢒ ꢏꢍꢖ ꢌ ꢑ ꢏꢀ
ꢗꢒ ꢆ ꢄ ꢅ ꢌ ꢐꢋ ꢕ ꢋꢁ ꢉ ꢏ ꢕꢐ ꢀꢐ ꢆ
SCLS169E − DECEMBER 1982 − REVISED APRIL 2004
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
40
SN54HCT74
SN74HCT74
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
27
MAX
MIN
18
MAX
MIN
22
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
t
t
MHz
max
pd
t
30
46
20
24
21
35
31
28
25
15
14
53
48
42
38
22
20
44
40
35
31
19
17
PRE or CLR
CLK
Q or Q
Q or Q
Q or Q
17
ns
ns
20
18
8
7
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance per flip-flop
No load
35
pF
pd
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
From Output
Under Test
Test
Point
High-Level
1.3 V
1.3 V
1.3 V
Pulse
C
= 50 pF
L
t
w
(see Note A)
3 V
0 V
Low-Level
Pulse
1.3 V
LOAD CIRCUIT
3 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
1.3 V
1.3 V
t
t
PLH
PHL
90%
3 V
V
V
OH
In-Phase
Output
Reference
Input
90%
t
1.3 V
1.3 V
10%
1.3 V
10%
0 V
OL
t
r
f
f
t
t
h
su
t
t
PLH
PHL
90%
3 V
0 V
Out-of-
Phase
Output
V
V
Data
Input
OH
2.7 V
2.7 V
90%
t
1.3 V
0.3 V
1.3 V
0.3 V
1.3 V
10%
1.3 V
10%
OL
t
t
t
r
f
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. For clock inputs, f
is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time, with one input transition per measurement.
max
E.
t
and t
PHL
are the same as t .
pd
PLH
Figure 1. Load Circuit and Voltage Waveforms
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ꢛ
ꢣ
ꢥ
ꢡ
ꢜ
ꢡ
ꢛ
ꢚ
ꢭ
ꢢ
ꢭ
ꢝ
ꢣ
ꢨ
ꢛ
ꢩ
ꢆ
ꢡ
ꢪ
ꢣ
ꢛ
ꢒ
ꢢ
ꢛ
ꢘ
ꢥ
ꢟ
ꢠ
ꢡ
ꢢ
ꢘ
ꢛ
ꢥ
ꢞ ꢙ ꢣ ꢢ ꢭꢡ ꢝꢥ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟ ꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢦꢥ ꢝ ꢜꢟꢞ ꢘꢛ ꢫ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢩ
ꢡ
ꢛ
ꢡ
ꢥ
ꢮ
ꢡ
ꢛ
ꢘ
ꢙ
ꢡ
ꢥ
ꢚ
ꢭ
ꢙ
ꢘ
ꢘ
ꢝ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
JM38510/65352B2A
JM38510/65352BCA
JM38510/65352BDA
M38510/65352B2A
M38510/65352BCA
M38510/65352BDA
SN74HCT74D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
20
14
14
14
1
1
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
A42
N / A for Pkg Type
N / A for Pkg Type
W
FK
J
1
LCCC
CDIP
CFP
1
POST-PLATE N / A for Pkg Type
1
A42
A42
N / A for Pkg Type
N / A for Pkg Type
W
D
1
SOIC
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SN74HCT74DBR
SN74HCT74DBRE4
SN74HCT74DBRG4
SN74HCT74DE4
SN74HCT74DG4
SN74HCT74DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DB
DB
DB
D
14
14
14
14
14
14
14
14
14
14
14
2000
2000
2000
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
2500
250
Green (RoHS
& no Sb/Br)
SN74HCT74DRE4
SN74HCT74DRG4
SN74HCT74DT
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
SN74HCT74DTE4
SN74HCT74DTG4
D
250
Green (RoHS
& no Sb/Br)
D
250
Green (RoHS
& no Sb/Br)
SN74HCT74N
ACTIVE
ACTIVE
PDIP
PDIP
N
N
14
14
25
25
Pb-Free (RoHS)
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
SN74HCT74NE4
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2012
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74HCT74NSR
SN74HCT74NSRE4
SN74HCT74NSRG4
SN74HCT74PW
SO
SO
NS
NS
NS
PW
PW
PW
14
14
14
14
14
14
2000
2000
2000
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SO
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
SN74HCT74PWE4
SN74HCT74PWG4
90
Green (RoHS
& no Sb/Br)
90
Green (RoHS
& no Sb/Br)
SN74HCT74PWLE
SN74HCT74PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
2000
2000
2000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SN74HCT74PWRE4
SN74HCT74PWRG4
SN74HCT74PWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
14
14
14
14
14
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74HCT74PWTE4
SN74HCT74PWTG4
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2012
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HCT74, SN74HCT74 :
Catalog: SN74HCT74
•
Military: SN54HCT74
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCT74DBR
SN74HCT74DR
SN74HCT74DT
SN74HCT74NSR
SN74HCT74PWR
SN74HCT74PWT
SSOP
SOIC
DB
D
14
14
14
14
14
14
2000
2500
250
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
12.4
12.4
8.2
6.5
6.5
8.2
6.9
6.9
6.6
9.0
9.0
10.5
5.6
5.6
2.5
2.1
2.1
2.5
1.6
1.6
12.0
8.0
16.0
16.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
SOIC
D
8.0
SO
NS
PW
PW
2000
2000
250
12.0
8.0
TSSOP
TSSOP
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HCT74DBR
SN74HCT74DR
SN74HCT74DT
SN74HCT74NSR
SN74HCT74PWR
SN74HCT74PWT
SSOP
SOIC
DB
D
14
14
14
14
14
14
2000
2500
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
38.0
35.0
35.0
SOIC
D
SO
NS
PW
PW
2000
2000
250
TSSOP
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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