SN54HC595-SP [TI]
具有三态输出寄存器的 8 位移位寄存器;
| 型号： | SN54HC595-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出寄存器的 8 位移位寄存器 移位寄存器 |
| 文件： | 总20页 (文件大小：638K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢉ ꢊꢋꢌ ꢍ ꢀꢄꢌ ꢎ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏ
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SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004
SN54HC595 . . . J OR W PACKAGE
SN74HC595 . . . D, DB, DW, N, OR NS PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
8-Bit Serial-In, Parallel-Out Shift
Wide Operating Voltage Range of 2 V to 6 V
High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
B
Q
C
D
A
Low Power Consumption, 80-µA Max I
Typical t = 13 ns
pd
6-mA Output Drive at 5 V
CC
Q
SER
OE
Q
E
Q
12 RCLK
F
Low Input Current of 1 µA Max
Shift Register Has Direct Clear
11
10
9
Q
SRCLK
SRCLR
G
Q
H
GND
Q
H′
description/ordering information
SN54HC595 . . . FK PACKAGE
(TOP VIEW)
The ’HC595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
both the shift and storage register. The shift
register has a direct overriding clear (SRCLR)
input, serial (SER) input, and serial outputs for
cascading. When the output-enable (OE) input is
high, the outputs are in the high-impedance state.
3
2
1
20 19
18
SER
OE
Q
4
5
6
7
8
D
Q
17
16
E
NC
NC
15 RCLK
14
9 10 11 12 13
Q
F
SRCLK
Q
G
Both the shift register clock (SRCLK) and storage
register clock (RCLK) are positive-edge triggered.
If both clocks are connected together, the shift
register always is one clock pulse ahead of the
storage register.
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Tube of 40
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
SN74HC595N
SN74HC595N
SN74HC595D
SN74HC595DR
SN74HC595DT
SN74HC595DW
SN74HC595DWR
SN74HC595NSR
SN74HC595DBR
SNJ54HC595J
SNJ54HC595W
SNJ54HC595FK
HC595
−40°C to 85°C
SOIC − DW
HC595
SOP − NS
SSOP − DB
CDIP − J
HC595
HC595
SNJ54HC595J
SNJ54HC595W
SNJ54HC595FK
−55°C to 125°C
CFP − W
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
ꢕ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢌ ꢰꢊ ꢗꢏ ꢎ ꢊꢓꢉꢂ ꢓꢂꢇ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢂꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢂ ꢆ ꢂ
ꢉꢊ ꢋꢌ ꢍ ꢀꢄ ꢌ ꢎ ꢍ ꢏ ꢐꢑ ꢌꢀ ꢍꢐ ꢏꢀ
ꢒꢌ ꢍ ꢄ ꢓ ꢊꢀꢍꢔꢍ ꢐ ꢕꢖꢍ ꢗꢖ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏꢀ
SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004
FUNCTION TABLE
INPUTS
FUNCTION
Outputs Q −Q are disabled.
SER SRCLK SRCLR RCLK
OE
H
X
X
X
X
X
X
X
X
L
X
X
X
A
H
L
Outputs Q −Q are enabled.
A H
X
Shift register is cleared.
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
H
X
↑
H
X
X
X
X
X
↑
Shift-register data is stored in the storage register.
2
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SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004
logic diagram (positive logic)
13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
SER
1D
C1
R
3R
C3
3S
15
Q
Q
A
B
2S
2R
C2
3R
C3
1
2
3
4
5
6
R
3S
2S
2R
3R
C2
C3
Q
Q
C
D
R
3S
2S
2R
3R
C2
C3
R
3S
2S
2R
3R
Q
Q
Q
C2
C3
E
F
R
3S
2S
2R
3R
C2
C3
R
3S
2S
2R
3R
C2
C3
G
R
3S
2S
2R
C2
3R
C3
3S
7
9
Q
Q
H
R
H′
Pin numbers shown are for the D, DB, DW, J, N, NS, and W packages.
3
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ꢉꢊ ꢋꢌ ꢍ ꢀꢄ ꢌ ꢎ ꢍ ꢏ ꢐꢑ ꢌꢀ ꢍꢐ ꢏꢀ
ꢒꢌ ꢍ ꢄ ꢓ ꢊꢀꢍꢔꢍ ꢐ ꢕꢖꢍ ꢗꢖ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏꢀ
SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H’
NOTE:
implies that the output is in 3-State mode.
4
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ꢀ
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ꢈ
ꢃ
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ꢅ
ꢂ
ꢆ
ꢂ
ꢀ
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ꢒ ꢌꢍ ꢄ ꢓ ꢊꢀꢍꢔꢍ ꢐ ꢕ ꢖꢍ ꢗꢖꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏ
SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC595
MIN NOM
SN74HC595
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
‡
= 4.5 V
= 6 V
∆t/∆v
Input transition rise/fall time
ns
T
A
Operating free-air temperature
−55
−40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
‡
If this device is used in the threshold region (from V max = 0.5 V to V min = 1.5 V), there is a potential to go into the wrong state from induced
IL IH
grounding, causing double clocking. Operating with the inputs at t = 1000 ns and V
CC
= 2 V does not damage the device; however, functionally,
t
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
5
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢂꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢂ ꢆ ꢂ
ꢉꢊ ꢋꢌ ꢍ ꢀꢄ ꢌ ꢎ ꢍ ꢏ ꢐꢑ ꢌꢀ ꢍꢐ ꢏꢀ
ꢒꢌ ꢍ ꢄ ꢓ ꢊꢀꢍꢔꢍ ꢐ ꢕꢖꢍ ꢗꢖ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏꢀ
SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC595
SN74HC595
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
3.7
5.2
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
4.4
I
= −20 µA
OH
5.9
Q
, I
H′ OH
= −4 mA
3.98
4.3
4.3
3.84
3.84
5.34
5.34
V
OH
V = V or V
IH IL
V
I
4.5 V
6 V
Q −Q , I
= −6 mA
3.98
5.48
5.48
A
H
OH
Q
, I
H′ OH
= −5.2 mA
5.8
Q −Q , I
= −7.8 mA
5.8
A
H
OH
2 V
4.5 V
6 V
0.002
0.001
0.001
0.17
0.17
0.15
0.15
0.1
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
OL
0.1
0.1
0.1
Q
, I
H′ OL
= 4 mA
= 6 mA
= 5.2 mA
0.26
0.26
0.26
0.26
100
0.5
0.4
0.33
0.33
0.33
0.33
1000
5
V
OL
V = V or V
V
I
IH
IL
4.5 V
6 V
Q −Q , I
OL
0.4
A
H
Q
, I
H′ OL
0.4
Q −Q , I
= 7.8 mA
0.4
A
H
H
OL
I
I
I
V = V
or 0
6 V
6 V
6 V
1000
10
nA
µA
µA
I
I
CC
V
O
= V
CC
or 0, Q −Q
0.01
OZ
CC
A
V = V
I CC
or 0,
I
O
= 0
8
160
80
2 V
to 6 V
C
3
10
10
10
pF
i
6
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ꢏ
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ꢀ
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SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC595
SN74HC595
A
V
UNIT
CC
MIN
MAX
6
MIN
MAX
4.2
21
MIN
MAX
5
2 V
4.5 V
6 V
31
25
f
Clock frequency
Pulse duration
MHz
clock
36
25
29
2 V
80
16
14
80
16
14
100
20
17
75
15
13
50
10
9
120
24
20
120
24
20
150
30
25
113
23
19
75
15
13
75
15
13
0
100
20
17
100
20
17
125
25
21
94
19
16
65
13
11
60
12
11
0
4.5 V
6 V
SRCLK or RCLK high or low
SRCLR low
t
w
ns
2 V
4.5 V
6 V
2 V
4.5 V
6 V
SER before SRCLK↑
2 V
†
4.5 V
6 V
SRCLK↑ before RCLK↑
t
su
Setup time
ns
2 V
4.5 V
6 V
SRCLR low before RCLK↑
2 V
50
10
9
4.5 V
6 V
SRCLR high (inactive) before SRCLK↑
2 V
0
t
h
Hold time, SER after SRCLK↑
4.5 V
6 V
0
0
0
ns
0
0
0
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢂꢆ ꢂꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢂ ꢆ ꢂ
ꢉꢊ ꢋꢌ ꢍ ꢀꢄ ꢌ ꢎ ꢍ ꢏ ꢐꢑ ꢌꢀ ꢍꢐ ꢏꢀ
ꢒꢌ ꢍ ꢄ ꢓ ꢊꢀꢍꢔꢍ ꢐ ꢕꢖꢍ ꢗꢖ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏꢀ
SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
26
38
42
50
17
14
50
17
14
51
18
15
40
15
13
42
23
20
28
8
SN54HC595
SN74HC595
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
6
MAX
MIN
4.2
21
MAX
MIN
5
MAX
2 V
4.5 V
6 V
31
36
25
29
f
t
MHz
max
pd
25
2 V
160
32
240
48
200
40
4.5 V
6 V
SRCLK
RCLK
SRCLR
OE
Q
H′
27
41
34
ns
2 V
150
30
225
45
187
37
4.5 V
6 V
Q −Q
A
H
26
38
32
2 V
175
35
261
52
219
44
4.5 V
6 V
t
t
t
Q
ns
ns
ns
PHL
H′
30
44
37
2 V
150
30
225
45
187
37
4.5 V
6 V
Q −Q
A
en
H
H
H
26
38
32
2 V
200
40
300
60
250
50
4.5 V
6 V
OE
Q −Q
A
dis
34
51
43
2 V
60
90
75
4.5 V
6 V
12
18
15
Q −Q
A
6
10
15
13
t
t
ns
2 V
28
8
75
110
22
95
Q
4.5 V
6 V
15
19
H′
6
13
19
16
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
60
SN54HC595
SN74HC595
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
200
40
MIN
MAX
300
60
MIN
MAX
250
50
2 V
4.5 V
6 V
22
t
pd
t
en
t
t
RCLK
OE
Q −Q
A
ns
H
H
H
19
34
51
43
2 V
70
200
40
298
60
250
50
4.5 V
6 V
23
Q −Q
ns
ns
A
19
34
51
43
2 V
45
210
42
315
63
265
53
Q −Q
A
4.5 V
6 V
17
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
400
pF
pd
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢂ
ꢇ
ꢉ ꢊꢋꢌ ꢍ ꢀꢄꢌ ꢎ ꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏ
ꢀ
ꢁ
ꢈ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢂ
ꢀ
ꢀ
ꢒ ꢌꢍ ꢄ ꢓ ꢊꢀꢍꢔꢍ ꢐ ꢕ ꢖꢍ ꢗꢖꢍ ꢏꢐ ꢑ ꢌꢀ ꢍꢐ ꢏ
SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
t
Open
Closed
Closed
Open
S1
S2
PZH
Test
Point
t
t
1 kΩ
1 kΩ
en
R
t
L
PZL
From Output
Under Test
t
t
Open
Closed
Open
PHZ
PLZ
C
L
50 pF
dis
(see Note A)
Closed
50 pF
or
150 pF
t
or t
−−
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
High-Level
Pulse
50%
50%
t
t
h
su
0 V
V
CC
t
Data
Input
w
90%
90%
50%
10%
50%
10%
V
CC
Low-Level
Pulse
0 V
50%
50%
t
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
V
CC
V
CC
Control
(Low-Level
Enabling)
Input
50%
50%
50%
50%
0 V
V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
OH
≈V
CC
50%
≈V
CC
Output
Waveform 1
(See Note B)
In-Phase
Output
90%
t
50%
10%
50%
10%
10%
t
V
OL
V
OL
t
r
f
f
t
t
t
PZH
PHZ
PHL
90%
PLH
V
V
OH
V
Output
Waveform 2
(See Note B)
OH
90%
t
90%
Out-of-
Phase
Output
50%
10%
50%
10%
50%
≈0 V
OL
t
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time, with one input transition per measurement.
max
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CDIP
CFP
Drawing
5962-86816012A
5962-8681601EA
5962-8681601VEA
5962-8681601VFA
SN54HC595J
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
16
16
16
16
1
1
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
J
1
W
J
1
CDIP
SOIC
1
SN74HC595D
D
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR
SN74HC595DBR
SN74HC595DR
SN74HC595DT
SN74HC595DW
SN74HC595DWR
SN74HC595N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
SOIC
SOIC
PDIP
SO
DB
D
16
16
16
16
16
16
16
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR
DW
DW
N
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
2000
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74HC595NSR
NS
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SNJ54HC595FK
SNJ54HC595J
SNJ54HC595W
ACTIVE
ACTIVE
LCCC
CDIP
FK
J
20
16
16
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
OBSOLETE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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