SN54HC125_15 [TI]
Quadruple Bus Buffer Gates;
| 型号： | SN54HC125_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quadruple Bus Buffer Gates 栅 |
| 文件： | 总6页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC125, SN74HC125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS104B – MARCH 1984 – REVISED MAY 1997
SN54HC125 . . . J OR W PACKAGE
SN74HC125 . . . D, DB, OR N PACKAGE
(TOP VIEW)
High-Current 3-State Outputs Interface
Directly With System Bus or Can Drive up
to 15 LSTTL Loads
Package Options Include Plastic
1OE
1A
V
CC
4OE
4A
1
2
3
4
5
6
7
14
13
12
11
Small-Outline (D), Shrink Small-Outline
(DB), and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and Standard
Plastic (N) and Ceramic (J) 300-mil DIPs
1Y
2OE
2A
4Y
10 3OE
9
8
2Y
3A
3Y
description
GND
These quadruple bus buffer gates feature
independent line drivers with 3-state outputs.
Each output is disabled when the associated
output-enable (OE) input is high.
SN54HC125 . . . FK PACKAGE
(TOP VIEW)
The SN54HC125 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC125 is characterized for
operation from –40°C to 85°C.
3
2
1
20 19
18
4A
NC
4Y
1Y
NC
4
5
6
7
8
17
16
2OE
NC
FUNCTION TABLE
(each buffer)
15 NC
14
9 10 11 12 13
3OE
2A
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
H
L
NC – No internal connection
H
X
Z
†
logic symbol
1
EN
1OE
2
3
1Y
1A
4
2OE
5
6
2Y
2A
10
8
3OE
3A
4OE
4A
3Y
9
13
12
11
4Y
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, and W packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC125, SN74HC125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS104B – MARCH 1984 – REVISED MAY 1997
logic diagram (positive logic)
1
10
9
1OE
3OE
3A
2
3
6
8
1A
1Y
2Y
3Y
4Y
4
13
12
2OE
4OE
4A
5
11
2A
Pin numbers shown are for the D, DB, J, N, and W packages.
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HC125
MIN NOM
SN74HC125
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
3.15
4.2
0
5
6
2
1.5
3.15
4.2
0
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
0
0
0
0
V
V
Input voltage
0
V
V
0
V
V
V
V
I
CC
CC
Output voltage
0
0
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
0
1000
500
400
125
0
1000
500
400
85
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
0
0
ns
t
0
0
T
–55
–40
°C
A
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC125, SN74HC125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS104B – MARCH 1984 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC125
SN74HC125
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.4
OH
V
V = V or V
IH
5.9
V
OH
OL
I
IL
IL
I
I
= –6 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= –7.8 mA
OH
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
4.5 V
6 V
OL
V
V = V or V
0.1
0.1
0.1
V
I
IH
I
I
= 6 mA
4.5 V
6 V
0.26
0.26
±100
±0.5
8
0.4
0.33
0.33
±1000
±5
OL
= 7.8 mA
0.15
0.4
OL
I
I
I
V = V
I
or 0
6 V
±0.1
±1000
±10
160
10
nA
µA
µA
pF
I
CC
CC
V
O
= V
or 0
6 V
±0.01
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
80
C
2 V to 6 V
3
10
10
i
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
48
14
11
SN54HC125
SN74HC125
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
120
24
MIN
MAX
150
36
MIN
MAX
150
30
2 V
4.5 V
6 V
t
t
t
t
A
Y
Y
ns
pd
en
dis
t
20
25
26
2 V
53
14
11
120
24
180
36
150
30
OE
OE
4.5 V
6 V
ns
ns
ns
20
31
26
2 V
30
15
14
28
8
120
24
180
36
150
30
Y
4.5 V
6 V
20
31
26
2 V
60
90
75
Any
4.5 V
6 V
12
18
15
6
10
15
13
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC125, SN74HC125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS104B – MARCH 1984 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
67
SN54HC125
SN74HC125
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
150
30
MIN
MAX
225
45
MIN
MAX
190
38
2 V
4.5 V
6 V
t
pd
t
en
t
t
A
Y
Y
19
ns
15
25
39
32
2 V
100
20
135
27
200
40
170
34
OE
4.5 V
6 V
ns
ns
17
23
34
29
2 V
45
210
42
315
63
265
53
Any
4.5 V
6 V
17
13
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
Power dissipation capacitance per gate
TEST CONDITIONS
TYP
UNIT
C
No load
45
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC125, SN74HC125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS104B – MARCH 1984 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
S1
S2
t
t
Open
Closed
Closed
Open
PZH
Test
Point
t
t
1 kΩ
1 kΩ
en
R
L
From Output
Under Test
PZL
t
t
Open
Closed
Open
PHZ
PLZ
50 pF
C
dis
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
––
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Input
50%
50%
0 V
t
t
PLH
PHL
90%
V
V
OH
In-Phase
Output
90%
50%
10%
50%
10%
OL
t
Output
Control
(Low-Level
Enabling)
t
r
f
f
V
CC
t
t
PLH
PHL
90%
50%
50%
V
V
OH
90%
t
0 V
Out-of-Phase
Output
50%
10%
50%
10%
t
t
PLZ
PZL
OL
t
≈ V
≈ V
r
Output
Waveform 1
(See Note B)
CC
CC
50%
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
10%
90%
V
OL
t
PZH
V
CC
V
Output
Waveform 2
(See Note B)
OH
90%
t
90%
Input
50%
10%
50%
10%
50%
0 V
≈ 0 V
t
PHZ
t
r
f
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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