SN54F109_15 [TI]
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET;
| 型号： | SN54F109_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET |
| 文件： | 总5页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54F109, SN74F109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS047A – MARCH 1987 – REVISED OCTOBER 1993
SN54F109 . . . J PACKAGE
SN74F109 . . . D OR N PACKAGE
(TOP VIEW)
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
1CLR
1J
VCC
2CLR
2J
1
2
3
4
5
6
7
8
16
15
14
13
12
description
1K
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K input meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by
grounding K and trying J high. They also can
perform as D-type flip-flops if J and K are tied
together.
1CLK
1PRE
1Q
2K
2CLK
11 2PRE
10
9
1Q
2Q
2Q
GND
SN54F109 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
1K
1CLK
NC
4
5
6
7
8
2J
17
16
15
14
2K
NC
1PRE
1Q
2CLK
2PRE
9 10 11 12 13
The SN54F109 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F109 is characterized for
operation from 0°C to 70°C.
NC – No internal connection
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
H
CLK
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
†
H
†
H
L
L
X
H
H
↑
L
H
H
H
↑
H
L
L
Toggle
H
H
↑
H
H
X
Q
Q
0
0
H
H
↑
H
X
H
L
H
H
L
Q
Q
0
0
†
The output levels are not guaranteed to meet the minimum
levelsforV .Furthermore,thisconfigurationisnonstable;
OH
that is, it will not persist when PRE or CLR returns to its
inactive (high) level.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F109, SN74F109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS047A – MARCH 1987 – REVISED OCTOBER 1993
†
logic symbol
5
S
1PRE
1J
6
7
2
4
3
1
1Q
1Q
1J
1CLK
C1
1K
R
1K
1CLR
11
14
12
13
15
2PRE
2J
10
9
2Q
2Q
2CLK
2K
2CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Operating free-air temperature range: SN54F109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
SN74F109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
SN54F109
SN74F109
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
0.8
–18
– 1
0.8
–18
– 1
20
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
20
T
A
–55
125
0
70
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F109, SN74F109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS047A – MARCH 1987 – REVISED OCTOBER 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54F109
SN74F109
PARAMETER
TEST CONDITIONS
UNIT
V
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
I = –18 mA
I
–1.2
–1.2
IK
I
I
I
= – 1 mA
= – 1 mA
= 20 mA
2.5
3.4
0.3
2.5
2.7
3.4
0.3
OH
OH
OL
V
OH
OL
0.5
0.1
0.5
0.1
V
I
I
V = 7 V
I
mA
µA
I
IH
V = 2.7 V
I
20
20
J, K, CLK
– 0.6
– 1.8
–150
17
– 0.6
– 1.8
–150
17
I
V
= 5.5 V,
V = 0.5 V
mA
IL
CC
I
PRE or CLR
‡
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0
O
–60
–60
mA
mA
OS
CC
CC
See Note 2
11.7
11.7
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2:
I
is measured with J, K, CLK, and PRE grounded then with J, K, CLK, and CLR grounded.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
T
= 5 V,
= 25°C
CC
A
SN54F109
SN74F109
UNIT
′F74
MIN
0
MAX
MIN
0
MAX
70
MIN
0
MAX
90
f
t
Clock frequency
Pulse duration
100
MHz
ns
clock
CLK high, PRE or CLR low
4
4
4
w
CLK low
5
5
5
High
3
3
3
Setup time, data before CLK↑
Setup time, inactive-state before CLK↑
Hold time, data after CLK↑
Low
3
3
3
t
t
ns
ns
su
§
PRE or CLR to CLK
2
2
2
High
Low
1
1
1
h
1
1
1
§
Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Note 3)
V
C
R
= 5 V,
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
CC
L
L
= 50 pF,
= 500 Ω,
= 25°C
= 500Ω,
= MIN to MAX
FROM
(INPUT)
TO
(OUTPUT)
¶
PARAMETER
UNIT
T
A
T
A
′F109
TYP
150
4.9
SN54F109
SN74F109
MIN
100
3
MAX
MIN
70
MAX
MIN
90
MAX
f
MHz
ns
max
PLH
PHL
PLH
PHL
t
t
t
t
7
8
7
9
3
9
10.5
9
3
8
9.2
8
CLK
Q or Q
Q or Q
3.6
2.4
2.7
5.8
3.6
2.4
2.7
3.6
2.4
2.7
4.8
PRE or CLR
ns
6.6
11.5
10.5
¶
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–4
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
SN54F112FK-00
F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20
TI
SN54F112J
F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, CERAMIC, DIP-16
TI
SN54F113FK
F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20
TI
SN54F113FK
J-K Flip-Flop, F/FAST Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CQCC20, QCC-20
ROCHESTER
SN54F113FK-00
F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20
TI
SN54F113J
F/FAST SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
TI
©2020 ICPDF网 联系我们和版权申明