SN54ALS563A [TI]
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS; 八路D型透明锁存器带3态输出
| 型号： | SN54ALS563A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总4页 (文件大小：57K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS563A, SN74ALS563B
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SDAS163 – D2661, DECEMBER 1982 – REVISED JANUARY 1989
SN54ALS563A . . . J PACKAGE
SN74ALS563B . . . DW OR N PACKAGE
• 3-State Buffer-Type Outputs Drive Bus-Lines
Directly
(TOP VIEW)
• Bus Structured Pinout
• Package Options include Plastic Small Outline
Package, Ceramic Chip Carriers and Standard
Plastic and Ceramic DIPs
OC
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
C
• Dependable Texas Instruments Quality and
Reliability
description
These 8-bit latches feature three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
GND
SN54ALS563A . . . FK PACKAGE
(TOP VIEW)
The eight latches are transparent D-type latches.
While the enable (C) is high the Q outputs will
follow the complements of data (D) inputs. When
the enable is taken low the output will be latched
at the inverses of the levels that were set up at the
D inputs.
3
2
1
20 19
18
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
4
5
6
7
8
17
16
15
14
A buffered output-control input can be used to
place the eight outputs in either a normal logic
9 10 11 12 13
state (high or low logic levels) or
a
high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased high-logic level provide the capability to
drive the bus lines in a bus-organized system
without need for interface or pull-up components.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
The output control (OC) does not affect the
internal operation of the latches. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
ENABLE
C
D
OC
L
H
H
L
H
L
L
H
X
X
H
L
Q
0
The SN54ALS563A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS563B is characterized for
operation from 0°C to 70°C.
H
X
Z
Copyright 1989, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS563A, SN74ALS563B
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SDAS163 – D2661, DECEMBER 1982 – REVISED JANUARY 1989
†
logic symbol
logic diagram (positive logic)
1
1
OC
C
EN
C1
OC
C
11
11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
19
18
17
16
15
14
13
12
C1
D1
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
2
3
4
5
6
7
8
9
1Q
2Q
3Q
4Q
5Q
1D
3Q
4Q
5Q
C1
D1
2D
3D
4D
5D
6D
7D
8D
C1
D1
6Q
7Q
8Q
C1
D1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for DW, J, and N packages.
C1
D1
C1
D1
6Q
7Q
8Q
C1
D1
C1
D1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range: SN54ALS563A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
SN74ALS563B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
recommended operating conditions
SN54ALS563A
MIN NOM MAX
SN74ALS563B
MIN NOM MAX
UNIT
V
V
V
Supply Voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Pulse duration, C high
Setup time, data before C↓
Hold time, data after C↓
Operating free-air temperature
IH
0.7
–1
12
0.8
–2.6
24
V
IL
I
I
t
t
t
mA
mA
ns
ns
ns
°C
OH
OL
w
15
10
15
10
10
0
su
h
10
T
A
–55
125
70
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS563A, SN74ALS563B
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SDAS163 – D2661, DECEMBER 1982 – REVISED JANUARY 1989
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS563A
SN74ALS563B
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
IK
V
V
V
V
V
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V to 5.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
–1.2
–1.2
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
I
I
I
I
= –0.4 mA
= –1 mA
= –2.6 mA
= 12 mA
= 24 mA
= 2.7 V
V
CC
–2
V –2
CC
OH
OL
OH
OL
OL
V
OH
2.4
3.3
V
2.4
3.2
0.25
0.35
0.25
0.4
0.4
0.5
V
OL
V
I
I
I
I
I
I
V
20
–20
0.1
20
µA
µA
OZH
OZL
I
O
O
V
= 0.4 V
–20
0.1
V = 7 V
I
mA
µA
V = 2.7 V
I
20
20
IH
V = 0.4 V
I
– 0.1
–112
17
– 0.1
–112
17
mA
mA
IL
‡
V
O
= 2.25 V
–30
–30
O
Outputs high
Outputs low
10
16
17
10
16
17
I
V
CC
= 5.5 V
26
26
mA
CC
Outputs disabled
29
29
†
‡
All typical Values are at V
CC
= 5 V, T = 25°C.
A
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
OS.
switching characteristics (see Note 1)
V
C
= 5 V,
= 50pF,
V
= 4.5 V to 5.5 V,
C = 50pF,
L
CC
L
CC
R1 = 500 Ω,
R2 = 500 Ω,
T
A
R1 = 500 Ω,
R2 = 500 Ω,
§
T = MIN to MAX
A
FROM
PARAMETER
TO
(OUTPUT)
UNIT
(INPUT)
= 25°C
’ALS563
SN54ALS563A SN74ALS563B
TYP
10
8
MIN
3
MAX
21
MIN
3
MAX
18
t
t
t
t
PLH
PHL
PLH
PHL
PZH
D
C
Q
Q
Q
Q
ns
ns
ns
ns
3
15
3
14
8
8
29
6
22
14
8
8
22
6
21
t
4
21
3
18
OC
OC
t
10
5
4
21
4
18
PZL
PHZ
t
2
12
1
10
t
7
3
18
1
15
PLZ
§
For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 1: Load circuit and voltage waveforms are shown in Section 1 of the ALS/AS Logic Data Book, 1986.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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