SN54AHC132FK [TI]

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS; 翻两番正与非门施密特触发器输入
SN54AHC132FK
型号: SN54AHC132FK
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
翻两番正与非门施密特触发器输入

栅极 触发器 逻辑集成电路 输入元件
文件: 总8页 (文件大小:130K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN54AHC132, SN74AHC132  
QUADRUPLE POSITIVE-NAND GATES  
WITH SCHMITT-TRIGGER INPUTS  
SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002  
Operating Range 2-V to 5.5-V V  
Same Pinouts as ’AHC00  
CC  
Operation From Very Slow Input  
Transitions  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Temperature-Compensated Threshold  
Levels  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
High Noise Immunity  
– 1000-V Charged-Device Model (C101)  
SN54AHC132 . . . J OR W PACKAGE  
SN74AHC132 . . . D, DB, DGV, N, NS,  
OR PW PACKAGE  
SN54AHC132 . . . FK PACKAGE  
SN74AHC132 . . . RGY PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
(TOP VIEW)  
1
14  
3
2
1
20 19  
18  
1A  
1B  
V
CC  
4B  
14  
13  
1
2
3
4
5
6
7
4A  
17 NC  
1Y  
NC  
2A  
4
5
6
7
8
1B  
1Y  
2A  
2B  
2Y  
13 4B  
12 4A  
2
3
4
5
6
1Y  
12 4A  
16  
15  
14  
4Y  
NC  
3B  
11  
10  
9
4Y  
3B  
3A  
11  
10  
9
2A  
4Y  
3B  
3A  
3Y  
NC  
2B  
2B  
2Y  
9 10 11 12 13  
7
8
8
GND  
NC – No internal connection  
description/ordering information  
The ’AHC132 devices are quadruple positive-NAND gates designed for 2-V to 5.5-V V  
operation.  
CC  
These devices perform the Boolean function Y = A B or Y = A + B in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN – RGY  
PDIP – N  
Tape and reel  
Tube  
SN74AHC132RGYR  
SN74AHC132N  
HA132  
SN74AHC132N  
Tube  
SN74AHC132D  
SOIC – D  
AHC132  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHC132DR  
SN74AHC132NSR  
SN74AHC132DBR  
SN74AHC132PWR  
SN74AHC132DGVR  
SNJ54AHC132J  
–40°C to 85°C  
SOP – NS  
AHC132  
SSOP – DB  
TSSOP – PW  
TVSOP – DGV  
CDIP – J  
HA132  
HA132  
HA132  
SNJ54AHC132J  
SNJ54AHC132W  
SNJ54AHC132FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHC132W  
SNJ54AHC132FK  
LCCC – FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54AHC132, SN74AHC132  
QUADRUPLE POSITIVE-NAND GATES  
WITH SCHMITT-TRIGGER INPUTS  
SCLS365G MAY 1997 REVISED SEPTEMBER 2002  
description/ordering information (continued)  
Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels  
for positive- and negative-going signals.  
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give  
clean jitter-free output signals.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
X
logic diagram, each gate (positive logic)  
A
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
+ 0.5 V  
O
CC  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
IK  
I
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA  
Continuous current through V  
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA  
JA  
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W  
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W  
(see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W  
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W  
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W  
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
3. The package thermal impedance is calculated in accordance with JESD 51-5.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54AHC132, SN74AHC132  
QUADRUPLE POSITIVE-NAND GATES  
WITH SCHMITT-TRIGGER INPUTS  
SCLS365G MAY 1997 REVISED SEPTEMBER 2002  
recommended operating conditions (see Note 4)  
SN54AHC132 SN74AHC132  
UNIT  
MIN  
MAX  
MIN  
MAX  
V
V
V
Supply voltage  
Input voltage  
Output voltage  
2
5.5  
2
5.5  
V
V
V
CC  
0
5.5  
0
5.5  
I
0
V
0
V
CC  
O
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 2 V  
50  
4  
8  
50  
4
50  
4  
8  
50  
4
A
I
High-level output current  
= 3.3 V ± 0.3 V  
= 5 V ± 0.5 V  
= 2 V  
OH  
OL  
mA  
A
I
Low-level output current  
= 3.3 V ± 0.3 V  
= 5 V ± 0.5 V  
mA  
8
8
T
A
Operating free-air temperature  
55  
125  
40  
85  
°C  
NOTE 4: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
SN54AHC132 SN74AHC132  
PARAMETER  
TEST CONDITIONS  
V
UNIT  
CC  
MIN  
1.2  
TYP  
MAX  
2.2  
MIN  
1.2  
MAX  
2.2  
MIN  
1.2  
MAX  
2.2  
3 V  
4.5 V  
5.5 V  
3 V  
V
T+  
1.75  
2.15  
0.9  
3.15  
3.85  
1.9  
1.75  
2.15  
0.9  
3.15  
3.85  
1.9  
1.75  
2.15  
0.9  
3.15  
3.85  
1.9  
V
Positive-going  
input threshold voltage  
V
T–  
4.5 V  
5.5 V  
3 V  
1.35  
1.65  
0.3  
2.75  
3.35  
1.2  
1.35  
1.65  
0.3  
2.75  
3.35  
1.2  
1.35  
1.65  
0.3  
2.75  
3.35  
1.2  
V
V
Negative-going  
input threshold voltage  
V  
T
4.5 V  
5.5 V  
2 V  
0.4  
1.4  
0.4  
1.4  
0.4  
1.4  
Hysteresis (V V  
T+  
)
T–  
0.5  
1.6  
0.5  
1.6  
0.5  
1.6  
1.9  
2
3
1.9  
1.9  
I
= 50  
A
3 V  
2.9  
2.9  
2.9  
OH  
V
4.5 V  
3 V  
4.4  
4.5  
4.4  
4.4  
V
V
OH  
OL  
I
I
= 4 mA  
= 8 mA  
2.58  
3.94  
2.48  
3.8  
2.48  
3.8  
OH  
4.5 V  
2 V  
OH  
0.1  
0.1  
0.1  
0.1  
0.1  
0.5  
0.5  
±1*  
20  
0.1  
0.1  
0.1  
0.44  
0.44  
±1  
I
= 50  
A
3 V  
OL  
V
4.5 V  
3 V  
0.1  
I
I
= 4 mA  
= 8 mA  
0.36  
0.36  
±0.1  
2
OL  
4.5 V  
0 V to 5.5 V  
5.5 V  
5 V  
OL  
I
I
V = 5.5 V or GND  
A
A
I
I
V = V  
or GND,  
or GND  
I = 0  
O
20  
CC  
I
CC  
CC  
C
V = V  
1.9  
10  
10  
pF  
i
I
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V  
= 0 V.  
CC  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54AHC132, SN74AHC132  
QUADRUPLE POSITIVE-NAND GATES  
WITH SCHMITT-TRIGGER INPUTS  
SCLS365G MAY 1997 REVISED SEPTEMBER 2002  
switching characteristics over recommended operating free-air temperature range,  
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)  
CC  
T = 25°C  
A
SN54AHC132 SN74AHC132  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
UNIT  
ns  
MIN  
TYP  
MAX  
MIN  
1*  
1*  
1
MAX  
14*  
MIN  
1
MAX  
14  
t
t
t
t
5.6* 11.9*  
5.6* 11.9*  
PLH  
PHL  
PLH  
PHL  
A or B  
A or B  
Y
Y
C
C
= 15 pF  
= 50 pF  
L
L
14*  
1
14  
7.6  
7.6  
15.4  
15.4  
17.5  
17.5  
1
17.5  
17.5  
ns  
1
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.  
switching characteristics over recommended operating free-air temperature range,  
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)  
CC  
T
A
= 25°C  
TYP  
3.9*  
3.9*  
5.3  
SN54AHC132 SN74AHC132  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
UNIT  
ns  
MIN  
MAX  
7.7*  
7.7*  
9.7  
MIN  
1*  
1*  
1
MAX  
9*  
MIN  
1
MAX  
9
t
t
t
t
PLH  
PHL  
PLH  
PHL  
A or B  
A or B  
Y
Y
C
C
= 15 pF  
= 50 pF  
L
L
9*  
1
9
11  
1
11  
11  
ns  
5.3  
9.7  
1
11  
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.  
noise characteristics, V  
= 5 V, C = 50 pF, T = 25°C (see Note 5)  
CC  
L
A
SN74AHC132  
PARAMETER  
UNIT  
MIN  
TYP  
0.45  
0.35  
4.8  
MAX  
V
V
V
V
V
Quiet output, maximum dynamic V  
0.8  
V
V
V
V
V
OL(P)  
OL(V)  
OH(V)  
IH(D)  
IL(D)  
OL  
Quiet output, minimum dynamic V  
Quiet output, minimum dynamic V  
High-level dynamic input voltage  
Low-level dynamic input voltage  
0.8  
OL  
OH  
3.5  
1.5  
NOTE 5: Characteristics are for surface-mount packages only.  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
TEST CONDITIONS  
No load, f = 1 MHz  
TYP  
UNIT  
C
Power dissipation capacitance  
11  
pF  
pd  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54AHC132, SN74AHC132  
QUADRUPLE POSITIVE-NAND GATES  
WITH SCHMITT-TRIGGER INPUTS  
SCLS365G MAY 1997 REVISED SEPTEMBER 2002  
PARAMETER MEASUREMENT INFORMATION  
V
CC  
Open  
GND  
S1  
R
= 1 kΩ  
L
TEST  
S1  
From Output  
Under Test  
Test  
Point  
From Output  
Under Test  
t
t
/t  
Open  
PLH PHL  
/t  
C
C
L
t
V
CC  
L
PLZ PZL  
/t  
(see Note A)  
(see Note A)  
GND  
PHZ PZH  
Open Drain  
V
CC  
LOAD CIRCUIT FOR  
LOAD CIRCUIT FOR  
TOTEM-POLE OUTPUTS  
3-STATE AND OPEN-DRAIN OUTPUTS  
V
CC  
50% V  
CC  
Timing Input  
0 V  
t
w
t
h
t
su  
V
CC  
V
CC  
50% V  
50% V  
CC  
Input  
CC  
50% V  
50% V  
CC  
Data Input  
CC  
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
V
CC  
CC  
Output  
Control  
50% V  
50% V  
50% V  
50% V  
t
Input  
CC  
CC  
CC  
CC  
0 V  
0 V  
t
PZL  
t
t
t
PLZ  
PLH  
PHL  
Output  
Waveform 1  
V
OH  
V  
CC  
In-Phase  
Output  
50% V  
50% V  
CC  
50% V  
CC  
CC  
V
S1 at V  
(see Note B)  
V
OL  
+ 0.3 V  
CC  
V
OL  
OL  
t
t
t
PHL  
PLH  
PZH  
PHZ  
Output  
Waveform 2  
S1 at GND  
V
V
OH  
OH  
Out-of-Phase  
Output  
V
OH  
0.3 V  
50% V  
50% V  
50% V  
CC  
CC  
CC  
V
0 V  
(see Note B)  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t 3 ns, t 3 ns.  
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.  
E. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Aug-2005  
PACKAGING INFORMATION  
Orderable Device  
SN74AHC132D  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHC132DBR  
SN74AHC132DBRE4  
SN74AHC132DE4  
SN74AHC132DGVR  
SN74AHC132DGVRE4  
SN74AHC132DR  
SSOP  
SSOP  
SOIC  
DB  
DB  
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TVSOP  
TVSOP  
SOIC  
DGV  
DGV  
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHC132DRE4  
SN74AHC132N  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
PDIP  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SN74AHC132NE4  
SN74AHC132NSR  
SN74AHC132NSRE4  
SN74AHC132PW  
PDIP  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
SO  
NS  
NS  
PW  
PW  
PW  
PW  
RGY  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
QFN  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHC132PWG4  
SN74AHC132PWR  
SN74AHC132PWRG4  
SN74AHC132RGYR  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Aug-2005  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
IMPORTANT NOTICE  
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