SCAN921260 [TI]
具有 IEEE 1149.1 和全速度 BIST 的六个 1 至 10 解串器;
| 型号： | SCAN921260 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 IEEE 1149.1 和全速度 BIST 的六个 1 至 10 解串器 |
| 文件： | 总22页 (文件大小：838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SCAN921260
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SNLS139F –DECEMBER 2001–REVISED APRIL 2013
SCAN921260 X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST
Check for Samples: SCAN921260
1
FEATURES
DESCRIPTION
The SCAN921260 integrates six deserializer devices
2
•
IEEE 1149.1 (JTAG) Compliant and At-Speed
BIST Test Modes
into
a
single chip. The SCAN921260 can
simultaneously deserialize up to six data streams that
have been serialized by the Texas Instruments
SCAN921023 Bus LVDS serializer. The device also
includes a seventh serial input channel that serves as
a redundant input.
•
•
•
Deserializes One to Six BusLVDS Input Serial
Data Streams With Embedded Clocks
Seven Selectable Serial Inputs to Support N+1
Redundancy of Deserialized Streams
Seventh Channel Has Single Pin Monitor
Output That Reflects Input From Seventh
Channel Input
Each deserializer block in the SCAN921260 operates
independently with its own clock recovery circuitry
and lock-detect signaling.
•
•
•
Parallel Clock Rate Up To 66 MHz
On Chip Filtering for PLL
The SCAN921260 uses a single +3.3V power supply
with an estimated power dissipation of 1.2W at 3.3V
with a PRBS-15 pattern. Refer to the Connection
Diagrams for packaging information.
High Impedance Inputs Upon Power Off (Vcc
0V)
=
•
•
Single Power Supply at +3.3V
196-Pin NFBGA Package (Low-Profile Ball Grid
Array) Package
•
Industrial Temperature Range Operation: −40
to +85
Functional Block Diagram
Figure 1. Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
SCAN921260
SNLS139F –DECEMBER 2001–REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating free-air temperature range (unless otherwise noted)
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to 3.9V
−0.3V to 3.9V
−0.3V to 3.9V
−0.3V to 3.9V
10ms
LVCMOS/LVTTL Input Voltage
LVCMOS/LVTTL Output Voltage
Bus LVDS Receiver Input Voltage
Bus LVDS Driver Output Voltage
Bus LVDS Output Short Circuit Duration
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
+225°C
Lead Temperature (Soldering, 10 seconds)
Max Pkg Power Dissipation Capacity @ 25°C
Package Derating:
196 NFBGA
196 NFBGA
θJA
3.7 W
29.4 mW/°C above +25°C
34°C/W
Thermal Resistance:
θJC
8°C/W
ESD Rating:
Human Body Model
Machine Model
>2KV
>750V
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications
(2) Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that
the devices should be operated at these limits. The table of Electrical Characteristics specifies conditions of device operation.
RECOMMENDED OPERATING CONDITIONS
Min
3.0
−40
20
Nom
3.3
Max
3.6
Units
V
Supply Voltage (VCC
)
Operating Free Air Temperature (TA)
Clock Rate
+25
+85
66
°C
MHz
2
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SNLS139F –DECEMBER 2001–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS(1)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS/LVTTL DC Specifications: Applies to pins in Pin Description table with type CMOS Input or Output
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Pins
2.0
VCC
0.8
V
V
Input Pins
GND
VCL
IIN
Input Pins
-0.87
-1.5
+20
VCC
0.4
V
Input Current
Vin = 0 or 3.6V, Input Pins
IOH = 6mA, Output Pins
IOL = 6mA, Output Pins
IOH = 12mA, TDO Output
IOL = 12mA, TDO Output
Vout = 0V, Output Pins
Vout = 0V, TDO Output
-20
2
uA
V
VOH
VOL
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
Output short Circuit Current
Output short Circuit Current
3
GND
2
0.18
3
V
VCC
0.4
V
GND
-15
-15
0.18
-46
V
-85
mA
mA
IOS
-120
PD* or REN = 0.8V
Vout = 0V or VCC
IOZ
Tri-state Output Current
-10
+/-0.2
+10
+50
+10
uA
Bus LVDS DC specifications: Applies to pins in Pin Description table with type Bus LVDS Inputs
VTH
VTL
Differential Threshold High Voltage VCM = 1.1V (VRI+-VRI-
Differential Threshold Low Voltage
)
+3
-2
mV
mV
-50
-10
Vin = +2.4V or 0V,
Vcc = 3.6 or 0V
IIN
Input Current
+/- 1
uA
Supply Current
3.6V, Checker Board Pattern,
CL = 15pF, 66Mhz
ICCR
Worst Case Supply Current
600
660
1
mA
mA
Supply Current when Powered
Down
PWRDN= 0.8V
REN = 0.8V
ICCXR
0.36
Timing Requirements for REFCLK
tRFCP
tRFDC
tRFCP/tTC
REFCLK Period
15.15
40
50
60
ns
%
REFCLK Duty Cycle
50
Ratio of REFCLK to TCLK
0.95
1.05
8
P
tRFTT
REFCLK Transition Time
ns
Deserializer Switching Characteristics
tRCP
tRDC
RCLK Period
RCLK
RCLK(2)
15.15
45
50
55
ns
%
RCLK Duty Cycle
50
Period of Bus LVDS signal when
CHTST is selected by MUX
tCHTST
tCLH
CHTST(3)
CL = 15pF
CL = 15pF
25
ns
ns
ns
CMOS/TTL Low-to-High Transition
Time
1.7
1.6
6
6
CMOS/TTL High-to-Low Transition
Time
tCHL
tROS
tROH
tHZR
tLZR
tZHR
tZLR
tDD
Rout Data Valid before RCLK
Rout Data Valid after RCLK
High to Tri-state Delay
Low to Tri-state Delay
Tri-state to High Delay
Tri-state to Low Delay
Deserializer Delay
CL = 15pF, see Figure 3
CL = 15pF, see Figure 3
0.35*tRCP
-0.35*tRCP
ns
ns
ns
ns
ns
ns
ns
12
12
CL = 15pF, see Figure 8
See Figure 2
12
12
1.75*tRCP +3 1.75*tRCP +7
1.75*tRCP +10.5
(1) Typical values are given for Vcc = 3.3V and TA =25°C
(2) Specified by design using statistical analysis.
(3) Because the Bus LVDS serial data stream is not decoded, the maximum frequency of the CHTST output driver could be exceeded if the
data stream were switched to CHTST. The maximum frequency of the BUS LVDS input should not exceed the parallel clock rate.
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ELECTRICAL CHARACTERISTICS(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
2
Units
us
66 MHz
20 MHz
66 MHz
20 MHz
Deserializer PLL LOCK Time from
PWRDN (with SYNCPAT)
tDSR1
See Figure 4(4)
See Figure 5(4)
10
us
1.5
5
us
Deserializer PLL Lock Time from
SYNCPAT
tDSR2
us
tRNMI-R
tRNMI-L
Ideal Strobe Window Right
Ideal Strobe Window Left
66 MHz, see Figure 11
66 MHz, see Figure 11
+400
ps
-400
ps
(4) For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and
specific conditions of the incoming data stream (SYNCPATs). tDSR1 is the time required for the deserializer to indicate lock upon power-
up or when leaving the power-down mode. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when
the input (RI+ and RI−) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). The time to lock
to random data is dependent upon the incoming data.
SCAN CIRCUITRY TIMING REQUIREMENTS
Symbol
Parameter
Conditions
Min
Typ
Max
Units
fMAX
Maximum TCK Clock
Frequency
25.0
50.0
MHz
tS
TDI to TCK, H or L
TDI to TCK, H or L
TMS to TCK, H or L
TMS to TCK, H or L
TCK Pulse Width, H or L
TRST Pulse Width, L
1.0
2.0
2.5
1.5
10.0
2.5
2.0
ns
ns
ns
ns
ns
ns
ns
tH
tS
RL = 500Ω, CL = 35 pF
tH
tW
tW
tREC
Recovery Time, TRST to
TCK
4
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SNLS139F –DECEMBER 2001–REVISED APRIL 2013
BLOCK DIAGRAM
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CONTROL PINS TRUTH TABLE
PWRDN
H
REN
H
SEL2
L
SEL1
L
SEL0
Rout(1)
CHTST
LOCK[0:5]
Active(3)
RCLK[0:5]
L
Din6 Decoded to
Rout 0 (0:9)(2)
Din0 (not decoded)
Active(4)(2)
Active(4)(2)
Active(4)(2)
Active(4)(2)
Active(4)(2)
Active(4)(2)
Active(4)(2)
Active(4)(2)
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
L
Din6 Decoded to
Rout 1 (0:9)(2)
Din1 (not decoded)
Din2 (not decoded)
Din3 (not decoded)
Din4 (not decoded)
Din5 (not decoded)
Z
Active(3)
Active(3)
Active(3)
Active(3)
Active(3)
Active(3)
Active(3)
Din6 Decoded to
Rout 2 (0:9)(2)
L
H
L
Din6 Decoded to
Rout 3 (0:9)(2)
H
H
H
H
Din6 Decoded to
Rout 4 (0:9)(2)
L
H
L
Din6 Decoded to
Rout 5 (0:9)(2)
H
H
Din6 is not
Decoded
H
Din6 is not
Decoded
Din6 (not decoded)
L
X
L
X
X
X
X
X
X
Z
Z
Z
Z
Z
Z
Z
H
Active(3)
(1) The routing of the Din inputs to the Deserializers and to the CHTST outputs are dependent on the states of SEL [0:2].
(2) Rout n[0:9] and RCLK [0:5] are tri-stated when LOCKn[0:5] is High.
(3) LOCK Active indicates that the LOCK output will reflect the state of its respective Deserializer with regard to the selected data stream.
(4) RCLK Active indicates that the RCLK will be running if the Deserializer is locked.
TIMING DIAGRAMS
Figure 2. Deserializer Delay tDD
Figure 3. Output Timing tROS and tROH
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Figure 4. Locktime from PWRDN* tDSR1
Figure 5. Locktime to SYNCPAT tDSR2
Figure 6. Unlock
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Note: CL includes Jig and stray capacitance. For the TDO output, CL = 35pF.
Figure 7. Output Load for Timing and Switching Characteristics
Note: CL includes Jig and stray capacitance. For the TDO output, CL = 35pF.
Figure 8. Deserializer Tri-state Test Circuit and Timing
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SNLS139F –DECEMBER 2001–REVISED APRIL 2013
APPLICATION INFORMATION
USING THE SCAN921023 and SCAN921260
The SCAN921260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a
BusLVDS data stream up to 660 Mbps from TI's SCAN921023 Serializer. The deserializers then recover the
embedded two clock bits and data to deliver the resulting 10-bit wide words to the output. A seventh serial data
input provides n+1 redundancy capability. The user can program the seventh input to be an alternative input to
any of the six deserializers. Whichever input is replaced by the seventh input is then routed to the CHANNEL
TEST (CHTST) pin on receiver output port. The Deserializer uses a separate reference clock (REFCLK) and an
onboard PLL to extract the clock information from the incoming data stream and then deserialize the data. The
Deserializer monitors the incoming clock information, determines lock status, and asserts the LOCKn output high
when loss of lock occurs.
Each of the 6 channels acts completely independent of each other. Each independent channel has outputs for a
10-bit wide data word, the recovered clock out, and the lock-detect output.
The SCAN921260 has three operating states: Initialization, Data Transfer, and Resynchronization. In addition,
there are two passive states: Powerdown and Tri-state.
The following sections describe each operating mode and passive state.
INITIALIZATION
Before the SCAN921260 receives and deserializes data, it and the transmitting serializer devices must initialize
the link. Initialization refers to synchronizing the Serializer's and the Deserializer's PLL's to local clocks. The local
clocks must be the same frequency or within a specified range if from different sources. After all devices
synchronize to local clocks, the Deserializers synchronize to the Serializers as the second and final initialization
step.
Step 1: After applying power to the Deserializer, the outputs are held in Tri-state and the on-chip power-
sequencing circuitry disables the internal circuits. When Vcc reaches VccOK (2.1V), the PLL in each deserializer
begins locking to the local clock (REFCLK). A local on-board oscillator or other source provides the specified
clock input to the REFCLK pin.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. Refer to the
Serializer data sheet for the proper operation during this step of the Initialization State. The Deserializer identifies
the rising clock edge in a synchronization pattern or random data and after 80 clock cycles will synchronize to the
data stream from the serializer. At the point where the Deserializer's PLL locks to the embedded clock, the
LOCKn pin goes low and valid data appears on the output. Note that this differs from previous deserializers
where the LOCKn signal was not synchronous to valid data appearing on the outputs.
DATA TRANSFER
After initialization, the serializer transfers data to the deserializers. The serial data stream includes a start and
stop bit appended by the serializer, which frame the ten data bits. The start bit is always high and the stop bit is
always low. The start and stop bits also function as clock bits embedded in the serial stream.
The Serializer transmits the data and clock bits (10+2 bits) at 12 times the TCLK frequency. For example, if
TCLK is 40 MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10 bits are from input data, the serial
'payload' rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data is 40 X 10 =
400 Mbps. TCLK is provided by the data source and must be in the range 20 MHz to 40 MHz nominal.
When one of six Deserializer channels synchronizes to the input from a Serializer, it drives its LOCKn pin low
and synchronously delivers valid data on the output. The Deserializer locks to the embedded clock, uses it to
generate multiple internal data strobes, and drives the embedded clock to the RCLKn pin. The RCLKn is
synchronous to the data on the ROUT[n0:n9] pins. While LOCKn is low, data on ROUT [n0:n9] is valid.
Otherwise, ROUT[n0:n9] is invalid.
All ROUT, LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF load) with a 66 MHz
clock. This amount of drive allows bussing outputs of two Deserializers and a destination ASIC. REN controls Tri-
state of all the outputs.
The Deserializer input pins are high impedance during Powerdown (PWRDN low) and power-off (Vcc = 0V).
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RESYNCHRONIZATION
Whenever one of the six Deserializers loses lock, it will automatically try to resynchronize. For example, if the
embedded clock edge is not detected two times in succession, the PLL loses lock and the LOCKn pin is driven
high. The system must monitor the LOCKn pin to determine when data is valid.
The user has the choice of allowing the deserializer to re-synch to the data stream or to force synchronization by
pulsing the Serializer SYNC1 or SYNC2 pin. This scheme is left up to the user discretion. One recommendation
is to provide a feedback loop using the LOCKn pin itself to control the sync request of the Serializer (SYNC1 or
SYNC2). Dual SYNC pins are given for multiple control in a multi-drop application.
POWERDOWN
The Powerdown state is a low power sleep mode that the Serializer and Deserializer typically occupy while
waiting for initialization, or to reduce power consumption when no data is transferred. The Deserializer enters
Powerdown when PWRDN is driven low. In Powerdown, the PLL stops and the outputs go into Tri-state, which
reduces supply current to the microamp range. To exit Powerdown, the system drives PWRDN high.
Upon exiting Powerdown, the Deserializer enters the Initialization state. The system must then allow time to
Initialize before data transfer can begin.
TRI-STATE
When the system drives REN pin low, the Deserializer enters Tri-state. This will tri-state the receiver output pins
(ROUT[00:59]) and RCLK[0:5]. When the system drives REN high, the Deserializer will return to the previous
state as long as all other control pins remain static (PWRDN).
IEEE 1149.1 TEST MODES
The SCAN921260 features interconnect test access that is compliant to the IEEE 1149.1 Standard for Boundary
Scan Test (JTAG). All digital TTL I/O's on the device are accessible using IEEE 1149.1, and entering this test
mode will override all input control cases including PWRDN and REN. In addition to the 4 required Test Access
Port (TAP) signals of TMS, TCK, TDI, and TDO, TRST is provided for test reset.
To supplement the test coverage provided by the IEEE 1149.1 test access to the digital TTL pins, the
SCAN921260 has two instructions to test the LVDS interconnects. The first is EXTEST. This is implemented at
LVDS levels and is only intended as a go no-go test (e.g. missing cables). The second method is the RUNBIST
instruction. It is an "at-system-speed" interconnect test. It is executed in approximately 33mS with a system clock
speed of 66MHz. There are 12 bits in the RX BIST data register for notification of PASS/FAIL and
TEST_COMPLETE; two bits for each of the six channels. The RX BIST register is defined as (from MSB to LSB):
[BIST COMPLETE for Channel 6, BIST PASS/FAIL for Channel 6, BIST COMPLETE for Channel 5, BIST
PASS/FAIL for Channel 5, BIST COMPLETE for Channel 4, BIST PASS/FAIL for Channel 4, BIST COMPLETE
for Channel 3, BIST PASS/FAIL for Channel 3, BIST COMPLETE for Channel 2, BIST PASS/FAIL for Channel 2,
BIST COMPLETE for Channel 1, BIST PASS/FAIL for Channel 1]
A "pass" indicates that the BER (Bit-Error-Rate) is better than 10-7. This is a minimum test, so a "fail" indication
means that the BER is higher than 10-7.
The BIST features of the SCAN921260 six (6) channel deserializer are compatible with the BIST features on the
SCAN921023 Serializer.
An important detail is that once both devices have the RUNBIST instruction loaded into their respective
instruction registers, both devices must move into the RTI state within 4K system clocks (At a system CLK of
66Mhz and TCK of 1MHz this allows for 66 TCK cycles). This is not a concern when both devices are on the
same scan chain or LSP, however, it can be a problem with some multi-drop devices. This test mode has been
simulated and verified using Tl's SCANSTA111.
Typical applications of 1149.1 are based around TTL-type inputs. With the introduction of 1149.1 into LVDS there
have been many hurdles to overcome. One issue is that TTL inputs and outputs do not require bias circuits and
are always on when power is applied. In the case of LVDS, there are many circuits required to make the inputs
and outputs achieve their tight tolerances. These circuits require settle time once power is applied to ensure they
function properly. These circuits are also the largest users of power within the device. To reduce power in
standby, these devices have a PWRDN pin to shut these circuits down. There is also a REN pin that
enables/disables the TTL outputs.
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In the case of the 1149.1 functionality, these circuits need appropriate time to stabilize before they can be
utilized. To achieve stability, these circuits are powered up when the TAP controller state machine is not in the
Test-Logic-Reset state. The time that it takes a TAP to traverse from Test-Logic-Reset to Capture-Data-Register
running at 25MHz is sufficient to allow these circuits to stabilize.
Once the TAP has left Test-Logic-Reset, the internal value of PWRDN is overridden and the device is powered
up. This includes all fore mentioned circuits as well as all outputs. If an application requires that the outputs are
to remain disabled during 1149.1 test, use REN and not PWRDN.
KNOWN ERRATA: On the SCAN921260 only the overridden value of PWRDN ("1") is captured during all 1149.1
tests and not the external value as seen on the pin.
BIST ALONE TEST MODES
The SCAN921260 also supports a BIST Alone feature which can be run without enabling the JTAG TAP
controller. This feature provides the ability to run continuos BER testing on all channels, or on individual channels
without affecting live traffic on other channels. The ability to run the BERT while adjacent channels are carrying
normal traffic is a useful tool to determine how normal traffic will affect BER on any given channel.
The BIST Alone features can be accessed using the 5 pins defined as BIST_SEL0, BIST_SEL1, BIST_SEL2,
BIST_ACT, and BISTMODE_REQ.
BIST_ACT activates the BIST Alone mode. The BIST Alone mode will continue until deactivated by the
BIST_ACT pin. The BIST_ACT input must be high or low for 4 or more clock cycles in order to activate or
deactivate the BIST Alone mode. The BIST_ACT input is pulled low internally.
BISTMODE_REQ is used to select either gross error reporting or a specific output error report. When the BIST
Alone mode is active, the LOCK(1:6) output for all channels running BIST Alone will go low, and ROUT(0:9)
reports any error. When BISTMODE_REQ is low the error reporting is set to Gross Mode, and whenever a bit
contains one or more errors, ROUT(0:9) for that channel goes high and stays high until deactivation by the
BIST_ACT input. When BISTMODE_REQ is high, the output error reporting is set to Bit Error mode. Whenever
any data bit contains an error, the data output for that corresponding bit goes high. The default is Gross Error
mode.
The three BIST_SELn inputs determine which channel is in BIST Alone mode according to the following table:
Table 1. BIST Alone Mode Selection
BIST_ACT
BIST_SEL2
BIST_SEL1
BIST_SEL0
BIST for Channel
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0
1
2
3
4
5
All Channels
IDLE
IDLE
POWER CONSIDERATIONS
An all CMOS design of the Deserializer makes it an inherently low power device.
POWERING UP THE DESERIALIZER
The SCAN921260 can be powered up at any time by following the proper sequence. The REFCLK input can be
running before the Deserializer powers up, and it must be running in order for the Deserializer to lock to incoming
data. The Deserializer outputs will remain in Tri-state until the Deserializer detects data transmission at its inputs
and locks to the incoming data stream.
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TRANSMITTING DATA
Once you power up the Deserializer, it must be phase locked to the transmitter to transmit data. Phase locking
occurs when the Deserializer locks to incoming data or when the Serializer sends sync patterns. The Serializer
sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCKn output of the Deserializer
remains high until it has locked to the incoming data stream. Connecting the LOCKn output of the Deserializer to
one of the SYNC inputs of the Serializer will ensure that enough SYNC patterns are sent to achieve Deserializer
lock.
The Deserializer can also lock to incoming data by simply powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
While the Deserializer LOCKn output is low, data at the Deserializer outputs (ROUT0-9) are valid, except for the
specific case of loss of lock during transmission which is further discussed in RECOVERING FROM LOCK
LOSS.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic factors include:
•
•
•
Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise)
Media: ISI, Large VCM shifts
Deserializer: VCC noise
RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data transmission, up to 1 cycle of data that was previously
received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that
invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been
lost, it is possible that data was also lost during these cycles. Therefore, after the Deserializer relocks to the
incoming data stream and the Deserializer LOCKn pin goes low, at least one previous data cycle should be
suspect for bit errors.
The Deserializer can relock to the incoming data stream by making the Serializer resend SYNC patterns, as
described above, or by random locking, which can take more time, depending on the data patterns being
received.
HOT INSERTION
All the BusLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s)
makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be
unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 11.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the SCAN921260 should be designed to provide noise-free power to the
device. Good layout practice will separate high frequency or high level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. There are a few common practices which should be followed
when designing PCB's for Bus LVDS Signaling. Recommended layout practices are:
•
Use at least 4 PCB board layers (Bus LVDS signals, ground, power, and TTL signals).
–
Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for
power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which
improves power supply filtering, especially at high frequencies, and makes the value and placement of
external bypass capacitors less critical.
•
Keep Serializers and Deserializers as close to the (Bus LVDS port side) connector as possible.
–
Longer stubs lower the impedance of the bus, increase the load on the Serializer, and lower the threshold
margin at the Deserializers. Deserializer devices should be placed much less than one inch from slot
connectors. Because transition times are very fast on the Serializer Bus LVDS outputs, reducing stub
lengths as much as possible is the best method to ensure signal integrity.
•
Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes.
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–
Surface mount capacitors placed close to power and ground pins work best. External bypass capacitors
should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range 0.001 µF to 0.1 µF. Tantalum capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for
tantalum capacitors should be at least 5X the power supply voltage being used. Randomly distributed by-
pass capacitors should also be used.
–
Package and pin layout permitting, it is also recommended to use two vias at each power pin as well as all
RF bypass capacitor terminals. Dual vias reduce the interconnect inductance between layers by up to half,
thereby reducing interconnect inductance and extending the effective frequency range of the bypass
components.
•
•
Leave unused Bus LVDS receiver inputs open (floating).
Isolate TTL signals from Bus LVDS signals.
There are more common practices which should be followed when designing PCBs for BLVDS/LVDS signaling.
General application guidelines are available in the LVDS Owner's Manual, which may be found at
www.ti.com/ww/en/analog/interface/lvds.shtml. For packaging information on BGA's, please see AN-
1126(SNOA021)
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-point configurations, through PCB trace, or through
twisted pair cable. In point-to-point configurations, the transmission media need only be terminated at the
receiver end. Please note that in point-to-point configurations, the potential of offsetting the ground levels of the
Serializer vs. the Deserializer must be considered. Also, Bus LVDS provides a +/− 1.2V common mode range at
the receiver inputs.
FAILSAFE BIASING FOR THE SCAN921260
The SCAN921260 has internal failsafe biasing and an improved input threshold sensitivity of +/− 50mV versus
+/− 100mV for the DS92LV1210 or DS92LV1212. This allows for greater differential noise margin in the
SCAN921260. However, in cases where the receiver input is not being actively driven, the increased sensitivity
of the SCAN921260 can pickup noise as a signal and cause unintentional locking. For example, this can occur
when the input cable is disconnected.
External resistors can be added to the receiver circuit board to prevent noise pick-up. Typically, the non-inverting
receiver input is pulled up and the inverting receiver input is pulled down by high value resistors. The pull-up and
pull-down resistors (R1 and R2) provide a current path through the termination resistor (RL) which biases the
receiver inputs when they are not connected to an active driver. The value of the pull-up and pull-down resistors
should be chosen so that enough current is drawn to provide a +15mV drop across the termination resistor.
Please see Figure 9 for the Failsafe Biasing Setup.
The parameter tRNM is calculated by first measuring how much of the ideal bit the receiver needs to ensure
correct sampling. After determining this amount, what remains of the ideal bit that is available for external
sources of noise is called tRNM. It is the offset from tDJIT(min or max) for the test mask within the eye opening.
The vertical limits of the mask are determined by the SCAN921260 receiver input threshold of +/− 50mV.
Please refer to the eye mask pattern of Figure 10 for a graphic representation of tDJIT and tRNM
.
Figure 9. Failsafe Biasing Setup
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Figure 10. Deterministic Jitter and ideal Bit Position
tRNMI-L is the ideal noise margin on the left of the figure, it is a negative value to indicate early with respect to ideal.
tRNMI-R is the ideal noise margin on the right of the above figure, it is a positive value to indicate late with respect to
ideal.
Figure 11. Ideal Deserializer Noise Margin (tRNMI) and Sampling Window
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PIN DIAGRAM
Figure 12. SCAN921260UJB and SCAN921260UJBX (196 pin NFBGA)
Table 2. PIN DESCRIPTIONS
Pin Name
Type
Pins
Description
These pins control which Bus LVDS input is
steered to the CHTST output. The Control Pins
Truth Table describes their function. There are
weak internal pull-ups that should default all
SEL(0:2) to high. For example, if you choose
not to use Channel Test Mode and want the
CHTST output permanently disabled, you can
tie SEL2 and SEL1 high and SEL0 low. In a
noisy operating environment, it is
CMOS
Input
SEL (0:2)
Rin +/- n
B13, C12, C13
recommended that an external pull up be used
to ensure that SELn is in the high state.
Bus LVDS
Input
A4-A3, A7-A6, A10-A9, A13-A12, C6-C5, C9-
C8, C11-C10,
Bus LVDS differential input pins
AGND
AVDD
A5, A8, B7, B8, B11
A11, B6, B9, C7
Analog Ground
Analog Voltage Supply
A low on this pin puts the device into sleep
mode and a high makes the part active. There
is an internal pull-down that defaults PWRDN to
sleep mode. Active operation requires asserting
a high on PWRDN.
CMOS
Input
PWRDN
B5
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Table 2. PIN DESCRIPTIONS (continued)
Pin Name
Type
CMOS
Pins
Description
Enables the Routn and RCLKn outputs. There
is an internal pull-down that defaults REN to tri-
state the outputs. Active outputs require
asserting a high on REN.
REN
A2
Input
CMOS
Input
REFCLK
CHTST
B4
C3
Frequency reference clock input.
CMOS
Output
Allows low speed testing of the Rin inputs
under control of the SEL (0:2) pins.
Indicates the status of the PLLs for the
individual deserializers: LOCK= L indicates
locked, LOCK= H indicates unlocked.
CMOS
Output
LOCK (0:5)
F3, P1, N3, P12, P13, D13
E2, E4, E12, E13, E14, F4, G3, G4, G11, G12,
H2, H3, H4, H11, H12, J2, J3, J11, J12, K2,
CMOS
Output
K3, K4, K12, K13, L1, L3, L6, L8, L9, L11, L12, Outputs for the ten bit deserializers, n =
Rout nx
L13, L14, M1, M2, M3, M4, M5, M6, M7, M8,
M9, M10, M11, M12, M14, N1, N2, N4, N6, N9,
N11, N12, N13, N14, P2, P3, P4, P11, P14
deserializer number, x = bit number
CMOS
Output
Recovered clock for each deserializer's output
data.
RCLK (0:5)
DVDD
F2, F13, L2, M13, N5, N10
B1, B3, C4, D6, D12, E6, E7, E9, E10, F7, F10,
F12, G6, G10, H6, H10, J5, J8, J9, J10, K5,
K6, K7, K10, L10
Digital Supply Voltage.
Digital Ground.
A1, B2, B14, D4, D5, D7, D9, D11, E5, E8, F5,
F6, F9, G5, G7, G8, G9, H5, H7, H8, H9, J6,
J7, K8, K9, L7
DGND
E1, F1, F14, G14, J1, J14, K1, K14, P5, P6,
P9, P10
PVDD
PGND
TMS
PLL Supply Voltage.
A14, B12, D10, F8, G1, G2, G13, H1, H13,
H14, J4, J13, N7, N8, P7, P8
PLL Ground.
CMOS
Input
C1
C2
D1
D2
D3
B10
Test Mode Select input to support IEEE 1149.1
Test Reset Input to support IEEE 1149.1
Test Data Input to support IEEE 1149.1
Test Clock to support IEEE 1149.1
Test Data Output to support TDO
BIST Alone Error Reporting Mode Select Input
CMOS
Input
TRST
CMOS
Input
TDI
CMOS
Input
TCK
CMOS
Output
TDO
CMOS
Input
BISTMODE_REQ
These pins control which channels are active
for the BIST Alone operation mode. The BIST
Alone Mode Selection Table describes their
function. There are internal pull-ups that default
all BIST_SEL(0:2) to high, which is the idle
state for all channels in BIST Alone mode.
CMOS
Input
BIST_SEL(0:2)
CHTST_EN
C14, D8, D14
A high on this input enables the CHTST output.
There is an internal pull-up that defaults the
CHTST output to the active mode. Note:
CHTEST_EN requires two clock cycles before
CHTST is enabled or disabled. When not using
CHTST output, assert a low on this control pin
to reduce power consumption.
CMOS
Input
E3
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Table 2. PIN DESCRIPTIONS (continued)
Pin Name
Type
Pins
Description
A high on this pin activates the BIST Alone
operating mode. There is a weak internal pull-
down that should default the BIST_ACT to de-
activate the BIST Alone operating mode. In a
noisy operating environment, it is
recommended that an external pull down be
used to ensure that BIST_ACT is in the low
state.
CMOS
Input
BIST_ACT
N/C
K11
E11, F11, L4, L5
Unused solder ball location. Do not connect.
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REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SCAN921260UJB/NOPB
ACTIVE
NFBGA
NZH
196
119
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
SCAN921260
UJB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
SCAN921260UJB/NOPB
NZH
NFBGA
196
119
7 X 17
150
322.6 135.9 7620 18.1
12.7
12.9
Pack Materials-Page 1
MECHANICAL DATA
NZH0196A
UJB196A (Rev C)
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