REF7025QFKHR [TI]

REF70 Ultra-High-Precision Voltage Reference with Low Noise and Low Drift;
REF7025QFKHR
型号: REF7025QFKHR
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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REF70 Ultra-High-Precision Voltage Reference with Low Noise and Low Drift

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REF70
SNAS781 – OCTOBER 2020  
REF70 Ultra-High-Precision Voltage Reference with Low Noise and Low Drift  
1 Features  
3 Description  
Low noise :  
The REF70 device family offers a unique combination  
of very low noise (0.22 ppmp-p), low thermal drift (2  
ppm/°C), and high accuracy (±0.025%). These  
characteristics of the REF70, when paired with high-  
resolution data converters, enable various end  
equipment to achieve their performance targets.  
– 1/f Noise (0.1 Hz to 10 Hz): 0.22 ppmp-p  
– 10 Hz to 1 kHz: 0.5 ppmrms  
Low temperature drift coefficient :  
– 2 ppm/°C (maximum for -40°C to 125°C)  
High accuracy: ±0.025% (maximum)  
Available in humidity resistance ceramic package  
(LCCC)  
Low dropout: 250 mV  
Wide input voltage: 3 V to 18 V  
Output current: ±10 mA  
High initial accuracy with very low temperature and  
long-term drift help reduce the need for frequent in  
system calibration.  
LCCC (FKH) package helps improve the long term  
drift and thermal hysteresis performance further for  
applications requiring a very stable reference.  
Industry standard voltage options: 2.5 V, 3.0 V, 3.3  
V, 4.096 V, 5.0 V  
Operating temperature range: −40°C to +125°C  
REF70 is specified for the wide temperature range of  
−40°C to +125°C. The wide temperature range  
enables the device to operate across various  
applications. Contact the TI sales representative for  
additional voltage and package options.  
2 Applications  
Precision data acquisition systems  
Industrial instrumentation  
Semiconductor test equipment  
Power monitoring  
PLC analog I/O modules  
Field transmitters  
Device Information  
PART NAME(1)  
REF7025  
PACKAGE  
BODY SIZE (NOM)  
LCCC (8)  
5.00 mm × 5.00 mm  
REF7025  
VSSOP (8)  
3.00 mm x 3.00 mm  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
2.501  
2.50075  
2.5005  
2.50025  
2.5  
VIN  
REF70  
VIN  
10µF  
+
2.49975  
2.4995  
2.49925  
2.499  
AIN+  
REFIN  
ADS124S08  
OUT  
OPS2320  
+
AIN-  
-50  
-25  
0
25 50  
Temperature (°C)  
75  
100  
125  
Output Voltage Vs Free-Air-Temperature  
Simplified Schematic  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change  
without notice.  
 
 
 
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Table of Contents  
1 Features............................................................................1  
2 Applications.....................................................................1  
3 Description.......................................................................1  
4 Revision History.............................................................. 2  
5 Device Comparison Table...............................................3  
6 Pin Configuration and Functions...................................3  
7 Specifications.................................................................. 4  
7.1 Absolute Maximum Ratings ....................................... 4  
7.2 ESD Ratings .............................................................. 4  
7.3 Recommended Operating Conditions ........................4  
7.4 Thermal Information ...................................................4  
7.5 REF7025 Electrical Characteristics ........................... 5  
7.6 Typical Characteristics................................................6  
8 Parameter Measurement Information............................9  
8.1 Solder Heat Shift.........................................................9  
8.2 Long-Term Stability................................................... 10  
8.3 Thermal Hysteresis...................................................10  
8.4 Power Dissipation..................................................... 10  
8.5 Noise Performance................................................... 11  
9 Detailed Description......................................................12  
9.1 Overview...................................................................12  
9.2 Functional Block Diagram.........................................12  
9.3 Feature Description...................................................12  
9.4 Device Functional Modes..........................................12  
10 Application and Implementation................................13  
10.1 Application Information........................................... 13  
10.2 Typical Application: Basic Voltage Reference  
Connection.................................................................. 13  
11 Power Supply Recommendation................................15  
12 Layout Guidelines....................................................... 15  
13 Layout Example...........................................................16  
14 Device and Documentation Support..........................17  
14.1 Documentation Support.......................................... 17  
14.2 Receiving Notification of Documentation Updates..17  
14.3 Support Resources................................................. 17  
14.4 Community Resources............................................17  
14.5 Trademarks.............................................................17  
14.6 Electrostatic Discharge Caution..............................17  
14.7 Glossary..................................................................17  
15 Mechanical, Packaging, and Orderable  
Information.................................................................... 17  
4 Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
DATE  
REVISION  
NOTES  
October 2020  
*
Initial APL Release  
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5 Device Comparison Table  
PRODUCT  
REF7025  
REF7030  
REF7033  
REF7040  
REF7050  
VOUT  
2.5 V  
3.0 V  
3.3 V  
4.096 V  
5.0 V  
6 Pin Configuration and Functions  
GND  
8
OUTF  
OUTS  
GND  
1
2
3
7
6
5
EN  
VIN  
GND  
4
GND  
Figure 6-1. FKH Package, 8-Pin LCCC, Top View  
GND  
1
2
8
7
EN  
VIN  
OUTF  
3
4
6
5
GND  
GND  
OUTS  
GND  
Figure 6-2. DGK Package, 8-Pin VSSOP, Top View  
Table 6-1. Pin Functions  
PIN  
FKH  
TYPE  
DESCRIPTION  
NAME  
EN  
DGK  
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Input  
Power  
Ground  
Ground  
Ground  
Input  
Enable connection. Enables or disable the device.  
VIN  
Input supply voltage connection.  
Ground connection.  
GND  
GND  
GND  
OUTS  
OUTF  
GND  
Ground connection.  
Ground connection  
Reference voltage output sense connection.  
Reference voltage output force connection.  
Ground connection.  
Output  
Ground  
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7 Specifications  
7.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
-0.3  
-0.3  
-0.3  
MAX  
UNIT  
V
Input voltage  
VIN  
EN  
20  
VIN + 0.3  
6
Enable voltage  
V
Output voltage  
VOUT  
ISC  
V
Output short circuit current  
Operating temperature range  
Storage temperature range  
40  
mA  
°C  
°C  
TA  
-55  
-65  
150  
Tstg  
170  
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not implied. These are stress ratings only and functional operation of the device at these or any other conditions  
beyond those specified in the Electrical Characteristics Table is not implied.  
7.2 ESD Ratings  
VALUE  
UNIT  
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,  
all pins(1)  
±TBD  
V(ESD)  
Electrostatic discharge  
V
Charged device model (CDM), per JEDEC specification  
JESD22-C101, all pins(2)  
±TBD  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
7.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
MIN  
NOM  
MAX  
UNIT  
VOUT + VDO  
VIN  
Input voltage  
18  
V
(1)  
EN  
IL  
Enable voltage  
0
–10  
–40  
VIN  
10  
V
Output current  
mA  
°C  
TA  
Operating temperature  
25  
125  
(1) Dropout voltage  
7.4 Thermal Information  
DEVICE  
THERMAL METRIC(1)  
FKH (CERAMIC)  
DGK (MSOP)  
8 PINS  
201.2  
UNIT  
8 PINS  
95.8  
59.0  
58.3  
48.2  
58.1  
28.5  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
85.7  
122.9  
ΨJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
21.2  
ΨJB  
121.4  
RθJC(bot)  
N/A  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
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7.5 REF7025 Electrical Characteristics  
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS  
connected to OUTF, unless otherwise noted  
PARAMETER  
TEST CONDITION  
MIN  
TYP  
MAX  
UNIT  
ACCURACY AND DRIFT  
Output voltage accuracy TA = 25°C  
–0.025  
0.025  
2
%
Output voltage  
–40°C ≤ TA ≤ 125°C  
ppm/  
temperature coefficient  
LINE AND LOAD REGULATION  
VOUT + VDO ≤ VIN ≤ 18 V  
4
5
40  
ΔVO / ΔVIN Line regulation  
ppm/V  
VOUT + VDO ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C  
IL = 0 mA to 10mA, VIN = VOUT + VDO  
100  
IL = 0 mA to 10mA, VIN = VOUT + VDO, –40°C ≤  
TA ≤ 125°C  
15  
15  
ΔVO / ΔIL  
Load regulation  
ppm/mA  
IL = 0 mA to –10mA, VIN = VOUT + VDO  
10  
IL = 0 mA to –10mA, VIN = VOUT + VDO, –40°C ≤  
TA ≤ 125°C  
NOISE  
enp-p  
en  
Low frequency noise  
Output voltage noise  
ƒ = 0.1 Hz to 10 Hz  
ƒ = 10 Hz to 1 kHz  
0.22  
0.5  
ppmp-p  
ppmrms  
HYSTERESIS AND LONG-TERM STABILITY  
Long-term stability  
0 to 250h at 35°C - FKH package  
16  
60  
ppm  
ppm  
25°C, –40°C, 125°C, 25°C (cycle 1) – FKH  
package  
Output voltage  
hysteresis  
25°C, –40°C, 125°C, 25°C (cycle 2) – FKH  
package  
60  
TURN ON TIME  
tON Turn-on time  
CAPACITIVE LOAD  
0.1% settling, COUT = 1µF  
0.5  
ms  
Stable input capacitor  
range  
CIN  
–40≤ TA ≤ 125℃  
–40≤ TA ≤ 125℃  
0.1  
1
µF  
µF  
Stable output capacitor  
range (1)  
COUT  
100  
POWER SUPPLY  
VIN Input voltage  
3
18  
6
V
TA = 25°C  
4
5
mA  
mA  
uA  
uA  
V
Active mode  
–40°C ≤ TA ≤ 125°C  
6.5  
10  
12  
IQ  
Quiescent current  
TA = 25°C  
Shutdown mode  
–40°C ≤ TA ≤ 125°C  
Active mode (EN=1)  
1.6  
VEN  
Enable pin voltage  
Enable pin current  
Shutdown mode (EN=0)  
VIN = VEN = 18V  
0.5  
3
V
1
uA  
uA  
mV  
mV  
mA  
IEN  
VIN = VEN = 18V, 40°C ≤ TA ≤ 125°C  
IL = 5mA, –40°C ≤ TA ≤ 125°C  
IL = 10mA, –40°C ≤ TA ≤ 125°C  
VOUT = 0V  
5
250  
500  
VDO  
ISC  
Dropout voltage  
Short circuit current  
35  
(1) ESR for the capacitor can range from 10mΩ to 400mΩ  
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7.6 Typical Characteristics  
at TA= 25°C, VIN= VEN= 5.5 V, IL= 0 mA, CL= 10 μF, CIN= 0.1 μF (unless otherwise noted)  
2.501  
40%  
2.50075  
2.5005  
30%  
2.50025  
2.5  
20%  
2.49975  
2.4995  
10%  
2.49925  
2.499  
-50  
-25  
0
25 50  
Temperature (°C)  
75  
100  
125  
0
Figure 7-1. Output Voltage Vs Free-Air-  
Temperature  
Temperature Drift -40èC to 125èC (ppm/èC)  
Figure 7-2. Temperature Drift Distribution (28  
Units)  
60  
50  
40  
30  
20  
10  
0
50%  
40%  
30%  
20%  
10%  
0
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (èC)  
Figure 7-4. Line Regulation vs Temperature  
Output Initial Accuracy (%)  
Figure 7-3. Accuracy Distribution  
50  
40  
30  
20  
10  
0
20  
15  
10  
5
0
-50  
-25  
0
25 50  
Temperature (°C)  
75  
100  
125  
-50  
-25  
0
25 50  
Temperature (°C)  
75  
100  
125  
Figure 7-5. Load Regulation (Sourcing) vs  
Temperature  
Figure 7-6. Load Regulation (Sinking) vs  
Temperature  
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10mA  
10 mA/div  
VIN  
-10mA  
-10mA  
5 V/div  
VOUT  
100 mV/div  
10 mV/div  
100µs/div  
200µs/div  
Figure 7-7. Line Regulation Response  
Figure 7-8. Load Transient Response (CL = 1 μF)  
6
10mA  
10 mA/div  
5
4
3
2
1
0
-10mA  
-10mA  
10 mV/div  
200µs/div  
-50  
-25  
0
25 50  
Temperature (°C)  
75  
100  
125  
Figure 7-9. Load Transient Response (CL = 10 μF)  
Figure 7-10. Quiescent Current vs Temperature  
2.4  
2
1.5  
VEN_HIGH  
VEN_LOW  
1.2  
0.9  
0.6  
0.3  
0
1.6  
1.2  
0.8  
0.4  
0
-50  
-25  
0
25 50  
Temperature (°C)  
75  
100  
125  
0
4
8 12  
Input Voltage (V)  
16  
20  
Figure 7-11. Shutdown Current vs Temperature  
Figure 7-12. Enable Threshold vs VIN  
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0.25  
-40  
25  
125  
0.2  
0.64  
0.56  
0.48  
0.4  
0.225  
0.175  
0.15  
0.125  
0.1  
0.32  
0.24  
0.16  
0.08  
0
0.075  
0.05  
0.025  
0
0
1
2
3
4
5
6
Load Current (mA)  
7
8
9
10  
Noise (ppmp-p  
)
Figure 7-13. Dropout Voltage vs Load Current  
Figure 7-14. 0.1-Hz to 10-Hz Voltage Noise  
Distribution (300 units)  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
120  
100  
CL = 10 mF  
80  
60  
40  
20  
0
10  
100  
1k  
Frequency (Hz)  
10k  
100k  
10  
100  
1k 10k  
Frequency (Hz)  
100k  
1M  
Figure 7-15. Noise Performance 10 Hz to 100 kHz  
Figure 7-16. Power-Supply Rejection Ratio vs  
Frequency  
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8 Parameter Measurement Information  
8.1 Solder Heat Shift  
The materials used in the manufacture of the REF70 have differing coefficients of thermal expansion, resulting in  
stress on the device die when the part is heated. Mechanical and thermal stress on the device die can cause the  
output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is a  
common cause of this error. In order to illustrate this effect, a total of 32 devices were soldered on two printed  
circuit boards [16 devices on each printed circuit board (PCB)] using lead-free solder paste and the paste  
manufacturer suggested reflow profile. The reflow profile is as shown in Figure 8-1. The printed circuit board is  
comprised of FR4 material. The board thickness is 1.65 mm and the area is 114 mm × 152 mm.  
300  
250  
200  
150  
100  
50  
0
0
50  
100  
150  
200  
250  
300  
350  
400  
Time (seconds)  
C01  
Figure 8-1. Reflow Profile  
The reference output voltage is measured before and after the reflow process. Although all tested units exhibit  
very low shifts (< TBD %), higher shifts are also possible depending on the size, thickness, and material of the  
printed circuit board. An important note is that the histograms display the typical shift for exposure to a single  
reflow profile. Exposure to multiple reflows, as is common on PCBs with surface-mount components on both  
sides, causes additional shifts in the output bias voltage. If the PCB is exposed to multiple reflows, the device  
must be soldered in the second pass to minimize its exposure to thermal stress.  
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8.2 Long-Term Stability  
One of the key parameters of the REF70 references is long-term stability. Typical characteristic expressed as:  
curves shows the typical drift value for the REF70 VOUT FKH is 18 ppm from 0 to 250 hours. It is important to  
understand that long-term stability is not ensured by design and that the output from the device may shift beyond  
the typical 18 ppm specification at any time. For systems that require highly stable output voltages over long  
periods of time, the designer should consider burning in the devices prior to use to minimize the amount of  
output drift exhibited by the reference over time.  
10  
0
-10  
-20  
-30  
-40  
0
50  
100  
150  
200  
250  
Time (Hr)  
Figure 8-2. Long Term Stability FKH -250 hours (VOUT  
)
8.3 Thermal Hysteresis  
Thermal hysteresis is measured with the REF70 soldered to a PCB, similar to a real-world application. Thermal  
hysteresis for the device is defined as the change in output voltage after operating the device at 25°C, cycling  
the device through the specified temperature range, and returning to 25°C. The PCB was baked at 150°C for 30  
minutes before thermal hysteresis was measured. Hysteresis can be expressed by Equation 1:  
«
÷
| VPRE - VPOST  
VNOM  
|
VHYST  
=
ì106 ppm  
(
)
(1)  
where  
VHYST = thermal hysteresis (in units of ppm)  
VNOM = the specified output voltage  
VPRE = output voltage measured at 25°C pre-temperature cycling  
VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature  
range of –40°C to +125°C and returns to 25°C.  
8.4 Power Dissipation  
The REF70 voltage references are capable of source and sink up to 10 mA of load current across the rated input  
voltage range. However, when used in applications subject to high ambient temperatures, the input voltage and  
load current must be carefully monitored to ensure that the device does not exceeded its maximum power  
dissipation rating. The maximum power dissipation of the device can be calculated with Equation 2:  
TJ = TA +P ì RqJA  
D
(2)  
where  
PD is the device power dissipation  
TJ is the device junction temperature  
TA is the ambient temperature  
RθJA is the package (junction-to-air) thermal resistance  
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Because of this relationship, acceptable load current in high temperature conditions may be less than the  
maximum current-sourcing capability of the device. In no case should the device be operated outside of its  
maximum power rating because doing so can result in premature failure or permanent damage to the device.  
8.5 Noise Performance  
Typical 1/f noise (0.1-Hz to 10-Hz) can be seen in Figure 8-3. Device noise increases with output voltage and  
operating temperature. Typically 1/f noise is not practical to filter out which makes it a key parameter for ultra-low  
noise measurements. Additional filtering can be used to improve broadband noise output noise levels, although  
care must be taken to ensure the output impedance does not degrade ac performance.  
Time 1s/div  
Figure 8-3. 0.1-Hz to 10-Hz Voltage Noise  
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9 Detailed Description  
9.1 Overview  
The REF70 is family of ultra low-noise, precision bandgap voltage references that are specifically designed for  
excellent initial voltage accuracy and drift. The Section 9.2 is a simplified block diagram of the REF70 showing  
basic band-gap topology.  
9.2 Functional Block Diagram  
VIN  
Digital  
Core  
Bandgap  
Core  
+
Reference  
Buffer  
Å
VIN  
OUTF  
OUTS  
REN  
Enable  
Controller  
EN  
GND  
9.3 Feature Description  
9.3.1 Low Temperature Drift  
The REF70 is designed for minimal drift error, which is defined as the change in output voltage over  
temperature. The drift is calculated using the box method, as described by Equation 3:  
VREF(MAX) - VREF(MIN)  
«
÷
Drift =  
ì 106  
VREF ì Temperature Range  
(3)  
9.4 Device Functional Modes  
9.4.1 EN Pin  
The EN pin of the REF70 has an internal 16 MΩ pull-up resistor (REN) to VIN. This allows the EN pin of the  
REF70 to be left floating. When the EN pin of the REF70 is pulled high, the device is in active mode. The device  
must be in active mode for normal operation. The REF70 can be placed in a low-power mode by pulling the  
ENABLE pin low. When in shutdown mode, the output of the device becomes high impedance and the quiescent  
current of the device reduces to 10 µA in shutdown mode. The EN pin must not be pulled higher than VIN supply  
voltage. See the Section 7.5 for logic high and logic low voltage levels.  
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10 Application and Implementation  
Note  
Information in the following applications sections is not part of the TI component specification, and TI  
does not warrant its accuracy or completeness. TI’s customers are responsible for determining  
suitability of components for their purposes. Customers should validate and test their design  
implementation to confirm system functionality.  
10.1 Application Information  
As this device has many applications and setups, there are many situations that this datasheet can not  
characterize in detail. Basic applications include positive/negative voltage reference and data acquisition  
systems. The table below shows the typical application of REF70 and its companion data converters.  
Application  
Data Converter  
Precision Data Acquisition  
Industrial Instrumentation  
Semiconductor Test  
ADS8900B, ADS1278, ADS1262, DAC80501, DAC8562  
ADS127L01, ADS8699, ADS1256, ADS1251, DAC9881, DAC8811,  
DAC1220, DAC80508  
ADS8598H, ADS131M08, ADS8686S, ADS8881, DAC11001A,  
DAC7744,  
Power Monitoring, PLC Analog I/O  
Field Transmitters  
ADS131E04, ADS131A02,  
ADS1247, ADS1220  
10.2 Typical Application: Basic Voltage Reference Connection  
The circuit shown in Figure 10-1 shows the basic configuration for the REF70 references. Connect bypass  
capacitors according to the guidelines in Section 10.2.2.1.  
VIN  
REF70  
VIN  
10µF  
+
AIN+  
REFIN  
OUT  
ADS124S08  
OPS2320  
+
AIN-  
Figure 10-1. Basic Reference Connection  
10.2.1 Design Requirements  
A detailed design procedure is based on a design example. For this design example, use the parameters listed  
in Table 10-1 as the input parameters.  
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Table 10-1. Design Example Parameters  
DESIGN PARAMETER  
VALUE  
Input voltage VIN  
5.5 V  
2.5 V  
10 µF  
10 µF  
Output voltage VOUT  
REF7025 input capacitor  
REF7025 output capacitor  
10.2.2 Detailed Design Procedure  
10.2.2.1 Input and Output Capacitors  
A 1-μF to 10-μF electrolytic or ceramic capacitor can be connected to the input to improve transient response in  
applications where the supply voltage may fluctuate. Connect an additional 0.1-μF ceramic capacitor in parallel  
to reduce high frequency supply noise.  
A low ESR capacitor of 1-μF to 100-μF must be connected to the output to improve stability and help filter out  
high frequency noise. Best performance and stability is attained with low-ESR output capacitors (X5R, X7R, or  
similar) with an ESR of 100 mΩ or less. For very low noise applications, special care must be taken with X7R  
and other MLCC capacitors due to their piezoelectric effect. The inherit piezoelectric effect can cause a  
mechanical vibration which appears as noise in the μV range which can dominate the noise of the REF70. It is  
recommended to use film capacitors for noise sensitive applications.  
10.2.2.2 4-Wire Kelvin Connections  
Current flowing through a PCB trace produces an IR voltage drop, and with longer traces, this drop can reach  
several millivolts or more, introducing a considerable error into the output voltage of the reference. A 1-inch long,  
5-millimeter wide trace of 1-ounce copper has a resistance of approximately 100 mΩ at room temperature; at a  
load current of 10 mA, this can introduce a full millivolt of error. In an ideal board layout, the reference must be  
mounted as close as possible to the load to minimize the length of the output traces, and, therefore, the error  
introduced by voltage drop. However, in applications where this is not possible or convenient, force and sense  
connections (sometimes referred to as Kelvin sensing connections) are provided as a means of minimizing the  
IR drop and improving accuracy.  
Kelvin connections work by providing a set of high impedance voltage-sensing lines to the output and ground  
nodes. Because very little current flows through these connections, the IR drop across their traces is negligible,  
and the output and ground  
It is always advantageous to use Kelvin connections whenever possible. However, in applications where the IR  
drop is negligible or an extra set of traces cannot be routed to the load, the force and sense pins for both VOUT  
and GND can simply be tied together, and the device can be used in the same fashion as a normal 3-terminal  
reference.  
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11 Power Supply Recommendation  
The REF70 family of references features a low-dropout voltage. These references can be operated with a supply  
of only 50 mV above the output voltage for 0-mA output current conditions. The dropout voltage will vary with the  
output current so refer to the dropout voltage to see typical dropout voltage requirements. TI recommends a  
supply bypass capacitor ranging between 0.1 µF to 10 µF.  
During start-up the REF70 can experience moments of high input current due to the output capacitors. The input  
current can momentarily rise to ISC  
.
0.25  
0.225  
0.2  
-40  
25  
125  
0.175  
0.15  
0.125  
0.1  
0.075  
0.05  
0.025  
0
0
1
2
3
4
5
6
Load Current (mA)  
7
8
9
10  
Figure 11-1. Dropout Voltage  
12 Layout Guidelines  
Figure 13-1 illustrates an example of a PCB layout for a data acquisition system using the REF70. Some key  
considerations are:  
Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN of the REF70.  
Connect low-ESR, 1-uF to 100-uF capacitor at OUTF of the REF70.  
Decouple other active devices in the system per the device specifications.  
Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise  
pickup.  
Place the external components as close to the device as possible. This configuration prevents parasitic errors  
(such as the Seebeck effect) from occurring.  
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if  
possible, and only make perpendicular crossings when absolutely necessary.  
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13 Layout Example  
Analog GND  
GND  
8
OUTF  
6 OUTS  
GND  
7
EN 1  
VIN  
GND 3  
Input Voltage  
VREF  
C
C
2
5
4
GND  
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Figure 13-1. Layout Example  
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14 Device and Documentation Support  
14.1 Documentation Support  
14.1.1 Related Documentation  
For related documentation see the following:  
Voltage Reference Design Tips For Data Converters  
Voltage Reference Selection Basics  
14.2 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on Alert me to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
14.3 Support Resources  
TI E2Esupport forums are an engineer's go-to source for fast, verified answers and design help — straight  
from the experts. Search existing answers or ask your own question to get the quick design help you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do  
not necessarily reflect TI's views; see TI's Terms of Use.  
14.4 Community Resources  
14.5 Trademarks  
TI E2Eis a trademark of Texas Instruments.  
All other trademarks are the property of their respective owners.  
14.6 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
14.7 Glossary  
TI Glossary  
This glossary lists and explains terms, acronyms, and definitions.  
15 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical packaging and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGE OPTION ADDENDUM  
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10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
PREF7025QFKHR  
REF7025QFKHR  
REF7025QFKHT  
ACTIVE  
LCCC  
LCCC  
LCCC  
FKH  
8
8
8
3000 RoHS (In work)  
& Non-Green  
Call TI  
Call TI  
Call TI  
Call TI  
-40 to 125  
-40 to 125  
-40 to 125  
PREVIEW  
PREVIEW  
FKH  
4000 RoHS (In work)  
& Non-Green  
Call TI  
Call TI  
FKH  
250  
RoHS (In work)  
& Non-Green  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
IMPORTANT NOTICE AND DISCLAIMER  
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Copyright © 2020, Texas Instruments Incorporated  

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