REF2125IDBVR [TI]
具有零噪声启动功能的低漂移、低功耗、小型串联电压基准 | DBV | 5 | -40 to 125;
| 型号： | REF2125IDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有零噪声启动功能的低漂移、低功耗、小型串联电压基准 | DBV | 5 | -40 to 125 光电二极管 |
| 文件： | 总28页 (文件大小：2071K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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REF2125
ZHCSGP1 –SEPTEMBER 2017
REF2125 具有干净启动功能的低漂移、低功耗、小型串联
电压基准
1 特性
3 说明
1
•
初始精度：±0.05%（最大值）
温度系数：6ppm/°C（最大值）
REF2125 器件是低温度漂移(6ppm/°C)、低功耗、高
精度 CMOS 电压基准，具有 ±0.05% 初始精度、低运
行电流以及小于 95μA 的功耗。该器件还提供 5μVp-p/V
的极低输出噪声，这使得它在用于高分辨率数据转换器
和噪声关键应用时能够保持高度的信号完整性。
•
•
•
•
•
•
•
•
运行温度范围：−40°C 至 +125°C
输出电流：±10mA
低静态电流：95μA（最大值）
宽输入电压：12V
该器件的低输出电压迟滞和低长期输出电压漂移进一步
提高了稳定性和系统可靠性。此外，器件的小尺寸和低
运行电流 (95μA) 使其非常适合便携式和电池供电的应
用 。
输出 1/f 噪声（0.1Hz 至 10Hz）：5µVPP/V
出色的长期稳定性（30ppm/1000 小时）
小型 5 引脚 SOT-23 封装
2 应用
REF2125 具有宽额定温度范围（−40°C 至 +125°
C）。有关其他电压选项，请联系 TI 销售代表。
•
•
•
•
•
•
•
•
精密数据采集系统
电源监控
器件信息(1)
PLC 模拟 I/O 模块
工业仪表
部件名称
REF2125
封装
SOT-23 (5)
封装尺寸（标称值）
2.90mm × 1.60mm
场发射器
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
测试设备
4 - 20mA 环路传感器
LCR 表
简化电路原理图
10 ꢀ
10 ꢀ
124 ꢀ
-
ADS1287
REF
Input Signal
1 nF
+
VIN
REF21xx
CIN
1µF
COUT
10 µF
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS798
REF2125
ZHCSGP1 –SEPTEMBER 2017
www.ti.com.cn
目录
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 16
Applications and Implementation ...................... 18
9.1 Application Information............................................ 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Parameter Measurement Information ................ 11
7.1 Solder Heat Shift..................................................... 11
7.2 Long-Term Stability................................................. 12
7.3 Thermal Hysteresis ................................................. 12
7.4 Power Dissipation ................................................... 13
7.5 Noise Performance ................................................. 14
Detailed Description ............................................ 15
9
9.2 Typical Application: Basic Voltage Reference
Connection............................................................... 18
10 Power-Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 器件和文档支持 ..................................................... 21
12.1 文档支持................................................................ 21
12.2 接收文档更新通知 ................................................. 21
12.3 社区资源................................................................ 21
12.4 商标....................................................................... 21
12.5 静电放电警告......................................................... 21
12.6 Glossary................................................................ 21
13 机械、封装和可订购信息....................................... 21
7
8
4 修订历史记录
日期
修订版本
说明
2017 年 9 月
*
初始发行版
2
Copyright © 2017, Texas Instruments Incorporated
REF2125
www.ti.com.cn
ZHCSGP1 –SEPTEMBER 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
1
5
EN
GND
2
VIN
3
4
CS
VOUT
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
EN
Input
Power
Input
Enable connection. Enables or disables the device.
Input supply voltage connection.
2
VIN
3
CS
Clean start pin. Connect to a resistor or capacitor to enable the clean start feature.
4
VOUT
GND
Output
Ground
Reference voltage output.
Ground connection.
5
Copyright © 2017, Texas Instruments Incorporated
3
REF2125
ZHCSGP1 –SEPTEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VREF + 0.05
–0.3
MAX
13
UNIT
IN
Input voltage
EN
V
IN + 0.3
5.5
Output voltage
VREF
–0.3
V
Output short circuit current
20
mA
Operating, TA
Storage Tstg
–55
–65
150
Temperature
°C
170
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
12
UNIT
(1)
IN
EN
IL
Supply input voltage (IL = 0 mA, TA = 25°C)
Enable voltage
VREF + VDO
V
V
0
IN
Output current
–10
–40
10
mA
°C
TA
Operating temperature
25
125
(1) Dropout voltage.
6.4 Thermal Information
REF2125
THERMAL METRIC(1)
DBV (SOT-23)
6 PINS
185
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
156
29.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
33.8
ψJB
29.1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
REF2125
www.ti.com.cn
ZHCSGP1 –SEPTEMBER 2017
6.5 Electrical Characteristics
At TA = 25°C unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage
accuracy
–0.05%
0.05%
6
–40°C ≤ TA ≤ 125°C
Output voltage
temperature
coefficient(1)
2.5
2
ppm/°C
ppm/V
LINE AND LOAD REGULATION
VIN = 2.55 V to 12 V , TA = 25°C
VIN = VREF + VDO(2) to 12 V, −40°C ≤ TA
125°C
≤
ΔV(OΔVIN)
Line regulation
15
30
IL = 0 mA to 10 mA, VIN = 3 V,
TA = 25°C
Sourcing
Sourcing
Sinking
20
40
IL = 0 mA to 10 mA, VIN = 3 V,
−40°C ≤ TA ≤ 125°C
ΔV(OΔIL)
Load regulation
ppm/mA
IL = 0 mA to –10 mA, VIN
VREF+ VDO(2), TA = 25°C
=
=
IL = 0 mA to –10 mA, VIN
VREF+ VDO(2), −40°C ≤ TA
≤
Sinking
70
125°C
VREF = 0, CCS = No connect, TA = 25°C
Short-circuit current(3) RCS = 500kΩ, TA = 25°C
18
7
mA
mA
mA
ISC
CCS = GND, TA = 25°C
0.5
NOISE
ƒ = 0.1 Hz to 10 Hz
ƒ = 10 Hz to 10 kHz
5
μV p-p/V
μV rms
Output voltage
noise(4)
en p-p
24
Output voltage noise
density
en
ƒ = 1 kHz
0.25
ppm/√Hz
HYSTERESIS AND LONG TERM STABILITY
Long-term stability(5)
1000 hours
30
30
10
ppm
ppm
TA = 25°C to −40°C to 125°C to 25°C, Cycle 1
TA = 25°C to −40°C to 125°C to 25°C, Cycle 2
Output voltage
hysteresis(6)
TURNON
0.1% of output voltage settling, CL = 10 µF,
REF2125
tON
Turnon time
2.5
ms
CAPACITIVE LOAD
Stable output
capacitor value
OUTPUT VOLTAGE
VREF Output voltage
CL
−40°C ≤ TA ≤ 125°C
0.1
10
µF
V
REF2125
2.5
(1) Temperature drift is specified according to the box method. See Feature Description for more details.
(2) Dropout voltage under test condition is 100mV.
(3) In clean start section it is referred as IPEAK
.
(4) The peak-to-peak noise measurement procedure is explained in more detail in Noise Performance.
(5) Long-term stability measurement procedure is explained in more in detail in Long-Term Stability.
(6) The thermal hysteresis measurement procedure is explained in more detail in Thermal Hysteresis.
Copyright © 2017, Texas Instruments Incorporated
5
REF2125
ZHCSGP1 –SEPTEMBER 2017
www.ti.com.cn
Electrical Characteristics (continued)
At TA = 25°C unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage
VREF + VDO
12
V
VIN = VREF + VDO(2) to 12 V
VIN = VREF + VDO(2) to 12 V
Sourcing
Sinking
10
Output current
capacity
IL
mA
–10
−40°C ≤ TA ≤ 125°C
Active mode
72
2.5
50
95
3
IQ
Quiescent current
µA
Shutdown
mode
−40°C ≤ TA ≤ 125°C
IL = 0 mA, TA= 25°C
VDO
Dropout voltage
IL = 0 mA, −40°C ≤ TA ≤ +125°C
IL = 10 mA, −40°C ≤ TA ≤ +125°C
100
500
mV
Voltage reference in active mode (EN = 1)
Voltage reference in shutdown mode (EN = 0)
1.6
VEN
IEN
ENABLE pin voltage
V
0.5
2
ENABLE pin leakage
current
ENABLE = VIN, −40°C ≤ TA ≤ 125°C
1
µA
6
Copyright © 2017, Texas Instruments Incorporated
REF2125
www.ti.com.cn
ZHCSGP1 –SEPTEMBER 2017
6.6 Typical Characteristics
at TA = 25°C, VIN = VEN = 12 V, IL = 0 mA , CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
0.02
0.015
0.01
0.005
0
-0.005
-0.01
-0.015
-0.02
-50
-25
0
25
50
75
100
125
D001
Temperature (°C)
D002
Drift (ppm/°C)
(-40°C to 125°C)
Figure 1. Temperature Drift
Figure 2. Output Voltage Accuracy vs Temperature
75
74.5
74
-20
-40
CL = 1uF
CL = 10uF
73.5
73
-60
-80
72.5
72
-100
71.5
71
-120
-50
-25
0
25
50
75
100
125
10
100
1k
10k
100k
Temperature (°C)
Frequency (Hz)
D004
D005
Figure 3. Quiescent Current vs Temperature
Figure 4. Power-Supply Rejection Ratio vs Frequency
800
720
640
560
480
400
320
240
160
80
ILOAD
+1mA
+1mA
-1mA
1mA/div
4mV/div
VOUT
0
10
250µs/div
100
1k
10k
100k
Frequency(Hz)
(CL = 1µF, IOUT = 1mA)
D010
D009
Figure 6. Load Transient
Figure 5. Noise Performance 10 Hz to 10 kHz
Copyright © 2017, Texas Instruments Incorporated
7
REF2125
ZHCSGP1 –SEPTEMBER 2017
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Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = 12 V, IL = 0 mA , CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
ILOAD
ILOAD
+1mA
+10mA
+10mA
+1mA
10mA/div
-1mA
-10mA
1mA/div
4mV/div
VOUT
VOUT
100mV/div
250µs/div
250µs/div
(CL = 10µF, IOUT = 1mA)
(CL = 1µF, IOUT = 10mA)
D010
D010
D011
D010
Figure 7. Load Transient
Figure 8. Load Transient
ILOAD
-10mA
+10mA
10mA/div
20mV/div
VIN
4V/div
+10mA
VOUT
VOUT
15mV/div
250µs/div
(CL = 1µF)
250µs/div
D011
(CL = 10µF, IOUT = 10mA)
Figure 9. Load Transient
Figure 10. Line Transient
VIN
En
4V/div
1V/div
VOUT
5mV/div
VOUT
250µs/div
0.5ms/div
(CL = 10µF)
D018
Figure 12. Start-Up
Figure 11. Line Transient
8
Copyright © 2017, Texas Instruments Incorporated
REF2125
www.ti.com.cn
ZHCSGP1 –SEPTEMBER 2017
Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = 12 V, IL = 0 mA , CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
2.6
2.5
2.4
2.3
2.2
2.1
2
30%
25%
20%
15%
10%
5%
0
-40
-15
10
35
60
85
110 125
D016
Temperature (°C)
Thermal Hysteresis - Cycle 1 (ppm)
D013
Figure 14. Thermal Hysteresis Distribution (Cycle 1)
Figure 13. Quiescent Current Shutdown Mode
50%
30%
25%
20%
15%
10%
5%
40%
30%
20%
10%
0
0
D017
D016
Solder Heat Shift (%)
Thermal Hysteresis - Cycle 2 (ppm)
Refer to Solder Heat Shift for more information
Figure 16. Solder Heat Shift Distribution
Figure 15. Thermal Hysteresis Distribution (Cycle 2)
0.24
0.23
0.22
0.21
0.2
8.7
8.4
8.1
7.8
7.5
7.2
6.9
6.6
6.3
6
0.19
0.18
0.17
0.16
0.15
0.14
0.13
5.7
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D019
D020
Figure 17. Line Regulation
Figure 18. Load Regulation Sourcing
Copyright © 2017, Texas Instruments Incorporated
9
REF2125
ZHCSGP1 –SEPTEMBER 2017
www.ti.com.cn
Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = 12 V, IL = 0 mA , CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
55
52.5
50
47.5
45
42.5
40
37.5
35
32.5
30
Time 1s/div
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
D08_
D021
Figure 20. 0.1-Hz to 10-Hz Noise (VREF
)
Figure 19. Load Regulation Sinking
65
55
45
35
25
15
5
-5
-15
-25
0
100 200 300 400 500 600 700 800 900 1000
Hours
D015
Figure 21. Long Term Stability - 1000 hours (VREF
)
10
Copyright © 2017, Texas Instruments Incorporated
REF2125
www.ti.com.cn
ZHCSGP1 –SEPTEMBER 2017
7 Parameter Measurement Information
7.1 Solder Heat Shift
The materials used in the manufacture of the REF2125 have differing coefficients of thermal expansion, resulting
in stress on the device die when the part is heated. Mechanical and thermal stress on the device die can cause
the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is a
common cause of this error.
In order to illustrate this effect, a total of 32 devices were soldered on four printed circuit boards [16 devices on
each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow
profile. The reflow profile is as shown in Figure 22. The printed circuit board is comprised of FR4 material. The
board thickness is 1.65 mm and the area is 114 mm × 152 mm.
300
250
200
150
100
50
0
0
50
100
150
200
250
300
350
400
Time (seconds)
C01
Figure 22. Reflow Profile
The reference and bias output voltages are measured before and after the reflow process; the typical shift is
displayed in Figure 23. Although all tested units exhibit very low shifts (< 0.01%), higher shifts are also possible
depending on the size, thickness, and material of the printed circuit board. An important note is that the
histograms display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is
common on PCBs with surface-mount components on both sides, causes additional shifts in the output bias
voltage. If the PCB is exposed to multiple reflows, solder the device in the second pass to minimize its exposure
to thermal stress.
50%
40%
30%
20%
10%
0
D017
Solder Heat Shift (%)
Figure 23. Solder Heat Shift Distribution, VREF (%)
Copyright © 2017, Texas Instruments Incorporated
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ZHCSGP1 –SEPTEMBER 2017
www.ti.com.cn
7.2 Long-Term Stability
One of the key parameters of the REF2125 reference is long-term stability. Typical characteristic expressed as:
curves shows the typical drift value for the REF2125 is 30 ppm from 0 to 1000 hours. This parameter is
characterized by measuring 32 units at regular intervals for a period of 1000 hours. It is important to understand
that long-term stability is not ensured by design and that the output from the device may shift beyond the typical
30 ppm specification at any time. For systems that require highly stable output voltages over long periods of
time, the designer should consider burning in the devices prior to use to minimize the amount of output drift
exhibited by the reference over time
65
55
45
35
25
15
5
-5
-15
-25
0
100 200 300 400 500 600 700 800 900 1000
Hours
D015
Figure 24. Long Term Stability - 1000 hours (VREF
)
7.3 Thermal Hysteresis
Thermal hysteresis is measured with the REF2125 soldered to a PCB, similar to a real-world application.
Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C,
cycling the device through the specified temperature range, and returning to 25°C. Hysteresis can be expressed
by Equation 1:
≈
∆
«
’
÷
◊
| VPRE - VPOST
|
VHYST
=
ì106 ppm
(
)
VNOM
where
•
•
•
•
VHYST = thermal hysteresis (in units of ppm)
VNOM = the specified output voltage
VPRE = output voltage measured at 25°C pre-temperature cycling
VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature
range of –40°C to +125°C and returns to 25°C.
(1)
Typical thermal hysteresis distribution is as shown in Figure 25.
12
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REF2125
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ZHCSGP1 –SEPTEMBER 2017
Thermal Hysteresis (continued)
30%
25%
20%
15%
10%
5%
0
D016
Thermal Hysteresis - Cycle 1 (ppm)
Figure 25. Thermal Hysteresis Distribution (VREF
)
7.4 Power Dissipation
The REF2125 voltage reference is capable of source and sink up to 10 mA of load current across the rated input
voltage range. However, when used in applications subject to high ambient temperatures, the input voltage and
load current must be carefully monitored to ensure that the device does not exceeded its maximum power
dissipation rating. The maximum power dissipation of the device can be calculated with Equation 2:
TJ = TA +P ì RqJA
D
where
•
•
•
•
PD is the device power dissipation
TJ is the device junction temperature
TA is the ambient temperature
RθJA is the package (junction-to-air) thermal resistance
(2)
Because of this relationship, acceptable load current in high temperature conditions may be less than the
maximum current-sourcing capability of the device. In no case should the part be operated outside of its
maximum power rating because doing so can result in premature failure or permanent damage to the device.
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REF2125
ZHCSGP1 –SEPTEMBER 2017
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7.5 Noise Performance
Typical 0.1-Hz to 10-Hz voltage noise can be seen in Figure 26 . Device noise increases with output voltage and
operating temperature. Additional filtering can be used to improve output noise levels, although care must be
taken to ensure the output impedance does not degrade ac performance. Peak-to-peak noise measurement
setup is shown in Figure 26.
Time 1s/div
D08_
Figure 26. 0.1-Hz to 10-Hz Noise (VREF
)
14
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REF2125
www.ti.com.cn
ZHCSGP1 –SEPTEMBER 2017
8 Detailed Description
8.1 Overview
The REF2125 is part of a family of low-noise, precision bandgap voltage references that are specifically designed
for excellent initial voltage accuracy and drift. The Functional Block Diagram is a simplified block diagram of the
REF2125 showing basic band-gap topology.
8.2 Functional Block Diagram
Enable
Blocks
EN
IN
GND
Vdd
Digital
Clean
Start
Bandgap
core
CS
Buffer
OUT
Copyright © 2017, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Supply Voltage
The REF2125 family of references features an extremely low dropout voltage. The REF2125 can be operated
with a supply of only 1 mV above the output voltage in an unloaded condition. For loaded conditions, a typical
dropout voltage versus load is shown on the front page. The REF2125 features a low quiescent current that is
extremely stable over changes in both temperature and supply. The typical room temperature quiescent current
is 72 μA, and the maximum quiescent current over temperature is just 95 μA. Supply voltages below the
specified levels can cause the REF2125 to momentarily draw currents greater than the typical quiescent current.
Use a power supply with a fast rising edge and low output impedance to easily prevent this issue.
8.3.2 Low Temperature Drift
The REF2125 is designed for minimal drift error, which is defined as the change in output voltage over
temperature. The drift is calculated using the box method, as described by Equation 3:
VREF(MAX) - VREF(MIN)
≈
∆
«
’
÷
◊
Drift =
ì 106
VREF ì Temperature Range
(3)
8.3.3 Load Current
The REF2125 family is specified to deliver a current load of ±10 mA per output. The VREF output of the device
are protected from short circuits by limiting the output short-circuit current to 18 mA. The device temperature
increases according to Equation 4:
TJ = TA +P ì RqJA
D
where
•
•
•
•
TJ = junction temperature (°C),
TA = ambient temperature (°C),
PD = power dissipated (W), and
RθJA = junction-to-ambient thermal resistance (°C/W)
(4)
15
The REF2125 maximum junction temperature must not exceed the absolute maximum rating of 150°C.
Copyright © 2017, Texas Instruments Incorporated
REF2125
ZHCSGP1 –SEPTEMBER 2017
www.ti.com.cn
Feature Description (continued)
8.3.4 Clean Start Feature
In many applications (for example, loop powered applications), the supply at VIN has inductive impedance. This
can cause the supply to dip during start-up because of the large output capacitor connected to the voltage
reference and the inductive supply. The REF2125 family has an internal clean start block to control the peak of
the inrush current during start-up. This feature is illustrated in Functional Block Diagram. The peak of inrush
current can be calculated as Equation 5:
IPEAK ö 466mA +13.54mAìRCS
where
•
•
IPEAK = Peak of inrush current (µA), has a range of [0.5 mA, 19 mA],
Rcs = External resistor connected to the CS pin
(5)
During power up, IPEAK is split between the device current and output current. The output current (IOUT) is split
between output capacitor and load current (ILOAD). The device current can be estimated to be IQ+IOUT/183, where
IQ is quiescent current at no load. Hence for a given ILOAD it is important to choose Rcs such that IPEAK is larger
than ILOAD. Above equations capture typical characteristics and hence it is suggested to include ±25% margins
while budgeting for inrush current and also while choosing Rcs for a given ILOAD. This inrush current continues to
stay at the limiting value (IPEAK) till output reaches close to VREF (2.5 V).
When a Ccs is also connected in parallel to Rcs, The inrush current limit shall rise exponentially to the steady
state value (IPEAK) as calculated using above equations, with a time constant of Rcs × Ccs. Hence the initial (and
maximum) rate of rise of inrush current shall be IPEAK /(Rcs × Ccs). Because the inrush current rate is limited, the
loop powered supply dip is controlled.
8.4 Device Functional Modes
8.4.1 EN Pin
When the ENABLE pin of the REF2125 is pulled high, the device is in active mode. The device must be in active
mode for normal operation. The REF2125 can be placed in a low-power mode by pulling the ENABLE pin low.
When in shutdown mode, the output of the device becomes high impedance and the quiescent current of the
device reduces to 2 µA in shutdown mode. The EN pin must not be pulled higher than VIN supply voltage. See
the Thermal Information for logic high and logic low voltage levels.
8.4.2 Negative Reference Voltage
For applications requiring a negative and positive reference voltage, the REF2125 and OPA735 can be used to
provide a dual-supply reference from a 5-V supply. Figure 27 shows the REF2125 used to provide a 2.5-V supply
reference voltage. The low drift performance of the REF2125 complements the low offset voltage and zero drift of
the OPA735 to provide an accurate solution for split-supply applications. Take care to match the temperature
coefficients of R1 and R2.
16
Copyright © 2017, Texas Instruments Incorporated
REF2125
www.ti.com.cn
ZHCSGP1 –SEPTEMBER 2017
Device Functional Modes (continued)
+5V
1
2
REF2125
4
+2.5V
3
5
R1
10 kΩ
R2
10 kΩ
RCS
CCS
_
-2.5V
OPA735
+
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 27. REF2125 and OPA735 Create Positive and Negative Reference Voltages
Copyright © 2017, Texas Instruments Incorporated
17
REF2125
ZHCSGP1 –SEPTEMBER 2017
www.ti.com.cn
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
As this device has many applications and setups, there are many situations that this datasheet can not
characterize in detail. Basic applications includes positive/negative voltage reference and data acquisition
systems. For more information see application sections in the REF32xx data sheet.
9.2 Typical Application: Basic Voltage Reference Connection
The circuit shown in Figure 28 shows the basic configuration for the REF2125 references. Connect bypass
capacitors according to the guidelines in Input and Output Capacitors.
10 ꢀ
10 ꢀ
124 ꢀ
-
ADS1287
REF
Input Signal
1 nF
+
VIN
REF21xx
CIN
1µF
COUT
10 µF
Copyright © 2017, Texas Instruments Incorporated
Figure 28. Basic Reference Connection
9.2.1 Design Requirements
A detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 1 as the input parameters.
Table 1. Design Example Parameters
DESIGN PARAMETER
Input voltage VIN
VALUE
5 V
Output voltage VOUT
2.5 V
1 µF
REF2125 input capacitor
REF2125 output capacitor
10 µF
9.2.2 Detailed Design Procedure
9.2.2.1 Input and Output Capacitors
A 1-μF to 10-μF electrolytic or ceramic capacitor can be connected to the input to improve transient response in
applications where the supply voltage may fluctuate. Connect an additional 0.1-μF ceramic capacitor in parallel to
reduce high frequency supply noise.
A ceramic capacitor of at least 0.1 μF must be connected to the output to improve stability and help filter out high
frequency noise. An additional 1-μF to 10-μF electrolytic or ceramic capacitor can be added in parallel to improve
transient performance in response to sudden changes in load current; however, keep in mind that doing so
increases the turnon time of the device.
18
Copyright © 2017, Texas Instruments Incorporated
REF2125
www.ti.com.cn
ZHCSGP1 –SEPTEMBER 2017
Best performance and stability is attained with low-ESR, low-inductance ceramic chip-type output capacitors
(X5R, X7R, or similar). If using an electrolytic capacitor on the output, place a 0.1-μF ceramic capacitor in parallel
to reduce overall ESR on the output.
9.2.2.2 VIN Slew Rate Considerations
In applications with slow-rising input voltage signals, the reference exhibits overshoot or other transient
anomalies that appear on the output. These phenomena also appear during shutdown as the internal circuitry
loses power.
To avoid such conditions, ensure that the input voltage wave-form has both a rising and falling slew rate close to
6 V/ms.
9.2.2.3 Shutdown/Enable Feature
The REF2125 references can be switched to a low power shut-down mode when a voltage of 0.5 V or lower is
input to the ENABLE pin. Likewise, the reference becomes operational for ENABLE voltages of 1.6 V or higher.
During shutdown, the supply current drops to less than 2 μA, useful in applications that are sensitive to power
consumption.
If using the shutdown feature, ensure that the ENABLE pin voltage does not fall between 0.5 V and 1.6 V
because this causes a large increase in the supply current of the device and may keep the reference from
starting up correctly. If not using the shutdown feature, however, the ENABLE pin can simply be tied to the IN
pin, and the reference remains operational continuously.
9.2.3 Application Curves
75
74.5
74
2.6
2.5
2.4
2.3
2.2
2.1
2
73.5
73
72.5
72
71.5
71
-50
-25
0
25
50
75
100
125
-40
-15
10
35
60
85
110 125
Temperature (°C)
Temperature (°C)
D004
D013
Figure 29. Quiescent Current vs Temperature
Figure 30. Quiescent Current Shutdown Mode
10 Power-Supply Recommendations
The REF2125 family of references feature an extremely low-dropout voltage. These references can be operated
with a supply of only 50 mV above the output voltage. TI recommends a supply bypass capacitor ranging
between 0.1 µF to 10 µF.
Copyright © 2017, Texas Instruments Incorporated
19
REF2125
ZHCSGP1 –SEPTEMBER 2017
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
Figure 31 illustrates an example of a PCB layout for a data acquisition system using the REF2125. Some key
considerations are:
•
•
•
•
Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF of the REF2125.
Decouple other active devices in the system per the device specifications.
Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
•
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
11.2 Layout Example
EN
IN
1
2
5 GND
REF21XX
C
CS
OUT
4
3
R
C
Figure 31. Layout Example
20
版权 © 2017, Texas Instruments Incorporated
REF2125
www.ti.com.cn
ZHCSGP1 –SEPTEMBER 2017
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
《INA21x 电压输出、低侧或高侧测量、双向、零漂移系列分流监控器》
《低漂移双向单电源低侧电流感应参考设计》
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据如有变更，恕
不另行通知和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
21
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
REF2125IDBVR
ACTIVE
SOT-23
DBV
5
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
19DD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
REF2125IDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
445.0 220.0 345.0
REF2125IDBVR
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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