PTSM82903SISB2R [TI]
具有集成电感器的 3V 至 17V、3A 高效率、低 IQ 同步降压转换器模块 | SIS | 11 | -40 to 125;
| 型号： | PTSM82903SISB2R |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电感器的 3V 至 17V、3A 高效率、低 IQ 同步降压转换器模块 | SIS | 11 | -40 to 125 电感器 转换器 |
| 文件： | 总42页 (文件大小：4867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPSM82903
ZHCSPZ6B –FEBRUARY 2022 –REVISED NOVEMBER 2022
采用MicroSiPTM 封装并具有集成电感器的TPSM82903 3A 3V 至17V，高效率和
低IQ 降压转换器模块
1 特性
3 说明
• 在宽占空比和负载范围内可实现高效率
– IQ：4µA（典型值）
– 62mΩ高侧和22mΩ低侧RDS(ON)
• 3mm × 2.8mm × 1.6mm MicroSiP™ 封装
• 高达3A 的持续输出电流
TPSM82903 是一款高效、小巧、灵活且易用的同步降
压直流/直流转换器 MicroSiP 封装模块。2.5MHz 或
1.0MHz 的可选开关频率支持使用小型元件，并提供快
速瞬态响应。该器件利用 DCS-Control 拓扑支持 ± 1%
的高 VOUT 精度。3V 至 17V 的宽输入电压范围支持各
种标称输入，例如 12V 电源轨、单节或多节锂离子电
池、5V 或3.3V 电源轨。
• 整个温度范围（-40°C 至125°C）内的反馈电压
精度达±0.9%
• 可配置的输出电压选项：
TPSM82903 可在轻负载时自动进入省电模式（如果选
择了自动 PFM/PWM）以保持高效率。此外，为了在
非常小的负载下提供高效率，该器件具有 4µA 的低典
型静态电流。AEE（如果启用）可在 VIN、VOUT 和负
载电流范围内提供高效率。该器件包含一个 MODE/
Smart-CONF 输入，用来设置内部/外部分压器、开关
频率、输出电压放电和自动省电模式或强制 PWM 操
作。
– VFB 外部分压器：0.6V 至5.5V
– VSET 内部分压器：16 个电压选项（0.4V 至
5.5V）
• 带100% 模式的DCS-Control 拓扑
• 通过MODE/S-CONF 引脚实现灵活性
– 2.5MHz 或1.0MHz 开关频率
– 具有动态模式更改选项的强制PWM 或自动
(PFM) 省电模式
该器件采用小型 11 引脚 MicroSiP 封装，尺寸为
3.0mm × 2.8mm × 1.6mm，带有集成1μH 电感器。
– 自动效率增强(AEE)
– 输出放电开/关
• 高度灵活且易于使用
封装信息
封装(1)
– 针对单层布线的引脚排列进行了优化
– 精密使能输入
– 电源正常状态输出
封装尺寸（标称值）
器件型号
TPSM82903
SIS (uSiP, 11)
3.00mm × 2.80mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 可调软启动和跟踪
• 无需外部自举电容器
• 使用TPSM82903 并借助WEBENCH® Power
Designer 创建定制设计方案
2 应用
• 数据中心和企业级计算
• 有线网络
• 无线基础设施
• 工厂自动化和控制
• 测试和测量
100%
90%
80%
70%
60%
50%
40%
VIN
3V t 17V
VOUT
0.6V t 5.5V
TPSM8290x
VIN
VOUT
EN
GND
C2
22…F
C1
10…F
R1
R2
FB/
VSET
SS/TR
MODE/
S-CONF
PG
R3
C3
30%
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
20%
10%
0
1E-6
1E-5
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3
IOUT (A)
简化版原理图
效率与输出电流间的关系（频率为2.5MHz 时VO 为
1.2V，自动PFM/PWM）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSG64
TPSM82903
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ZHCSPZ6B –FEBRUARY 2022 –REVISED NOVEMBER 2022
Table of Contents
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Application with Adjustable Output Voltage.. 17
8.3 Typical Application with Setable VO Using VSET .... 29
8.4 Power Supply Recommendations.............................32
8.5 Layout....................................................................... 32
9 Device and Documentation Support............................35
9.1 Device Support......................................................... 35
9.2 接收文档更新通知..................................................... 35
9.3 支持资源....................................................................35
9.4 Trademarks...............................................................35
9.5 Electrostatic Discharge Caution................................35
9.6 术语表....................................................................... 35
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................7
7 Detailed Description........................................................8
7.1 Overview.....................................................................8
7.2 Functional Block Diagram...........................................8
7.3 Feature Description.....................................................9
Information.................................................................... 36
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (October 2022) to Revision B (November 2022)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
Changes from Revision * (February 2022) to Revision A (October 2022)
Page
• 通篇更新了商标信息........................................................................................................................................... 1
• Added Peak reflow case temperature.................................................................................................................4
• Added Maximum number of reflows allowed......................................................................................................4
• Added Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted................................................................... 4
• Added Mil-STD-883D, Method 2007.2, 20 to 2000 Hz....................................................................................... 4
• Updated 图8-4 “SW”pin to “VOUT”pin to reflect accurate pin name.................................................... 19
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5 Pin Configuration and Functions
VOUT
VIN
10
1
VIN
EN
VOUT
2
3
9
11
GND
SW/NC
8
FB/VSET
7
4
MODE/S-CONF
SS/TR
PG
6
5
图5-1. 11-Pin SIS MicroSiP™ Package (Top View, Device Pins Face Down)
表5-1. Pin Functions
Pin
I/O
Description
Name
Number
Power supply input pin. Ensure the input capacitor is connected as close as possible between
the VIN and GND pins.
VIN
1, 2
I
I
Enable input pin. Connect to logic low to disable the device. Pull high to enable the device. Do
not leave this pin unconnected.
EN
3
4
Device mode selection (auto PFM/PWM or forced PWM operation) and SmartConfig™
application. Connect high, low, or to a resistor to configure the device according to 表7-2. Do
not leave this pin unconnected.
MODE/
S-CONF
I
Soft start/tracking pin. An external capacitor connected from this pin to GND defines the rise
time for the internal reference voltage. The pin can also be used as an input for tracking and
sequencing. The pin can be left floating for the fastest ramp-up time.
SS/TR
PG
5
6
I
Open-drain power-good output. High = VOUT is ready. Low = VOUT is below nominal regulation.
This pin requires a pullup resistor.
O
Depends on device configuration (see 节7.3.1)
•
•
FB: Voltage feedback input. Connect a resistive output voltage divider to this pin.
VSET: Output voltage setting pin. Connect a resistor to GND to choose the output voltage
according to 表7-3.
FB/VSET
7
I
SW/NC
VOUT
8
NC
O
Switch pin of the converter. Do not connect, leave floating.
9, 10
Output voltage pin. Connect directly to the positive pin of the output capacitor.
Ground pin. It must be connected directly to the common ground plane. It must be soldered to
achieve appropriate power dissipation and mechanical reliability.
GND
11
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–55
MAX
18
UNIT
VIN
EN, PG
Voltage(2)
18
V
MODE/S-CONF
18
FB/VSET, SS/TR, VOUT
6
TJ
Junction temperature
125
260
3
°C
°C
Peak reflow case temperature
Maximum number of reflows allowed
Mechanical
shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
1500
G
Mechanical
vibration
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
Storage temperature
20
G
Tstg
125
°C
–55
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
3.0
0.4
3
NOM
MAX
17
UNIT
V
VI
Input voltage range
VO
Output voltage range
5.5
V
CI
Effective input capacitance
Effective output capacitance (2.5MHz selection)
Effective output capacitance (1.0MHz selection)
Output current
10
22
22
µF
µF
µF
A
CO
10
6
100 (1)
50 (1)
3
CO
IOUT
ISINK_PG
TJ
0
Sink current at PG-Pin
1
mA
°C
Junction temperature (2)
-40
125
(1) This is for capacitors directly at the output of the device. More capacitance is allowed if there is a series resistance associated to the
capacitor.
(2) Operating lifetime is derated at junction temperatures greater than 125°C.
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6.4 Thermal Information
TPSM8290x
THERMAL METRIC(1)
uSIP11-Pin
TPSM8290xEVM-188
UNIT
JEDEC PCB
58.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
48.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
34.5
26.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
0.8
ΨJT
26.6
27.8
ΨJB
RθJC(bot)
26.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VI = 3 V to 17 V, TJ = -40°C to +125°C, Typical values at VI = 12.0 V and TA = 25°C,unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Operating Quiescent Current (Power
Save Mode)
IQ_PSM
Iout = 0 mA, device not switching
4
8
µA
Operating Quiescent Current (PWM
Mode)
VIN=12 V, VOUT=1.2 V; Iout = 0 mA,
device switching
IQ_PWM
ISD
mA
Shutdown current into VIN pin
Under Voltage Lock-Out
EN = 0 V
VIN rising
VIN falling
Hysteresis
0.27
2.925
2.775
150
3.5
3.0
µA
V
2.85
2.7
VUVLO
Under Voltage Lock-Out
2.85
V
VUVLO_HYS
Under Voltage Lock-Out Hysteresis
mV
CONTROL & INTERFACE
ILKG
EN Input leakage current
EN = 12 V
10
300
nA
V
High-Level Input Voltage at MODE/S-
CONF-Pin
VIH_MODE
1.0
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
High-level input voltage at EN-Pin
Low-level input voltage at EN-Pin
TJ rising
170
20
TSD
°C
Hysteresis
VIH
VIL
0.97
0.87
1.0
0.9
1.03
0.93
V
V
Smart-Enable Internal Pulldown
Resistor
REN_PD
EN = LOW
0.5
MΩ
VFB rising, referenced to VFB nominal
VFB falling, referenced to VFB nominal
Hysteresis
93.5%
88.5%
1.5%
96%
93%
3.5%
99%
96%
6%
VPG
Power good threshold
VPG_OL
IPG_LKG
tPG_DLY
RSET
Low-level output voltage at PG pin
Input leakage current into PG pin
Power good delay time
ISINK = 1 mA
0.4
V
nA
µs
%
VPG = 5 V
15
32
550
VFB falling
S-CONF/VSET Resistor Tolerance
+4
30
–4
Maximum Capacitance connected to
S-CONF/VSET Pins
CSET
pF
POWER SWITCHES
ILKG_SW Leakage current into SW-Pin
VSW = VOS = 5.5 V
2
62
22
7
111
40
µA
High-side FET on resistance
Low-side FET on resistance
VIN > 4 V, ISW = 500 mA
VIN > 4 V, ISW = 500 mA
RDS_ON
mΩ
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6.5 Electrical Characteristics (continued)
VI = 3 V to 17 V, TJ = -40°C to +125°C, Typical values at VI = 12.0 V and TA = 25°C,unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
4.1
3.8
1.3
TYP
4.9
4.3
1.7
2.5
50
MAX
5.8
UNIT
A
High-side FET current limit
Low-side FET current limit
Low-side FET sink current limit
Switching frequency
Minimum On-time
ILIM
4.7
A
ILIM_SINK
fSW
TON(MIN)
fSW
2.5
A
2.5-MHz selection
MHz
ns
Switching frequency
Dutycycle
1.0-MHz selection
1.0
MHz
D
1
RPD
Dropout resistance
100% mode, VIN > 4 V
100
mΩ
OUTPUT
VSET Configuration selected. TJ =
25°C.
VO_Reg1
VO_Reg2
VO_Reg3
Output Voltage Regulation
Output Voltage Regulation
Output Voltage Regulation
+0.9%
+1.1%
–0.9%
–1.1%
VSET Configuration selected. 0 °C<
TJ < 85°C
VSET Configuration selected. –40°C
< TJ < 125°C
+1.25%
–1.25%
VFB
Feedback Regulation Voltage
Feedback Voltage Regulation
Feedback Voltage Regulation
Adjustable Configuration selected
FB-Option selected. TJ = 25°C.
FB-Option selected. 0°C < TJ < 85°C.
0.6
V
VFB_Reg1
VFB_Reg2
+0.6%
–0.6%
+0.65%
–0.65%
FB-Option selected. –40°C < TJ <
125°C
VFB_Reg3
IFB
Feedback Voltage Regulation
+0.9%
70
–0.9%
Input leakage current into FB pin
Adjustable configuration, VFB = 0.6 V
1
nA
µs
IO = 0 mA, time from EN=HIGH until
start switching, Adjustable
Configuration selected
Start-up delay time
Start-up delay time
600
1400
1850
Tdelay
IO = 0 mA, time from EN=HIGH until
start switching, VSET Configuration
selected. The typical value is based on
the first option of VSET configuration.
650
150
µs
IO = 0 mA after Tdelay, from 1st
switching pulse until target VO; TR/SS-
Pin = OPEN
TSS
Soft-Start time
200
2.7
µs
ISS
SS/TR source current
2.3
2.5
0.75
±8
µA
Tracking Gain, Adjustable
Configuration
VFB/VSS/TR
VFB/VSS/TR
RDISCH
Tracking Gain tolerance
mV
Discharge = ON - Option Selected, EN
= LOW,
Active Discharge Resistance
7.5
20
Ω
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6.6 Typical Characteristics
9
80
70
60
50
40
30
20
10
0
-40C
0C
25C
17V
12V
6V
8
125C
3V
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120125
VIN (V)
Temperature (C)
图6-1. Typical Quiescent Current vs VIN
图6-2. Maximum Quiescent Current vs
Temperature
1
0.85
-40C
-25C
0C
25C
85C
125C
-40C
25C
85C
0.8
0.75
0.7
125C
0.8
0.6
0.4
0.2
0
0.65
0.6
0.55
0.5
0.45
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
VIN (V)
VIN (V)
图6-3. Typical Shutdown Current
图6-4. Output Voltage Accuracy –VFEB Selected
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7 Detailed Description
7.1 Overview
The TPSM82903 synchronous step-down converter MicroSiP package module is based on DCS-Control (Direct
Control with Seamless Transition into power save mode). DCS-Control is an advanced regulation topology that
combines the advantages of hysteretic, voltage mode, and current mode control. This control loop takes
information about output voltage changes and feeds it directly to a fast comparator stage. The control loop sets
the switching frequency, which is constant for steady-state operating conditions, and provides immediate
response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low-ESR capacitors.
7.2 Functional Block Diagram
PG
VIN
VI
Ref
–
1.0 V
HS Limit
+
EN
VO
Device Control
and Logic
Power Control
Internal/External
Divider
FB
/VSET
Gate
Driver
Resistor-to-Digital
VFB
Power Save Mode
Forced PWM
100% Mode
Smart-Enable
Ref-System
UVLO
SS/TR
Start-up Handling
SmartConfigTM
PG-Control
Thermal Shutdown
Resistor-to-
Digital
MODE
/S-CONF
LS Limit
MODE Detection
VOUT
VO
VOS
Direct
Control
VI
TON Timer
VFB
–
VO
+
DCS-ControlTM
Device
Control
VREF
GND
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7.3 Feature Description
7.3.1 Mode Selection and Device Configuration (MODE/S-CONF)
With MODE/S-CONF (SmartConfig application), this device features an input with two functions. It can be used
to customize the device behavior in two ways:
• Select the device mode (FPWM or auto PFM/PWM with AEE operation) traditionally with a HIGH- or LOW-
level.
• Select the device configuration (switching frequency, internal/external feedback, output discharge, and
PFM/PWM mode) by connecting a single resistor to the MODE/S-CONF pin.
The device interprets this pin during the start-up sequence after the internal OTP readout and before it starts
switching in soft start. If the device reads a HIGH- or LOW-level, the dynamic mode change is active and
PFM/PWM mode can be changed during operation. If the device reads a resistor value, there is no further
interpretation during operation and device mode or other configurations cannot be changed afterward.
备注
The MODE/S-CONF pin must not be left floating. Connect the pin high, low, or to a resistor to
configure the device according to 表7-2.
EN and UVLO
Precise
Enable
Detection
PG to High
Switching
Operation
OTP
Readout
S-CONF
Readout
VSET
Readout
Softstart
Resistor-to-Digitial
Readout and
Interpretation
No Interpretation of
MODE/S-CONF or VSET
MODE-Pin Toggling Detection
VOUT
图7-1. Interpretation of S-CONF and VSET Flow
CAUTION
For each operating mode and switching frequency, the following VOUT range is recommended:
表7-1. Recommended VOUT Ranges with Respect to MODE and FSW
Mode
Auto PFM/PWM
Forced PWM
FSW (MHz)
VOUT
1 MHz
0.4 V < VOUT < 2.0 V
0.4 V < VOUT < 2.0 V
0.4 V < VOUT< 5.5 V
2.0 V < VOUT < 5.5 V
1 MHz
Auto PFM/PWM with AEE
Forced PWM
2.5 MHz
2.5 MHz
Failure to follow the recommended VOUT ranges causes the device to malfunction.
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表7-2. SmartConfig™ Application Setting Table
FB/VSET-
Pin
Output
Discharge
Mode (Auto or Forced
PWM)
Dynamic Mode
Change
Level Or Resistor Value [Ω]
#
FSW (MHz)
(1)
Setting Options by Level
Auto PFM/PWM with
AEE
1
2
GND
external FB
external FB
2.5
2.5
yes
yes
active
HIGH (>VIH_MODE
)
Forced PWM
Setting Options by Resistor
Auto PFM/PWM with
AEE
3
7.15 k
external FB
2.5
no
4
5
6
7
8
8.87 k
11.0 k
13.7 k
16.9 k
21.0 k
external FB
external FB
external FB
external FB
external FB
2.5
1
no
yes
yes
no
Forced PWM
Auto PFM/PWM
Forced PWM
1
1
Auto PFM/PWM
Forced PWM
1
no
Auto PFM/PWM with
AEE
9
26.1 k
32.4 k
40.2 k
VSET
VSET
VSET
2.5
2.5
2.5
yes
yes
no
not active
10
11
Forced PWM
Auto PFM/PWM with
AEE
12
13
14
15
16
49.9 k
61.9 k
76.8 k
95.3 k
118 k
VSET
VSET
VSET
VSET
VSET
2.5
1
no
yes
yes
no
Forced PWM
Auto PFM/PWM
Forced PWM
1
1
Auto PFM/PWM
Forced PWM
1
no
(1) E96 Resistor Series, 1% Accuracy, Temperature Coefficient better or equal than ±200 ppm/°C
7.3.2 Adjustable VO Operation (External Voltage Divider)
The TPSM82903 can be programmed by the MODE/S-CONF pin to either classical configuration where the FB/
VSET pin is used as the feedback pin, sensing VO through an external resistive divider. The TPSM82903 can
also be programmed to 16 different fixed output voltages. These are set through an external resistor between the
FB/VSET pin and GND. In this configuration, VO is directly sensed at the VOS internal terminal connection of the
device.
If the device is configured to operate in classical adjustable VO operation, the FB/VSET pin is used as the
feedback pin and needs to sense VO through an external divider network. 图 7-2 shows the typical schematic for
this configuration.
VIN
3V t 17V
VOUT
0.6V t 5.5V
TPSM8290x
VIN
VOUT
EN
GND
C2
22…F
C1
10…F
R1
R2
FB/
VSET
SS/TR
MODE/
S-CONF
PG
R3
C3
图7-2. Adjustable VO Operation Schematic
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7.3.3 Setable VO Operation (VSET and Internal Voltage Divider)
If the device is configured to VSET operation, VO is sensed only through the internal VOS connection by an
internal resistor divider. The target VO is programmed by an external resistor connected between the VSET pin
and GND. 图7-3 shows the typical schematic for this configuration.
VIN
3V t 17V
VOUT
0.4V t 5.5V
TPSM8290x
VIN
VOUT
EN
GND
C2
22…F
C1
10…F
FB/
VSET
SS/TR
R2
MODE/
S-CONF
PG
R3
C3
图7-3. Setable VO Operation Schematic
表7-3. VSET Selection Table
#
1
Target VO [V]
Resistor Value [Ω]
GND
4.64 k
1.2
0.4
0.6
0.8
1.0
1.1
1.3
1.35
1.8
1.9
2.5
3.8
5.0
5.1
5.5
3.3
2
3
5.76 k
4
7.15 k
5
8.87 k
6
11.0 k
7
13.7 k
8
16.9 k
9
21.0 k
10
11
12
13
14
15
16
26.1 k
40.2 k
61.9 k
76.8 k
95.3 k
118.0 k
249.00 k or larger/Open
7.3.4 Soft Start/Tracking (SS/TR)
With the SS/TR pin, it is possible to adjust the soft-start behavior and track an external voltage. See 节 8.2.2.4
for operation details.
The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and makes sure there is a controlled output voltage rise time. It also prevents unwanted voltage drops
from high impedance power sources or batteries. When EN is set high to start operation, the device starts
switching after a delay, then the internal reference, and hence VO, rises with a slope controlled by an external
capacitor connected to the SS/TR pin.
Leaving the SS/TR pin unconnected provides the fastest start-up, limited internally (the pin must not be pulled
LOW externally).
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If the device is set to shut down (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistor
pulls the SS/TR pin down to ensure a proper low level. Returning from those states causes a new start-up
sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used to track a primary voltage. The output voltage follows this voltage up
and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load current.
7.3.5 Smart Enable with Precise Threshold
The voltage applied at the enable pin of the TPSM82903 is compared to a fixed threshold rising voltage, allowing
the user to drive the pin by a slowly changing voltage and enables the use of an external RC network to achieve
a power-up delay.
The precise enable input allows the user to program the undervoltage lockout by adding a resistor divider to the
input of the enable pin.
The enable input threshold for a falling edge is lower than the rising edge threshold. The TPSM82903 starts
operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must
not be left floating. Pulling the EN pin low forces the device into shutdown. In this mode, the internal high-side
and low-side MOSFETs are turned off and the entire internal control circuitry is switched off.
An internal resistor pulls the EN pin to GND when the device is disabled and avoids floating the pin after the
device is enabled, the pulldown is removed. This prevents an uncontrolled start-up of the device in case the EN
pin cannot be driven to a low level safely. With EN low, the device is in shutdown mode. The device is turned on
with EN set to a high level. The pulldown control circuit disconnects the pulldown resistor on the EN pin after the
internal control logic and the reference have been powered up. With EN set to a low level, the device enters
shutdown mode and the pulldown resistor is activated again.
7.3.6 Power Good (PG)
The TPSM82903 has a built-in power-good (PG) feature to indicate whether the output voltage has reached its
target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is
an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level.
PG is low when the device is turned off due to EN, UVLO (undervoltage lockout), or thermal shutdown. VIN must
remain present for the PG pin to stay low.
If the power-good output is not used, it is recommended to tie to GND or leave it open.
表7-4. Power Good Indicator Functional Table
Logic Signals
PG Status
VI
EN Pin
Thermal Shutdown
VO
VO on target
High Impedance
LOW
No
HIGH
VO < target
VI > UVLO
Yes
x
x
x
x
x
LOW
LOW
LOW
1.8 V< VI < UVLO
VI < 1.8 V
x
x
x
LOW
x
Undefined
7.3.7 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the
power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the
input voltage trips below the threshold for a falling supply voltage.
7.3.8 Current Limit And Short Circuit Protection
The TPSM82903 is protected against overload and short circuit events. If the inductor current exceeds the high-
side FET current limit (ILIMH), the high-side switch is turned off and the low-side switch is turned on to ramp down
the inductor current. The high-side FET turns on again only if the current in the low-side FET has decreased
below the low-side FET current limit threshold.
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Due to internal propagation delay, the actual current can exceed the static current limit during that time. The
dynamic current limit is given as 方程式1:
V
L
Ipeak(typ) = ILIMH
+
´tPD
(1)
where
• ILIMH is the static high-side FET current limit as specified in the Electrical Characteristics.
• L is the effective inductance at the peak current (approximately 0.9 μH).
• VL is the voltage across the inductor (VIN –VOUT).
• tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
V IN - VO U T
I
peak ( typ ) = IL IM H
+
´ 50 ns
L
(2)
7.3.9 Thermal Shutdown
The junction temperature, TJ, of the device is monitored by an internal temperature sensor. If TJ rises and
exceeds the thermal shutdown threshold, TSD, the device shuts down. Both the high-side and low-side power
FETs are turned off and PG goes low. When TJ decreases below the hysteresis, the converter resumes normal
operation, beginning with soft start. During a PFM skip pause, the thermal shutdown feature is not active. A
shutdown or re-start is only triggered during a switching cycle. See 节7.4.3.
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7.4 Device Functional Modes
7.4.1 Pulse Width Modulation (PWM) Operation
The TPSM82903 has two operating modes: forced PWM mode discussed in this section and PWM/PFM as
discussed in 节7.4.3.
With the MODE/S-CONF pin configured for PWM mode, the TPSM82903 operates with pulse width modulation
in continuous conduction mode (CCM) with a nominal switching frequency of 2.5 MHz/1.0 MHz. The frequency
variation in PWM is controlled and depends on VIN, VOUT, and the inductance. The on time in forced PWM mode
is given by 方程式3:
VOUT
VIN
1
TON =
ì
fsw
(3)
7.4.2 AEE (Automatic Efficiency Enhancement)
When the MODE/S-CONF pin is configured for AEE mode, the TPSM82903 provides the highest efficiency over
the entire input voltage and output voltage range by automatically adjusting the switching frequency of the
converter. This is achieved by setting the predictive off time of the converter. The efficiency of a switched mode
converter is determined by the power losses during the conversion. The efficiency decreases if VOUT decreases,
V
IN increases as shown in 方程式 4, or both. In order to keep the efficiency high over the entire duty cycle range
(VOUT/VIN ratio), the switching frequency is adjusted while maintaining the ripple current.
VIN -VOUT
VIN
F (MHz) =10ìVOUT
ì
sw
2
(4)
The AEE function in the TPSM82903 adjusts the on time (TON) in power save mode, depending on the input
voltage and the output voltage to maintain highest efficiency. The on time in steady-state operation can be
estimated as using 方程式5:
VIN
TON =100´
[ns]
VIN -VOUT
(5)
方程式6 shows the relationship among the inductor ripple current, switching frequency, and duty cycle.
VOUT
1-(
)
1- D
Lì fSW
VIN
DIL =VOUT ì(
) =VOUT ì(
)
Lì fSW
(6)
Efficiency increases by decreasing switching losses and preserving high efficiency for varying duty cycles, while
the ripple current amplitude remains low enough to deliver the full output current without reaching current limit.
The AEE feature provides an efficiency enhancement for various duty cycles, especially for lower VOUT values
where fixed frequency converters suffer from a significant efficiency drop. Furthermore, this feature compensates
for the very small duty cycles of high VIN to low VOUT conversion, which limits the control range in other
topologies.
7.4.3 Power Save Mode Operation (Auto PFM/PWM)
When the MODE/S-CONF pin is configured for power save mode (auto PFM/PWM), the device operates in
PWM mode as long the output current is higher than half of the ripple current of the inductor. To maintain high
efficiency at light loads, the device enters power save mode at the boundary to discontinuous conduction mode
(DCM). This happens if the output current becomes smaller than half of the ripple current of the inductor. The
power save mode is entered seamlessly when the load current decreases. This makes sure there is a high
efficiency in light load operation. The device remains in power save mode as long as the inductor current is
discontinuous.
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In power save mode, the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition in and out of power save mode is seamless in both directions.
In addition to adjusting the switching, the TPSM82903 adjusts the on time (TON) in power save mode,
depending on the input voltage and the output voltage to maintain the highest efficiency using the AEE function
when 2.5 MHz is selected as described in 节7.4.2.
In power save mode, the TON time can be estimated using 方程式 3 for 1 MHz and 方程式 5 for 2.5 MHz (given
the AEE is enabled for 2.5 MHz).
For very small output voltages, an absolute minimum on time of about 50 ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using TON, the
typical peak inductor current in power save mode is approximated by 方程式7:
(V IN - VO U T )´ TO N
=
IL P SM ( peak )
L
(7)
There is a minimum off time that limits the duty cycle of the TPSM82903. When VIN decreases to typically 15%
above VOUT, the TPSM82903 does not enter power save mode, regardless of the load current. The device
maintains output regulation in PWM mode.
The output voltage ripple in power save mode is given by 方程式8:
2 æ
ç
ö
÷
ø
L´VIN
1
1
DV =
+
200´C VIN -VOUT VOUT
è
(8)
where
• L is the effective inductance (approximately 0.9 μF).
• C is the output effective capacitance.
7.4.4 100% Duty-Cycle Operation
The duty cycle of the buck converter operating in PWM mode is given as D = VOUT/VIN. The duty cycle increases
as the input voltage comes close to the output voltage and the off time gets smaller. When the minimum off time
of typically 80 ns is reached, the TPSM82903 scales down its switching frequency while it approaches 100%
mode. In 100% mode, the device keeps the high-side switch on continuously. The high-side switch stays turned
on as long as the output voltage is below the internal set point. This allows the conversion of small input to
output voltage differences (for example, getting longest operation time of battery-powered applications). In 100%
duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
VIN(min) =VOUT + IOUT(RDS(on) + R
)
L
(9)
where
• IOUT is the output current.
• RDS(on) is the on-state resistance of the high-side FET.
• RL is the DC resistance of the inductor used (approximately 40 mΩ).
7.4.5 Output Discharge Function
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is
being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge
feature is only active after the TPSM82903 has been enabled at least once since the supply voltage was
applied. The internal discharge resistor is connected to the VOS pin. The discharge function is enabled as soon
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as the device is disabled, in thermal shutdown, or in undervoltage lockout. The minimum supply voltage required
for the discharge function to remain active typically is 2 V.
7.4.6 Starting into a Pre-Biased Load
The TPSM82903 is capable of starting into a pre-biased output. The device only starts switching when the
internal soft-start ramp is equal or higher than the feedback voltage. If the voltage at the feedback pin is biased
to a higher voltage than the nominal value, the TPSM82903 does not start switching unless the voltage at the
feedback pin drops to the target.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TPSM82903 device is highly efficient, small, and flexible synchronous step-down DC-DC converter
MicroSiP package module that is easy to use. A wide input voltage range of 3 V to 17 V supports a wide variety
of inputs like 12-V supply rails, single-cell or multi-cell Li-Ion, and 5-V or 3.3-V rails.
8.2 Typical Application with Adjustable Output Voltage
VIN
3V t 17V
VOUT
0.6V t 5.5V
TPSM8290x
VIN
VOUT
EN
GND
C2
22…F
C1
10…F
R1
R2
FB/
VSET
SS/TR
MODE/
S-CONF
PG
R3
C3
图8-1. Typical Application Circuit
8.2.1 Design Requirements
表8-1. List of Components
Reference
Description
Manufacturer
IC
17 V, 3-A Step-Down Converter
TPSM8290x series; Texas Instruments
C3216X7R1E106M160AE, TDK
C2012X7S1A226M125AC, TDK
16 V, Ceramic, X7R
CIN
COUT
CSS
R1
10 µF, 25 V, Ceramic, 0805
22 µF, 16 V, Ceramic, 0805
Depends on soft start time; see 节8.2.2.3.3.
Depending on VOUT; see 节8.2.2.2.
Depending on VOUT; see 节8.2.2.2.
Depending on device setting, see 节7.3.1.
Standard 1% metal film
R2
Standard 1% metal film
R3
Standard 1% metal film
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM82903 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
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In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Programming the Output Voltage
The output voltage of the TPSM82903 is adjustable. It can be programmed for output voltages from 0.6 V to 5.5
V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of the
output voltage is set by the selection of the resistor divider from 方程式 10. It is recommended to choose resistor
values that allow a current of at least 2 μA, meaning the value of R2 must not exceed 400 kΩ. Lower resistor
values are recommended for highest accuracy and most robust design.
VOUT
æ
ç
è
ö
÷
ø
R1
= R2 ´
-1
VFB
(10)
With typical VFB = 0.6 V, 1-MHz switching frequency is not recommended for VOUT > 1.8 V.
表8-2. Setting the Output Voltage
Nominal Output Voltage
R1
R2
Exact Output Voltage
0.749 V
1.2 V
0.75 V
1.2 V
1.5 V
1.8 V
2.0 V
2.5 V
3.0 V
3.3 V
5.0 V
24.9 kΩ
100 kΩ
150 kΩ
200 kΩ
49.9 kΩ
100 kΩ
100 kΩ
113 kΩ
182 kΩ
100 kΩ
100 kΩ
100 kΩ
100 kΩ
21.5 kΩ
31.6 kΩ
24.9 kΩ
24.9 kΩ
24.9 kΩ
1.5 V
1.8 V
1.992 V
2.498 V
3.009 V
3.322 V
4.985 V
8.2.2.3 Capacitor Selection
8.2.2.3.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. Output capacitance above 100 µF needs to have a
ESR of ≥10 mΩfor stable operation. The architecture of the TPSM82903 allows the use of tiny ceramic output
capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and
are recommended. To keep its low resistance up to high frequencies and to get narrow capacitance variation
with temperature, use X7R or X5R dielectric. Using a higher value has advantages like smaller voltage ripple
and a tighter DC output accuracy in power save mode (see the Optimizing the TPS62130/40/50/60 Output Filter
application report).
In power save mode, the output voltage ripple depends on the output capacitance, its ESR, ESL, and the peak
inductor current. Using ceramic capacitors provides small ESR, ESL, and low ripple. The output capacitor needs
to be as close as possible to the device.
For large output voltages, the DC bias effect of ceramic capacitors is large and the effective capacitance must be
observed.
8.2.2.3.2 Input Capacitor
For most applications, 10 µF nominal is sufficient and is recommended, though a larger value reduces input
current ripple further. The input capacitor buffers the input voltage for transient events and also decouples the
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converter from the supply. A low-ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and
must be placed between VIN and GND as close as possible to those pins.
表8-3. List of Capacitors
Type (1)
Nominal Capacitance [µF]
Voltage Rating [V]
Size
0805
0805
Manufacturer
TDK
C3216X7R1E106K160AB
C2012X7S1A226M125AC
10
22
25
10
TDK
(1) Lower of IRMS at 40°C rise or ISAT at 30% drop
8.2.2.3.3 Soft-Start Capacitor
A capacitor connected between SS/TR pin and GND allows a user-programmable start-up slope of the output
voltage.
ISS
SS/TR
to VREF
图8-2. Soft-Start Operation Simplified Schematic
An internal constant current source is provided to charge the external capacitance. The capacitor required for a
given soft-start ramp time is given by:
ISS
CSS = TSS ì
VREF
(11)
where
• CSS is the capacitance required at the SS/TR pin.
• TSS is the desired soft-start ramp time.
• ISS is the SS/TR source current, see the Electrical Characteristics.
• VREF is the feedback regulation voltage divided by tracking gain (VFB/0.75), see the Electrical Characteristics.
The fastest achievable typical ramp time is 150 µs even if the external Css capacitance is lower than 680 pF or
the pin is open.
8.2.2.4 Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage with the typical gain and offset as specified in the
Electrical Characteristics.
ISS
SS/TR
to VREF
图8-3. Tracking Operation Simplified Schematic
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VFB = 0.75ìVSS/TR
(12)
When the SS/TR pin voltage is above 0.8 V, the internal voltage is clamped and the device goes to normal
regulation. This works for rising and falling tracking voltages with the same behavior, as long as the input voltage
is inside the recommended operating conditions. For decreasing SS/TR pin voltage in PFM mode, the device
does not sink current from the output. The resulting decrease of the output voltage can therefore be slower than
the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the
voltage rating of the SS/TR pin, which is 6 V. The SS/TR pin is internally connected with a resistor to GND when
EN = 0.
If the input voltage drops below undervoltage lockout, the output voltage goes to zero, independent of the
tracking voltage. 图 8-4 shows how to connect devices to get ratiometric and simultaneous sequencing by using
the tracking function.
Device 1
TPSM8290x
VOUT1
22 F
VIN=12V
VIN
VOUT
EN
GND
R1
R2
10uF
SS/
TR
FB/
VSET
MODE/
S-CONF
PG
CSS
R3
Device 2
TPSM8290x
VOUT2
VIN
VOUT
EN
GND
22 F
R7
R8
R4
R5
10uF
SS/
TR
FB/
VSET
MODE/
S-CONF
PG
R6
图8-4. Schematic for Ratiometric and Simultaneous Start-Up
The resistive divider of R7 and R8 can be used to change the ramp rate of VOUT2 to be faster, slower, or the
same as VOUT1.
A sequential start-up is achieved by connecting the PG pin of VOUT of device 1 to the EN pin of device 2. PG
requires a pullup resistor. Ratiometric start-up sequence happens if both supplies are sharing the same soft-start
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capacitor. 方程式 11 gives the soft-start time, though the SS/TR current has to be doubled. Details about these
and other tracking and sequencing circuits are found in Sequencing and Tracking With the TPS621-Family and
TPS821-Family application report.
备注
If the voltage at the FB pin is below its typical value of 0.6 V, the output voltage accuracy can have a
wider tolerance than specified. The current of 2.5 µA out of the SS/TR pin also has an influence on the
tracking function, especially for high resistive external voltage dividers on the SS/TR pin.
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8.2.3 Application Curves
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
1E-6
1E-5
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3
1E-6
1E-5
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3
IOUT (A)
IOUT (A)
Auto PFM/PWM
Fsw = 1 MHz
Auto PFM/PWM
Fsw = 2.5 MHz
图8-5. Efficiency vs Output Current
图8-6. Efficiency vs Output Current
VOUT = 1.2 V
VOUT = 1.2 V
100%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
0.0005
0.002 0.005 0.01 0.02
0.05 0.1 0.2 0.3 0.5
1
2
3
1E-6
1E-5
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3
IOUT (A)
IOUT (A)
FPWM
Fsw = 1 MHz
Auto PFM/PWM
Fsw = 1 MHz
图8-7. Efficiency vs Output Current
图8-8. Efficiency vs Output Current
VOUT = 1.2 V
VOUT = 1.8 V
100%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
1E-6
1E-5
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3
0.0005
0.002 0.005 0.01 0.02
0.05 0.1 0.2 0.3 0.5
1
2
3
IOUT (A)
IOUT (A)
Auto PFM/PWM
Fsw = 2.5 MHz
FPWM
Fsw = 1 MHz
图8-9. Efficiency vs Output Current
图8-10. Efficiency vs Output Current
VOUT = 1.8 V
VOUT = 1.8 V
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100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
0
1E-6
1E-5
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3
0.0005
0.002 0.005 0.01 0.02
0.05 0.1 0.2 0.3 0.5
1
2
3
IOUT (A)
IOUT (A)
Auto PFM/PWM
Fsw = 2.5 MHz
FPWM
Fsw = 2.5 MHz
图8-11. Efficiency vs Output Current
图8-12. Efficiency vs Output Current
VOUT = 3.3 V
VOUT = 3.3 V
100%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=17V
VIN=15V
VIN=12V
VIN=9V
1E-6
1E-5
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3
0.0005
0.002 0.005 0.01 0.02
0.05 0.1 0.2 0.3 0.5
1
2
3
IOUT (A)
IOUT (A)
Auto PFM/PWM
Fsw = 2.5 MHz
FPWM
Fsw = 2.5 MHz
图8-13. Efficiency vs Output Current
图8-14. Efficiency vs Output Current
VOUT = 5.5 V
VOUT = 5.5 V
2
3.5
3
IOUT=3A
IOUT=3A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
1.75
1.5
1.25
1
2.5
2
1.5
1
0.75
0.5
0.25
0
0.5
0
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
VIN (V)
VIN (V)
Auto PFM/PWM
Fsw = 1 MHz
Auto PFM/PWM
Fsw = 2.5 MHz
图8-15. Switching Frequency vs Input Voltage
图8-16. Switching Frequency vs Input Voltage
VOUT = 1.2 V
VOUT = 1.2 V
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2
2
1.75
1.5
1.25
1
IOUT=3A
IOUT=3A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0.75
0.5
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
VIN (V)
VIN (V)
FPWM
Fsw = 1 MHz
Auto PFM/PWM
Fsw = 1 MHz
图8-17. Switching Frequency vs Input Voltage
图8-18. Switching Frequency vs Input Voltage
VOUT = 1.2 V
VOUT = 1.8 V
4.5
1.5
IOUT=3A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
IOUT=3A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
1.25
4
3.5
3
2.5
2
1
0.75
0.5
1.5
1
0.5
0
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
VIN (V)
VIN (V)
Auto PFM/PWM
Fsw = 2.5 MHz
FPWM
Fsw = 1 MHz
图8-19. Switching Frequency vs Input Voltage
图8-20. Switching Frequency vs Input Voltage
VOUT = 1.8 V
VOUT = 1.8 V
3.5
3.5
IOUT=3A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
IOUT=3A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
3
3.25
3
2.5
2
1.5
1
2.75
2.5
2.25
2
0.5
0
5
7
9
11
13
15
17
18
4
6
8
10
12
14
16
18
VIN (V)
VIN (V)
Auto PFM/PWM
Fsw = 2.5 MHz
FPWM
Fsw = 2.5 MHz
图8-21. Switching Frequency vs Input Voltage
图8-22. Switching Frequency vs Input Voltage
VOUT = 3.3 V
VOUT = 3.3 V
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4
3.5
3
3.5
3.25
3
IOUT=3A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
IOUT=3A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
2.5
2
2.75
2.5
1.5
1
0.5
0
8
2.25
10
12
14
16
18
8
10
12
14
16
18
VIN (V)
VIN (V)
Auto PFM/PWM
Fsw = 2.5 MHz
FPWM
Fsw = 2.5 MHz
图8-23. Switching Frequency vs Input Voltage
图8-24. Switching Frequency vs Input Voltage
VOUT = 5.5 V
VOUT = 5.5 V
1.8125
VIN=17V
VIN=15V
VIN=12V
VIN=9V
1.81
VIN=6V
VIN=3V
1.8075
1.805
1.8025
1.8
1.7975
1.795
0.0005
0.002 0.005 0.01 0.02
0.05 0.1 0.2 0.3 0.5
1
2
3
IOUT (A)
VIN = 12 V
1-MHz FPWM
IO = 0 mA
TA = 25°C
FPWM
Fsw = 1 MHz
VOUT = 1.2 V
图8-25. Output Voltage vs Output Current
图8-26. Start-Up Timing
VOUT = 1.8 V
VIN = 12 V
VOUT = 5 V
2.5-MHz FPWM
IO = 1 A
VIN = 12 V
1-MHz Auto
PFM/PWM
IO = 1 A
TA = 25°C
VOUT = 1.8 V
TA = 25°C
图8-28. Start-Up Timing
图8-27. Start-Up Timing
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VIN = 12 V
VOUT = 5 V
2.5-MHz
IO = 1 A
VIN = 12 V
1-MHz Auto
PFM/PWM
IO = 3 A
PFM/PWM
TA = 25°C
VOUT = 1.2 V
TA = 25°C
图8-29. Start-Up Timing
图8-30. Output Voltage Ripple
VIN = 12 V
VOUT = 1.2 V
1-MHz Auto
PFM/PWM
IO = 0.1 A
TA = 25°C
VIN = 12 V
VOUT = 1.2 V
2.5-MHz Auto
PFM/PWM
IO = 3 A
TA = 25°C
图8-31. Output Voltage Ripple
图8-32. Output Voltage Ripple
VIN = 12 V
VOUT = 3.3 V
2.5-MHz Auto
PFM/PWM
IO = 1 A
TA = 25°C
VIN = 12 V
VOUT = 1.2 V
2.5-MHz Auto
PFM/PWM
IO = 0.1 A
TA = 25°C
图8-34. Output Voltage Ripple
图8-33. Output Voltage Ripple
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VIN = 12 V
VOUT = 3.3 V
2.5-MHz FPWM
IO = 0.1 A
TA = 25°C
VIN = 12 V
2.5-MHz FPWM
IO = 1 A
VOUT = 5.0 V
TA = 25°C
图8-35. Output Voltage Ripple
图8-36. Output Voltage Ripple
VIN = 12 V
VOUT = 1.2 V
1-MHz Auto
PFM/PWM
IO = 0.1 A to 1 A
TA = 25°C
VIN = 12 V
VOUT = 5.0 V
2.5-MHz Auto PFM/PWM
IO = 1 A
TA = 25°C
图8-37. Output Voltage Ripple
图8-38. PSM-to-PWM Transition
VIN = 12 V
1-MHz Auto
PFM/PWM
IO = 5 mA to 1 A
TA = 25°C
VIN = 12 V
1-MHz Auto
PFM/PWM
IO = 5 mA to 1 A to 5
mA
VOUT = 1.2 V
VOUT = 1.2 V
TA = 25°C
图8-40. Load Transient Response –Rising Edge
图8-39. Load Transient Response
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VIN = 12 V
1-MHz Auto
PFM/PWM
IO = 1 A to 5 mA
TA = 25°C
VIN = 12 V
IO = 5 mA to 2 A to 5 mA
VOUT = 3.3 V
2.5-MHz Auto
PFM/PWM
TA = 25°C
VOUT = 1.2 V
图8-41. Load Transient Response –Falling Edge
图8-42. Load Transient Response
VIN = 12 V
IO = 5 mA to 2 A to 5 mA
2.5-MHz FPWM TA = 25°C
VIN = 12 V
Output Discharge = Yes
TA = 25°C
VOUT = 3.3 V
VOUT = 1.2 V
图8-43. Load Transient Response
图8-44. Output Discharge Function –Enabled
4
3.5
3
4
VIN=15V
VIN=12V
VIN=9V
VIN=15V
VIN=12V
VIN=9V
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
25
35
45
55
65
75
85
95
105
115
125130
25
35
45
55
65
75
85
95
105
115
125130
Ambient Temperature ( °C )
Ambient Temperature ( °C )
Auto PFM/PWM
Fsw = 2.5 MHz
Auto PFM/PWM
Fsw = 2.5 MHz
图8-45. Thermal Derating VOUT = 1.2 V
图8-46. Thermal Derating VOUT = 3.3 V
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8.3 Typical Application with Setable VO Using VSET
VIN
VOUT
0.4V t 5.5V
TPSM8290x
3V t 17V
VIN
VOUT
EN
GND
C2
22…F
C1
10…F
FB/
VSET
SS/TR
R2
MODE/
S-CONF
PG
R3
C3
图8-47. Typical Application Circuit (VSET)
8.3.1 Design Requirements
VSET allows the user to set the output voltage using only one resistor to ground on the FB/VSET pin. 表 7-3
shows the 16 available options.
8.3.2 Detailed Design Procedure
The VSET option needs to be selected using the MODE/S-CONF pin. After the device is configured to VSET
operation, VO is sensed only through the VOS pin by an internal resistor divider. The target VO is programmed by
an external resistor R2 connected between FB/VSET and GND.
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8.3.3 Application Curves
VIN = 12 V
1-MHz Auto
PFM/PWM
IO = 1 A
VIN = 12 V
1-MHz Auto
PFM/PWM
IO = 100 mA
TA = 25°C
VOUT = 0.4 V
TA = 25°C
VOUT = 0.4 V
图8-48. Output Voltage Ripple
图8-49. Output Voltage Ripple
VIN = 12 V
VOUT = 0.4 V
1-MHz FPWM
IO = 1 A
TA = 25°C
VIN = 12 V
VOUT = 0.4 V
1-MHz FPWM
IO = 100 mA
TA = 25°C
图8-50. Output Voltage Ripple
图8-51. Output Voltage Ripple
1.2
1.15
1.1
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
-40C
-20C
0C
25C
85C
125C
1.05
1
0.95
0.9
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
0.85
0.8
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
1E-6
1E-5
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3
VIN (V)
IOUT (A)
VIN = 3 V–17 V
Temp = –40°C to 150°C
Auto PFM/PWM
Fsw = 1 MHz
图8-52. Output Voltage Accuracy –VSET Selected
图8-53. Efficiency vs Output Current
VOUT = 0.4 V
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90%
80%
70%
60%
50%
40%
30%
20%
10%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
0
1E-6
1E-5
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3
0.0005
0.002 0.005 0.01 0.02
0.05 0.1
0.2 0.3 0.50.7
1
2
3
IOUT (A)
IOUT (A)
Auto PFM/PWM
Fsw = 2.5 MHz
FPWM
Fsw = 1 MHz
图8-54. Efficiency vs Output Current
图8-55. Efficiency vs Output Current
VOUT = 0.4 V
VOUT = 0.4 V
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
2
IOUT=3A
IOUT=3A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
1.5
1
0.5
0
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
2
4
6
8
10
12
14
16
18
VIN (V)
VIN (V)
Auto PFM/PWM
Fsw = 1 MHz
Auto PFM/PWM
Fsw = 2.5 MHz
图8-56. Switching Frequency vs Input Voltage
图8-57. Switching Frequency vs Input Voltage
VOUT = 0.4 V
VOUT = 0.4 V
2
1.23
IOUT=3A
IOUT=2A
IOUT=1A
IOUT=0.4A
IOUT=0.1A
VIN=17V
VIN=15V
VIN=12V
VIN=9V
VIN=6V
VIN=3V
1.225
1.22
1.75
1.5
1.25
1
1.215
1.21
1.205
1.2
0.75
0.5
1.195
1.19
2
4
6
8
10
VIN (V)
12
14
16
18
1E-5
0.0001
0.001
0.010.02 0.05 0.1 0.2 0.5
IOUT (A)
1
2 3
FPWM
Fsw = 1 MHz
Auto PFM/PWM
Fsw = 1 MHz
图8-58. Switching Frequency vs Input Voltage
图8-59. Output Voltage vs Output Current
VOUT = 0.4 V
VOUT = 1.2 V
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5.6
5.55
5.5
VIN=17V
VIN=15V
VIN=12V
VIN=9V
5.45
5.4
1E-6
1E-5
0.0001
0.001
0.01
0.05
0.2 0.5
1
2 3
IOUT (A)
Auto PFM/PWM
Fsw = 2.5 MHz
图8-60. Output Voltage vs Output Current
VOUT = 5.5 V
8.4 Power Supply Recommendations
The power supply to the TPSM82903 must have a current rating according to the supply voltage, output voltage,
and output current of the TPSM82903.
8.5 Layout
8.5.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPSM82903 demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation, bad thermal performance, and noise sensitivity.
• See 图8-61 for the recommended layout of the TPSM82903, which is designed for common external ground
connections. TI recommends placing all components as close as possible to the package pins. The input and
output capacitors placement specifically, must be closest to the VIN, VOUT, and GND pins of the
TPSM82903.
• Provide low capacitive paths (with respect to all other nodes) for traces with high dv/dt. Therefore, the input
and output capacitance must be placed as close as possible to the IC pins and parallel wiring over long
distances as well as narrow traces must be avoided. Loops which conduct an alternating current must outline
an area as small as possible, as this area is proportional to the energy radiated.
• Sensitive nodes like FB needs to be connected with short wires and not nearby high dv/dt signals. As it
carries information about the output voltage, it must be connected as close as possible to the actual output
voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R1 and R2,
must be kept close to the module and connect directly to those pins and the system ground plane. The same
applies to VSET resistor if VSET is used to scale the output voltage.
• The package uses the pins for power dissipation. Thermal vias on the VIN, VOUT, and GND pins help to
spread the heat through the PCB.
• In case of the EN, and MODE/S-CONF need to be tied to the input supply voltage at VIN, the connection must
be made directly at the input capacitor as indicated in the schematics.
• The SW/NC pin must not be connected to any other traces. For best practice, this pin must be left floating. If
the pin is soldered to PCB copper, the pour needs to be: as small as possible, no inner layer connections, no
vias, electrically floating, and limited to the pin area as possible.
• Refer to 图8-61 for an example of component placement, routing and thermal design. The recommended
layout is implemented on the EVM and shown in its user's guide.
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8.5.2 Layout Example
图8-61. Layout
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8.5.2.1 Thermal Considerations
Implementation of power converter modules with low-profile and fine-pitch such as MircoSiP packages typically
requires special attention to power dissipation and thermal rise. Many system-dependent issues such as thermal
coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating
components affect the power-dissipation limits of a given component.
The TPSM82903 is designed for a maximum operating junction temperature (TJ) of 125°C. Therefore, the
maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,
given by the package and the surrounding PCB structures. If the thermal resistance of the package is given, the
size of the surrounding copper area and a proper thermal connection of the module can reduce the thermal
resistance. To get an improved thermal behavior, TI recommends to follow the following guidelines:
• Use a multi-layer PCB boards (at least four layers, with 1-oz or more copper).
• Use thermal vias on the GND pin to connect the GND top layer with the GND inner and bottom layers. This
helps dissipate the heat across layers.
• Generate as large a GND plane as allowable on the top and bottom layers, especially right near the package.
The exposed thermal pad of the device sits right at the middle of the package. This is ideal for thermal
dissipation. To take advantage of that, TI recommends the ground plan to cross through the package to allow
maximum ground plan connection with the exposed pad. See 图8-61 how the north ground pour is
connecting with the south ground pour as it crosses through the exposed pad of the package.
• Use thermal vias on the VIN and VOUT pins (as close as possible to the pin) and around input and output
capacitors to connect the VIN and VOUT top layer with the inner and bottom layers. This helps dissipate the
heat across layers as well as decreases the resistance drop on these traces.
• Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance and
helps on thermal dissipation.
• Introduce airflow in the system if possible.
• Refer to 图8-61 for an example of component placement, routing and thermal design.
For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic
Packages Using JEDEC PCB Designs and Semiconductor and IC Package Thermal Metrics application reports.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
The device is qualified for long term qualification with a 125°C junction temperature.
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9 Device and Documentation Support
9.1 Device Support
9.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
9.1.2 Development Support
9.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM82903 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.4 Trademarks
MicroSiP™, SmartConfig™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTSM82903SISB2R
TPSM82903SISR
ACTIVE
ACTIVE
uSiP
uSiP
SIS
SIS
11
11
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
Samples
Samples
3000 RoHS & Green
ENEPIG
Level-2-260C-1 YEAR
TM2903
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2023
Addendum-Page 2
PACKAGE OUTLINE
SIS0011A
MicroSiPTM - 1.6 mm max height
S
C
A
L
E
4
.
0
0
0
MICRO SYSTEM IN PACKAGE
2.9
2.7
B
A
(0.05)
PIN 1 INDEX &
MARKING AREA
3.1
2.9
PKG
DESIGNATED LASER
MARKING AREA
TEXT HEIGHT TO BE
150um MINIMUM
2.7
2.3
PICK AREA
NOTE 3
PKG
(0.1)
(0.1)
2.2
1.8
1.60 MAX
C
SEATING PLANE
0.08 C
0.34 MAX
2.1
0.94
0.86
EXPOSED
THERMAL PAD
(0.1) TYP
0.29
5
6X
6
0.21
0.1
0.05
C A
C
B
2X
2.275
SYMM
11
2.84
2.76
4X 0.5
0.565
0.485
4X
10
1
0.54
0.46
SYMM
PIN 1 ID
(OPTIONAL)
10X
0.1
C A
C
B
0.05
4226726/B 07/2021
MicroSiP is a trademark of Texas Instruments
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pick and place nozzle 1.3 mm or smaller recommended.
4. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
SIS0011A
MicroSiPTM - 1.6 mm max height
MICRO SYSTEM IN PACKAGE
10X (0.55)
(0.9)
(R0.05)
TYP
10
1
4X (0.5)
11
SYMM
(2.9)
2X
(2.325)
(2.4)
6X (0.25)
6
5
4X (0.575)
SYMM
(2.15)
(
0.2)
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:25X
(0.07) TYP
ALL AROUND
(0.05)
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON-SOLDER
MASK DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4226726/B 07/2021
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented
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EXAMPLE STENCIL DESIGN
SIS0011A
MicroSiPTM - 1.6 mm max height
MICRO SYSTEM IN PACKAGE
SOLDER MASK
EDGE TYP
2X (0.8)
10X (0.55)
1
10
2X
(1.3)
4X (0.5)
11
2X
(2.325)
SYMM
2X
(0.75)
6X (0.25)
4X
(0.575)
5
6
(R0.05)
TYP
EXPOSED
METAL
TYP
SYMM
(2.15)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4226726/B 07/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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