PTCAN3403DRBRQ1 [TI]
具有灵活 IO 和待机模式的汽车级 3.3V CAN FD 收发器 | DRB | 8 | -40 to 150;
| 型号： | PTCAN3403DRBRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有灵活 IO 和待机模式的汽车级 3.3V CAN FD 收发器 | DRB | 8 | -40 to 150 |
| 文件： | 总25页 (文件大小：2090K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCAN3404-Q1, TCAN3403-Q1
ZHCSRF5 –DECEMBER 2022
TCAN340x-Q1 具有待机模式的3.3V 汽车类CAN FD 收发器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100（1 级）标准
• 3.3 V 单电源工作
TCAN3403-Q1 和 TCAN3404-Q1 是满足 ISO
11898-2:2016 高速 CAN 规范中物理层要求的 3.3V 控
制器局域网(CAN) FD 收发器。
– 无需使用5V 稳压器，从而节省BOM 成本并减
小PCB 空间
• 符合ISO 11898-2:2016 物理层标准要求
• 支持传统CAN 和经优化的CAN FD 性能（数据速
率为2、5 和8Mbps）
– 具有较短的对称传播延迟时间，可增加时序裕量
• TCAN3403-Q1：I/O 电压范围支持：
1.7V 至3.6V
• 接收器共模输入电压：±12V
• 保护特性：
– 欠压保护
此类收发器具有经过认证的电磁兼容性 (EMC)，适用
于数据速率高达 5 兆位/秒 (Mbps) 的传统 CAN 和
CAN FD 网络。这些器件可以在更简单的网络中实现高
达 8Mbps 的运行速度。TCAN3403-Q1 包括通过 VIO
引脚实现的内部逻辑电平转换功能，能够将收发器 I/O
直接连接到 1.8V 、2.5V 或 3.3V 逻辑电平。
TCAN3404-Q1 具有关断功能，可将所有块断电并使器
件进入超低功耗模式。此类收发器支持低功耗待机模
式，并且可通过符合 ISO 11898-2:2016 所定义唤醒模
式(WUP) 的CAN 来唤醒。
– TXD 显性超时(DTO)
– 热关断保护(TSD)
• 工作模式：
此类收发器可进行热关断 (TSD)、TXD 显性超时
(DTO) 和电源欠压检测。这些器件定义了电源欠压或
浮动引脚情况下的失效防护行为。这些器件采用业界通
用的 SOIC-8、VSON-8 和节省空间的小尺寸 SOT-23
封装。
– 正常模式
– 支持远程唤醒请求功能的低功耗待机模式
– 超低功耗关断模式：
封装信息
封装(1)
仅限TCAN3404-Q1
• 优化了未上电时的性能
封装尺寸（标称值）
4.90mm x 3.91mm
3.00mm x 3.00mm
2.90mm x 1.60mm
器件型号
SOIC (D)
– 总线和逻辑引脚为高阻抗（运行总线或应用上无
负载）
– 支持热插拔：在总线和RXD 输出上可实现上电
和断电无干扰运行
TCAN3403-Q1
TCAN3404-Q1
VSON (DRB)
SOT-23 (DDF)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 具有可湿性侧面的小型8 引脚SOIC SOT-23 和无
引线VSON-8 封装，可实现自动光学检测(AOI)
2 应用
VOUT
VIN
VIN
• 汽车和运输
3.3 V Voltage
Regulator
3
VCC
7
VDD
CANH
– 车身控制模块
– 汽车网关
8
5
STB
SHDN
TCAN3404
MCU
– 高级驾驶辅助系统(ADAS)
– 信息娱乐系统
4
1
CAN FD
Controller
RXD
TXD
6
CANL
GND
Optional:
Terminating Node
Optional: Filtering,
Transient and ESD
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFT5
TCAN3404-Q1, TCAN3403-Q1
ZHCSRF5 –DECEMBER 2022
www.ti.com.cn
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................2
6 Pin Configuration and Functions...................................3
7 Device and Documentation Support..............................4
7.1 接收文档更新通知....................................................... 4
7.2 支持资源......................................................................4
7.3 Trademarks.................................................................4
7.4 Electrostatic Discharge Caution..................................4
7.5 术语表......................................................................... 4
8 Mechanical, Packaging, and Orderable Information....4
8.1 Tape and Reel Information..........................................5
8.2 Mechanical Data......................................................... 7
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2022
*
Initial Release
5 Device Comparison
Part Number
TCAN3404-Q1
Pin 5
Pin 8
Ultra-low power shutdown mode
Low voltage I/O support
Low Power Standby Mode with Remote
Wake
TCAN3403-Q1
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6 Pin Configuration and Functions
TXD
1
2
3
4
8
7
6
5
STB
TXD
1
2
3
4
8
7
6
5
STB
GND
CANH
CANL
SHDN,V
GND
CANH
CANL
SHDN,V
V
ꢀ
V
ꢀ
CC
RXD
CC
RXD
ꢀ
ꢀ
IO
IO
Not to scale
Not to scale
图6-1. DDF Package, 8-Pin SOT-23
图6-2. D Package, 8-Pin SOIC
(Top View)
(Top View)
TXD
1
2
3
4
8
7
6
5
STB
GND
CANH
CANL
Thermal
Pad
V
ꢀ
CC
RXD
SHDN,V
ꢀ
IO
Not to scale
图6-3. DRB Package, 8-Pin VSON
(Top View)
表6-1. Pin Functions
PINS
TYPE(1)
DESCRIPTION
NAME
TXD
NO.
1
Digital Input CAN transmit data input; integrated pull-up
GND
VCC
2
G
Ground connection
3.3 V supply voltage
3
Supply
RXD
4
Digital Output CAN receive data output, tri-stated when device powered off
Device in ultra-low power shutdown mode if pin is high; integrated pull-down (TCAN3404-
Q1 only)
SHDN
Digital Input
5
VIO
Supply
Bus I/O
Bus I/O
I/O supply voltage (TCAN3403-Q1 only)
Low-level CAN bus input/output line
High-level CAN bus input/output line
CANL
CANH
STB
6
7
8
Digital Input Standby input for mode control; integrated pull-up
Connect the thermal pad to any internal PCB ground plane using multiple vias for optimal
thermal performance.
Thermal Pad (VSON only)
—
(1) I = Input, O = Output, I/O = Input or Output, G = Ground.
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7 Device and Documentation Support
7.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
7.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
7.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
7.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
7.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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8.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
SOT-23-
THN
PTCAN3403DDFRQ1
DDF
8
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
PTCAN3403DRBRQ1
PTCAN3403DRBRQ1
VSON
SOIC
DRB
D
8
8
3000
2500
330.0
330.0
12.4
12.4
3.3
6.4
3.3
5.2
1.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
SOT-23-THN
VSON
Package Drawing Pins
SPQ
3000
3000
2500
Length (mm) Width (mm)
Height (mm)
35.0
PTCAN3403DDFRQ1
PTCAN3403DRBRQ1
PTCAN3403DRBRQ1
DDF
DRB
D
8
8
8
210.0
367.0
356.0
185.0
367.0
356.0
35.0
SOIC
35.0
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8.2 Mechanical Data
PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
.041
[1.04]
4221445/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.055)
[1.4]
8X (.061 )
[1.55]
SEE
DETAILS
SEE
DETAILS
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
(R.002 ) TYP
[0.05]
(R.002 )
[0.05]
TYP
5
5
4
6X (.050 )
[1.27]
4
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSDE
METAL
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
.0028 MAX
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
(R.002 ) TYP
[0.05]
(R.002 )
[0.05]
TYP
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1 MAX
C
SEATING PLANE
0.05
0.00
0.08
C
1.75
1.55
(0.2) TYP
6X 0.65
(0.19)
4
5
SYMM
9
2.5
2.3
1.95
1
8
0.36
8X
0.26
0.1
0.05
PIN 1 ID
(OPTIONAL)
C
A B
SYMM
C
0.5
0.3
8X
4225036/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.55)
( 0.2) VIA
TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222121/C 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
2X
(1.51)
8X (0.6)
8X (0.31)
SYMM
1
8
2X
(1.06)
6X (0.65)
SYMM
(1.95)
(0.63)
9
(R0.05) TYP
4
5
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED COVERAGE BY AREA
SCALE: 20X
4225036/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TCAN3404-Q1 TCAN3403-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTCAN3403DDFRQ1
PTCAN3403DRBRQ1
PTCAN3403DRQ1
ACTIVE SOT-23-THIN
DDF
DRB
D
8
8
8
8
8
8
3000
3000
2500
3000
3000
2500
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
Samples
Samples
Samples
Samples
Samples
Samples
ACTIVE
ACTIVE
SON
Call TI
Call TI
Call TI
Call TI
Call TI
SOIC
PTCAN3404DDFRQ1
PTCAN3404DRBRQ1
PTCAN3404DRQ1
ACTIVE SOT-23-THIN
DDF
DRB
D
ACTIVE
ACTIVE
SON
SOIC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jul-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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