PGA112AIDGSTG4_技术文档

PGA112, PGA113

PGA116, PGA117

www.ti.com ............................................................................................................................................ SBOS424B–MARCH 2008–REVISED SEPTEMBER 2008

Zerø-Drift

PROGRAMMABLE GAIN AMPLIFIER with MUX

1

FEATURES

APPLICATIONS

•

Remote e-Meter Reading

Automatic Gain Control

23

•

Rail-to-Rail Input/Output

•

Offset: 25µV (typ), 100µV (max)

Zerø Drift: 0.35µV/°C (typ), 1.2µV/°C (max)

Low Noise: 12nV/√Hz

Portable Data Acquisition

PC-Based Signal Acquisition Systems

Test and Measurement

Programmable Logic Controllers

Battery-Powered Instruments

Handheld Test Equipment

Input Offset Current: ±5nA max (+25°C)

Gain Error: 0.1% max (G ≤ 32),

0.3% max (G > 32)

•

Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128

(PGA112, PGA116)

DESCRIPTION

Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200

(PGA113, PGA117)

The PGA112 and PGA113 (binary/scope gains) offer

two analog inputs, a three-pin SPI interface, and

software shutdown in an MSOP-10 package. The

PGA116 and PGA117 (binary/scope gains) offer 10

•

Gain Switching Time: 200ns

Two Channel MUX: PGA112, PGA113

10 Channel MUX: PGA116, PGA117

analog inputs,

a

four-pin SPI interface with

daisy-chain capability, and hardware and software

shutdown in a TSSOP-20 package.

•

Four Internal Calibration Channels

Amplifier Optimized for Driving CDAC ADCs

Output Swing: 50mV to Supply Rails

AV_DDand DV_DDfor Mixed Voltage Systems

I_Q= 1.1mA (typ)

All versions provide internal calibration channels for

system-level calibration. The channels are tied to

GND, 0.9V_CAL, 0.1V_CAL, and V_REF, respectively. V_CAL

,

an external voltage connected to Channel 0, is used

as the system calibration reference. Binary gains are:

1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2,

5, 10, 20, 50, 100, and 200.

Software/Hardware Shutdown: I_Q≤ 4µA (typ)

Temperature Range: –40°C to +125°C

SPI™ Interface (10MHz) with Daisy-Chain

Capability

+3V

+5V

C_BYPASS

0.1mF

AV_DD

1

DV_DD

10

MSP430

PGA112

Microcontroller

ADC

PGA113

3

2

MUX

V_CAL/CH0

CH1

5

V_OUT

Output

Stage

CAL1

10kW

80kW

R_F

G = 1

0.9V_CAL

0.1V_CAL

CAL2

CAL3

CAL4

V_REF

R_I

7

8

9

SCLK

DIO

CS

SPI

Interface

CAL2/3

10kW

6

4

GND

V_REF

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PGA112, PGA113

PGA116, PGA117

SBOS424B–MARCH 2008–REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE AND MODEL COMPARISON

SHUTDOWN

# OF MUX

INPUTS

GAINS

(Eight Each)

SPI

DEVICE

PGA112

PGA113

PGA116

PGA117

DAISY-CHAIN

HARDWARE

SOFTWARE

PACKAGE

MSOP-10

TSSOP-20

Two

10

Binary

Scope

Binary

Scope

No

ü

No

ü

10

ü

ORDERING INFORMATION⁽¹⁾

DESCRIPTION

PACKAGE

PRODUCT

PGA112

PGA113

PGA116

PGA117

(Gains/Channels)

Binary⁽²⁾/2 Channels

Scope⁽³⁾/2 Channels

Binary⁽²⁾/10 Channels

Scope⁽³⁾/10 Channels

PACKAGE-LEAD

MSOP-10

DESIGNATOR

MARKING

DGS

PW

P112

MSOP-10

P113

TSSOP-20

PGA116

PGA117

PW

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Binary gains: 1, 2, 4, 8, 16, 32, 64, and 128.

(3) Scope gains: 1, 2, 5, 10, 20, 50, 100, and 200.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

PGA112, PGA113, PGA116, PGA117

UNIT

V

Supply Voltage

+7

Signal Input Terminals, Voltage⁽²⁾

Signal Input Terminals, Current⁽²⁾

Output Short-Circuit

GND – 0.5 to (AV_DD) + 0.5

V

±10

Continuous

–40 to +125

–65 to +150

+150

mA

Operating Temperature

Storage Temperature

°C

V

Junction Temperature

Human Body Model (HBM)

3000

ESD Ratings:

Charged Device Model (CDM)

Machine Model (MM)

1000

V

300

V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should

be current limited to 10mA or less.

2

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PGA112, PGA113

PGA116, PGA117

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ELECTRICAL CHARACTERISTICS: V_S= AV_DD= DV_DD= +5V

Boldface limits apply over the specified temperature range, T_A= –40°C to +125°C.

At T_A= +25°C, R_L= 10kΩ//C_L= 100pF connected to DV_DD/2, and V_REF= GND, unless otherwise noted.

PGA112, PGA113, PGA116, PGA117

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

Input Offset Voltage

V_OS

AV_DD= DV_DD= +5V, V_REF= V_IN= AV_DD/2, V_CM= 2.5V

AV_DD= DV_DD= +5V, V_REF= V_IN= AV_DD/2, V_CM= 4.5V

AV_DD= DV_DD= +5V, V_CM= 2.5V

±25

±75

0.35

0.15

0.6

±100

±325

1.2

µV

vs Temperature, –40°C to +125°C

vs Temperature, –40°C to +85°C

vs Temperature, –40°C to +125°C

vs Temperature, –40°C to +85°C

dV_OS/dT

µV/°C

AV_DD= DV_DD= +5V, V_CM= 2.5V

0.9

AV_DD= DV_DD= +5V, V_CM= 4.5V

1.8

AV_DD= DV_DD= +5V, V_CM= 4.5V

0.3

1.3

AV_DD= DV_DD= +2.2V to +5.5V, V_CM= 0.5V,

V_REF= V_IN= AV_DD/2

vs Power Supply

PSRR

5

20

µV/V

AV_DD= DV_DD= +2.2V to +5.5V, V_CM= 0.5V,

V_REF= V_IN= AV_DD/2

Over Temperature, –40°C to +125°C

5

40

INPUT ON-CHANNEL CURRENT

Input On-Channel Current (Ch0, Ch1)

Over Temperature, –40°C to +125°C

INPUT VOLTAGE RANGE

Input Voltage Range⁽¹⁾

I_IN

V_REF= V_IN= AV_DD/2

±1.5

±5

nA

V_REF= V_IN= AV_DD/2

See Typical Characteristics

nA

I_VR

GND – 0.1

AV_DD+ 0.1

AV_DD+ 0.3

V

Overvoltage Input Range

INPUT IMPEDANCE (Channel On)⁽³⁾

Channel Input Capacitance

Channel Switch Resistance

Amplifier Input Capacitance

Amplifier Input Resistance

V_CAL/CH0

No Output Phase Reversal⁽²⁾

GND – 0.3

C_CH

R_SW

C_AMP

R_AMP

R_IN

2

pF

Ω

150

3

pF

GΩ

kΩ

Input Resistance to GND

CAL1 or CAL2 Selected

10

100

GAIN SELECTIONS

Nominal Gains

Binary gains: 1, 2, 4, 8, 16, 32, 64, 128

Scope gains: 1, 2, 5, 10, 20, 50, 100, 200

V_OUT= GND + 85mV to DV_DD– 85mV

1

128

200

0.1

0.3

DC Gain Error

G = 1

1 < G ≤ 32

G ≥ 50

0.006

%

DC Gain Drift

G = 1

0.5

2

ppm/°C

1 < G ≤ 32

G ≥ 50

6

Op Amp + Input = 0.9V_CAL

V_REF= V_CAL= AV_DD/2, G = 1

,

CAL2 DC Gain Error⁽⁴⁾

CAL2 DC Gain Drift⁽⁴⁾

CAL3 DC Gain Error⁽⁴⁾

CAL3 DC Gain Drift⁽⁴⁾

0.02

2

%

Op Amp + Input = 0.9V_CAL

V_REF= V_CAL= AV_DD/2, G = 1

,

ppm/°C

%

Op Amp + Input = 0.1V_CAL

,

0.02

2

V_REF= V_CAL= AV_DD/2, G = 1

Op Amp + Input = 0.1V_CAL

V_REF= V_CAL= AV_DD/2, G = 1

,

ppm/°C

INPUT IMPEDANCE (Channel Off)⁽³⁾

Input Impedance

C_CH

See Figure 1

2

pF

nA

INPUT OFF-CHANNEL CURRENT

V_REF= GND, V_OFF-CHANNEL= AV_DD/2,

V_ON-CHANNEL= AV_DD/2 – 0.1V

Input Off-Channel Current (Ch0, Ch1)⁽⁵⁾

I_LKG

±0.05

±1

V_REF= GND, V_OFF-CHANNEL= AV_DD/2,

V_ON-CHANNEL= AV_DD/2 – 0.1V

Over Temperature, –40°C to +125°C

See Typical Characteristics

Channel-to-Channel Crosstalk

130

dB

(1) Gain error is a function of the input voltage. Gain error outside of the range (GND + 85mV ≤ V_OUT≤ DV_DD– 85mV) increases to 0.5%

(typical).

(2) Input voltages beyond this range must be current limited to < |10mA| through the input protection diodes on each channel to prevent

permanent destruction of the device.

(3) See Figure 1.

(4) Total V_OUTerror must be computed using input offset voltage error multiplied by gain. Includes op amp G = 1 error.

(5) Maximum specification limitation limited by final test time and capability.

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PGA112, PGA113

PGA116, PGA117

SBOS424B–MARCH 2008–REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= AV_DD= DV_DD= +5V (continued)

Boldface limits apply over the specified temperature range, T_A= –40°C to +125°C.

At T_A= +25°C, R_L= 10kΩ//C_L= 100pF connected to DV_DD/2, and V_REF= GND, unless otherwise noted.

PGA112, PGA113, PGA116, PGA117

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

(6)

Voltage Output Swing from Rail

I_OUT= ±0.25mA, AV_DD≥ DV_DD

GND + 0.05

GND + 0.25

DV_DD– 0.05

DV_DD– 0.25

V

(6)

I_OUT= ±5mA, AV_DD≥ DV_DD

DC Output Nonlinearity

Short-Circuit Current

Capacitive Load Drive

NOISE

V_OUT= GND + 85mV to DV_DD– 85mV⁽⁷⁾

0.0015

%FSR

mA

I_SC

–30/+60

C_LOAD

See Typical Characteristics

Input Voltage Noise Density

e_n

I_n

f > 10kHz, C_L= 100pF, V_S= 5V

f > 10kHz, C_L= 100pF, V_S= 2.2V

f = 0.1Hz to 10Hz, C_L= 100pF, V_S= 5V

f = 0.1Hz to 10Hz, C_L= 100pF, V_S= 2.2V

f = 10kHz, C_L= 100pF

12

22

nV/√Hz

µV_PP

Input Voltage Noise

0.362

0.736

400

µV_PP

Input Current Density

SLEW RATE

fA/√Hz

Slew Rate

SR

t_S

See Table 1

V/µs

µs

SETTLING TIME

Settling Time

FREQUENCY RESPONSE

Frequency Response

THD + NOISE

MHz

G = 1, f = 1kHz, V_OUT= 4V_PPat 2.5V_DC, C_L= 100pF

G = 10, f = 1kHz, V_OUT= 4V_PPat 2.5V_DC, C_L= 100pF

G = 50, f = 1kHz, V_OUT= 4V_PPat 2.5V_DC, C_L= 100pF

G = 128, f = 1kHz, V_OUT= 4V_PPat 2.5V_DC, C_L= 100pF

G = 200, f = 1kHz, V_OUT= 4V_PPat 2.5V_DC, C_L= 100pF

G = 1, f = 20kHz, V_OUT= 4V_PPat 2.5V_DC, C_L= 100pF

G = 10, f = 20kHz, V_OUT= 4V_PPat 2.5V_DC, C_L= 100pF

G = 50, f = 20kHz, V_OUT= 4V_PPat 2.5V_DC, C_L= 100pF

G = 128, f = 20kHz, V_OUT= 4V_PPat 2.5V_DC, C_L= 100pF

G = 200, f = 20kHz, V_OUT= 4V_PPat 2.5V_DC, C_L= 100pF

0.003

0.005

0.03

0.08

0.1

%

0.02

0.01

0.03

0.08

0.11

POWER SUPPLY

Operating Voltage Range⁽⁶⁾

AV_DD

DV_DD

I_QA

2.2

5.5

V

Quiescent Current Analog

I_O= 0, G = 1, V_OUT= V_REF

0.33

0.75

0.45

mA

Over Temperature, –40°C to +125°C

I_O= 0, G = 1, V_OUT= V_REF, SCLK at 10MHz,

CS = Logic 0, DIO or DIN = Logic 0

Quiescent Current Digital^(8)(9)(10)

I_QD

1.2

mA

I_O= 0, G = 1, V_OUT= V_REF, SCLK at 10MHz,

CS = Logic 0, DIO or DIN = Logic 0

Over Temperature, –40°C to +125°C^(8)(9)(10)

1.2

mA

µA

Shutdown Current Analog + Digital⁽⁸⁾⁽⁹⁾

I_SDA+ I_SDD

I_O= 0, V_OUT= V_REF, G = 1, SCLK Idle

4

I_O= 0, V_OUT= 0, G = 1, SCLK at 10MHz,

CS = Logic 0, DIO or DIN = Logic 0

245

µA

POWER-ON RESET (POR)

Digital interface disabled and Command Register set to POR

values for DV_DD< POR Trip Voltage

POR Trip Voltage

1.6

V

(6) When AV_DDis less than DV_DD, the output is clamped to AV_DD+ 300mV.

(7) Measurement limited by noise in test equipment and test time.

(8) Does not include current into or out of the V_REFpin. Internal R_Fand R_Iare always connected between V_OUTand V_REF

(9) Digital logic levels: DIO or DIN = logic 0. 10µA internal pull-down current source.

(10) Includes current from op amp output structure.

.

4

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PGA112, PGA113

PGA116, PGA117

www.ti.com ............................................................................................................................................ SBOS424B–MARCH 2008–REVISED SEPTEMBER 2008

ELECTRICAL CHARACTERISTICS: V_S= AV_DD= DV_DD= +5V (continued)

Boldface limits apply over the specified temperature range, T_A= –40°C to +125°C.

At T_A= +25°C, R_L= 10kΩ//C_L= 100pF connected to DV_DD/2, and V_REF= GND, unless otherwise noted.

PGA112, PGA113, PGA116, PGA117

PARAMETER

TEMPERATURE RANGE

CONDITIONS

MIN

TYP

MAX

UNIT

Specified Range

–40

+125

°C

Operating Range

Thermal Resistance

MSOP-10

θ_JA

164

°C/W

DIGITAL INPUTS (SCLK, CS, DIO, DIN)

Logic Low

0

0.3DV_DD

+1

V

µA

V

Input Leakage Current (SCLK and CS only)

Weak Pull-Down Current (DIO, DIN only)

Logic High

–1

10

0.7DV_DD

DV_DD

Hysteresis

700

mV

DIGITAL OUTPUT (DIO, DOUT)

Logic High

I_OH= –3mA (sourcing)

I_OL= +3mA (sinking)

DV_DD– 0.4

GND

DV_DD

V

Logic Low

GND + 0.4

CHANNEL AND GAIN TIMING

Channel Select Time

Gain Select Time

0.2

µs

SHUTDOWN MODE TIMING

Enable Time

4.0

2.0

µs

V_OUTgoes high-impedance, R_Fand R_Iremain connected

between V_OUTand V_REF

Disable Time

POWER-ON-RESET (POR) TIMING

POR Power-Up Time

DV_DD≥ 2V

40

5

µs

POR Power-Down Time

DV_DD≤ 1.5V

Table 1. Frequency Response versus Gain (C_L= 100pF, R_L= 10kΩ)

0.1%

0.01%

0.1%

0.01%

TYPICAL

–3dB

FREQUENCY

(MHz)

SLEW

RATE-

FALL

SLEW

RATE-

RISE

SETTLING SETTLING

TYPICAL

–3dB

FREQUENCY

(MHz)

SLEW

RATE-

FALL

SLEW

RATE-

RISE

SETTLING SETTLING

TIME:

4V_PP

(µs)

TIME:

4V_PP

(µs)

SCOPE

GAIN

(V/V)

TIME:

4V_PP

(µs)

TIME:

4V_PP

(µs)

BINARY

GAIN (V/V)

(V/µs)

1

2

10

3.8

2

8

3

2

2.55

2.6

3

1

2

10

3.8

8

9

3

2

2.55

2.6

2.8

3.8

7

9

6.4

10.6

9.1

7.1

3.5

2

4

12.8

4

10.6

12.8

13.3

3.5

2

5

1.8

12.8

9.1

4

2

8

1.8

1.6

1.8

0.6

0.35

2

10

20

50

100

200

1.8

2.2

2.3

2.4

4.4

6.9

16

32

64

128

2.3

3

1.3

0.9

6

0.38

0.23

2.5

4.8

8

2.3

10

Mux

Switch

R_SW

CHx

(Input)

V_OUT

C_CH

Break-Before-Make

C_AMP

R_AMP

R_F

R_I

V_REF

Figure 1. Equivalent Input Circuit

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PGA112, PGA113

PGA116, PGA117

SBOS424B–MARCH 2008–REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com

SPI TIMING: V_S= AV_DD= DV_DD= +2.2V to +5V

Boldface limits apply over the specified temperature range, T_A= –40°C to +125°C.

At T_A= +25°C, R_L= 10kΩ//C_L= 100pF connected to DV_DD/2, and V_REF= GND, unless otherwise noted.

PGA112, PGA113,

PGA116, PGA117

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input Capacitance (SCLK, CS, and DIO pins)

1

pF

Input Rise/Fall Time⁽¹⁾

(CS, SCLK, and DIO pins)

t_RFI

2

µs

Output Rise/Fall Time (DIO pin)⁽¹⁾

CS High Time (CS pin)⁽¹⁾

SCLK Edge to CS Fall Setup Time⁽¹⁾

CS Fall to First SCLK Edge Setup Time

SCLK Frequency⁽²⁾

SCLK High Time⁽³⁾

SCLK Low Time⁽³⁾

SCLK Last Edge to CS Rise Setup Time⁽¹⁾

CS Rise to SCLK Edge Setup Time⁽¹⁾

DIN Setup Time

t_RFO

t_CSH

t_CSO

t_CSSC

f_SCLK

t_HI

C_LOAD= 60pF

10

ns

40

10

ns

10

MHz

ns

40

10

t_LO

ns

t_SCCS

t_CS1

t_SU

ns

DIN Hold Time

t_HD

ns

SCLK to DOUT Valid Propagation Delay⁽¹⁾

CS Rise to DOUT Forced to Hi-Z⁽¹⁾

t_DO

25

20

ns

t_SOZ

ns

(1) Ensured by design; not production tested.

(2) When using devices in daisy-chain mode, the maximum clock frequency for SCLK is limited by SCLK rise/fall time, DIN setup time, and

DOUT propagation delay. See Figure 63. Based on this limitation, the maximum SCLK frequency for daisy-chain mode is 9.09MHz.

(3) t_HIand t_LOmust not be less than 1/SCLK (max).

6

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PGA112, PGA113

PGA116, PGA117

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SPI TIMING DIAGRAMS

t_CSH

CS

t_CSSC

t_SCCSt_CS1

t_CS0

t_LO

t_HI

SCLK

1/f_SCLK

t_SU

t_HD

DIN

t_DO

t_SOZ

Hi-Z

DOUT

Figure 2. SPI Mode 0, 0

t_CSH

CS

SCLK

DIN

t_CSSC

t_SCCSt_CS1

t_CS0

t_HI

t_LO

1/f_SCLK

t_SU

t_HD

t_DO

t_SOZ

Hi-Z

DOUT

Figure 3. SPI Mode 1, 1

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PGA112, PGA113

PGA116, PGA117

SBOS424B–MARCH 2008–REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com

PIN CONFIGURATIONS

MSOP-10

DGS PACKAGE

(TOP VIEW)

AV_DD

CH1

1

2

3

4

5

10 DV_DD

9

8

7

6

CS

PGA112

PGA113

V_CAL/CH0

V_REF

DIO

SCLK

GND

V_OUT

PGA112, PGA113 TERMINAL FUNCTIONS

MSOP

PACKAGE

PIN #

NAME

AV_DD

CH1

DESCRIPTION

1

2

Analog supply voltage (+2.2V to +5.5V)

Input MUX channel 1

Input MUX channel 0 and V_CALinput. For system calibration purposes, connect this pin to a

low-impedance external reference voltage to use internal calibration channels. The four internal

calibration channels are connected to GND, 0.9V_CAL, 0.1V_CAL, and V_REF, respectively. V_CALis loaded

with 100kΩ (typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise,

V_CAL/CH0 appears as high impedance.

3

V_CAL/CH0

Reference input pin. Connect external reference for V_OUToffset shift or to midsupply for midsupply

referenced systems. V_REFmust be connected to a low-impedance reference capable of sourcing and

sinking at least 2mA or V_REFmust be connected to GND.

4

V_REF

5

6

7

8

9

V_OUT

GND

SCLK

DIO

Analog voltage output. When AV_DD< DV_DD, V_OUTis clamped to AV_DD+ 300mV.

Ground pin

Clock input for SPI serial interface

Data input/output for SPI serial interface. DIO contains a weak, 10µA internal pull-down current source.

Chip select line for SPI serial interface

CS

Digital and op amp output stage supply voltage (+2.2V to +5.5V). Useful in multi-supply systems to

prevent overvoltage/lockup condition on an analog-to-digital (ADC) input (for example, a microcontroller

10

DV_DD

with an ADC running on +3V and the PGA powered from +5V). Digital I/O levels to be relative to DV_DD

DV_DDshould be bypassed with a 0.1µF ceramic capacitor, and DV_DDmust supply the current for the

digital portion of the PGA as well as the load current for the op amp output stage.

.

8

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TSSOP-20

PW PACKAGE

(TOP VIEW)

AV_DD

CH5

1

2

3

4

5

6

7

8

9

20 CH6

19 DV_DD

18 CS

CH4

CH3

17 DOUT

PGA116

PGA117

CH2

16

DIN

CH1

15 SCLK

14 GND

13 ENABLE

12 CH9

V_CAL/CH0

V_REF

V_OUT

CH7 10

11 CH8

PGA116, PGA117 TERMINAL FUNCTIONS

TSSOP

PACKAGE

PIN #

NAME

AV_DD

CH5

CH4

CH3

CH2

CH1

DESCRIPTION

1

2

3

4

5

6

Analog supply voltage (+2.2V to +5.5V)

Input MUX channel 5

Input MUX channel 4

Input MUX channel 3

Input MUX channel 2

Input MUX channel 1

Input MUX channel 0 and V_CALinput. For system calibration purposes, connect this pin to a

low-impedance external reference voltage to use internal calibration channels. The four internal

calibration channels are connected to GND, 0.9V_CAL, 0.1V_CAL, and V_REF, respectively. V_CALis loaded

with 100kΩ (typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise,

V_CAL/CH0 appears as high impedance.

7

8

V_CAL/CH0

Reference input pin. Connect external reference for V_OUToffset shift or to midsupply for midsupply

referenced systems. V_REFmust be connected to a low-impedance reference capable of sourcing and

sinking at least 2mA or to GND.

V_REF

9

V_OUT

CH7

Analog voltage output. When AV_DD< DV_DD, V_OUTis clamped to AV_DD+ 300mV.

10

11

12

13

14

15

Input MUX channel 7

CH8

Input MUX channel 8

CH9

Input MUX channel 9

ENABLE

GND

Hardware enable pin. Logic low puts the part into Shutdown mode (I_Q< 1µA).

Ground pin

SCLK

Clock input for SPI serial interface

Data input for SPI serial interface. DIN contains a weak, 10µA internal pull-down current source to

allow for ease of daisy-chain configurations.

16

DIN

Data output for SPI serial interface. DOUT goes to high-Z state when CS goes high for standard SPI

interface.

17

18

DOUT

CS

Chip select line for SPI serial interface

Digital and op amp output stage supply voltage (+2.2V to +5.5V). Useful in multi-supply systems to

prevent overvoltage/lockup condition on an ADC input (for example, a microcontroller with an ADC

running on +3V and the PGA powered from +5V). Digital I/O levels to be relative to DV_DD. DV_DDshould

be bypassed with a 0.1µF ceramic capacitor, and DV_DDmust supply the current for the digital portion of

the PGA as well as the load current for the op amp output stage.

19

20

DV_DD

CH6

Input MUX channel 6

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TYPICAL APPLICATION CIRCUITS

+3V

+5V

C_BYPASS

0.1mF

AV_DD

1

DV_DD

10

MSP430

PGA112

Microcontroller

ADC

PGA113

3

2

MUX

V_CAL/CH0

CH1

5

V_OUT

Output

Stage

CAL1

10kW

80kW

R_F

G = 1

0.9V_CAL

0.1V_CAL

CAL2

CAL3

CAL4

V_REF

R_I

7

8

9

SCLK

DIO

CS

SPI

Interface

CAL2/3

10kW

6

4

GND

V_REF

Figure 4. PGA112, PGA113 (MSOP-10)

+5V

C_BYPASS

0.1mF

AV_DD

1

7

+3V

V_CAL/CH0

6

19 DV_DD

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

5

C_BYPASS

0.1mF

PGA116

PGA117

C_BYPASS

4

0.1mF

3

2

MSP430

20

10

11

12

Microcontroller

MUX

9

V_OUT

Output

Stage

ADC

CAL1

10kW

80kW

R_F

G = 1

0.9V_CAL

0.1V_CAL

CAL2

CAL3

CAL4

15 SCLK

16 DIN

V_REF

R_I

SPI

Interface

18 CS

CAL2/3

10kW

17 DOUT

14

8

13

ENABLE

GND

V_REF

Figure 5. PGA116, PGA117 (TSSOP-20)

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TYPICAL CHARACTERISTICS

At T_A= +25°C, AV_DD= DV_DD= 5V, R_L= 10kΩ connected to DV_DD/2, V_REF= GND, and C_L= 100pF, unless otherwise noted.

OFFSET VOLTAGE

V_CM= 4.5V

V_CM= 2.5V

Offset Voltage (mV)

Figure 6.

Figure 7.

OFFSET VOLTAGE DRIFT

(–40°C to +85°C)

OFFSET VOLTAGE DRIFT

(–40°C TO +85°C)

V_CM= 4.5V

V_CM= 2.5V

Offset Voltage Drift (mV/°C)

Figure 8.

Figure 9.

OFFSET VOLTAGE DRIFT

(–40°C to +125°C)

OFFSET VOLTAGE DRIFT

(–40°C TO +125°C)

V_CM= 4.5V

V_CM= 2.5V

Offset Voltage Drift (mV/°C)

Figure 10.

Figure 11.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AV_DD= DV_DD= 5V, R_L= 10kΩ connected to DV_DD/2, V_REF= GND, and C_L= 100pF, unless otherwise noted.

INPUT OFFSET VOLTAGE vs INPUT VOLTAGE

PGA112/PGA116 NONLINEARITY

0.0010

0.0008

0.0006

0.0004

0.0002

0

100

80

AV_DD= DV_DD= +5V

G = 1

G = 2

60

40

20

0

-0.0002

-0.0004

-0.0006

-0.0008

-0.0010

-20

-40

-60

-80

-100

G = 16

G = 128

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0

1

2

3

4

5

Input Voltage (V)

V_OUT(V)

Figure 12.

Figure 13.

GAIN ERROR (G = 1)

GAIN ERROR (1 < G ≤ 32)

Gain Error (%)

Figure 14.

Figure 15.

GAIN ERROR DRIFT

(–40°C to +125°C)

GAIN ERROR (G ≥ 50)

G = 1

Gain Error Drift (ppm/°C)

Gain Error (%)

Figure 16.

Figure 17.

12

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AV_DD= DV_DD= 5V, R_L= 10kΩ connected to DV_DD/2, V_REF= GND, and C_L= 100pF, unless otherwise noted.

GAIN ERROR DRIFT

(–40°C to +125°C)

GAIN ERROR DRIFT

(–40°C to +125°C)

1 < G £ 32

G ³ 50

Gain Error Drift (ppm/°C)

Figure 19.

Gain Error Drift (ppm/°C)

Figure 18.

CAL2 GAIN ERROR

CAL3 GAIN ERROR

Gain Error (%)

Figure 20.

Figure 21.

CAL2 GAIN ERROR DRIFT

(–40°C to +125°C)

CAL3 GAIN ERROR DRIFT

(–40°C to +125°C)

Gain Error Drift (ppm/°C)

Figure 22.

Figure 23.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AV_DD= DV_DD= 5V, R_L= 10kΩ connected to DV_DD/2, V_REF= GND, and C_L= 100pF, unless otherwise noted.

0.1Hz TO 10Hz NOISE

V_S= 2.2V

V_S= 5V

2.5s/div

Figure 24.

Figure 25.

PGA112, PGA116 THD + NOISE vs FREQUENCY

(V_OUT= 2V_PP

SPECTRAL NOISE DENSITY

)

1

0.1

100

50

1k

G = 128

G = 16

G = 32

G = 64

500

Current Noise, V_S= 5V

Voltage Noise, V_S= 2.2V

0.01

20

10

200

100

0.001

0.0001

Voltage Noise, V_S= 5V

G = 8

G = 1

G = 4

G = 2

1

10

100

1k

10k

100k

10

100

1k

10k

100k

Frequency (Hz)

Figure 26.

Figure 27.

PGA112, PGA116 THD + NOISE vs FREQUENCY

(V_OUT= 4V_PP

PGA113, PGA117 THD + NOISE vs FREQUENCY

(V_OUT= 2V_PP

)

1

0.1

G = 200

G = 50

G = 100

G = 20

G = 128

G = 32 G = 16

G = 64

0.1

0.01

G = 8

0.001

0.0001

G = 4

G = 2

G = 1

G = 5

G = 1

G = 10

0.0001

10

100

1k

10k

100k

10

100

1k

10k

100k

Frequency (Hz)

Figure 28.

Figure 29.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AV_DD= DV_DD= 5V, R_L= 10kΩ connected to DV_DD/2, V_REF= GND, and C_L= 100pF, unless otherwise noted.

PGA113, PGA117 THD + NOISE vs FREQUENCY

(V_OUT= 4V_PP

QUIESCENT CURRENT

vs TEMPERATURE

)

1

0.1

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

G = 100

G = 200

G = 50

G = 20

Digital

0.01

Analog

G = 1

0.001

0.0001

V_S= 5.5V

V_S= 2.2V

G = 2

G = 5

G = 10

f_SCLK= 10MHz

75 100 125

10

100

1k

10k

100k

-50

-25

0

25

50

Frequency (Hz)

Temperature (°C)

Figure 30.

Figure 31.

TOTAL QUIESCENT CURRENT

vs SUPPLY VOLTAGE

SHUTDOWN QUIESCENT CURRENT

vs TEMPERATURE

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

1.2

1.0

0.8

0.6

0.4

0.2

0

SCLK = 5MHz

SCLK = 10MHz

Digital

SCLK = 2MHz

SCLK = 500kHz

Analog

-50

-25

0

25

50

75

100

125

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Supply Voltage (V)

Figure 32.

Temperature (°C)

Figure 33.

OUTPUT VOLTAGE

vs OUTPUT CURRENT

OUTPUT VOLTAGE

vs OUTPUT CURRENT

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V_S= 5.5V

G = 1

V_S= 2.2V

G = 1

+125°C

+25°C

+125°C

+25°C

-40°C

0

10

20

30

40

50

60

70

80

90 100

0

2

4

6

8

10 12 14 16 18 20 22 24

Output Current (mA)

Figure 34.

Figure 35.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AV_DD= DV_DD= 5V, R_L= 10kΩ connected to DV_DD/2, V_REF= GND, and C_L= 100pF, unless otherwise noted.

PGA112, PGA116 OUTPUT VOLTAGE SWING vs

FREQUENCY

PGA112, PGA116 OUTPUT VOLTAGE SWING vs

FREQUENCY

2.5

2.0

1.5

1.0

0.5

0

2.5

2.0

1.5

1.0

0.5

0

AV_DD= DV_DD= 2.2V

G = 4

G = 8

G = 16

G = 2

G = 64

G = 32

G = 1

G = 128

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

Frequency (Hz)

Figure 36.

Frequency (Hz)

Figure 37.

PGA112, PGA116 OUTPUT VOLTAGE SWING vs

FREQUENCY

PGA112, PGA116 OUTPUT VOLTAGE SWING vs

FREQUENCY

6

5

4

3

2

1

0

6

5

4

3

2

1

0

G = 8

G = 4

G = 16

G = 32

G = 1

G = 64

G = 2

AV_DD= DV_DD= 5.5V

100 1k

G = 128

1M

100

1k

10k

100k

1M

10M

10k

100k

10M

Frequency (Hz)

Figure 38.

Figure 39.

PGA113, PGA117 OUTPUT VOLTAGE SWING vs

FREQUENCY

PGA113, PGA117 OUTPUT VOLTAGE SWING vs

FREQUENCY

2.5

2.0

1.5

1.0

0.5

0

2.5

2.0

1.5

1.0

0.5

0

G = 20

G = 10

G = 2

G = 50

G = 100

G = 200

G = 1

G = 5

AV_DD= DV_DD= 2.2V

10k

1k

10k

100k

1M

10M

1k

100k

1M

10M

Frequency (Hz)

Figure 40.

Figure 41.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AV_DD= DV_DD= 5V, R_L= 10kΩ connected to DV_DD/2, V_REF= GND, and C_L= 100pF, unless otherwise noted.

PGA113, PGA117 OUTPUT VOLTAGE SWING vs

FREQUENCY

PGA113, PGA117 OUTPUT VOLTAGE SWING vs

FREQUENCY

6

5

4

3

2

1

0

6

5

4

3

2

1

0

G = 10

G = 5

G = 50

G = 20

G = 100

G = 1

G = 200

G = 2

1M

AV_DD= DV_DD= 5.5V

100

1k

AV_DD= DV_DD= 5.5V

10k

100k

10M

100

1k

10k

100k

1M

10M

Frequency (Hz)

Figure 42.

Figure 43.

SMALL-SIGNAL OVERSHOOT

vs LOAD CAPACITANCE

GAIN vs SETTLING TIME

50

40

30

20

10

0

12

10

8

C_L= 100pF//R_L= 10kW

V_OUT= 4V_PP

0.01%

G = 1

6

G > 2

0.1%

4

2

0

100

200

300

400

500

600

700

800

0

50

100

150

200

Gain

Load Capacitance (pF)

Figure 44.

Figure 45.

INPUT ON-CHANNEL CURRENT

vs TEMPERATURE

INPUT OFF-CHANNEL LEAKAGE CURRENT

vs TEMPERATURE

25

20

15

10

5

25

20

15

10

5

0.15

Measurement made with channel pin

connected to midsupply

Measurement made with channel pin

connected to midsupply

0.10

0.05

0

CH0

CH1 to

CH9

-0.05

-0.01

-0.15

CH0

CH1 to

CH9

0

-5

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (°C)

Figure 46.

Figure 47.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AV_DD= DV_DD= 5V, R_L= 10kΩ connected to DV_DD/2, V_REF= GND, and C_L= 100pF, unless otherwise noted.

POWER-SUPPLY REJECTION RATIO

vs FREQUENCY

CROSSTALK vs FREQUENCY

140

130

120

110

100

90

110

100

90

80

70

60

50

40

30

20

10

0

G = 1

G = 50

G = 200

G ³ 2

G = 2

80

70

G = 10

10k 100k 1M

60

10

100

1k

10k

100k

1M

10M

0.1

1

10

100

1k

10M

Frequency (Hz)

Figure 48.

Figure 49.

SMALL-SIGNAL PULSE RESPONSE

G = 20

G = 10

G = 1

100mV

0V

100mV

G = 50

Output

G = 100, 200

Output

Input

0V

V_IN/G

Input

0V

2.5ms/div

Figure 50.

Figure 51.

LARGE-SIGNAL PULSE RESPONSE

G = 10

G = 2

G = 1

G = 50

Output

G = 100, 200

Input

2.5ms/div

Figure 53.

Figure 52.

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TYPICAL CHARACTERISTICS (continued)

At T_A= +25°C, AV_DD= DV_DD= 5V, R_L= 10kΩ connected to DV_DD/2, V_REF= GND, and C_L= 100pF, unless otherwise noted.

POWER-UP/POWER-DOWN TIMING

OUTPUT OVERDRIVE PERFORMANCE

V_IN

5V

Output (1V/div)

V_OUT

0V

Supply (5V/div)

V_S= 5V

R_L= 10kW

0V

C_L= 100pF

25ms/div

1ms/div

Figure 54.

Figure 55.

OUTPUT VOLTAGE vs SHUTDOWN MODE

PGA116, PGA117 HARDWARE SHUTDOWN MODE

Active

In

Shutdown

Output

In

Shutdown

Output

Enable

CS

10ms/div

Figure 56.

Figure 57.

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SERIAL INTERFACE INFORMATION

SPI Mode 0, 0 (CPOL = 0, CPHA = 0)

CS

5

6

7

8

9

10

11

12

13

14

15

16

1

2

3

4

SCLK

DIN

DOUT

SPI Mode 1, 1 (CPOL = 1, CPHA = 1)

CS

SCLK

DIN

1

2

3

5

6

7

8

9

10

11

12

13

14

15

16

4

DOUT

Figure 58. SPI Mode 0,0 and Mode 1,1

Table 2. SPI Mode Setting Description

MODE

0, 0

CPOL

CPHA

0⁽¹⁾

1⁽²⁾

CPOL DESCRIPTION

Clock idles low

CPHA DESCRIPTION

0

1

Data are read on the rising edge of clock. Data change on the falling edge of clock.

1, 1

Clock idles high

(1) CPHA = 0 means sample on first clock edge (rising or falling) after a valid CS.

(2) CPHA = 1 means sample on second clock edge (rising or falling) after a valid CS.

SERIAL DIGITAL INTERFACE: SPI MODES

The PGA uses a standard serial peripheral interface

(SPI). Both SPI Mode 0,0 and Mode 1,1 are

supported, as shown in Figure 58 and described in

Table 2.

DOUT

If there are not even-numbered increments of 16

clocks (that is, 16, 32, 64, and so forth) between CS

going low (falling edge) and CS going high (rising

edge), the device takes no action. This condition

provides reliable serial communication. Furthermore,

this condition also provides a way to quickly reset the

SPI interface to a known starting condition for data

DIN

10mA

PGA116

PGA117

synchronization. Transmitted data are latched

internally on the rising edge of CS.

Figure 59. Digital I/O Structure—PGA116/PGA117

On the PGA116/PGA117, CS, DIN, and SCLK are

Schmitt-triggered CMOS logic inputs. DIN has a weak

internal

pull-down

to

support

daisy-chain

communications on the PGA116/PGA117. DOUT is a

CMOS logic output. When CS is high, the state of

DOUT is high-impedance. When CS is low, DOUT is

driven as illustrated in Figure 59.

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On the PGA112/PGA113, there are digital output and

digital input gates both internally connected to the

DIO pin. DIN is an input-only gate and DOUT is a

digital output that can give a 3-state output. The DIO

pin has a weak 10µA pull-down current source to

prevent the pin from floating in systems with a

high-impedance SPI DOUT line. When CS is high,

the state of the internal DOUT gate is

high-impedance. When CS is low, the state of DIO

depends on the previous valid SPI communication;

either DIO becomes an output to clock out data or it

remains an input to receive data. This structure is

shown in Figure 60.

used (see Table 4) to ensure that data are written or

read in the proper sequence. There is a special

daisy-chain NOP command (No OPeration) which,

when presented to the desired device in the

daisy-chain, causes no changes in that respective

device. Detailed timing diagrams for daisy-chain

operation are shown in Figure 65 through Figure 67.

CS

SCLK

DOUT

PGA116/PGA117

DIN

MSP430

CS

U1

U2

SCLK

DIN1

DOUT1

DIN2

DOUT2

DOUT

DIO

Figure 61. Daisy-Chain Read/Write Configuration

The PGA112/PGA113 can be used as the last device

in a daisy-chain as shown in Figure 62 if write-only

communication

is

acceptable,

because

the

PGA112/PGA113 have no separate DOUT pin to

connect back to the microcontroller DIN pin in order

to read back data in this configuration.

DIN

10mA

PGA112

PGA113

CS

SCLK

DOUT

Figure 60. Digital I/O Structure—PGA112/PGA113

PGA116/PGA117

PGA112/PGA113

DIN

MSP430

CS

U1

U2

SCLK

SERIAL DIGITAL INTERFACE: SPI

DAISY-CHAIN COMMUNICATIONS

DIN1

DOUT1

DIO

To reduce the number of I/O port pins used on a

microcontroller, the PGA116/PGA117 support SPI

daisy-chain communications with full read/write

capability. A two-device daisy-chain configuration is

shown in Figure 61, although any number of devices

can be daisy-chained. The SPI daisy-chain

communication uses a common SCLK and CS line

for all devices in the daisy chain, rather than each

device requiring a separate CS line. The daisy-chain

mode of communication routes data serially through

each device in the chain by using its respective DIN

and DOUT pins as shown. Special commands are

Figure 62. Daisy-Chain Write-Only Configuration

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The maximum SCLK frequency that can be used in

daisy-chain operation is directly related to SCLK

t_RFI

rise/fall times, DIN setup time, and DOUT

propagation delay. Any number of two or more

devices have the same limitations because it is the

timing considerations between adjacent devices that

limit the clock speed.

10ns

SCLK

Figure 63 analyzes the maximum SCLK frequency for

daisy-chain mode based on the circuit of Figure 61. A

clock rise and fall time of 10ns is assumed to allow

for extra bus capacitance that could occur as a result

of multiple devices in the daisy-chain.

t_DO

25ns

DOUT1

t_SU

10ns

DIN2

t_MIN= 55ns

SCLK_MAX= 9.09MHz

Figure 63. Daisy-Chain Maximum SCLK

Frequency

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SPI SERIAL INTERFACE

Figure 64. SPI Serial Interface Timing Diagrams

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Figure 65. SPI Daisy-Chain Write Timing Diagrams

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Figure 66. SPI Daisy-Chain Read Timing Diagram (Mode 0,0)

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Figure 67. SPI Daisy-Chain Read Timing Diagram (Mode 1,1)

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SPI COMMANDS

Table 3. SPI Commands (PGA112/PGA113)⁽¹⁾⁽²⁾

THREE-WIRE

D15

0

D14

1

D13

1

D12

0

D11

1

D10

0

D9

1

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

SPI COMMAND

0

READ

0

1

0

1

0

1

0

G3

0

G2

0

G1

0

G0

0

CH3

0

CH2

0

CH1

0

CH0 WRITE

0

1

NOP WRITE

SDN_DIS

WRITE

1

0

1

0

1

0

1

0

1

0

1

0

SDN_EN WRITE

(1) SDN = Shutdown mode. Enter Shutdown mode by issuing an SDN_EN command. Shutdown mode is cleared (returned to the last valid

write configuration) by a SDN_DIS command or by any valid Write command.

(2) POR (Power-on-Reset) value of internal Gain/Channel Select Register is all 0s; this value sets Gain = 1, and Channel = V_CAL/CH0.

Table 4. SPI Daisy-Chain Commands⁽¹⁾⁽²⁾

DAISY-CHAIN

D15

0

D14

0

D13

0

D12

1

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

COMMAND

NOP

1

0

1

0

SDN_DIS

SDN_EN

READ

1

0

1

0

1

0

1

0

1

0

1

0

1

0

G3

G2

G1

G0

CH3

CH2

CH1

CH0 WRITE

(1) SDN = Shutdown Mode. Shutdown Mode is entered by an SDN_EN command. Shutdown Mode is cleared (returned to the last valid

write configuration) by a SDN_DIS command or by any valid Write command.

(2) POR (Power-on-Reset) value of internal Gain/Channel Register is all 0s; this value sets Gain = 1, V_CAL/CH0 selected.

Table 5. Gain Selection Bits (PGA112/PGA113)

G3

0

G2

0

G1

0

G0

0

BINARY GAIN

SCOPE GAIN

1

2

1

2

0

1

0

1

0

4

5

0

1

8

10

20

50

100

200

0

1

0

16

32

64

128

0

1

0

1

0

1

0

1

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Table 6. Mux Channel Selection Bits

CH3

0

CH2

0

CH1

0

CH0

0

PGA112, PGA113

PGA116, PGA117

VCAL/CH0

CH1

VCAL/CH0

0

1

CH1

0

1

0

X⁽¹⁾

CH2

0

1

X

CH3

0

1

0

X

CH4

0

1

0

1

X

CH5

0

1

0

X

CH6

0

1

X

CH7

1

0

X

CH8

1

0

1

CH9

1

0

1

0

X

X⁽¹⁾

1

0

1

Factory Reserved

CAL1⁽²⁾

CAL2⁽³⁾

CAL3⁽⁴⁾

CAL4⁽⁵⁾

Factory Reserved

CAL1⁽²⁾

CAL2⁽³⁾

CAL3⁽⁴⁾

CAL4⁽⁵⁾

1

0

1

0

1

0

1

(1) X = channel is not used.

(2) CAL1: connects to GND.

(3) CAL2: connects to 0.9V_CAL

(4) CAL3: connects to 0.1V_CAL

.

(5) CAL4: connects to V_REF

.

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APPLICATION INFORMATION

PMOS transistors. The result of this transition

appears as a small input offset voltage transition that

is reflected to the output by the selected PGA gain.

This transition may be either increasing or

decreasing, and differs from part to part as described

in Figure 69 and Figure 70. These figures illustrate

possible differences in input offset voltage between

two different devices when used with AV_DD= +5V.

Because the exact transition region varies from

device to device, the Electrical Characteristics table

specifies an input offset voltage above and below this

input transition region.

FUNCTIONAL DESCRIPTION

The PGA112/PGA113 and PGA116/PGA117 are

single-ended input, single-supply, programmable gain

amplifiers (PGAs) with an input multiplexer.

Multiplexer channel selection and gain selection are

done through

a

standard SPI interface. The

PGA112/PGA113 have a two-channel input MUX and

the PGA116/PGA117 have a 10-channel input MUX.

The PGA112 and PGA116 provide binary gain

selections (1, 2, 4, 8, 16, 32, 64, 128) and the

PGA113 and PGA117 provide scope gain selections

(1, 2, 5, 10, 20, 50, 100, 200). All models use a

AV_DD

split-supply architecture with an analog supply, AV_DD

and digital supply, DV_DDThis split-supply

architecture allows for ease of interface to

analog-to-digital converters (ADCs) and

,

Reference

Current

a

.

microcontrollers in mixed-supply voltage systems,

such as where the analog supply is +5V and the

digital supply is +3V. Four internal calibration

channels are provided for system-level calibration.

The channels are tied to GND, 0.9V_CAL, 0.1V_CAL, and

V_IN+

V_IN-

V_REF

,

respectively. V_CAL

,

an external voltage

connected to V_CAL/CH0, acts as the system

calibration reference. If V_CALis the system ADC

reference, then gain and offset calibration on the

ADC are easily accomplished through the PGA using

only one MUX input. If calibration is not used, then

V_CAL/CH0 can be used as a standard MUX input. All

four versions provide a V_REFpin that can be tied to

ground or, for ease of scaling, to midsupply in

single-supply systems where midsupply is used as a

GND

Figure 68. PGA Rail-to-Rail Input Stage

virtual ground. The PGA112/PGA113 offer

a

80

software-controlled shutdown feature for low standby

power. The PGA116/PGA117 offer both hardware-

and software-controlled shutdown for low standby

power. The PGA112/PGA113 have a three-wire SPI

70

60

50

40

30

20

10

0

digital interface; the PGA116/PGA117 have

a

four-wire SPI digital interface. The PGA116/117 also

have daisy-chain capability.

OP AMP: INPUT STAGE

The PGA op amp is a rail-to-rail input and output

(RRIO) single-supply op amp. The input topology

uses two separate input stages in parallel to achieve

rail-to-rail input. As Figure 68 shows, there is a

PMOS transistor on each input for operation down to

ground; there is also an NMOS transistor on each

input in parallel for operation to the positive supply

rail. When the common-mode input voltage (that is,

the single-ended input, because this PGA is

configured internally for noninverting gain) crosses a

level that is typically about 1.5V below the positive

supply, there is a transition between the NMOS and

AV_DD= 5V

5 6

0

1

2

3

4

Input Voltage (V)

Figure 69. V_OSversus Input Voltage—Case 1

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50

CH0

PGA112

AV_DD= 5V

PGA113

MUX

CH1

40

30

V_OUT

R_I

V_IN0

V_IN1

V_REF

R_F

20

+

G = 1

10

V_S/2

-

0

-10

-20

-30

Figure 72. PGA112/PGA113 Configuration for

Positive and Negative Excursions Around

Midsupply Virtual Ground

0

1

2

3

4

5

6

V_OUT0= G ´ V_IN0- AV_DD/2 ´ (G - 1)

Input Voltage (V)

(2)

When: G = 1

Figure 70. V_OSversus Input Voltage—Case 2

OP AMP: GENERAL GAIN EQUATIONS

Then: V_OUT0= G × V_IN0

V_OUT1= G ´ (V_IN1+ AV_DD/2) - AV_DD/2 ´ (G - 1)

Figure 71 shows the basic configuration for using the

PGA as a gain block. V_OUT/V_INis the selected

noninverting gain, depending on the model selected,

for either binary or scope gains.

V_OUT1= G ´ V_IN1+ AV_DD/2, where: -AV_DD/2 < G ´ V_IN1< +AV_DD/2

(3)

Where:

G = 1, 2, 4, 8, 16, 32, 64, and 128 (binary gains)

G = 1, 2, 5, 10, 20, 50, 100, and 200 (scope

gains)

CH1

V_OUT

R_I

Table 7 details the internal typical values for the op

amp internal feedback resistor (R_F) and op amp

internal input resistor (R_I) for both binary and scope

gains.

V_IN

V_REF

R_F

G = 1

Table 7. Typical R_Fand R_Iversus Gain

Binary

Gain

(V/V)

Scope

Gain

(V/V)

Figure 71. PGA Used as a Gain Block

R_F(Ω)

0

R_I(Ω)

3.25k

R_F(Ω)

0

R_I(Ω)

3.25k

1

2

1

2

V_OUT= G ´ V_IN

(1)

3.25k

Where:

4

9.75k

5

13k

G = 1, 2, 4, 8, 16, 32, 64, and 128 (binary gains)

G = 1, 2, 5, 10, 20, 50, 100, and 200 (scope

gains)

8

22.75k

48.75k

100.75k

204.75k

412.75k

10

20

50

100

200

29.25k

61.75k

159.25k

321.75k

646.75k

16

32

64

128

Figure 72 shows the PGA configuration and gain

equations for V_REF= AV_DD/2. V_OUT0is V_OUTwhen

CH0 is selected and V_OUT1is V_OUTwhen CH1 is

selected. Notice the V_REFpin has no effect for G = 1

because the internal feedback resistor, R_F, is shorted

out. This configuration allows for positive and

negative voltage excursions around a midsupply

virtual ground.

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OP AMP: FREQUENCY RESPONSE VERSUS

GAIN

ANALOG MUX

The analog input MUX provides two input channels

for the PGA112/PGA113 and 10 input channels for

the PGA116/PGA117. The MUX switches are

designed to be break-before-make and thereby

eliminate any concerns about shorting the two input

signal sources together.

Table 8 documents how small-signal bandwidth and

slew rate change correspond to changes in PGA

gain.

Full power bandwidth (that is, the highest frequency

that a sine wave can pass through the PGA for a

given gain) is related to slew rate by Equation 4:

Four internal MUX CAL channels are included in the

analog MUX for ease of system calibration. These

CAL channels allow ADC gain and offset errors to be

calibrated out. This calibration does not remove the

offset and gain errors of the PGA for gains greater

than 1, but most systems should see a significant

increase in the ADC accuracy. In addition, these CAL

channels can be used by the ADC to read the

minimum and maximum possible voltages from the

PGA. With these minimum and maximum levels

known, the system architecture can be designed to

indicate an out-of-range condition on the measured

analog input signals if these levels are ever

measured.

SR (V/ms) = 2pf ´ V_OP(1 ´ 10^-6)

(4)

Where:

SR = Slew rate in V/µs

f = Frequency in Hz

V_OP= Output peak voltage in volts

Example:

For G = 8, then SR = 10.6V/µs (slew rate rise is

minimum slew rate).

For a 5V system, choose 0.1V < V_OUT< 4.9V or

V_OUTPP= 4.8V or V_OUTP= 2.4V.

SR (V/µs) = 2πf × V_OP(1 × 10^–6).

To use the CAL channels, V_CAL/CH0 must be

permanently connected to the system ADC reference.

There is a typical 100kΩ load from V_CAL/CH0 to

ground. Table 9 illustrates how to use the CAL

channels with V_REF= ground. Table 10 describes how

to use the CAL channels with V_REF= AV_DD/2. The

V_REFpin must be connected to a source that is

low-impedance for both dc and ac in order to

maintain gain and nonlinearity accuracy. Worst-case

current demand on the V_REFpin occurs when G = 1

because there is a 3.25kΩ resistor between V_OUTand

V_REF. For a 5V system with AV_DD/2 = 2.5V, the V_REF

pin buffer must source and sink 2.5V/3.25kΩ = 0.7mA

minimum for a V_OUTthat can swing from ground to

+5V.

10.6 = 2πf (2.4) (1 × 10^–6) → f = 702.9kHz

This example shows that a G = 8 configuration

can produce a 4.8V_PPsine wave with frequency

up to 702.9kHz. This computation only shows the

theoretical upper limit of frequency for this

example, but does not indicate the distortion of

the sine wave. The acceptable distortion depends

on the specific application. As

a

general

guideline, maintain two to three times the

calculated slew rate to minimize distortion on the

sine wave. For this example, the application

should only use G = 8, 4.8V_PP, up to a frequency

range of 234kHz to 351kHz, depending upon the

acceptable distortion. For a given gain and slew

rate requirement, check for adequate small-signal

bandwidth (typical –3dB frequency) in order to

assure that the frequency of the signal can be

passed without attenuation.

Table 8. Frequency Response versus Gain (C_L= 100pF, R_L= 10kΩ)

0.1%

0.01%

0.1%

0.01%

TYPICAL

–3dB

FREQUENCY

(MHz)

SLEW

RATE-

FALL

SLEW

RATE-

RISE

SETTLING SETTLING

TYPICAL

–3dB

FREQUENCY

(MHz)

SLEW

RATE-

FALL

SLEW

RATE-

RISE

SETTLING SETTLING

TIME:

4V_PP

(µs)

TIME:

4V_PP

(µs)

SCOPE

GAIN

(V/V)

TIME:

4V_PP

(µs)

TIME:

4V_PP

(µs)

BINARY

GAIN (V/V)

(V/µs)

1

2

10

3.8

2

8

3

2

2.55

2.6

3

1

2

10

3.8

8

9

3

2

2.55

2.6

2.8

3.8

7

9

6.4

10.6

9.1

7.1

3.5

2

4

12.8

4

10.6

12.8

13.3

3.5

2

5

1.8

12.8

9.1

4

2

8

1.8

1.6

1.8

0.6

0.35

2

10

20

50

100

200

1.8

2.2

2.3

2.4

4.4

6.9

16

32

64

128

2.3

3

1.3

0.9

6

0.38

0.23

2.5

4.8

8

2.3

10

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+3V

C_BYPASS

0.1mF

AV_DD

DV_DD

ADC Ref

2.5V

REF3225

PGA112

PGA113

V_CAL/CH0

CH1

MUX

V_OUT

Output

Stage

ADC

CAL1

10kW

80kW

R_F

G = 1

0.9V_CAL

0.1V_CAL

MSP430

CAL2

CAL3

CAL4

Microcontroller

R_I

V_REF

SCLK

DIO

CS

SPI

Interface

CAL2/3

10kW

GND

V_REF

Figure 73. Using CAL Channels with V_REF= Ground

Table 9. Using the MUX CAL Channels with V_REF= GND

(AV_DD= 3V, DV_DD= 3V, ADC Ref = 2.5V, and V_REF= GND)

MUX

SELECT

GAIN

SELECT

OP AMP

(+In)

OP AMP

(V_OUT

FUNCTION

MUX INPUT

)

DESCRIPTION

Minimum signal level that the

MUX, op amp, and ADC can

read. Op amp V_OUTis limited

by negative saturation.

Minimum Signal

Gain Calibration

CAL1

CAL2

1

GND

50mV

2.25V

90% ADC Ref for system

full-scale or gain calibration

of the ADC.

0.9 ×

(V_CAL/CH0)

2.25V

Maximum signal level that

the MUX, op amp, and ADC

can read. Op amp V_OUTis

limited by positive saturation.

System is limited by ADC

max input of 2.5V (ADC Ref

= 2.5V).

0.9 ×

(V_CAL/CH0)

Maximum Signal

CAL2

2

2.25V

2.95V

0.1 ×

(V_CAL/CH0)

10% ADC Ref for system

offset calibration of the ADC.

Offset Calibration

Minimum Signal

CAL3

CAL4

1

0.25V

GND

0.25V

50mV

Minimum signal level that the

MUX, op amp, and ADC can

read. Op amp V_OUTis limited

by negative saturation.

V_REF

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+3V

C_BYPASS

0.1mF

AV_DD

DV_DD

PGA112

PGA113

ADC Ref

V_CAL/CH0

CH1

MUX

V_OUT

Output

Stage

ADC

CAL1

10kW

80kW

R_F

G = 1

0.9V_CAL

0.1V_CAL

MSP430

CAL2

CAL3

CAL4

Microcontroller

R_I

V_REF

SCLK

DIO

CS

SPI

Interface

CAL2/3

10kW

GND

V_REF

R_F

10kW

C_F

2.7nF

+3V

C_BYPASS

+3V

0.1mF

R_X

(1.5V)

100kW

OPA364

C_L2

0.1mF

R_Y

0.1mF

100kW

Figure 74. Using CAL Channels with V_REF= AV_DD/2

Table 10. Using the MUX CAL Channels with V_REF= AV_DD/2

(AV_DD= 3V, DV_DD= 3V, ADC Ref = 3V, and V_REF= 1.5V)

MUX

SELECT

GAIN

SELECT

OP AMP

(+In)

OP AMP

(V_OUT

FUNCTION

MUX INPUT

)

DESCRIPTION

Minimum signal level that the MUX,

op amp, and ADC can read. Op amp

V_OUTis limited by negative saturation.

Minimum Signal

CAL1

CAL2

1

GND

2.7V

50mV

2.7V

0.9 ×

(V_CAL/CH0)

90% ADC Ref for system full-scale or

gain calibration of the ADC.

Gain Calibration

Maximum signal level that the MUX,

op amp, and ADC can read. Op amp

V_OUTis limited by positive saturation.

0.9 ×

(V_CAL/CH0)

Maximum Signal

4 or 5

2.25V

2.95V

0.1 ×

(V_CAL/CH0)

10% ADC Ref for system offset

calibration of the ADC.

Offset Calibration

V_REFCheck

CAL3

CAL4

1

0.3V

1.5V

0.3V

1.5V

V_REF

Midsupply voltage used as V_REF.

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SYSTEM CALIBRATION USING THE PGA

In practice, the zero input (0V) or full-scale input

(V_{REF_ADC}– 1LSB) of ADCs cannot always be

measured because of internal offset error and gain

error. However, if measurements are made very close

to the full-scale input and the zero input, both zero

and full-scale can be calibrated very accurately with

the assumption of linearity from the calibration points

to the desired end points of the ADC ideal transfer

function. For the zero calibration, choose

10%V_{REF_ADC}; this value should be above the internal

offset error and sufficiently out of the noise floor

range of the ADC. For the gain calibration, choose

90%V_{REF_ADC}; this value should be less than the

internal gain error and sufficiently below the tolerance

of V_REF. These key points can be summarized in this

way:

Analog-to-digital converters (ADCs) contain two major

errors that can be easily removed by calibration at a

system level. These errors are gain error and offset

error, as shown in Figure 75. Figure 75 shows a

typical transfer function for a 12-bit ADC. The analog

input is on the x-axis with a range from 0V to

(V_{REF_ADC}– 1LSB), where V_{REF_ADC}is the ADC

reference voltage. The y-axis is the hexadecimal

equivalent of the digital codes that result from ADC

conversions. The dotted red line represents an ideal

transfer function with 0000h representing 0V analog

input and 0FFFh representing an analog input of

(V_{REF_ADC}– 1LSB). The solid blue line illustrates the

offset error. Although the solid blue line includes both

offset error and gain error, at an analog input of 0V

the offset error voltage, V_{Z_ACTUAL}, can be measured.

The dashed black line represents the transfer function

with gain error. The dashed black line is equivalent to

the solid blue line without the offset error, and can be

measured and computed using V_{Z_ACTUAL}and

V_{Z_IDEAL}. The difference between the dashed black

line and the dotted red line is the gain error. Gain and

offset error can be computed by taking zero input and

full-scale input readings. Using these error

calculations, compute a calibrated ADC reading to

remove the ADC gain and offset error.

For zero calibration:

•

The ADC cannot read the ideal zero because of

offset error

Must be far enough above ground to be above

noise floor and ADC offset error

Therefore, choose 10%V_{REF_ADC}for zero

calibration

For gain calibration:

•

The ADC cannot read the ideal full-scale because

of gain error

Must be far enough below full-scale to be below

the V_REFtolerance and ADC gain error

Therefore, choose 90%V_{REF_ADC}for gain

calibration

V_{FS_ACTUAL}

Gain Error

0FFFh

V_{FS_IDEAL}

Transfer Function

with Offset Error + Gain Error

Transfer Function

with Gain Error Only

V_{Z_ACTUAL}

0000h

Offset Error

V_{Z_IDEAL}

Analog Input

0V

V_{REF_ADC}- 1LSB

Figure 75. ADC Offset and Gain Error

34

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V_REF90 = 0.9(V_{REF_ADC}

)

The 12-bit ADC example in Figure 76 illustrates the

technique for calibrating an ADC using

(5)

a

V_REF10 = 0.1(V_{REF_ADC}

)

(6)

(7)

(8)

10%V_{REF_ADC}and 90%V_{REF_ADC}reading where

V_{REF_ADC}is the ADC reference voltage. Note that the

10%V_REFreading also contains a gain error because

it is not a V_IN= 0 calibration point. First, use the

90%V_REFand 10%V_REFpoints to compute the

measured gain error. The measured gain error is then

used to remove the gain error from the 10%V_REF

reading, giving a measured 10%V_REFnumber. The

measured 10%V_REFnumber is used to compute the

measured offset error.

V_MEAS90 = ADC_MEASUREMENTat V_REF90

V_MEAS10 = ADC_MEASUREMENTat V_REF10

2. Compute the ADC measured gain. The slope of

the curve connecting the measured 10%V_REFand

measured 90%V_REFpoint is computed and

compared to the slope between the ideal

10%V_REFand ideal 90%V_REF. This result is the

measured gain.

V_MEAS90 - V_MEAS10

G_MEAS

=

V_REF= +5V

V_REF90 - V_REF10

(9)

Offset Error = +4LSB

Gain Error = +6LSB

0FFFh (4.99878V)

(4.5114751443V)

3. Compute the ADC measured offset. The

measured offset is computed by taking the

difference between the measured 10%V_REFand

the (ideal 10%V_REF) × (measured gain).

Transfer Function

with Offset Error + Gain Error

O_MEAS= V_MEAS10 - (V_REF10 ´ G_MEAS

)

(10)

4. Compute the calibrated ADC readings.

V_{AD_MEAS}= Any V_INADC_MEASUREMENT

(11)

V

_{AD_MEAS}- O_MEAS

V_{ADC_CAL}

=

G_MEAS

(12)

(0.5056191443V)

0000h (0V)

Any ADC reading can therefore be calibrated by

removing the gain error and offset error. The

measured offset is subtracted from the ADC reading

and then divided by the measured gain to give a

corrected reading. If this calibration is performed on a

timed basis, relative to the specific application, gain

and offset error over temperature are also removed

from the ADC reading by calibration.

0V

0.5V

(0.1 ´ V_{REF_ADC}

4.5V

(0.9 ´ V_{REF_ADC}

4.99878V

(V_{REF_ADC}- 1LSB)

V_IN

)

Figure 76. 12-Bit Example of ADC Calibration for

Gain and Offset Error

The gain error and offset error in ADC readings can

be calibrated by

using 10%V_{REF_ADC}and

For example; given:

90%V_{REF_ADC}calibration points. Because the

calibration is ratiometric to V_{REF_ADC}, the exact value

of V_{REF_ADC}does not need to be known in the end

application.

•

12-Bit ADC

ADC Gain Error = +6LSB

ADC Offset Error = +4LSB

ADC Reference (V_{REF_ADC}) = +5V

Temperature = +25°C

Follow these steps to compute a calibrated ADC

reading:

1. Take the ADC reading at V_IN= 90% × V_REFand

V_IN= 10% × V_REF. The ADC readings for

10%V_REFand 90%V_REFare taken.

Table 11 shows the resulting system accuracy.

Table 11. Bits of System Accuracy⁽¹⁾(to 0.5LSB)

ADC ACCURACY WITHOUT

ADC ACCURACY WITH PGA112

CALIBRATION

V_IN

CALIBRATION

10%V_{REF_ADC}

90%V_{REF_ADC}

8.80 Bits

12.80 Bits

11.06 Bits

7.77 Bits

(1) Difference in maximum input offset voltage for V_IN= 10%V_{REF_ADC}and V_IN= 90%V_{REF_ADC}is the reason for different accuracies.

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APPLICATIONS: GENERAL-PURPOSE INPUT

SCALING

Table 12 summarizes the scaling resistor values for

R_A, R_X, and R_Bfor different ADC Ref voltages.

V_{REF_ADC}is the reference voltage used for the ADC

connected to the PGA112/PGA113 output. It is

assumed the ADC input range is 0V to V_{REF_ADC}. The

Bipolar Input to Single-Supply Scaling section gives

the algorithm to compute resistor values for

references not listed in Table 12. As a general

guideline, R_Bshould be chosen such that the input

on-channel current multiplied by R_Bis less than or

equal to the input offset voltage. This value ensures

that the scaling network contributes no more error

than the input offset voltage. Individual applications

may require other design trade-offs.

Figure 77 is an example application that

demonstrates the flexibility of the PGA for

general-purpose input scaling. V_IN0is a ±100mV input

that is ac-coupled into CH0. The PGA112/PGA113 is

powered from

a +5V supply voltage, V_S, and

configured with the V_REFpin connected to V_S/2

(+2.5V). V_CH0is the ±100mV input, level-shifted and

centered on V_S/2 (+2.5V). A gain of 20 is applied to

CH0, and because of the PGA113 configuration, the

output voltage at V_OUTis ±2V centered on V_S/2

(+2.5V).

CH1 is set to G = 1; through a resistive divider and

scalar network, we can read ±5V or 0V. This setting

provides bipolar to single-ended input scaling.

V_CH0

V_IN0

+2.6V

+2.5V

+2.4V

+100mV

0

C_A

-100mV

V_OUT0

V_IN0

V_S

PGA112

PGA113

+4.5V

+2.5V

+0.5V

200mV_PP

(+5V)

CH0

CH1

AV_DD

R_A

MUX

DV_DD

V_OUT

R_I

G = 20

V_REF

V_OUT1

R_F

+4.9625V

+37.5mV

V_{REF_ADC}

+

V_S/2

(+2.5V)

-

R_X

G = 1

R_A

R_B

V_IN1

Figure 77. General-Purpose Input Scaling

36

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Table 12. Bipolar to Single-Ended Input Scaling⁽¹⁾⁽²⁾

V_{REF_ADC}(V)

V_IN1(V)

–5

0

CH1 INPUT

0.047613

1.247613

2.447613

0.050317

1.250317

2.450317

0.058003

1.498003

2.938003

0.059303

1.499303

2.939303

0.082224

2.048304

4.014384

0.086018

2.052098

4.018178

0.093506

2.493506

4.893506

0.095227

2.495227

4.895227

R_A(kΩ)

R_X(Ω)

R_B(kΩ)

2.5

9.2

4.81k

10

5

2.5

–10

0

3.16

13.5

4.02

37

2.4k

5.76k

2.87k

7.87k

3.92k

965

10

–5

0

3

5

–10

0

10

–5

0

4.096

5

–10

0

6.49

24

10

–5

0

5

–10

0

9.2

4.81k

10

(1) Scaling is based on 0.02(V_{REF_ADC}) to 0.98(V_{REF_ADC}), using standard 0.1% resistor values.

(2) Assumes symmetrical V_INand symmetrical scaling for CH1 input minimum and maximum.

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2 ´ R_B´ g

1 - g

Bipolar Input to Single-Supply Scaling

R_A=

Note that this process assumes a symmetrical V_IN1

and that symmetrical scaling is used for CH1 input

minimum and maximum values. The following steps

give the algorithm to compute resistor values for

references not listed in Table 12.

2 ´ 10kW ´ 0.315789474

1 - 0.315789474

9.23077kW =

d. R_Xcan now be computed from the starting value

of R_Band the computed value for R_A.

R_B´ R_A

Step 1: Choose the following:

a. V_{REF_ADC}= 2.5V (ADC reference voltage)

b. | V_IN1| = 5

R_X=

R_B+ R_A

(magnitude of V_IN, assuming scaling is for ±V_IN1

)

10kW ´ 9.23077kW

4.81kW =

10kW + 9.23077kW

c. Choose R_Bas a standard resistor value. The

input on-channel current multiplied by R_Bshould

be less than the input offset voltage, such that R_B

is not a major source of inaccuracy.

+

V_{REF_ADC}

R_X

(2.5V)

R_B= 10kΩ (select as a starting value for

resistors)

4.81kW

R_B

10kW

CH1 Input

(2.447817V,

0.0474093V)

d. For the most negative V_IN1

,

choose the

percentage (in decimal format) of V_{REF_ADC}

desired at the ADC input.

V_IN1

R_A

(+5V, -5V)

9.2kW

k_VO–= 0.02

(CH1 input = k_VO–× V_{REF_ADC}when V_IN1= –V_IN1

)

e. For the most positive V_IN1, choose the percentage

(in decimal format) of V_{REF_ADC}desired at the

ADC input. Since this scaling is based on

symmetry, k_VO+must be the same percentage

away from V_{REF_ADC}at the upper limit as at the

lower limit where k_VO–is computed.

Figure 78. Bipolar to Single-Ended Input

Algorithm

APPLICATIONS: HIGH GAIN/WIDE

BANDWIDTH CONSIDERATIONS

As a result of the combination of wide bandwidth and

high gain capability of the PGA112/PGA113 and

PGA116/PGA117, there are several printed circuit

board (PCB) design and system recommendations to

consider for optimum application performance.

k_VO+= 1 – k_VO–

k_VO+= 1 – 0.02 = 0.98

(CH1 input = k_VO+× V_{REF_ADC}when V_IN1= +V_IN1

)

1. Power-supply

power-supply pin separately. Use a ceramic

capacitor connected directly from the

bypass.

Bypass

each

Step 2: Compute the following:

a. To simplify analysis, create one constant called

k_VO

k_VO= k_VO+- k_VO-

.

power-supply pin to the ground pin of the IC on

the same PCB plane. Vias can then be used to

connect to ground and voltage planes. This

configuration keeps parasitic inductive paths out

of the local bypass for the PGA. Good analog

design practice dictates the use of a large value

tantalum bypass capacitor on the PCB for each

respective voltage.

0.96 = 0.98 - 0.02

b. A constant, g, is created to simplify resistor value

computations.

k_VO´ V_{REF_ADC}

g =

2 ´ |V_IN1| - k_VO´ V_{REF_ADC}

0.96 ´ 2.5

0.315789474 =

2 ´ 5 - 0.96 ´ 2.5

c. R_Ais now selected from the starting value of R_B

and the g constant.

38

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2. Signal trace routing. Keep V_OUTand other low

impedance traces away from MUX channel inputs

that are high impedance. Poor signal routing can

cause positive feedback, unwanted oscillations,

or excessive overshoot and ringing on

step-changing signals. If the input signals are

particularly noisy, separate MUX input channels

with guard traces on either side of the signal

traces. Connect the guard traces to ground near

the PGA and at the signal entry point into the

PCB. On multilayer PCBs, ensure that there are

no parallel traces near MUX input traces on

adjacent layers; capacitive coupling from other

layers can be a problem. Use ground planes to

isolate MUX input signal traces from signal traces

on other layers.

Bypass capacitors greater than 100pF are

recommended. Lower impedances and a bypass

capacitor placed directly at the input MUX

channels keep crosstalk between channels to a

minimum as a result of parasitic capacitive

coupling from adjacent PCB traces and pin-to-pin

capacitance.

APPLICATIONS: DRIVING/INTERFACING TO

ADCS

CDAC SAR ADCs contain an input sampling

capacitor, C_SH, to sample the input signal during a

sample period as shown in Figure 79. After the

sample period, C_SHis removed from the input signal.

Subsequent comparisons of the charge stored on C_SH

are performed during the ADC conversion process.

To achieve optimal op amp stability, input signal

settling, and the demands for charge from the input

signal conditioning circuitry, most ADC applications

are optimized by the use of a resistor (R_FILT) and

capacitor (C_FILT) filter placed between the op amp

output and ADC input. For the PGA112/PGA113, or

Additionally, group and route the digital signals

into the PGA as far away as possible from the

analog MUX input signals. Most digital signals

are fast rise/fall time signals with low-impedance

drive capability that can easily couple into the

high-impedance inputs of the input MUX

channels. This coupling can create unwanted

the PGA116/PGA117, setting C_FILT= 1nF and R_FILT

=

noise that gains up to V_OUT

.

100Ω yields optimum system performance for

sampling converters operating at speeds up to

500kHz, depending upon the application settling time

and accuracy requirements.

3. Input MUX channels and source impedance.

Input MUX channels are high-impedance; when

combined with high gain, the channels can pick

up unwanted noise. Keep the input signal

sources low-impedance (< 10kΩ). Also, consider

bypassing input MUX channels with a ceramic

bypass capacitor directly at the MUX input pin.

+3V

+5V

C_BYPASS

0.1mF

C_BYPASS

0.1mF

AV_DD

1

DV_DD

10

PGA112

PGA113

R_FILT

3

2

(MSOP-10)

MUX

V_CAL/CH0

CH1

100W

5

V_OUT

Output

Stage

C_SH

40pF

C_FILT

CAL1

10kW

80kW

(1nF)

R_F

CDAC SAR

ADC

G = 1

0.9V_CAL

0.1V_CAL

CAL2

CAL3

CAL4

V_REF

R_I

7

8

9

SCLK

DIO

CS

SPI

Interface

CAL2/3

10kW

6

4

12-Bit Settling ® 500kHz

16-Bit Settling ® 300kHz

GND

V_REF

Figure 79. Driving/Interfacing to ADCs

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POWER SUPPLIES

At initial power-on, the state of the PGA is G = 1 and

Channel 0 active. CAUTION: For most applications,

set AV_DD≥ DV_DDto prevent V_OUTfrom driving

current into AV_DDand raising the voltage level of

Figure 80 shows a typical mixed-supply voltage

system where the analog supply, AV_DD, is +5V and

the digital supply voltage, DV_DD, is +3V. The analog

output stage of the PGA and the SPI interface digital

AV_DD

.

circuitry are both powered from DV_DD

.

When

SHUTDOWN AND POWER-ON-RESET (POR)

considering the power required for DV_DD, use the

Electrical Characteristics table and add any load

current anticipated on V_OUT; this load current must be

provided by DV_DD. This split-supply architecture

The PGA112/PGA113 have a software shutdown

mode, and the PGA116/PGA117 offer both

hardware and software shutdown mode. When the

PGA is shut down, it goes into a low-power standby

mode. The Electrical Characteristics table details the

current draw in shutdown mode with and without the

SPI interface being clocked. In shutdown mode, R_F

a

ensures

compatible

logic

levels

with

the

microcontroller. It also ensures that the PGA output

cannot run the input for the onboard ADC into an

overvoltage condition; this condition could cause

device latch-up and system lock-up, and require

power-supply sequencing. Each supply pin should be

individually bypassed with a 0.1µF ceramic capacitor

directly at the device to ground. If there is only one

power supply in the system, AV_DDand DV_DDcan both

be connected to the same supply; however, it is

recommended to use individual bypass capacitors

directly at each respective supply pin to a single point

ground. V_OUTis diode-clamped to AV_DD(as shown in

Figure 80); therefore, set DV_DDless than or equal to

AV_DD+ 0.3V. DV_DDand AV_DDmust be within the

operating voltage range of +2.2V to +5.5V.

and R_Iremain connected between V_OUTand V_REF

.

When DV_DDis less than 1.6V, the digital interface is

disabled and the channel and gain selections are

held to the respective POR states of Gain = 1 and

Channel = V_CAL/CH0. When DV_DDis above 1.8V, the

digital interface is enabled and the POR gain and

channel states remain unchanged until a valid SPI

communication is received.

+3V

+5V

AV_DD

DV_DD

1

10

PGA112

PGA113

MSP430

Microcontroller

(MSOP-10)

3

2

MUX

V_CAL/CH0

CH1

5

V_OUT

Output

Stage

ADC

CAL1

10kW

80kW

R_F

G = 1

0.9V_CAL

0.1V_CAL

CAL2

CAL3

CAL4

V_REF

R_I

7

8

9

SCLK

DIO

CS

SPI

Interface

CAL2/3

10kW

6

4

GND

V_REF

Figure 80. Split Power-Supply Architecture: AV_DD≠ DV_DD

40

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PACKAGE OPTION ADDENDUM

www.ti.com

13-Nov-2008

PACKAGING INFORMATION

Orderable Device

PGA112AIDGSR

PGA112AIDGSRG4

PGA112AIDGST

PGA112AIDGSTG4

PGA113AIDGSR

PGA113AIDGSRG4

PGA113AIDGST

PGA113AIDGSTG4

PGA116AIPW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

MSOP

DGS

10

20

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

MSOP

TSSOP

DGS

PW

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PGA116AIPWG4

PGA116AIPWR

PW

70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PW

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PGA116AIPWRG4

PGA117AIPW

PW

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PW

70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PGA117AIPWG4

PGA117AIPWR

PW

70 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PW

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PGA117AIPWRG4

PW

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

13-Nov-2008

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jan-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

PGA112AIDGSR

PGA112AIDGST

PGA113AIDGSR

PGA113AIDGST

PGA116AIPWR

PGA117AIPWR

MSOP

TSSOP

DGS

PW

10

20

2500

250

330.0

180.0

330.0

180.0

330.0

12.4

16.4

5.3

3.3

7.1

1.3

1.6

8.0

12.0

16.0

Q1

2500

250

5.3

2000

6.95

PW

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jan-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

PGA112AIDGSR

PGA112AIDGST

PGA113AIDGSR

PGA113AIDGST

PGA116AIPWR

PGA117AIPWR

MSOP

TSSOP

DGS

PW

10

20

2500

250

370.0

195.0

370.0

195.0

346.0

355.0

200.0

355.0

200.0

346.0

55.0

45.0

55.0

45.0

33.0

2500

250

2000

PW

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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Applications

Audio

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DLP® Products

DSP

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Interface

www.ti.com/automotive

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www.ti.com/security

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www.ti.com/video

dsp.ti.com

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interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

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Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

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www.ti.com/wireless

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型号：	PGA112AIDGSTG4
厂家：	TEXAS INSTRUMENTS
描述：	Zerø-Drift PROGRAMMABLE GAIN AMPLIFIER with MUX 零漂移可编程增益放大器与MUX 放大器
文件：	总47页 (文件大小：1542K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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