PCM1870RHFR [TI]
采用麦克风偏置、ALC、音效和陷波滤波器的 90dB SNR 低功耗立体声音频 ADC | RHF | 24 | -40 to 85;
| 型号： | PCM1870RHFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用麦克风偏置、ALC、音效和陷波滤波器的 90dB SNR 低功耗立体声音频 ADC | RHF | 24 | -40 to 85 转换器 |
| 文件： | 总53页 (文件大小：1004K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCM1870
SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
16-Bit Low-Power Stereo Audio ADC With Microphone Bias and Microphone Amplifier
1
FEATURES
•
Package:
•
Analog Front End:
–
–
24-QFN (4 mm × 5 mm)
24-DSBGA (2.49 mm × 3.49 mm)
–
–
–
–
Stereo Single End Input With MUX
Mono Differential Input
•
Operation Temperature Range: –40°C to 85°C
Stereo Programmable Gain Amplifier
Microphone Boost Amplifier and Bias
APPLICATIONS
•
•
•
Portable Audio Player, Cellular Phone
Video Camcorder, Movie Digital Still Camera
PMP/DMB, Voice Recorder
•
•
Analog Performances Dynamic Range: 90 dB
Power-Supply Voltage
–
–
–
1.71 V to 3.6 V for Digital I/O Section
1.71 V to 3.6 V for Digital Core Section
2.4 V to 3.6 V for Analog Section
DESCRIPTION
The PCM1870 is a low-power stereo ADC designed
for portable digital audio applications, with line-input
•
Low Power Dissipation:
amplifier,
boost
amplifier,
microphone
bias,
–
–
–
13 mW in Record, 1.8/2.4 V, 48 kHz, Stereo
5.3 mW in Record, 1.8/2.4 V, 8 kHz, Mono
3.3 μW in All Power Down
programmable gain control, sound effects, and auto
level control (ALC). It is available in 24-QFN (4-mm ×
5-mm) and 24-DSBGA (2.49-mm
×
3.49-mm)
packages to save footprint. The PCM1870 accepts
right-justified, left-justified, I2S, and DSP formats,
providing easy interfacing to audio DSP and encoder
chips. Sampling rates up to 50 kHz are supported.
The user-programmable functions are accessible
through a 2- or 3-wire serial control port.
•
•
•
•
Sampling Frequency: 5 kHz to 50 kHz
Auto Level Control for Recording
Operation by Single Clock Input Without PLL
System Clock: Common Audio Clock
(256 fS/384 fS), 12/24, 13/26, 13.5/27, 19.2/38.4,
19.68/39.36 MHz
2 (I2C) or 3 (SPI) Wire Serial Control
•
•
Programmable Function by Register Control:
–
–
–
–
–
–
–
Digital Soft Mute
Power Up/Down Control for Each Module
30-dB to –12-dB Gain for Analog Inputs
0/12/20-dB Boost for Microphone Input
Parameter Settings for ALC
Three-Band Tone Control and 3D Sound
High-Pass Filter and Two-Stage Notch Filter
•
Pop Noise Reduction Circuit
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
PCM1870
www.ti.com
SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
PCM1870
–0.3 to 4
±0.1
UNIT
V
VDD, VIO, VCC
Supply voltage
Ground voltage differences: DGND, AGND, PGND
Input voltage
V
–0.3 to 4
±10
V
Input current (any pins except supplies)
Ambient temperature under bias
Storage temperature
mA
°C
–40 to 110
–55 to 150
150
°C
Junction temperature
°C
Lead temperature (soldering)
Package temperature (reflow, peak)
260 / 5
260
°C / s
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicted under recommended operating
conditions is not impled. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabiltiy.
RECOMMENDED OPERATING CONDITIONS
MIN
2.4
NOM
3.3
MAX
3.6
UNIT
V
VCC
Analog supply voltage
Digital supply voltage
Digital input logic family
VDD, VIO
1.71
3.3
3.6
V
CMOS
SCKI system clock
3.072
8
18.432
48
MHz
kHz
pF
Digital input clock frequency
LRCK sampling clock
Digital output load capacitance
Operating free-air temperature
10
TA
–40
85
°C
2
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SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless
otherwise noted
PCM1870RHF, PCM1870YZF
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
AUDIO DATA
Data Format
Resolution
16
Bits
Bits
Audio data interface format
Audio data bit length
Audio data format
I2S, left-, right-justified, DSP
16
MSB-first, 2s-complement
fS
Sampling frequency
5
50
kHz
VDD < 2 V
VDD > 2 V
27
40
System clock
MHz
DIGITAL INPUT/OUTPUT
Logic family
CMOS compatible
VIH
0.7 VIO
Input logic level
VIL
VDC
μA
0.3 VIO
10
IIH
VIN = 3.3 V
VIN = 0 V
Input logic current
IIL
–10
VOH
IOH = –2 mA
IOL = 2 mA
0.75 VIO
Output logic level
VOL
VDC
0.25 VIO
LINE INPUT TO DIGITAL OUTPUT THROUGH ADC (AIN1L/R, AIN2L/R AND PGINL/R—ALC = OFF, PG1 = PG2 = PG3 = PG4 = 0 dB
Dynamic Performance
2.828
Vp-p
Vrms
dB
Full-scale input voltage
0 dB
1
90
Dynamic range
EIAJ, A-weighted
EIAJ, A-weighted
SNR
Signal-to-noise ratio
Channel separation
83
90
dB
87
dB
THD+N
Total harmonic distortion + noise
–1 dB
0.009%
0.017%
Analog Input
Center voltage
0.5 VCC
20
V
AIN1L, AIN1R, AIN2L, and AIN2R
10
70
Input impedance
PGINL and PGINR, PG3 = PG4 = –12 dB
PGINL and PGINR, PG3 = PG4 = 30 dB
142
kΩ
4.7
9.5
ANALOG OUTPUTS (AOL AND AOR)
Center voltage
0.5 VCC
V
Load resistance
10
kΩ
pF
Load capacitance
20
MICROPHONE BIAS—ALC = OFF, PG1 = PG2 = PG3 = PG4 = 0 dB
Bias voltage
0.75 VCC
V
Bias source current
Output noise
2
mA
μV
6.5
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless
otherwise noted
PCM1870RHF, PCM1870YZF
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
FILTER CHARACTERISTICS
Decimation Filter for ADC
Pass band
0.408 fS
±0.02
Stop band
0.591 fS
–60
Pass-band ripple
dB
dB
s
Stop-band attenuation
Group delay
f < 3.268 fS
17/fS
High-Pass Filter for ADC
–3 dB
3.74
10.66
Frequency response (fc = 4 Hz)
–0.5 dB
–0.1 dB
–3 dB
Hz
Hz
Hz
24.20
118.77
321.75
605.52
235.68
609.95
2601.2
Frequency response (fc = 120 Hz)
Frequency response (fc = 240 Hz)
–0.5 dB
–0.1 dB
–3 dB
–0.5 dB
–0.1 dB
POWER SUPPLY AND SUPPLY CURRENT
VIO
VIO
1.71
1.71
2.4
3.3
3.3
3.3
8
3.6
3.6
3.6
12
VDD
VCC
Voltage range
VDD
VCC
VDC
BPZ input, all active, no load
All inputs are held static.
BPZ input
mA
μA
Supply current
1
10
26.4
3.3
39.6
33
mW
μW
Power dissipation
All inputs are held static.
TEMPERATURE CONDITION
Operation temperature
–40
85
°C
θJA
Thermal resistance
35
°C/W
4
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SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
PIN ASSIGNMENTS
RHF Package
(Top View)
YZF Package
(Top View)
A
B
C
D
E
F
AIN1R AIN1L
PGINR PGINL
MICB
VCOM
24 23 22 21 20
1
2
3
4
5
6
7
19
18
17
16
15
14
13
VCOM
AIN2R
PGINL
AOL
VCC
AGND
AIN2L
PGINR
AOR
AOR
AOL
AIN2R AIN2L
MODE
TEST MODE MS/ADR MD/SDA
MS/ADR
MD/SDA
MC/SCL
TEST
LRCK
BCK
LRCK DGND
VIO
MC/SCL
8
9
10 11 12
BCK
1
SCKI
2
VDD
DOUT
4
3
P0057-01
Table 1. TERMINAL FUNCTIONS
TERMINAL
NO.
I/O
DESCRIPTION
NAME
AGND
RHF
24
21
20
3
YZF
B4
A2
A1
C4
C3
C2
C1
F1
E2
F4
E1
E4
D4
A3
D2
D3
B2
B1
F2
D1
B3
A4
F3
E3
–
I
Ground for analog
AIN1L
AIN1R
AIN2L
AIN2R
AOL
Analog input 1 for L-channel
Analog input 1 for R-channel
Analog input 2 for L-channel
Analog input 2 for R-channel
I
I
2
I
18
16
13
11
8
O
O
I/O
–
O
I/O
I
Microphone amplifier output for L-channel
Microphone amplifier output for R-channel
Serial bit clock
AOR
BCK
DGND
DOUT
LRCK
MC/SCL
MD/SDA
MICB
MODE
MS/ADR
PGINL
PGINR
SCKI
Ground for digital
Serial audio data output
14
7
Left- and right-channel clock
Mode control clock for 3-wire / 2-wire interface
Mode control data for 3-wire / 2-wire interface
Microphone bias source output
2- or 3-wire interface selection (LOW: SPI, HIGH: I2C)
Mode control select for 3-wire / 2-wire interface
Analog input to gain amplifier for L-channel
Analog input to gain amplifier for R-channel
System clock
6
I/O
O
I
22
4
5
I
19
17
12
15
23
1
I
I
I
TEST
VCC
I
Test Pin. Should be connected to ground.
Power supply for analog
–
–
–
–
VCOM
Common voltage for analog
VDD
10
9
Power supply for digital core
VIO
Power supply for digital I/O
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FUNCTIONAL BLOCK DIAGRAM
MD/SDA MC/SCL MS/ADR MODE
AOL
PGINL TEST
SCKI
DOUT BCK LRCK
Audio Interface
Serial Interface (SPI/I2C)
Clock
Manager
Mute
PG1
ATR
AIN2L
AIN1L
0/+12/+20 dB
ADL
PG3
DS
Digital
Filter
D2S
ADC
+30 to –12 dB
ADR
PG4
+30 to –12 dB
DS
Digital
Filter
ADC
PG2
AIN1R
AIN2R
Module That Can Be Powered Up/Down
0/+12/+20 dB
MCB
Mic Bias
MICB
VCOM
Power Up/Down
Power On
Manager
Reset
COM
VCOM
AOR PGINR
VIO
VDD
DGND
VCC
AGND
B0231-01
6
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SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
TYPICAL PERFORMANCE CURVES
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 8 kHz to 48 kHz, system clock = 256 fS and 16-bit data,
unless otherwise noted.
DECIMATION FILTER, STOP-BAND
DECIMATION FILTER, PASS-BAND
0
–20
0.2
0.1
–40
–60
0
–80
–0.1
–0.2
–100
–120
0
1
2
3
4
0
0.1
0.2
0.3
0.4
0.5
Frequency [´ fS]
Frequency [´ fS]
G001
G002
Figure 1.
Figure 2.
HIGH-PASS FILTER PASS-BAND CHARACTERISTICS
(fC = 4 Hz at 48 kHz)
HIGH-PASS FILTER PASS-BAND CHARACTERISTICS
(fC = 120 Hz at 48 kHz)
5
5
0
–5
0
–5
–10
–15
–20
–10
–15
–20
0
0.0005
0.001
0.0015
0.002
0
0.005
0.01
0.015
0.02
Frequency [´ fS]
Frequency [´ fS]
G003
G012
Figure 3.
Figure 4.
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TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 8 kHz to 48 kHz, system clock = 256 fS and 16-bit data,
unless otherwise noted.
HIGH-PASS FILTER PASS-BAND CHARACTERISTICS
(fC = 240 Hz at 48 kHz)
5
0
–5
–10
–15
–20
0
0.01
0.02
0.03
0.04
Frequency [´ fS]
G004
Figure 5.
8
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TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 44.1 kHz, system clock = 256 fS and 16-bit data, unless
otherwise noted.
3 BAND TONE CONTROL (BASS, MID, TREBLE)
3 BAND TONE CONTROL (BASS)
15
10
5
15
10
5
0
0
–5
–10
–15
–5
–10
–15
100k
0
1k
0.01
0.1
1
10
100
1k
10k
400
600
800
200
Frequency – Hz
Frequency – Hz
G005
G006
Figure 6.
Figure 7.
3 BAND TONE CONTROL (MID)
3 BAND TONE CONTROL (TREBLE)
15
10
5
15
10
5
0
0
–5
–10
–15
–5
–10
–15
0
5k
2k
12k
14k
2k
3k
4k
6k
8k
10k
1k
4k
Frequency – Hz
Frequency – Hz
G007
G008
Figure 8.
Figure 9.
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TYPICAL PERFORMANCE CURVES (continued)
All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS and 16-bit data, unless
otherwise noted.
ADC SNR AT HIGH GAIN (PG1/PG2 = 0 dB)
ADC SNR AT HIGH GAIN (PG1/PG2 = 20 dB)
100
90
85
70
60
50
40
90
85
80
75
70
65
60
55
50
45
40
fIN = 1 kHz
Single Input
Single Input
Differential Input
Differential Input
fIN = 1 kHz
0
25
30
0
25
30
10
15
20
10
15
20
5
5
PG3/PG4 Gain – dB
PG3/PG4 Gain – dB
G009
G010
Figure 10.
Figure 11.
THD+N/SNR vs POWER SUPPLY
(ADC TO DIGITAL OUTPUT)
0.012
92
91
90
89
fIN = 1 kHz
0.011
0.010
0.009
0.008
0.007
THD+N
SNR
88
87
2
2.5
3
3.5
4
Power Supply – V
G011
Figure 12.
10
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SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
PCM1870 DESCRIPTION
Analog Input
The AIN1L, AIN1R, AIN2L and AIN2R pins can be used as microphone or line inputs with selectable 0- or 20-dB
boost and 1-Vrms input. All analog inputs have high input impedance (20 kΩ), which is not changed by gain
settings. One pair of inputs is selected by register 87 (AIL[1:0], AIR[1:0]). AIN1L and AIN1R can also be used as
a monaural differential input.
Gain Setting for Analog Input
Analog signals can be adjusted from 30 dB to –12 dB in 1-dB steps after the 0-, 12- or 20-dB boost amplifier.
Gain level can be set for each channel by register 79, 80 (ALV[5:0], ARV[5:0]).
A/D Converter
The ADC includes a multilevel delta-sigma modulator, aliasing filter, decimation filter, high-pass filter and notch
filter and can accept 1 Vrms as full-scale input voltage. The decimation filter has a digital soft mute controlled by
register 81 (RMUL, RMUR), and the high-pass and notch filters can be disabled by register 81 (HPF[1:0]) and
registers 96 through 104 if they are not needed to cancel dc offset or avoid wind noise.
Common Voltage
Unbuffered common voltage. The VCOM pin is normally biased to 0.5 VCC, and it provides common voltage to
internal circuitry. Connecting a 4.7-μF capacitor to this pin is recommended to optimize analog performance.
Microphone Bias
The MICB pin is a microphone bias source for an external microphone, which can provide 2 mA (typ) bias
current.
Auto Level Control (ALC) for Recording
The sound when microphone recording should be adjusted to a suitable level without saturation. The digitally
controlled auto level control (ALC) automatically expands small input signals and compresses large input signals
while recording. Expansion level, compression level, attack time, and recovery time can be selected by register
83. See the bit descriptions of register 83 for detailed settings.
3D Sound
A 3D sound effect is provided by mixing L-channel and R-channel data through a band-pass filter with two
control parameters, mixing ratio and band-pass filter characteristic. The control parameters are set in register 95
(3DP[3:0], 3FLO). The 3D sound effect is applied to the ADC digital output.
3-Band Tone Control
Tone control has bass, midrange, and treble controls that can be adjusted from 12 dB to –12 dB in 1-dB steps by
register 92 to 94 (LGA[4:0], MGA[4:0] and HGA[4:0]). Register 92 (LPAE), which attenuates the digital input
signal automatically, can prevent clipping of the output signal at settings higher than 0 dB for bass control. LPAE
is not effective for midrange and treble control.
High-Pass Filter and Notch Filter
The high-pass filter cuts dc offset in the analog section of the ADC and can be set to 4 Hz, 120 Hz, or 240 Hz at
48-kHz sampling by register 81 (HPF[1:0]).
Notch filters remove noise at particular frequencies, CCD noise, motor noise and other mechanical noise in an
application. The PCM1870 has two notch filters, whose center frequency and frequency bandwidth can be
programmed by registers 96 to 104.
Digital Monaural Mixing
The audio data can be mixed to monaural digital data from stereo digital data in the internal audio interface
section by register 96 (MXEN).
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Zero-Cross Detection
Zero-cross detection minimizes audible zipper noise while changing analog volume and digital attenuation. This
function can be applied to digital input or digital output by register 86 (ZCRS).
Power Up/Down for Each Module
Using register 73 (PBIS), register 82 (PAIR, PAIL, PADS, PMCB, PADR, PADL), and register 90 (PCOM),
unused modules can be powered down to minimize power consumption (13 mW when recording only).
Digital Interface
All digital I/O pins can interface at various power supply voltages. The VIO pin can be connected to a 1.71-V to
3.6-V power supply.
Power Supply
The VCC pin can be connected to 2.4 V to 3.6 V. The VDD pin and VIO pin can be connected to 1.71 to 3.6 V. A
different voltage can be applied to each of these pins (for example, VDD = 1.8 V, VIO = 3.3 V).
12
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DESCRIPTION OF OPERATION
System Clock Input
The PCM1870 can accept input clocks of various frequencies without a PLL. The clocks are used for clocking of
the digital filters, auto level control, and delta-sigma modulators, and classified into common-audio and
application-specific clocks. Table 2 shows frequencies of the common audio clock and the application-specific
clock. Figure 13 shows timing requirements for system clock inputs. The sampling rate and frequency of the
system clock are determined by settings in register 86 (MSR[2:0]) and register 85 (NPR[5:0]). Note that the
sampling rate of the application-specific clock has a little sampling error. The details are shown in Table 8.
Table 2. Frequency of Common Audio Clock
FREQUENCY
Common audio clock
11.2896, 12.288, 16.9344, 18.432 MHz
Application-specific clock
12, 13, 13.5, 24, 26, 27, 19.2, 19.68, 38.4, 39.36 MHz
tw(SCKH)
0.7 VIO
SCKI
0.3 VIO
tw(SCKL)
T0005-12
PARAMETERS
SYMBOL
tw(SCKH)
tw(SCKL)
MIN
14
UNIT
ns
System clock pulse duration, high
System clock pulse duration, low
14
ns
Figure 13. System Clock Timing
Power-On Reset and System Reset
The power-on-reset circuit outputs reset signal, typically at VDD = 1.2 V, and this circuit does not depend on the
voltage of other power-supplies (VCC, VPA, and VIO). Internal circuits are cleared to default status, then signals
are removed from all analog and digital outputs. The PCM1870 does not require any power supply sequencing.
Register data must be written after turning all power supplies on.
System reset is enabled by setting register 85 (SRST), and all registers are cleared automatically. All circuits are
reset to their default status at once. Note that the PCM1870 has audible pop noise on the analog outputs when
enabling SRST.
Power On/Off Sequence
To reduce audible pop noise, a sequence of register settings is required after turning all power supplies on when
powering up, or before turning the power supplies off when powering down. If some modules are not required for
a particular application or operation, they should be placed in the power-down state after performing the
power-on sequence. The recommended power-on and power-off sequences are shown in Table 3 and Table 4,
respectively.
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Table 3. Recommended Power-On Sequence
REGISTER
SETTINGS
STEP
NOTE
1
2
—
Turn ON all power supplies(1)
ADC audio interface format (left-justified)
PG1, PG2 gain control (0 dB)
Analog bias power up
(2)
5102H
5A00H
4980H
5601H
4A01H
523FH
5711H
4F0CH
500CH
3
4
5
Zero-cross detection enable
VCOM power up
6
7
Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power up
Analog input (MUX3, MUX4) select. Analog input (MUX1, MUX2) select
Analog input L-ch (PG3) volume (0 dB)(3)
8
9
10
Analog input R-ch (PG4) volume (0 dB) (3)
(1) VDD should be turned on first or at the same time with other power supplies. It is recommended to set the register data after turning on
all power supplies and while the system clock is running.
(2) The audio interface format should be set to match the DSP or decoder being used.
(3) Any level is acceptable for volume or attenuation. The level should return to that recorded in the register data when system was last
powered off.
Table 4. Recommended Power-Off Sequence
REGISTER
STEP
NOTE
SETTINGS
5132H
5200H
4A00H
4900H
—
1
2
3
4
5
ADC L-ch/R-ch digital soft mute enable, ADC audio interface format (left-justified)(1)
Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power down
VCOM power down
Analog bias power down
(2)
Turn OFF all power supplies.
(1) The audio interface format should be set to match the DSP or decoder being used.
(2) Power-supply sequencing is not required. It is recommended to make the required register settings while the system clock is running,
then turn off all power supplies.
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Power-Supply Current
The current consumption of the PCM1870 depends on the power-up/down status of each circuit module. In order
to save power consumption, disabling each module is recommended when it is not used in an appliction or
operation. Table 5 shows current consumtption in some states.
Table 5. Power Consumption Table
POWER SUPPLY CURRENT [mA]
PD [mW]
OPERATION MODE
ALL POWER DOWN
VDD
VDD
VCC
(3.3 V)
VIO
(3.3 V)
TOTAL
(VDD = 1.8 V)
TOTAL
(VDD = 3.3 V)
(1.8 V) (3.3 V)
0.000
0.000
0.001
0.000
0.003
0.003
Recording (fS = 48 kHz)
Line input (AIN2L/AIN2R)
1.78
1.79
2.73
1.33
2.21
1.33
2.21
3.71
3.71
5.59
2.80
4.60
2.80
4.60
4.58
5.06
5.06
3.56
3.56
3.88
3.88
0.10
0.10
0.10
0.10
0.10
0.10
0.10
18.3
19.9
21.6
14.1
15.7
15.2
16.8
27.7
29.3
35.5
21.3
27.3
22.4
28.3
Mic input (AIN1L/AIN1R, 20 dB)
Mic input (AIN1L/AIN1R, 20 dB) with ALC
Mono mic input (AIN1L, 20 dB)
Mono mic input (AIN1L, 20 dB) with ALC
Mono diff mic input (AIN1L/AIN1R, 20 dB)
Mono diff mic input (AIN1L/AIN1R, 20 dB) with ALC
Recording (fS = 22.05 kHz)
Line input (AIN2L/AIN2R)
0.82
0.82
1.26
0.61
1.03
0.61
1.02
1.66
1.66
2.55
1.23
2.10
1.23
2.08
3.71
4.20
4.20
2.74
2.74
3.06
3.06
0.10
0.10
0.10
0.10
0.10
0.10
0.10
13.7
15.3
16.1
10.1
10.9
11.2
11.9
18.1
19.7
22.6
13.4
1.63
14.5
17.3
Mic input (AIN1L/AIN1R, 20 dB)
Mic input (AIN1L/AIN1R, 20 dB) with ALC
Mono mic input (AIN1L, 20 dB)
Mono mic input (AIN1L, 20 dB) with ALC
Mono diff mic input (AIN1L/AIN1R, 20 dB)
Mono diff mic input (AIN1L/AIN1R, 20 dB) with ALC
Recording (fS = 16 kHz)
Line input (AIN2L/AIN2R)
0.59
0.59
0.91
0.44
0.75
0.44
0.74
1.18
1.18
1.85
0.87
1.52
0.87
1.50
3.51
3.99
3.99
2.55
2.55
2.87
2.87
0.10
0.10
0.10
0.10
0.10
0.10
0.10
12.7
14.2
14.8
9.2
15.8
17.4
19.6
11.6
13.8
12.7
14.8
Mic input (AIN1L/AIN1R, 20 dB)
Mic input (AIN1L/AIN1R, 20 dB) with ALC
Mono mic input (AIN1L, 20 dB)
Mono mic input (AIN1L, 20 dB) with ALC
Mono diff mic input (AIN1L/AIN1R, 20 dB)
Mono diff mic input (AIN1L/AIN1R, 20 dB) with ALC
Recording (fS = 8 kHz)
9.8
10.3
10.8
Line input (AIN2L/AIN2R)
0.29
0.29
0.46
0.22
0.37
0.22
0.37
0.54
0.54
0.88
0.39
0.70
0.39
0.70
3.23
3.72
3.72
2.29
2.29
2.61
2.61
0.10
0.10
0.10
0.10
0.10
0.10
0.10
11.2
12.8
13.1
8.0
12.8
14.4
15.5
9.2
Mic input (AIN1L/AIN1R, 20 dB)
Mic input (AIN1L/AIN1R, 20 dB) with ALC
Mono mic input (AIN1L, 20 dB)
Mono mic input (AIN1L, 20 dB) with ALC
Mono diff mic input (AIN1L/AIN1R, 20 dB)
Mono diff mic input (AIN1L/AIN1R, 20 dB) with ALC)
8.2
10.2
10.2
11.3
9.0
9.3
Condition: 256 fS, 16 bits, slave mode, zero data input, no load
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Audio Serial Interface
The audio serial interface of the PCM1870 consists of LRCK, BCK and DOUT. Sampling rate (fS), left and right
channel are present on LRCK. DOUT transmits the serial data from the decimation filter for the ADC. BCK is
used to transmit the serial audio data on DOUT at its high-to-low transition. BCK and LRCK should be
synchronized with audio system clock. Ideally, it is recommended that they are derived from it.
The PCM1870 requires LRCK to be synchronized with the system clock. The PCM1870 do not need a specific
phase relationship between LRCK and the system clock.
The PCM1870 has both master mode and slave mode interface formats, which can be selected by register 84
(MSTR). LRCK and BCK are generated from the system clock in master mode.
Audio Data Formats and Timing
The PCM1870 supports I2S, right-justified, left-justified, and DSP formats. The data formats are shown in
Figure 16, and they are selected using resister 70 (RFM[1:0], PFM[1:0]). All formats require binary
2s-complement, MSB-first audio data. The default format is I2S. Figure 14 shows a detailed timing diagram.
50% of VIO
LRCK
tw(BCL)
tw(BCH)
t(LB)
50% of VIO
BCK
t(BL)
t(BCY)
t(CKDO)
t(LRDO)
50% of VIO
DOUT
T0010-12
PARAMETERS
SYMBOL
MIN
MAX
UNIT
BCK pulse cycle time (I2S, left- and right-justified formats)
BCK pulse cycle time (DSP format)
BCK high-level time
t(BCY)
t(BCY)
tw(BCH)
tw(BCL)
t(BL)
1/(64fS)(1)
1/(256fS)(1)
35
35
10
10
ns
ns
ns
ns
ns
BCK low-level time
BCK rising edge to LRCK edge
LRCK edge to BCK rising edge
DOUT delay time from BCK falling edge
t(LB)
t(CKDO)
40
(1) fS is the sampling frequency.
Figure 14. Audio Interface Timing (Slave Mode)
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t(SCY)
50% of VIO
SCKI
t(DL)
50% of VIO
LRCK (Output)
tw(BCL)
tw(BCH)
t(DB)
t(DB)
50% of VIO
BCK (Output)
t(BCY)
DOUT
50% of VIO
t(DS)
t(DH)
T0011-05
PARAMETERS
SYMBOL
t(SCY)
t(DL)
MIN
1/(256fS)(1)
MAX
UNIT
SCKI pulse cycle time
LRCK edge from SCKI rising edge
BCK edge from SCKI rising edge
BCK pulse cycle time
BCK high-level time
5
5
140
140
ns
ns
t(DB)
t(BCY)
tw(BCH)
tw(BCL)
t(DS)
1/(64fS)(1)
146
ns
ns
ns
ns
BCK low-level time
146
DOUT setup time
10
DOUT hold time
t(DH)
10
(1) fS is up to 48 kHz. fS is the sampling frequency
Figure 15. Audio Interface Timing (Master Mode)
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(a) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
L-Channel
R-Channel
BCK
(1)
(= 32 fS, 48 fS, or 64 fS
)
16-Bit Right-Justified
DOUT 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
4
4
2
3
4
7
7
5
6
7
8
9
10 11 12 13 14 15 16
MSB
LSB
MSB
LSB
(b) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
(1)
(= 32 fS, 48 fS, or 64 fS
)
DOUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
5
6
8
9
10 11 12 13 14 15 16
1
1
1
1
2
2
2
2
MSB
LSB
MSB
LSB
(c) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
L-Channel
R-Channel
BCK
(1)
(= 32 fS, 48 fS, or 64 fS
)
DOUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
5
6
8
9
10 11 12 13 14 15 16
MSB
LSB
MSB
LSB
(d) Burst BCK Interface Format in Master Mode; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
L-Channel
R-Channel
BCK
(1)
(= 32 fS, 48 fS, or 64 fS
)
DOUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
MSB
LSB
MSB
LSB
(e) DSP Format
1/fS
LRCK
BCK
(= 32 fS, 48 fS, 64 fS, 128 fS or 256 fS
)
DOUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
MSB
LSB
MSB
LSB
T0009-09
(1) All audio interface formats support BCK = 64 fS in master mode (register 69, MSTR = 1). When set to multisampling
rate, fS of BCK is set to half the rate of the DSM operation frequency.
Figure 16. Audio Data Output Formats
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THREE-WIRE INTERFACE (SPI, MODE (PIN 28) = LOW)
All write operations for the serial control port use 16-bit data words. Figure 17 shows the control data word
format. The most significant bit must be 0. There are seven bits, labeled IDX[6:0], that set the register address
for the write operation. The least-significant eight bits, D[7:0], contain the data to be written to the register
specified by IDX[6:0].
Figure 18 shows the functional timing diagram for writing to the serial control port. To write the data into the
mode register, the data is clocked into an internal shift register on the rising edge of the MC clock. The serial
data should change on the falling edge of the MC clock and should be LOW during write mode. The rising edge
of MS should be aligned with the falling edge of the last MC clock pulse in the 16-bit frame. The MC can run
continuously between transactions while MS is in the LOW state.
LSB
D0
MSB
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
Register Index (or Address)
D7
D6
D5
D4
D3
D2
D1
Register Data
R0001-01
Figure 17. Control Data Word Format for MD
(1) Single Write Operation
16 Bits
MS
MC
MD
MSB
LSB
MSB
(2) Continuous Write Operation
8 Bits x N Frames
MS
MC
MD
MSB
LSB MSB
LSB MSB
LSB
MSB
LSB
Register Index
Register (N) Data
Register (N+1) Data
Register (N+2) Data
8 Bits
N Frames
T0012-03
Figure 18. Register Write Operation
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Three-Wire Interface (SPI) Timing Requirements
Figure 19 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for
proper control port operation.
t
w(MHH)
MS
50% of V
IO
t
t
w(MCL)
(MLS)
t
t
(MLH)
w(MCH)
MC
MD
50% of V
IO
t
(MCY)
LSB
50% of V
IO
t
(MDS)
t
(MDH)
T0013-08
PARAMETERS
SYMBOL
t(MCY)
MIN
500(1)
50
TYP
MAX
UNIT
ns
MC pulse cycle time
MC low-level time
MC high-level time
MS high-level time
tw(MCL)
tw(MCH)
tw(MHH)
t(MLS)
ns
50
See (1)
ns
ns
MS falling edge to MC rising edge
MS hold time
50
ns
t(MLH)
20
ns
MD hold time
t(MDH)
15
ns
MD setup time
t(MDS)
20
ns
(1) 3/(128 fS) s (min), where fS is the sampling frequency
A
Figure 19. SPI Interface Timing
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TWO-WIRE INTERFACE [I2C, MODE (PIN 28) = HIGH]
The PCM1870 supports the I2C serial bus and the data transmission protocol for the I2C standard as a slave
device. This protocol is explained in I2C specification 2.0.
In I2C mode, the control terminals are changed as follows.
TERMINAL NAME
MS/ADR
PROPERTY
Input
DESCRIPTION
I2C address
I2C data
MD/SDA
Input/output
Input
MC/SCL
I2C clock
Slave Address
MSB
LSB
R/W
1
0
0
0
1
1
ADR
The PCM1870 has its 7-bit slave address. The first six bits (MSBs) of the slave address are factory preset to
1000 11. The next bit of the address byte is the device select bit, which can be user-defined by ADR terminal. A
maximum of two PCM1870s can be connected on the same bus at one time. Each PCM1870 responds when it
receives its own slave address.
Packet Protocol
A master device must control packet protocol, which is start condition, slave address with read/write bit, data if
write or acknowledgement if read, and stop condition. The PCM1870 supports only slave-receiver and
slave-transmitter.
SDA
SCL
St
1−7
8
9
1−8
9
1−8
9
Sp
Slave Address R/W
ACK
DATA
ACK
DATA
ACK
R/W: Read Operation if 1; Otherwise, Write Operation
ACK: Acknowledgement of a Byte if 0
DATA: 8 Bits (Byte)
Start
Condition
Stop
Condition
Write Operation
Transmitter
Data Type
M
M
M
S
M
S
M
S
M
St
Slave Address
R/W
ACK
DATA
ACK
DATA
ACK
Sp
Read Operation
Transmitter
Data Type
M
M
M
S
S
M
S
M
M
St
Slave Address
R/W
ACK
DATA
ACK
DATA
NACK
Sp
M: Master Device
St: Start Condition
S: Slave Device
Sp: Stop Condition
T0049-03
Figure 20. Basic I2C Framework
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Write Operation
A master can write any PCM1870 registers using single access. The master sends a PCM1870 slave address
with a write bit, a register address, and the data. When undefined registers are accessed, the PCM1870 does not
send an acknowledgement. The Figure 21 shows a diagram of the write operation.
Transmitter
Data Type
M
M
M
S
M
S
M
S
M
St
Slave Address
W
ACK
Reg Address
ACK
Write Data
ACK
Sp
M: Master Device S: Slave Device
St: Start Condition W: Write ACK: Acknowledge Sp: Stop Condition
R0002-01
Figure 21. Framework for Write Operation
Read Operation
A master can read the PCM1870 register. The value of the register address is stored in an indirect index register
in advance. The master sends a PCM1870 slave address with a read bit after storing the register address. Then
the PCM1870 transfers the data which the index register points to. Figure 22 shows a diagram of the read
operation.
Transmitter
Data Type
M
M
M
S
M
S
M
M
M
S
S
M
M
NACK
St
Slave Address
W
ACK
Reg Address
ACK Sr
Slave Address
R
ACK Read Data
Sp
M: Master Device S: Slave Device St: Start Condition
Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge
W: Write R: Read
R0002-02
NOTE: The slave address after the repeated start condition must be the same as the previous slave address.
Figure 22. Read Operation
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Timing Diagram
Start
Stop
t
t
(SDA-F)
(D-HD)
t
t
t
t
(P-SU)
(BUF)
(D-SU)
(SDA-R)
SDA
t
t
t
(SP)
(SCL-R)
(RS-HD)
t
(LOW)
SCL
t
t
t
(RS-SU)
(S-HD)
(HI)
t
(SCL-F)
T0050-03
TIMING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
fSCL
SCL clock frequency
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
100
kHz
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
pF
ns
t(BUF)
t(LOW)
t(HI)
Bus free time between a STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for START condition
Hold time for START condition
Data setup time
4.7
4.7
4
t(RS-SU)
t(S-HD)
t(D-SU)
t(D-HD)
t(SCL-R)
t(SCL-F)
t(SDA-R)
t(SDA-F)
t(P-SU)
CB
4.7
4
250
0
Data hold time
900
1000
1000
1000
1000
Rise time of SCL signal
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
4
Fall time of SCL signal
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Capacitive load for SDA and SCL line
Pulse duration of spike suppressed
400
25
t(SP)
Figure 23. I2C Interface Timing
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USER-PROGRAMMABLE MODE CONTROLS
Register Map
The mode control register map is shown in Table 6. Each register includes an index (or address) indicated by the
IDX[6:0] bits.
Table 6. Mode Control Register Map
IDX [6:0]
REGISTER
DESCRIPTION
Analog bias power up/down
B7
B6
B5
B4
B3
B2
B1
B0
(B14–B8)
49h
4Ah
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
5Ah
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
7Ch
Register 73
Register 74
Register 79
Register 80
Register 81
Register 82
Register 83
Register 84
Register 85
Register 86
Register 87
Register 90
Register 92
Register 93
Register 94
Register 95
Register 96
Register 97
Register 98
Register 99
Register 100
Register 101
Register 102
Register 103
Register 104
Register 124
PBIS
RSV
RSV
RSV
RSV
RSV
HPF0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
PCOM
ALV0
ARV0
RFM0
PADL
RLV0
BIT0
VCOM power up/down
Volume for ADC input (L-ch)
RSV
ALV5
ARV5
ALV4
ARV4
ALV3
ARV3
RSV
ALV2
ARV2
ALV1
ARV1
Volume for ADC input (R-ch)
RSV
ADC high pass-filter, soft mute, audio interface
ADC, MCB, PG1, 2, 5, 6, D2S power up/down
Auto level control for recording
HPF1
RSV
RMUL RMUR
DSMC RFM1
PAIR
RRTC
RSV
PAIL
RATC
RSV
PADS PMCB PADR
RALC
RSV
RCP1
RSV
RCP0
MSTR
NPR2
RSV
RLV1
RSV
Master mode
System reset, sampling rate control
BCK config, master mode, zero cross
Analog input select (MUX1, 2, 3, 4)
VCOM power up/down, ramp up/down time, boost
Bass boost gain level (200 Hz)
SRST
MBST
AD2S
RSV
NPR5
NPR4
MSR0
AIR0
RSV
NPR3
RSV
NPR1
RSV
NPR0
ZCRS
AIL0
MSR2 MSR1
RSV
RSV
AIR1
RSV
RSV
RSV
RSV
RSV
NUP2
F105
F113
F205
F213
S105
S113
S205
S213
RSV
RSV
RSV
AIL1
RSV
RSV
G20R
LGA1
G20L
LGA0
MGA0
HGA0
3DP0
MXEN
F100
F108
F200
F208
S100
S108
S200
S208
G12L
LPAE
RSV
RSV
LGA4
LGA3
LGA2
Middle boost gain level (1 kHz)
RSV
MGA4 MGA3 MGA2 MGA1
Treble boost gain level (5 kHz)
RSV
RSV
HGA4
3FL0
NUP1
F104
F112
F204
F212
S104
S112
S204
S212
RSV
HGA3
3DP3
RSV
HGA2
3DP2
RSV
HGA1
3DP1
RSV
Sound effect source select, 3D sound
2-stage notch filter, digital monaural mixing
1st-stage notch filter lower coefficient (a1)
1st-stage notch filter upper coefficient (a1)
1st-stage notch filter lower coefficient (a2)
1st-stage notch filter upper coefficient (a2)
2nd-stage notch filter lower coefficient (a1)
2nd-stage notch filter upper coefficient (a1)
2nd-stage notch filter lower coefficient (a2)
2nd-stage notch filter upper coefficient (a2)
Mic boost
RSV
3DEN
NEN1
F106
F114
F206
F214
S106
S114
S206
S214
RSV
NEN2
F107
F115
F207
F215
S107
S115
S207
S215
RSV
F103
F111
F203
F211
S103
S111
S203
S211
RSV
F102
F110
F202
F210
S102
S110
S202
S210
RSV
F101
F109
F201
F209
S101
S109
S201
S209
G12R
ADC: A/D converter MCB: Microphone bias
PGx: Analog input buffer D2S: Differential to single-ended amplifier
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Register 73
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 73
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
PBIS
RSV
RSV
RSV
RSV
RSV
RSV
RSV
IDX[6:0]: 100 1001b (49h) Register 73
PBIS: Power Up/Down Control for Bias
Default value: 0
This bit is used to control power up/down for the analog bias circuit.
PBIS = 0
PBIS = 1
Power down (default)
Power up
Register 74
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 74
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
RSV
RSV
RSV
RSV
RSV
RSV
RSV PCOM
IDX[6:0]: 100 1010b (4Ah) Register 74
PCOM: Power Up/Down Control for VCOM
Default value: 0
This bit is used to control power up/down for VCOM
.
PCOM = 0
PCOM = 1
Power down (default)
Power up
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Register 79 and 80
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
ALV5 ALV4 ALV3 ALV2 ALV1 ALV0
AR2 ARV1 ARV0
B4
B3
B2
B1
B0
Register 79
Register 80
0
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
RSV
RSV
RSV
RSV ARV5 ARV4 ARV3
IDX[6:0]: 100 1111b (4Fh) Register 79
IDX[6:0]: 101 0000b (50h) Register 80
ALV[5:0]: Gain Control for PG3 (ADC Analog Input R-Channel)
ARV[5:0]: Gain Control for PG4 (ADC Analog Input L-Channel)
Default value: 00
PG3 and PG4 can be independently controlled for ADC input from 30 dB to –12 dB in 1-dB steps. ADC output
may have zipper noise when changing levels. In the PCM1870, the noise can be reduced when making the
change by using zero-cross detection (Register 85, ZCRS).
Table 7. Gain Level Setting
ALV[5:0], ARV[5:0]
ALV[5:0], ARV[5:0]
GAIN LEVEL SETTING
GAIN LEVEL SETTING
BINARY
10 1010
10 1001
10 1000
10 0111
10 0110
10 0101
10 0100
10 0011
10 0010
10 0001
10 0000
01 1111
01 1110
01 1101
01 1100
01 1011
01 1010
01 1001
01 1000
01 0111
01 0110
01 0101
HEX
2A
29
28
27
26
25
24
23
22
21
20
1F
1E
1D
1C
1B
1A
19
18
17
16
15
BINARY
01 0100
01 0011
01 0010
01 0001
01 0000
00 1111
00 1110
00 1101
00 1100
00 1011
00 1010
00 1001
00 1000
00 0111
00 0110
00 0101
00 0100
00 0011
00 0010
00 0001
00 0000
HEX
14
13
12
11
10
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
02
01
00
30 dB
29 dB
28 dB
27 dB
26 dB
25 dB
24 dB
23 dB
22 dB
21 dB
20 dB
19 dB
18 dB
17 dB
16 dB
15 dB
14 dB
13 dB
12 dB
11 dB
10 dB
9 dB
8 dB
7 dB
6 dB
5 dB
4 dB
3 dB
2 dB
1 dB
0 dB
–1 dB
–2 dB
–3 dB
–4 dB
–5 dB
–6 dB
–7 dB
–8 dB
–9 dB
–10 dB
–11 dB
–12 dB (default)
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Register 81
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 81
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 HPF1 HPF0 RMUL RMUR RSV DSMC RFM1 RFM0
IDX[6:0]: 101 0001b (51h) Register 81
HPF[1:0]: High-Pass Filter Selection
Default value: 00
The PCM1870 has a digital high-pass filter to remove dc voltage at the input of the ADC. The cutoff frequency of
the high-pass filter can be selected.
HPF[1:0]
0 0
High Pass Filter Selection
fC = 4 Hz at 48 kHz (default)
fC = 240 Hz at 48 kHz
0 1
1 0
fC = 120 Hz at 48 kHz
1 1
High-pass filter disabled
RMUL: Digital Soft Mute Control for ADC L-Channel
RMUR: Digital Soft Mute Control for ADC R-Channel
Default value: 1
The digital output of the ADC can be independently muted or unmuted. The transition from the current volume
level to mute, or the return to the previous volume setting from mute, occurs at the rate of one 1-dB step for each
8/fS time period. When RMUL and RMUR = 0, the digital data is increased from mute to the previous attenuation
level, and when RMUL and RMUR = 1, the digital data is decreased from the current attenuation level to mute. In
the PCM1870, audible zipper noise can be reduced by using zero-cross detection (register 85, ZCRS).
RMUL, RMUR = 0 Mute disabled
RMUL, RMUR = 1 Mute enabled (default)
DSMC: Waiting Time Turn ADC Mute Off at Power Up
Default value: 0
ADC digital output has waiting time at power up when DSMC = 0. It is recommended to set DSMC = 0.
DSMC = 0
DSMC = 1
10 ms at 48 kHz (default)
No wait
RFM[1:0]: Audio Interface Selection for ADC (Digital Output)
Default value: 00
The audio interface format for ADC digital output has I2S, right-justified, left-justified, and DSP formats.
RFM[1:0]
0 0
Audio Interface Selection for ADC Digital Output
I2S (default)
Right-justified
Left-justified
DSP mode
0 1
1 0
1 1
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Register 82
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 82
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
RSV
RSV
PAIR
PAIL PADS PMCB PADR PADL
IDX[6:0]: 101 0010b (52h) Register 82
PAIR: Power Up/Down for PG2 and PG6 (Gain Amplifier for Analog Input R-Channel)
PAIR: Power Up/Down for PG1 and PG5 (Gain Amplifier for Analog Input L-Channel)
Default value: 0
This bit is used to control power up/down for PG1, -2 and PG5, -6 (gain amplifier for analog input).
PAIR, PAIL = 0
PAIR, PAIL = 1
Power down (default)
Power up
PADS: Power Up/Down for D2S (Differential Amplifier) of AIN1L and AIN1R
Default value: 0
This bit is used to control power up/down for D2S (differential-to-single amplifier).
PADS = 0
PADS = 1
Power down (default)
Power up
PMCB: Power Up/Down Control for Microphone Bias Source
Default value: 0
This bit is used to control power up/down for the microphone bias source.
PMCB = 0
PMCB = 1
Power down (default)
Power up
PADR: Power Up/Down Control for ADR (ADC and Digital Filter R-Channel)
PADL: Power Up/Down Control for ADL (ADC and Digital Filter L-Channel)
Default value: 0
This bit is used to control power up/down for the ADC and decimation filter.
PADR, PADL = 0 Power down (default)
PADR, PADL = 1 Power up
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Register 83
Register 83
SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RALC RSV RRTC RATC RCP1 RCP0 RLV1 RLV0
IDX[6:0]: 1010011b (53h) Register 83
RALC: Automatic Level Control (ALC) Enable for Recording
Default value: 0
Auto level control can be enabled with some parameters for microphone input or lower-level analog source.
RALC = 0
RALC = 1
Disabled (default)
Enabled
RRTC: ALC Recovery Time Control for Recording
Default value: 0
This bit selects the time during which a gain level change completes to compress the signal when the input to the
ADC increases in amplitude.
RRTC = 0
RRTC = 1
3.4 s (default)
13.6 s
RATC: ALC Attack Time Control for Recording
Default value: 0
This bit selects the time during which a gain level change completes to expand the signal when the input to the
ADC decreases in amplitude.
RATC = 0
RATC = 1
1 ms (default)
2 ms
RCP[1:0]: ALC Compression Level Control for Recording
Default value: 00
Auto level control can set the compression level to –2, –6, or –12 dB. Higher-level signals should be compressed
to avoid saturation or degradation of sound quality.
RCP[1:0]
0 0
ALC Compression Level Control for Recording
–2 dB (default)
–6 dB
0 1
1 0
–12 dB
1 1
Reserved
RLV[1:0]: ALC Expansion Level Control for Recording
Default value: 00
Auto level control can set the expansion level to 0, 6, 14, or 24 dB. Lower-level signals should be expanded to
make a small signal easy to hear. If set to 0 dB, the ALC can be operated only as a limiter.
RLV[1:0]
0 0
ALC Expansion Level Control for Recording
0 dB (default)
6 dB
0 1
1 0
14 dB
1 1
24 dB
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Register 84–86
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
BIT0
Register 84
Register 85
Register 86
0
0
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
RSV
RSV
RSV
RSV
RSV MSTR RSV
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST RSV NPR5 NPR4 NPR3 NPR2 NPR1 NPR0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MBST MSR2 MSR1 MSR0 RSV RSV RSV ZCRS
IDX[6:0]: 101 0100b (54h) Register 84
IDX[6:0]: 101 0101b (55h) Register 85
IDX[6:0]: 101 0110b (56h) Register 86
MSTR: Master or Slave Selection for Audio Interface
Default value: 0
This bit is used to select either master or slave mode for the audio interface. In master mode, PCM1870
generates LRCK and BCK from the system clock. In slave mode, it receives LRCK and BCK from another
device.
MSTR = 0
MSTR = 1
Slave interface (default)
Master interface
BIT0: Bit Length Selection for Audio Interface
Default value: 1
This bit is used to select data bit length for the ADC output.
BIT0 = 0
BIT0 = 1
Reserved
16 bits (default)
SRST: System Reset
Default value: 0
This bit is used to enable system reset. All circuits are reset by setting SRST = 1. After completing the reset
sequence, SRST resets to 0 automatically.
SRST = 0
SRST = 1
Reset disabled (default)
Reset enabled
NPR[5:0]: System Clock Rate Selection
Default value: 00 0000
These bits are used to select the system clock rate. See Table 8 for details.
MBST: BCK Output Configuration in Master Mode
Default value: 0
This bit is used to control the BCK output configuration in master mode. VIO (I/O cell power supply) power
consumption can be reduced by adjusting BCK edge to bit number when setting MBST = 1. This is effective in
master mode (register 69 MSTR = 1).
MBST = 0
MBST = 1
Normal output (default)
Burst output
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MSR[2:0]: System Clock Dividing Rate Selection in Master Mode (Register 70)
Default value: 000
These bits are used to set the dividing rate of the input system clock. See Table 8 for details.
Table 8. System Clock Frequency for Common Audio Clock
REGISTER SETTING
MSR[2:0]
SYSTEM CLOCK
SCK (MHz)
ADC SAMPLING RATE
ADC fS (kHz)
DAC SAMPLING RATE
DAC fS (kHz)
BIT CLOCK
BCK (fS)
NPR[5:0]
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
00 0000
24 (SCK/256)
010
011
100
101
110
111
010
100
110
010
011
100
101
110
111
011
101
111
010
011
100
101
110
111
010
011
100
101
110
111
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
16 (SCK/384)
12 (SCK/512)
6.144
8.192
8 (SCK/768)
6 (SCK/1024)
4 (SCK/1536)
32 (SCK/256)
16 (SCK/512)
8 (SCK/1024)
48 (SCK/256)
32 (SCK/384)
24 (SCK/512)
12.288
18.432
5.6448
16 (SCK/768)
12 (SCK/1024)
8 (SCK/1536)
48 (SCK/384)
24 (SCK/768)
12 (SCK/1536)
22.05 (SCK/256)
14.7 (SCK/384)
11.025 (SCK/512)
7.35 (SCK/768)
5.5125 (SCK/1024)
3.675 (SCK/1536)
44.1 (SCK/256)
29.4 (SCK/384)
22.05 (SCK/512)
14.7 (SCK/768)
11.025 (SCK/1024)
7.35 (SCK/1536)
11.2896
NOTE: Other settings are reserved.
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Table 9. System Clock Frequency for Application-Specific Audio Clock
REGISTER SETTING
MSR[2:0]
SYSTEM CLOCK
SCK (MHz)
ADC SAMPLING RATE
ADC fS (kHz)
DAC SAMPLING RATE
DAC fS (kHz)
BIT CLOCK
BCK (fS)
NPR[5:0]
00 0010
00 0001
10 0010
00 0010
00 0001
10 0010
00 0010
10 0010
01 0010
01 0001
11 0010
01 0010
01 0001
11 0010
01 0010
11 0010
00 0100
00 0011
10 0100
00 0100
00 0011
10 0100
00 0100
10 0100
01 0100
01 0011
11 0100
01 0100
01 0011
11 0100
01 0100
11 0100
00 0110
00 0101
10 0110
00 0110
00 0101
10 0110
00 0110
10 0110
48.214 (SCK/280)
010
010
010
100
100
100
110
110
010
010
010
100
100
100
110
110
010
010
010
100
100
100
110
110
010
010
010
100
100
100
110
110
011
011
011
101
101
101
111
111
70
76
70
70
76
70
70
70
70
76
70
70
76
70
70
70
62
68
62
62
68
62
62
62
62
68
62
62
68
62
62
62
66
72
66
66
72
66
66
66
44.407 (SCK/304)
32.142 (SCK/420)
24.107 (SCK/560)
22.203 (SCK/608)
16.071 (SCK/840)
12.053 (SCK/1120)
8.035 (SCK/1680)
48.214 (SCK/560)
44.407 (SCK/608)
32.142 (SCK/840)
24.107 (SCK/1120)
22.203 (SCK/1216)
16.071 (SCK/1680)
12.053 (SCK/2240)
8.035 (SCK/3360)
48.387 (SCK/248)
44.117 (SCK/272)
32.258 (SCK/372)
24.193 (SCK/496)
22.058 (SCK/544)
16.129 (SCK/744)
12.096 (SCK/992)
8.064 (SCK/1488)
48.387 (SCK/496)
44.117 (SCK/544)
32.258 (SCK/744)
24.193 (SCK/992)
22.058 (SCK/1088)
16.129 (SCK/1488)
12.096 (SCK/1984)
8.064 (SCK/2796)
48.484 (SCK/396)
44.444 (SCK/432)
32.323 (SCK/594)
24.242 (SCK/792)
22.222 (SCK/864)
16.161 (SCK/1188)
12.121 (SCK/1584)
8.080 (SCK/2376)
13.5
27
12
24
19.2
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Table 9. System Clock Frequency for Application-Specific Audio Clock (continued)
REGISTER SETTING
MSR[2:0]
SYSTEM CLOCK
SCK (MHz)
ADC SAMPLING RATE
ADC fS (kHz)
DAC SAMPLING RATE
DAC fS (kHz)
BIT CLOCK
BCK (fS)
NPR[5:0]
01 0110
01 0101
11 0110
01 0110
01 0101
11 0110
01 0110
11 0110
00 1000
00 0111
10 1000
00 1000
00 0111
10 1000
00 1000
10 1000
01 1000
01 0111
11 1000
01 1000
01 0111
11 1000
01 1000
11 1000
00 1010
00 1001
10 1010
00 1010
00 1001
10 1010
00 1010
10 1010
01 1010
01 1001
11 1010
01 1010
01 1001
11 1010
01 1010
11 1010
48.484 (SCK/792)
011
011
011
101
101
101
111
111
010
010
010
100
100
100
110
110
010
010
010
100
100
100
110
110
011
011
011
101
101
101
111
111
011
011
011
101
101
101
111
111
66
72
66
66
72
66
66
66
68
74
68
68
74
68
68
68
68
74
68
68
74
68
68
68
68
74
68
68
74
68
68
68
68
74
68
68
74
68
68
68
44.444 (SCK/864)
32.323 (SCK/1188)
24.242 (SCK/1584)
22.222 (SCK/1728)
16.161 (SCK/2376)
12.121 (SCK/3168)
8.080 (SCK/4752)
47.794 (SCK/272)
43.918 (SCK/296)
31.862 (SCK/408)
23.897 (SCK/544)
21.959 (SCK/592)
15.931 (SCK/816)
11.948 (SCK/1088)
7.965 (SCK/1632)
47.794 (SCK/544)
43.918 (SCK/592)
31.862 (SCK/816)
23.897 (SCK/1088)
21.959 (SCK/1184)
15.931 (SCK/1632)
11.948 (SCK/2176)
7.965 (SCK/3264)
48.235 (SCK/408)
44.324 (SCK/444)
32.156 (SCK/612)
24.117 (SCK/816)
22.162 (SCK/888)
16.078 (SCK/1224)
12.058 (SCK/1632)
8.039 (SCK/2448)
48.235 (SCK/816)
44.324 (SCK/888)
32.156 (SCK/1224)
24.117 (SCK/1632)
22.162 (SCK/1776)
16.078 (SCK/2448)
12.058 (SCK/3264)
8.039 (SCK/4896)
38.4
13
26
19.68
39.36
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ZCRS: Zero Cross for Digital Attenuation/Mute and Analog Gain Setting
Default value: 0
This bit is used to enable the zero-cross detector, which reduces zipper noise while the digital soft mute or
analog gain setting is being changed. If no zero-cross data is input for a 512/fS period (10.6 ms at a 48-kHz
sampling rate), then a time-out occurs and the PCM1870 starts changing the attenuation, gain, or volume level.
The zero-cross detector cannot be used with continuous-zero and dc data.
ZCRS = 0
ZCRS = 1
Zero cross disabled (default)
Zero cross enabled
Register 87
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 87
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AD2S RSV
AIR1
AIR0
RSV
RSV
AIL1
AIL0
IDX[6:0]: 101 0111b (57h) Register 87
AD2S: Differential Amplifier Selector (MUX3 and MUX4)
Default value: 0
This bit is used to select whether a single-ended amplifier or differential amplifier (D2S) is used as the input for
the ADC. MUX3 and MUX4 use the single-ended input when AD2S = 0. MUX3 and MUX4 use the monaural
differential input when AD2S = 1.
AD2S = 0
AD2S = 1
Single-ended amplifier (default)
Differential amplifier
AIL[1:0]: AIN1L and AIN2L Selector (MUX1)
Default value: 00
MUX1 selects the analog input, AIN1L or AIN2L.
AIL[1:0]
0 0
AIN L-channel Select
Disconnect (default)
AIN1L
0 1
1 0
AIN2L
1 1
Reserved
AIR[1:0]: AIN1R and AIN2R Selector (MUX2)
Default value: 00
MUX2 selects the analog input, AIN1R or AIN2R.
AIR[1:0]
0 0
AIN R-channel Select
Disconnect (default)
AIN1R
0 1
1 0
AIN2R
1 1
Reserved
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SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
Register 90
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 90
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
RSV
RSV
RSV
RSV
RSV
RSV G20R G20L
IDX[6:0]: 101 1010b (5Ah) Register 90
G20R: 20-dB Boost for PG2 (Gain Amplifier for AIN1R and AIN2R)
Default value: 0
This bit is used to boost the microphone signal when the analog input is small.
G12R
G20R
PG2 GAIN
(REGISTER 124)
(REGISTER 90)
0
0
1
1
0
1
0
1
0 dB (default)
20 dB
12 dB
Reserved
G20L: 20 dB Boost for PG1 (Gain Amplifier for AIN1L and AIN2L)
Default value: 0
This bit is used to boost the microphone signal when the analog input is small.
G12L
G20L
PG1 GAIN
(REGISTER 124)
(REGISTER 90)
0
0
1
1
0
1
0
1
0 dB (default)
20 dB
12 dB
Reserved
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Register 92
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 92
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 LPAE
RSV
RSV
LGA4 LGA3 LGA2 LGA1 LGA0
IDX[6:0]: 101 1100b (5Ch) Register 92
LPAE: Automatic Attenuation Setting for Bass Boost Gain Control
Default value: 0
A gain setting for bass boost may cause digital data saturation, depending on the input data level. Where this
could occur, LPAE can be used to set the same attenuation level as the bass boost gain level for the digital input
data.
LPAE = 0
LPAE = 1
Disble (default)
Enable
LGA[4:0]: Bass Boost Gain Control
Default value: 0 0000
These bits are used to set bass boost gain level for the digital data. The center frequency for boost is 200 Hz at
44.1 kHz.
LGA[4:0]
0 0000
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
TONE CONTROL GAIN (BASS)
LGA[4:0]
0 1111
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
TONE CONTROL GAIN (BASS)
0 dB (default)
12 dB
11 dB
10 dB
9 dB
0 dB
–1 dB
–2 dB
–3 dB
–4 dB
–5 dB
–6 dB
–7 dB
–8 dB
–9 dB
–10 dB
–11 dB
–12 dB
8 dB
7 dB
6 dB
5 dB
4 dB
3 dB
2 dB
1 dB
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SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
Register 93
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 93
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
RSV
RSV
RSV MGA4 MGA3 MGA2 MGA1 MGA0
IDX[6:0]: 101 1101b (5Dh) Register 93
MGA[4:0]: Middle Boost Gain Control
Default value: 0 0000
These bits are used to set midrange boost gain level for the digital data. The center frequency for boost is 1 kHz.
MGA[4:0]
0 0000
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
TONE CONTROL GAIN (MID)
MGA[4:0]
0 1111
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
TONE CONTROL GAIN (MID)
0 dB (default)
12 dB
11 dB
10 dB
9 dB
0 dB
–1 dB
–2 dB
–3 dB
–4 dB
–5 dB
–6 dB
–7 dB
–8 dB
–9 dB
–10 dB
–11 dB
–12 dB
8 dB
7 dB
6 dB
5 dB
4 dB
3 dB
2 dB
1 dB
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Register 94
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 94
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
RSV
RSV
RSV HGA4 HGA3 HGA2 HGA1 HGA0
IDX[6:0]: 101 1110b (5Eh) Register 94
HGA[4:0]: Treble Boost Gain Control
Default value: 0 0000
These bits are used to set treble boost gain level for the digital data. The center frequency for boost is 5 kHz.
HGA[4:0]
0 0000
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
TONE CONTROL GAIN (TREBLE)
HGA[4:0]
0 1111
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
TONE CONTROL GAIN (TREBLE)
0 dB (default)
12 dB
11 dB
10 dB
9 dB
0 dB
–1 dB
–2 dB
–3 dB
–4 dB
–5 dB
–6 dB
–7 dB
–8 dB
–9 dB
–10 dB
–11 dB
–12 dB
8 dB
7 dB
6 dB
5 dB
4 dB
3 dB
2 dB
1 dB
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SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
Register 95
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 95
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
RSV 3DEN RSV
3FL0 3DP3 3DP2 3DP1 3DP0
IDX[6:0]: 1011111b (5Fh) Register 95
3DEN: 3D Sound Effect Enable
Default value: 0
This bit is used for enabling the 3-D sound effect filter. This filter has two independently controlled parameters.
3DEN = 0
3DEN = 1
Disable (default)
Enable
3FL0: Filter Selection for 3D Sound
Default value: 0
This bit is used for selecting from two kinds of filter type, narrow and wide. These filters produce different 3-D
effects.
3FL0 = 0
3FL0 = 1
Narrow (default)
Wide
3DP[3:0]: Efficiency for 3D Sound Effect
Default value: 0000
These bits are used for adjusting the 3-D sound efficiency. Higher percentages have greater efficiency.
3DP[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
3D Sound Effect Efficiency
0% (default)
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
1011
:
Reserved
:
1111
Reserved
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Register 96
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 96
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 NEN2 NEN1 NUP2 NUP1 RSV
RSV
RSV MXEN
IDX[6:0]: 110 0000b (60h) Register 96
NEN2: Second-Stage Notch Filter Enable
Default value: 0
The PCM1870 has a two-stage notch filter. The two stages can separately set filter characteristics. This bit is
used to enable the second stage.
NEN2 = 0
NEN2 = 1
Disabled (default)
Enabled
NEN1: First-Stage Notch Filter Enable
Default value: 0
The PCM1870 has a two-stage notch filter. The two stages can separately set filter characteristics. This bit is
used to enable the first stage.
NEN1 = 0
NEN1 = 1
Disabled (default)
Enabled
NUP2: Second-Stage Notch Filter Coefficients Update
Default value: 0
This bit is used to update the coefficients for the second-stage notch filter. The coefficients written to registers
101, 102, 103, 104 are updated when NUP2 = 1.
NUP2 = 0
NUP2 = 1
No update (default)
Update
NUP1: First-Stage Notch Filter Coefficients Update
Default value: 0
This bit is used to update the coefficients for the first-stage notch filter. The coefficients written to registers 97,
98, 99, 100 are updated when NUP1 = 1.
NUP1 = 0
NUP1 = 1
No update (default)
Update
MXEN: Digital Monaural Mixing
Default value: 0
This bit is used to enable or disable monaural mixing in the section that combines L-ch and R-ch digital data.
MXEN = 0
MXEN = 1
Disabled (stereo, default)
Enabled (monaural mixing)
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Registers 97–100
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 97
Register 98
Register 99
Register 100
0
0
0
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
F107
F115
F207
F215
F106 F105
F114 F113
F206 F205
F214 F213
F104 F103 F102
F112 F111 F110
F204 F203 F202
F212 F211 F210
F101 F100
F109 F108
F201 F200
F209 F208
IDX[6:0]: 110 0001b (61h) Register 97
IDX[6:0]: 110 0010b (62h) Register 98
IDX[6:0]: 110 0011b (63h) Register 99
IDX[6:0]: 110 0100b (64h) Register 100
F[107:100]: Lower 8 Bits of Coefficient a1 for First-Stage Notch Filter
F[115:108]: Upper 8 Bits of Coefficient a1 for First-Stage Notch Filter
F[207:200]: Lower 8 Bits of Coefficient a2 for First-Stage Notch Filter
F[215:208]: Upper 8 Bits of Coefficient a2 for First-Stage Notch Filter
Default value: 0000 0000
These bits are used to change the characteristics of the first-stage notch filter. See Calculating Filter Coefficients
for details.
Registers 101–104
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 101
Register 102
Register 103
Register 104
0
0
0
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 S107 S106 S105 S104 S103 S102 S101 S100
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 S115 S114 S113 S112 S111 S110 S109 S108
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 S207 S206 S205 S204 S203 S202 S201 S200
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 S215 S214 S213 S212 S211 S210 S209 S208
IDX[6:0]: 110 0101b (65h) Register 101
IDX[6:0]: 110 0110b (66h) Register 102
IDX[6:0]: 110 0111b (67h) Register 103
IDX[6:0]: 110 1000b (68h) Register 104
S[107:100]: Lower 8 Bits of Coefficient a1 for Second-Stage Notch Filter
S[115:108]: Upper 8 Bts of Coefficient a1 for Second-Stage Notch Filter
S[207:200]: Lower 8 Bits of Coefficient a2 for Second-Stage Notch Filter
S[215:208]: Upper 8 Bits of Coefficient a2 for Second-Stage Notch Filter
Default value: 0000 0000
These bits are used to change the characteristics of the second-stage notch filter. See Calculating Filter
Coefficients for details.
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Calculating Filter Coefficients
The PCM1870 provides a dual-stage notch filter at the digital output of the ADC. The filter characteristics of each
filter stage can be programmed. The characteristics are determined by calculating coefficients for three
parameters, sampling frequency, center frequency and bandwidth, as shown in the following equations. All
coefficients must be written as 2s-complement binary data into registers 97, 98, 99, 100, 101, 102, 103, and 104.
f
+ Sampling frequency [Hz]
S
f
+ Center frequency [Hz]
C
f + Bandwidth [Hz]
b
2pf
C
a + * ǒ1 ) a Ǔcos
ǒ Ǔ
1
2
f
S
2pf ńf
b
S
1 * tan
ǒ Ǔ
2
a +
2
2pf ńf
b
S
1 ) tanǒ Ǔ
2
Register 124
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 124
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
RSV
RSV
RSV
RSV
RSV
RSV G12R G12L
IDX[6:0]: 111 1100b (7Ch) Register 124
G12R: 12-dB Boost for PG2 (Gain Amplifier for AIN1R and AIN2R)
G12L: 12-dB Boost for PG1 (Gain Amplifier for AIN1L and AIN2L)
Default value: 0
These bits are used to boost the microphone signal when the analog input is small. See Register 90 for the
detailed settings.
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SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
CONNECTION DIAGRAM
To Regulator
(9, E3) VIO
(10, F3) VDD
SCKI (12, F2)
BCK (13, F1)
LRCK (14, E1)
C6
C7
(11, E2) DGND
(23, B3) VCC
DOUT (8, F4)
C8
MS/ADR (5, D3)
MD/SDA (6, D4)
MC/SCL (7, E4)
MODE (4, D2)
(24, B4) AGND
Low or High
TEST (15, D1)
MICB (22, A3)
PCM1870
R1
R2
C1
(18, C2) AOL
AIN1L (21, A2)
AIN1R (20, A1)
AIN2L (3, C4)
AIN2R (2, C3)
C9
C2
C3
C4
(19, B2) PGINL
(16, C1) AOR
C10
(17, B1) PGINR
VCOM (1, A4)
C5
S0262-01
Figure 24. Connection Diagram
Table 10. Recommended External Parts
C1–C4
C5
1 μF–10 μF
1 μF–4.7 μF
0.1 μF
C9, C10
R1, R2
1 μF–10 μF
2.2 kΩ
C6
C7
1 μF
C8
1 μF–4.7 μF
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SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
BOARD DESIGN AND LAYOUT CONSIDERATIONS
VCC, VDD, and VIO Pins
The digital and analog power supply lines to the PCM1870 should be bypassed to the corresponding ground pins
with 0.1- to 4.7-μF ceramic capacitors or electrolytic capacitors, placed as close to the pins as possible to
maximize the dynamic performance of ADC.
AGND and DGND Pins
To maximize the dynamic performance of the PCM1870, the analog and digital grounds are not connected
internally. These grounds should have very low impedance to avoid digital noise feeding back into the analog
ground. So, they should be connected directly to each other under the part to reduce the potential of noise
problems.
AIN1L, AIN1R, AIN2L, and AIN2R Pins
AIN1L, AIN1R, AIN2L, and AIN2R are single-ended inputs. AIN1L and AIN1R can also be used as a monaural
differential input. The anti-aliasing low-pass filters are integrated on these inputs to remove the out-of-band noise
from the audio. If the performance of these filters is not good enough for an application, appropriate external
anti-aliasing filters are needed. The passive RC filter (100 Ω and 0.01 μF to 1 kΩ and 1000 pF) is used in
general. Any pins that are not used in an application should be left open. Do not select open pins through
register settings.
AOL, AOR, PGINL, and PGINR Pins
When AIN1L, AIN1R, AIN2L, and AIN2R pins are used as microphone inputs with high gain, AOL and AOR may
have a large dc offset. It is recommended to locate a dc-blocking capacitor (1- to 10-μF capacitor) between
AOL/AOR and PGINL/PGINR. If an application is not affected by dc offset, the PCM1870 does not need the
capacitors.
VCOM Pin
1-μF to 4.7-μF capacitor is recommended between VCOM and AGND to ensure low source impedance for the
ADC common voltage. This capacitor should be located as close as possible to the VCOM pin to reduce dynamic
errors on the ADC common voltage.
BCK (Master Mode) and DOUT Pins
BCK in the master mode and DOUT have adequate load drive capability, but if the BCK and DOUT lines are
long, locating a buffer near the PCM1870 and minimizing load capacitance is recommended in order to minimize
crosstalk between digital and analog circuits, maximize the dynamic performance of the ADC, and reduce power
consumption.
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SLAS544A–MAY 2007–REVISED SEPTEMBER 2007
Changes from Original (May 2007) to Revision A ........................................................................................................... Page
•
•
•
•
•
Added new package in FEATURES section.......................................................................................................................... 1
Added new package in DESCRIPTION section .................................................................................................................... 1
Added pinout for YZF package.............................................................................................................................................. 5
Inserted column in TERMINAL FUNCTIONS table for terminal numbers of YZF package................................................... 5
Added pin numbers for YZF package to connection diagram ............................................................................................. 43
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM1870RHFR
PCM1870RHFT
ACTIVE
ACTIVE
VQFN
VQFN
RHF
RHF
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
1870
1870
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM1870RHFR
PCM1870RHFT
VQFN
VQFN
RHF
RHF
24
24
3000
250
330.0
180.0
12.4
12.4
4.3
4.3
5.3
5.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
PCM1870RHFR
PCM1870RHFT
VQFN
VQFN
RHF
RHF
24
24
3000
250
356.0
210.0
356.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RHF0024A
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
0.5
0.3
5.1
4.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.65 0.1
2X 2
(0.1) TYP
12
EXPOSED
8
THERMAL PAD
20X 0.5
7
13
3.65 0.1
2X
3
25
SYMM
SEE TERMINAL
DETAIL
19
1
0.30
0.18
24X
0.1
C B A
PIN 1 ID
(OPTIONAL)
24
20
SYMM
0.05
0.5
0.3
24X
4219064 /A 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHF0024A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.65)
SYMM
20
24
24X (0.6)
1
19
24X (0.24)
(3.65)
(1.575)
20X (0.5)
25
SYMM
(4.8)
(0.62)
TYP
(R0.05)
TYP
13
7
(
0.2) TYP
VIA
8
12
(1.025)
TYP
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219064 /A 04/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHF0024A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
6X (1.17)
(0.685) TYP
20
24
24X (0.6)
1
19
24X (0.24)
(1.24)
TYP
20X (0.5)
SYMM
(4.8)
25
6X (1.04)
13
(R0.05) TYP
7
METAL
TYP
12
8
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219064 /A 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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