PCM1808PW [TI]
具有单端输入的 99dB SNR 立体声 ADC | PW | 14 | -40 to 85;
| 型号： | PCM1808PW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有单端输入的 99dB SNR 立体声 ADC | PW | 14 | -40 to 85 光电二极管 转换器 |
| 文件： | 总31页 (文件大小：608K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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PCM1808
SLES177B –APRIL 2006–REVISED AUGUST 2015
PCM1808 Single-Ended, Analog-Input 24-Bit, 96-kHz Stereo ADC
1 Features
2 Applications
1
•
•
•
24-Bit Delta-Sigma Stereo A/D Converter (ADC)
Single-Ended Voltage Input: 3 Vp-p
High Performance:
•
•
•
•
•
•
•
DVD Recorder
Digital TV
AV Amplifier or Receiver
MD Player
–
–
–
THD+N: –93 dB (Typical)
SNR: 99 dB (Typical)
CD Recorder
Multitrack Receiver
Electric Musical Instrument
Dynamic Range: 99 dB (Typical)
•
•
Oversampling Decimation Filter:
–
–
–
–
Oversampling Frequency: ×64
Pass-Band Ripple: ±0.05 dB
3 Description
The PCM1808 device is a high-performance, low-
cost, single-chip, stereo analog-to-digital converter
with single-ended analog voltage input. The
PCM1808 device uses a delta-sigma modulator with
Stop-Band Attenuation: –65 dB
On-Chip High-Pass Filter: 0.91 Hz (48 kHz)
Flexible PCM Audio Interface
64-times oversampling and includes
a
digital
–
–
Master- or Slave-Mode Selectable
Data Formats: 24-Bit I2S, 24-Bit Left-Justified
decimation filter and high-pass filter that removes the
dc component of the input signal. For various
applications, the PCM1808 device supports master
and slave mode and two data formats in serial audio
interface.
•
•
•
•
•
•
Power Down and Reset by Halting System Clock
Analog Antialias LPF Included
Sampling Rate: 8 kHz–96 kHz
System Clock: 256 fS, 384 fS, 512 fS
Resolution: 24 Bits
The PCM1808 device supports the power-down and
reset functions by means of halting the system clock.
The PCM1808 device is suitable for wide variety of
cost-sensitive consumer applications requiring good
performance and operation with a 5-V analog supply
and 3.3-V digital supply. Fabrication of the PCM1808
device uses a highly advanced CMOS process. The
device is available in
package.
Dual Power Supplies:
–
–
5-V for Analog
3.3-V for Digital
•
Package: 14-Pin TSSOP
a small, 14-pin TSSOP
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
PCM1808
TSSOP (14)
4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
PCM1808 Block Diagram
Antialias
LPF
Delta-Sigma
Modulator
BCK
VIN
L
Serial
Interface
LRCK
DOUT
FMT
1 / 64
Decimation
Filter
With
High-Pass
Filter
VREF
Reference
Mode/
Format
Control
MD1
MD0
Antialias
LPF
Delta-Sigma
Modulator
VINR
1
Power Supply
Clock and Timing Control
SCKI
VCC
AGND DGND
VDD
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM1808
SLES177B –APRIL 2006–REVISED AUGUST 2015
www.ti.com
Table of Contents
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 19
Power Supply Recommendations...................... 21
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 7
6.7 Typical Characteristics............................................ 11
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1 Community Resources.......................................... 23
11.2 Trademarks........................................................... 23
11.3 Electrostatic Discharge Caution............................ 23
11.4 Glossary................................................................ 23
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
Changes from Revision A (August 2006) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
2
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SLES177B –APRIL 2006–REVISED AUGUST 2015
5 Pin Configuration and Functions
14-Pin TSSOP
PW Package
Top View
VREF
AGND
VCC
1
2
3
4
5
6
7
VIN
VIN
R
L
14
13
12
11
10
9
FMT
MD1
MD0
DOUT
BCK
VDD
DGND
SCKI
LRCK
8
P0032-02
Pin Functions
PIN
I/O
DESCRIPTION
NAME
AGND
BCK
PIN
2
—
I/O
—
O
I
Analog GND
(1)
8
Audio-data bit-clock input or output
Digital GND
DGND
DOUT
FMT
5
9
Audio-data digital output
(2)
12
7
Audio-interface format select
(1)
LRCK
MD0
I/O
I
Audio-data latch-enable input or output
(2)
10
11
6
Audio-interface mode select 0
(2)
MD1
I
Audio-interface mode select 1
(3)
SCKI
VCC
I
System clock input; 256 fS, 384 fS or 512 fS
Analog power supply, 5-V
3
—
—
I
VDD
4
Digital power supply, 3.3-V
Analog input, L-channel
VINL
13
14
1
VINR
I
Analog input, R-channel
VREF
—
Reference-voltage decoupling (= 0.5 VCC)
(1) Schmitt-trigger input with internal pulldown (50-kΩ, typical)
(2) Schmitt-trigger input with internal pulldown (50-kΩ, typical), 5-V tolerant
(3) Schmitt-trigger input, 5-V tolerant
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SLES177B –APRIL 2006–REVISED AUGUST 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
MAX
UNIT
VCC
VDD
Analog supply voltage
Digital supply voltage
6.5
V
V
V
V
V
4
±0.1
Ground voltage differences
AGND, DGND
LRCK, BCK, DOUT
SCKI, MD0, MD1, FMT
–0.3
–0.3
(VDD + 0.3 V) < 4
6.5
Digital input voltage
Analog input voltage
VINL, VINR,
VREF
–0.3 (VCC + 0.3 V) < 6.5
V
Input current (any pins except supplies)
Junction temperature
±10
150
mA
°C
TJ
Tstg
Storage temperature
–55
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
VCC
VDD
Analog supply voltage (see Power Supply Recommendations)
4.5
2.7
5
5.5
3.6
3
V
Digital supply voltage
3.3
V
Analog input voltage, full scale (–0 dB)
High input logic level
VCC = 5 V
Vp-p
VDC
VDC
VDC
VDC
(1)
VIH
2
0
2
0
VDD
0.8
5.5
0.8
(1)
VIL
VIH
VIL
Low input logic level
(2) (3)
(2) (3)
High input logic level
Low input logic level
Digital input logic family
TTL compatible
Digital input clock frequency, system clock
Digital input clock frequency, sampling clock
Digital output load capacitance
Operating ambient temperature range
Junction temperature
2.048
8
49.152
96
MHz
kHz
pF
20
TA
TJ
–40
85
°C
150
°C
(1) Pins 7, 8: LRCK, BCK (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, in slave mode)
(2) Pin 6: SCKI (Schmitt-trigger input, 5-V tolerant)
(3) Pins 10–12: MD0, MD1, FMT (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant)
4
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SLES177B –APRIL 2006–REVISED AUGUST 2015
6.4 Thermal Information
PCM1808
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
89.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
25.6
30.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.4
ψJB
29.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted
PARAMETER
Resolution
DATA FORMAT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
24
Bits
Audio data interface format
Audio data bit length
Audio data format
I2S, left-justified
24
Bits
kHz
MHz
MSB-first, 2s complement
fS
Sampling frequency
8
2.048
3.072
4.096
48
12.288
18.432
24.576
96
24.576
36.864
49.152
256 fS
384 fS
512 fS
System clock frequency
INPUT LOGIC
(1)
VIH
VIL
VIH
VIL
IIH
High input logic level
2
0
2
0
VDD
0.8
VDC
VDC
VDC
VDC
µA
(1)
Low input logic level
High input logic level
Low input logic level
High input logic current
Low input logic current
High input logic current
Low input logic current
(2) (3)
(2) (3)
5.5
0.8
(2)
VIN = VDD
VIN = 0 V
VIN = VDD
VIN = 0 V
±10
±10
100
±10
(2)
IIL
IIH
IIL
µA
(1) (3)
(1) (3)
65
µA
µA
OUTPUT LOGIC
(4)
VOH
VOL
High output logic level
Low output logic level
IOUT = –4 mA
IOUT = 4 mA
2.8
VDC
VDC
(4)
0.5
DC ACCURACY
Gain mismatch, channel-to-channel
Gain error
% of
FSR
±1
±3
±3
±6
% of
FSR
(1) Pins 7, 8: LRCK, BCK (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, in slave mode)
(2) Pin 6: SCKI (Schmitt-trigger input, 5-V tolerant)
(3) Pins 10–12: MD0, MD1, FMT (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant)
(4) Pins 7–9: LRCK, BCK (in master mode), DOUT
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Electrical Characteristics (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(5)
DYNAMIC PERFORMANCE
VIN = –0.5 dB, fS = 48 kHz
–93
–87
–37
–39
99
–87
(6)
VIN = –0.5 dB, fS = 96 kHz
THD+N
Total harmonic distortion + noise
dB
VIN = –60 dB, fS = 48 kHz
(6)
VIN = –60 dB, fS = 96 kHz
fS = 48 kHz, A-weighted
95
95
93
Dynamic range
dBVDC
dB
(6)
fS = 96 kHz, A-weighted
101
99
fS = 48 kHz, A-weighted
S/N
Signal-to-noise ratio
Channel separation
(6)
fS = 96 kHz, A-weighted
101
97
fS = 48 kHz
dB
(6)
fS = 96 kHz
91
ANALOG INPUT
Input voltage
0.6 VCC
0.5 VCC
60
Vp-p
V
Center voltage (VREF
)
Input impedance
kΩ
Antialiasing filter frequency response
DIGITAL FILTER PERFORMANCE
–3 dB
1.3
MHz
Pass band
0.454 fS
±0.05
Hz
Hz
dB
dB
Stop band
0.583 fS
–65
Pass-band ripple
Stop-band attenuation
Delay time
17.4 / fS
0.019 fS
/
HPF frequency response
–3 dB
1000
POWER SUPPLY REQUIREMENTS
(6)
fS = 48 kHz, 96 kHz
8.6
1
11
8
mA
μA
(7)
ICC
Analog supply current
(8)
Powered down
fS = 48 kHz
5.9
10.2
150
62
mA
mA
µA
(7)
(6)
IDD
Digital supply current
fS = 96 kHz
(8)
Powered down
fS = 48 kHz
81
mW
µW
(7)
(6)
Power dissipation
fS = 96 kHz
77
(8)
Powered down
500
(5) Testing of analog performance specifications uses an audio measurement system by Audio Precision™ with 400-Hz HPF and 20-kHz
LPF in RMS mode.
(6) fS = 96 kHz, system clock = 256 fS.
(7) Minimum load on LRCK (pin 7), BCK (pin 8), DOUT (pin 9)
(8) Power-down and reset functions enabled by halting SCKI, BCK, LRCK.
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6.6 Timing Requirements
MIN
NOM
MAX UNIT
SYSTEM CLOCK TIMING
tw(SCKH)
tw(SCKL)
System clock pulse duration, HIGH
System clock pulse duration, LOW
System clock duty cycle
8
8
ns
ns
40%
60%
CLOCK-HALT POWER-DOWN AND RESET TIMING
t(CKR)
t(RST)
t(REL)
Delay time from SCKI halt to internal reset
Delay time from SCKI resume to reset release
Delay time from reset release to DOUT output
4
µs
1024 SCKI
µs
µs
8960 / fS
AUDIO DATA INTERFACE TIMING (Slave Mode: LRCK and BCK Work as Inputs)(1)
t(BCKP)
t(BCKH)
t(BCKL)
t(LRSU)
t(LRHD)
t(LRCP)
t(CKDO)
t(LRDO)
tr
BCK period
1 / (64 fS)
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
BCK pulse duration, HIGH
BCK pulse duration, LOW
LRCK setup time to BCK rising edge
LRCK hold time to BCK rising edge
LRCH period
1.5 × t(SCKI)
1.5 × t(SCKI)
50
10
10
Delay time, BCK falling edge to DOUT valid
Delay time, LRCK edge to DOUT valid
Rise time of all signals
–10
–10
40
40
20
20
tf
Fall time of all signals
AUDIO DATA INTERFACE TIMING (Master Mode: LRCK and BCK Work as Outputs)(2)
t(BCKP)
t(BCKH)
t(BCKL)
t(CKLR)
t(LRCP)
t(CKDO)
t(LRDO)
tr
BCK period
150 1 / (64 fS)
2000
1200
1200
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BCK pulse duration, HIGH
BCK pulse duration, LOW
Delay time, BCK falling edge to LRCK valid
LRCK period
65
65
–10
10
–10
–10
1 / fS
125
20
Delay time, BCK falling edge to DOUT valid
Delay time, LRCK edge to DOUT valid
Rise time of all signals
20
20
tf
Fall time of all signals
20
AUDIO CLOCK INTERFACE TIMING (Master Mode: BCK Work as Outputs)(3)
t(SCKBCK) Delay time, SCKI rising edge to BCK edge
5
30
ns
(1) Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Rise and fall times are from 10% to 90% of the input-
output signal swing. Load capacitance of DOUT is 20 pF. t(SCKI) is the SCKI period.
(2) Timing measurement reference level is 0.5 VDD. Rise and fall times are from 10% to 90% of the input-output signal swing. Load
capacitance of all signals is 20 pF.
(3) Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of BCK is 20 pF. This timing applies
when SCKI frequency is less than 25 MHz.
t
t
w(SCKL)
w(SCKH)
SCKI
2 V
SCKI
0.8 V
Figure 1. System Clock Timing
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2.6 V
2.2 V
1.8 V
VDD
Reset
Reset Release
Operation
Internal
Reset
1024 System Clocks
8960/fS
System
Clock
DOUT
Zero Data
Normal Data
Fade-In Complete
Fade-In Start
DOUT
BPZ
(Contents)
48/fIN or 48/fS
Figure 2. Power-On Timing
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SCKI Halt
SCKI Resume
Fixed to Low or High
SCKI
t(CKR)
Reset: t(RST)
Clock-Halt Reset
Reset Release: t
(REL)
Internal
Reset
Operation
Operation
DOUT
Normal Data
Zero Data
Normal Data
Fade-In Complete
Fade-In Start
Normal Data
DOUT
BPZ
(Contents)
48/fIN or 48/fS
Figure 3. Clock-Halt Power-Down and Reset Timing
t
(LRCP)
1.4 V
LRCK
t
t
(BCKL)
(LRSU)
t
(LRHD)
t
(BCKH)
1.4 V
BCK
t
t
(LRDO)
t
(CKDO)
(BCKP)
DOUT
Figure 4. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs)
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t(LRCP)
LRCK
0.5 VDD
t(BCKL)
t(BCKH)
t(CKLR)
0.5 VDD
BCK
t(CKDO)
t(
LRDO)
t(BCKP)
10
DOUT
0.5 VDD
Figure 5. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs)
1.4 V
SCKI
t(SCKBCK)
t(SCKBCK)
0.5 VDD
BCK
Figure 6. Audio Clock Interface Timing (Master Mode: BCK Works as Output)
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6.7 Typical Characteristics
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted.
0
−10
−20
−30
50
0
−40
−50
−60
−70
−80
−90
−50
−100
−150
−200
−100
0.00
0.25
0.50
0.75
1.00
0
8
16
24
32
Frequency [×fS]
Normalized Frequency [×fS]
G002
G001
Figure 8. Decimation-Filter Frequency Response
Stop-Band Attenuation Characteristics
Figure 7. Decimation-Filter Frequency Response
Overall Characteristics
0.2
0
−1
0.0
−0.2
−0.4
−2
−3
–4.13 dB at 0.5 fS
−4
−5
−6
−0.6
−0.8
−1.0
−7
−8
−9
−10
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
Normalized Frequency [× fS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Normalized Frequency [× f
]
S
]
G004
G003
Figure 10. Decimation-Filter Frequency Response
Transition-Band Characteristics
Figure 9. Decimation-Filter Frequency Response
Pass-Band Ripple Characteristics
0
0.2
−10
−20
−30
−40
−50
−60
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
−70
−80
−90
−100
0.0
0.1
0.2
0.3
0.4
0
1
2
3
4
Normalized Frequency [× f /1000]
S
Normalized Frequency [× f /1000]
S
G005
G006
Figure 11. High-Pass Filter Frequency Response
HPF Stop-Band Characteristics
Figure 12. High-Pass Filter Frequency Response
HPF Stop-Band Characteristics
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Typical Characteristics (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted.
105
−87
−88
−89
104
103
102
101
−90
−91
100
99
Dynamic Range
−92
−93
−94
−95
−96
−97
SNR
98
97
96
95
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
G007
G008
Figure 13. THD+N vs Temperature
Figure 14. Dynamic Range and SNR vs Temperature
105
−87
−88
−89
−90
−91
−92
−93
−94
−95
−96
−97
104
103
102
101
100
99
Dynamic Range
SNR
98
97
96
95
4.25
4.50
4.75
5.00
5.25
5.50
5.75
4.25
4.50
4.75
5.00
5.25
5.50
5.75
VCC – Supply Voltage – V
VCC – Supply Voltage – V
G010
G009
Figure 16. Dynamic Range and SNR vs Supply Voltage
Figure 15. THD+N vs Supply Voltage
105
−87
104
−88
−89
−90
−91
−92
−93
−94
−95
−96
−97
Dynamic Range
▲
SNR
103
102
101
100
99
▲
▲
98
(1)
(2)
(3)
(1)
(2)
(3)
System Clock = 384 f
System Clock = 512 f
System Clock = 256 f
System Clock = 384 f
S
S
S
S
97
System Clock = 512 f
S
System Clock = 256 f
S
96
95
(1)
(3)
(1)
(3)
96
(2)
(2)
44.1
96
44.1
48
fSAMPLECondition − kHz
48
fSAMPLECondition − kHz
G012
G011
Figure 17. THD+N vs fSAMPLE Condition
Figure 18. Dynamic Range and SNR vs fSAMPLE Condition
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Typical Characteristics (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless
otherwise noted.
0
0
Input Level = −0.5 dB
Data Points = 8192
Input Level = −60 dB
Data Points = 8192
−20
−20
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
−140
−140
0
5
10
f − Frequency − kHz
15
20
0
5
10
f − Frequency − kHz
15
20
G013
G014
Figure 19. Output Spectrum (–0.5 dB, N = 8192)
Figure 20. Output Spectrum (–60 dB, N = 8192)
15
10
5
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
ICC
IDD
(1)
System Clock = 384 f
S
(2)
System Clock = 512 f
S
(3)
System Clock = 256 f
S
0
(1)
(2)
(3)
96
44.1
48
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
fSAMPLE Condition − kHz
G016
Signal Level − dB
G015
Figure 22. Supply Current vs fSAMPLE Condition
Figure 21. Output Spectrum
THD+N vs Signal Level
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7 Detailed Description
7.1 Overview
The PCM1808 is high-performance, low-cost, single-chip, stereo analog-to-digital converter with single-ended
analog voltage input. The PCM1808 uses a delta-sigma modulator with 64-times oversampling and includes a
digital decimation filter and high-pass filter that removes the dc component of the input signal. For various
applications, the PCM1808 supports master and slave mode and two data formats in serial audio interface up to
96-kHz sampling. These features are controlled through hardware by pulling pins high or low with resistors or a
controller GPIO. The PCM1808 also supports a power-down and reset function by means of halting the system
clock.
7.2 Functional Block Diagram
Antialias
LPF
Delta-Sigma
Modulator
BCK
VIN
L
Serial
Interface
LRCK
DOUT
FMT
1 / 64
Decimation
Filter
With
High-Pass
Filter
VREF
Reference
Mode/
Format
Control
MD1
MD0
Antialias
LPF
Delta-Sigma
Modulator
VINR
1
Power Supply
Clock and Timing Control
SCKI
VCC
AGND DGND
VDD
7.3 Feature Description
7.3.1 Hardware Control
Pins FMT, MD0, and MD1 allow the device to be controlled by either pullup or pulldown resistors as well as
GPIO from a digital IC. These controls allow the option of switching between I2S or left-justified, and in which
interface mode the device operates.
7.3.2 System Clock
The PCM1808 device supports 256 fS, 384 fS, and 512 fS as system clock, where fS is the audio sampling
frequency. The system clock input must be on SCKI (pin 6).
The PCM1808 device has a system-clock detection circuit which automatically senses if the system-clock
operation is at 256 fS, 384 fS, or 512 fS in slave mode. In master mode, control of the system clock frequency
must be through the serial control port, which uses MD1 (pin 11) and MD0 (pin 10). An internal circuit
automatically divides down the system clock to generate frequencies of 128 fS and 64 fS, which operate the
digital filter and the delta-sigma modulator, respectively.
Table 1 shows some typical relationships between sampling frequency and system clock frequency, and Figure 1
shows system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SAMPLING FREQUENCY (kHz)
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
256 fS
2.048
384 fS
3.072
512 fS
4.096
8
16
4.096
6.144
8.192
32
8.192
12.288
16.9344
16.384
22.5792
44.1
11.2896
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Feature Description (continued)
Table 1. Sampling Frequency and System Clock Frequency (continued)
SAMPLING FREQUENCY (kHz)
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
384 fS
256 fS
12.288
16.384
22.5792
24.576
512 fS
24.576
32.768
45.1584
49.152
48
64
18.432
24.576
33.8688
36.864
88.2
96
7.3.3 Synchronization With Digital Audio System
In slave mode, the PCM1808 device operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6).
The PCM1808 device does not require a specific phase relationship between LRCK and SCKI, but does require
the synchronization of LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48
BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1 / fS
and digital output goes to zero data (BPZ code) until resynchronization between LRCK and SCKI occurs.
In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization
does not occur, and the previously described digital output control and discontinuity do not occur.
Figure 23 illustrates the digital output response for loss of synchronization and resynchronization. During
undefined data, the PCM1808 device can generate some noise in the audio signal. Also, the transition of normal
data to undefined data creates a discontinuity in the digital output data, which can generate some noise in the
audio signal. The digital output is valid after resynchronization completes and the time of 32 / fS has elapsed.
Because the fade-in operation is performed, it takes additional time of 48 / fin or 48 / fS to obtain the level
corresponding to the analog input signal. In the case of loss of synchronization during the fade-in or fade-out
operation, the operation stops and DOUT (pin 9) goes to zero data immediately. The fade-in operation resumes
from mute after the time of 32 / fS following resynchronization.
Resynchronization
Resynchronization
Synchronization Lost
Synchronization Lost
State of
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Synchronization
1/fS
32/f
S
Undefined
Data
DOUT
Normal Data
Zero Data
Normal Data
Zero Data
Normal Data
Fade-In Complete
Fade-In Start
Fade-In Restart
Normal Data
DOUT
BPZ
(Contents)
32/fS
48/fin or 48/fS
48/fin or 48/fS
Figure 23. ADC Digital Output for Loss of Synchronization and Resynchronization
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7.3.4 Power On
The PCM1808 device has an internal power-on-reset circuit, and initialization (reset) occurs automatically when
the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts
after VDD > 2.2 V (typical), the PCM1808 device stays in the reset state and the digital output remains zero. After
release of the reset state, 8960 / fS seconds must pass before the digital output becomes valid. Because of the
performing of the fade-in operation, it takes additional time of 48 / fin or 48 / fS to obtain the data corresponding to
the analog input signal. Figure 2 illustrates the power-on timing and the digital output.
7.3.5 Serial Audio Data Interface
The PCM1808 device interfaces the audio system through LRCK (pin 7), BCK (pin 8), and DOUT (pin 9).
7.3.5.1 Interface Mode
MD1 (pin 11) and MD0 (pin 10) select master mode and slave mode as interface modes, both of which the
PCM1808 device supports.Table 2 shows the interface-mode selections. It is necessary to set MD1 and MD0
prior to power on.
In master mode, the PCM1808 device provides the timing of serial audio data communications between the
PCM1808 device and the digital audio processor or external circuit. While in slave mode, the PCM1808 device
receives the timing for data transfer from an external controller.
Table 2. Interface Modes
MD1 (PIN 11)
Low
MD0 (PIN 10)
Low
INTERFACE MODE
Slave mode (256 fS, 384 fS, 512 fS autodetection)
Master mode (512 fS)
Low
High
High
Low
Master mode (384 fS)
High
High
Master mode (256 fS)
7.3.5.1.1 Master Mode
In master mode, BCK and LRCK work as output pins, timing which from the clock circuit of the PCM1808 device
controls these pins. The frequency of BCK is constant at 64 BCK/frame.
7.3.5.1.2 Slave Mode
In slave mode, BCK and LRCK work as input pins. The PCM1808 device accepts 64-BCK/frame or 48-
BCK/frame format (only for a 384-fS system clock), not 32-BCK/frame format.
7.3.5.2 Data Format
Table 3. Data Format
FORMAT NO.
FMT (Pin 12)
Low
FORMAT
0
1
I2S, 24-bit
High
Left-justified, 24-bit
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Format 0: FMT = LOW
24-Bit, MSB-First, I2S
Left-Channel
Right-Channel
LRCK
BCK
DOUT
1
2
3
22 23 24
LSB
1
2
3
22 23 24
LSB
MSB
MSB
Format 1: FMT = HIGH
24-Bit, MSB-First, Left-Justified
Left-Channel
Right-Channel
LRCK
BCK
DOUT
1
1
2
3
22 23 24
LSB
1
2
3
22 23 24
LSB
MSB
MSB
Figure 24. Audio Data Format (LRCK and BCK Work as Inputs in Slave Mode
and as Outputs in Master Mode)
7.3.5.3 Interface Timing
Figure 4 and Figure 5 illustrate the interface timing in slave mode and master mode, respectively.
7.4 Device Functional Modes
7.4.1 Fade-In and Fade-Out Functions
The PCM1808 device has fade-in and fade-out functions on DOUT (pin 9) to avoid pop noise, and the functions
come into operation in some cases as described in several following sections. Performance of the level changes
from 0 dB to mute or mute to 0 dB employs calculated pseudo S-shaped characteristics with zero-cross
detection. Because of the zero-cross detection, the time needed for the fade-in and fade-out depends on the
analog input frequency (fin). It takes 48 / fin to complete the processing. If there is no zero-cross during 8192 / fS,
a forced DOUT fade-in or fade-out occurs during 48 / fS (TIME OUT). Figure 25 illustrates the fade-in and fade-
out operation processing.
Fade-In Complete
Fade-In Start
Fade-Out Start
Fade-Out Complete
DOUT
BPZ
(Contents)
48/fin or 48/fS
48/fin or 48/fS
Figure 25. Fade-In and Fade-Out Operations
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Device Functional Modes (continued)
7.4.2 Clock-Halt Power-Down and Reset Function
The PCM1808 device has a power-down and reset function. Halting SCKI (pin 6) in both master and slave
modes triggers this function. The function is available any time after power on. Reset and power down occur
automatically 4 μs (minimum) after the halt of SCKI. During assertion of the clock-halt reset, the PCM1808
device stays in the reset and power-down mode, with DOUT (pin 9) forced to zero. Release the reset and power-
down mode requires the supply of SCKI. The digital output is valid after release of the reset state and elapse of
the time of 1024 SCKI + 8960 / fS. Performing the fade-in operation takes additional time of 48 / fin or 48 / fS to
attain the level corresponding to the analog input signal. Figure 3 illustrates the clock-halt reset timing.
To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) must synchronize with SCKI within 4480
/ fS after the resumption of SCKI. If it takes more than 4480 / fS for BCK and LRCK to synchronize with SCKI,
mask SCKI until it again achieves synchronization, taking care of glitch and jitter. See the typical circuit
connection diagram, Figure 26.
To avoid ADC performance degradation, assertion of the clock-halt reset is necessary when changing system
clock SCKI or the audio interface clocks BCK and LRCK (sampling rate fS) on the fly.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The PCM1808 device is suitable for wide variety of cost-sensitive consumer applications requiring good
performance and operation with a 5-V analog supply and 3.3-V digital supply.
8.2 Typical Application
PCM1808
(1)
(5)
(3)
C5
C1
+
+
+
R-ch IN
L-ch IN
1
2
3
4
5
6
7
VREF
AGND
VCC
VIN
R
14
13
12
11
10
9
(1)
C2
VIN
L
(2)
C4
+
5 V
FMT
MD1
4
µs (min)
High/Low
Pin
VDD
3.3 V
+
(2)
C3
Setting
DGND
SCKI
LRCK
MD0
Mask
DOUT
BCK
X1(4)
8
PLL170x
DSP
or
Audio
Processor
(1) C1, C2: A 1-μF electrolytic capacitor gives 2.7 Hz (τ = 1 μF × 60 kΩ) cutoff frequency for the input HPF in normal
operation and requires a power-on settling time with a 60-ms time constant in the power-on initialization period.
(2) C3, C4: Bypass capacitors, 0.1-μF ceramic and 10-μF electrolytic, depending on layout and power supply
(3) C5: Recommended capacitors are 0.1-μF ceramic and 10-μF electrolytic.
(4) X1: X1 masks the system clock input when using the clock-halt reset function with external control.
(5) Optional external antialiasing filter could be required, depending on the application.
Figure 26. Typical Circuit Connection Diagram
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 4 as the input parameters.
Table 4. Design Parameters
DESIGN PARAMETER
Analog input voltage range
Output
EXAMPLE VALUE
0 Vp-p to 3 Vp-p
PCM audio data
System clock input frequency
Output sampling frequency
Power supply
2.048 MHz to 49.152 MHz
8 kHz to 96 kHz
3.3 V and 5 V
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8.2.2 Detailed Design Procedure
8.2.2.1 Control Pins
The control pins FMT, MD0, and MD1 should be controlled either by biasing with a 10 kΩ resister to VDD or
GND, or by driving with GPIO from the DSP or audio processor.
8.2.2.2 Master Clock
In this application of the PCM1808 device, a PLL170X series device is used as the master clock source to drive
both the PCM1808 and the DSP or audio processor synchronously. With the addition of the AND gate, the
operation of the PCM1808 device can be halted by control of the MASK bit. A crystal that operates at the
standard audio multiples can also be used.
8.2.2.3 DSP or Audio Processor
In this application, the DSP or audio processor is acting as the audio master, and the PCM1808 is acting as the
audio slave. This means the DSP or audio processor must be able to output audio clocks that the PCM1808 can
use to process audio signals.
8.2.2.4 Input Filters
For the analog input circuit, an ac coupling capacitor should be placed in series with the input. This will remove
the dc component of the input signal. An RC filter can also be implemented to filter out-of-band noise to reduce
aliasing. The equation below can be used to calculate the cutoff frequency of the optional RC filter for the input.
1
fC
=
2pRC
(1)
8.2.3 Application Curve
0
−20
Input Level = −0.5 dB
Data Points = 8192
−40
−60
−80
−100
−120
−140
0
5
10
f − Frequency − kHz
15
20
G013
Figure 27. Output Spectrum
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9 Power Supply Recommendations
The PCM1808 device requires a 5-V nominal supply and a 3.3-V nominal supply. The 5-V supply is for the
analog circuitry powered by the VCC pin. The 3.3-V supply is for the digital circuitry powered by the VDD pin. The
decoupling capacitors for the power supplies should be placed close to the device terminals.
A VCC that varies from the nominal 5 V affects the reference voltage for the input. This has a slight impact on the
data conversion of the device.
10 Layout
10.1 Layout Guidelines
10.1.1 VCC, VDD Pins
Bypass the digital and analog power supply lines to the PCM1808 device to the corresponding ground pins with
both 0.1-μF ceramic and 10-μF electrolytic capacitors as close to the pins as possible to maximize the dynamic
performance of the ADC.
10.1.2 AGND, DGND Pins
To maximize the dynamic performance of the PCM1808 device, there are no internal connections to the analog
and digital grounds. These grounds should have low impedance to avoid digital noise feedback into the analog
ground. They should be connected directly to each other under the PCM1808 device package to reduce potential
noise problems.
10.1.3 VINL, VINR Pins
VINL and VINR are single-ended inputs. These inputs have integrated antialias low-pass filters to remove the
high-frequency noise outside the audio band. If the performance of these filters is not adequate for an
application, the application requires appropriate external antialiasing filters. An appropriate choice would typically
be a passive RC filter in the range of 100 Ω and 0.01 μF to 1 kΩ and 1000 pF.
10.1.4 VREF Pin
To ensure low source impedance of the ADC references, the recommended capacitors between VREF and AGND
are 0.1-μF ceramic and 10-μF electrolytic. These capacitors should be located as close as possible to the VREF
pin to reduce dynamic errors on the ADC references.
10.1.5 DOUT Pin
The DOUT pin has a large load-drive capability, but if the DOUT line is long, a recommended practice is to locate
a buffer near the PCM1808 device and minimize load capacitance to minimize the digital-analog crosstalk and
maximize the dynamic performance of the ADC.
10.1.6 System Clock
The quality of the system clock can influence dynamic performance, as the PCM1808 device operates based on
a system clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time difference
between system clock transition and BCK or LRCK transition in slave mode.
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10.2 Layout Example
It is recommended to place a top layer ground pour for
shielding around PCM1808 and connect to lower main PCB
ground plane by multiple vias
Optional External RC
Antialiasing Circuit
1 μF
10 μF
0.1 μF
1
+
R-ch IN
L-ch IN
14
13
12
11
10
9
VREF
AGND
VCC
VinR
VinL
2
3
4
5
6
7
0.1μF
+
10 μF
5 V
1 μF
FMT
MD1
MD0
DOUT
BCK
Make sure to have
ground pour separating
the left- and right-
PCM1808
3.3 V
VDD
+
channel traces to help
prevent crosstalk.
0.1μF
DGND
SCK
10μF
Part configuration
pullups or pulldowns
8
LRCK
Clock Signals to
DSP or Audio
Processor
Make sure to have
ground pour separating
the clock signals from
the surrounding traces.
Top Layer Ground Pour
Top Layer Signal Traces
Via to Bottom Ground Plane
Pad to Top Layer Ground Pour
Figure 28. PCM1808 Layout Example
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
Audio Precision is a trademark of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCM1808PW
PCM1808PWG4
PCM1808PWR
PCM1808PWRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
14
14
14
14
90
90
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PCM1808
NIPDAU
NIPDAU
NIPDAU
PCM1808
PCM1808
PCM1808
2000 RoHS & Green
2000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF PCM1808 :
Automotive: PCM1808-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCM1808PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
PCM1808PWR
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
PCM1808PW
PCM1808PW
PW
PW
PW
PW
TSSOP
TSSOP
TSSOP
TSSOP
14
14
14
14
90
90
90
90
530
530
530
530
10.2
10.2
10.2
10.2
3600
3600
3600
3600
3.5
3.5
3.5
3.5
PCM1808PWG4
PCM1808PWG4
Pack Materials-Page 3
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