PCA9554APWT [TI]
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| 型号： | PCA9554APWT |
| 厂家： | 
TEXAS INSTRUMENTS |
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PCA9554A
REMOTE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
www.ti.com
SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
FEATURES
•
•
•
I2C to Parallel Port Expander
•
Power-Up With All Channels Configured as
Inputs
Open-Drain Active-Low Interrupt Output
•
•
No Glitch on Power-Up
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
•
•
•
5-V Tolerant I/Os
400-kHz Fast I2C Bus
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Three Hardware Address Pins Allow up to
Eight Devices on the I2C/SMBus
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
•
•
•
Input/Output Configuration Register
Polarity Inversion Register
Internal Power-On Reset
1000-V Charged-Device Model (C101)
DB, DBQ, DGV, DW,
OR PW PACKAGE
(TOP VIEW)
RGV PACKAGE
(TOP VIEW)
RGT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
V
CC
16 15 14 13
16 15 14 13
SCL
SDA
SCL
INT
P7
P6
P5
1
12
11
A2
P0
P1
1
2
3
4
12
A2
P0
P1
P2
SCL
INT
P7
A2
P0
P1
P2
2
3
4
INT
11
10
9
10 P7
P6
9
P2
P6
5
6
7
8
P3
5
6
7
8
GND
P4
DESCRIPTION/ORDERING INFORMATION
This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. It
provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial
clock (SCL), serial data (SDA)].
The PCA9554A consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity
Inversion (active high or active low) registers. At power-on, the I/Os are configured as inputs with a weak pull up
to VCC. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The
polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by
the system master.
The system master can reset the PCA9554A in the event of a timeout or other improper operation by utilizing
the power-on reset feature which puts the registers in their default state and initializes the I2C/SMBus state
machine.
The PCA9554A open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the PCA9554A can remain a simple slave device.
The device's outputs (latched) have high-current drive capability for directly driving LEDs and low current
consumption.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2006–2007, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9554A
REMOTE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
www.ti.com
SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address and allow up to eight
devices to share the same I2C bus or SMBus.
The PCA9554A is pin-to-pin and I2C address compatible with the PCF8574A. However, software changes are
required, due to the enhancements in the PCA9554A over the PCF8574A.
The PCA9554A and PCA9554 are identical except for their fixed I2C address. This allows for up to sixteen of
these devices (eight of each) on the same I2C/SMBus.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
PCA9554ARGTR
PCA9554ARGVR
PCA9554ADBQ
TOP-SIDE MARKING
PREVIEW
QFN – RGT
QFN – RGV
Reel of 3000
Reel of 2500
Tube of 75
PREVIEW
QSOP – DBQ
SOIC – DW
PD554A
Reel of 2500
Tube of 40
PCA9554ADBQR
PCA9554ADW
PREVIEW
Reel of 2000
PCA9554ADWR
PCA9554ADB
–40°C to 85°C
Tube of 80
SSOP – DB
PCA9554ADBG4
PCA9554ADBR
PD554A
Reel of 2000
Tube of 90
PCA9554APW
TSSOP – PW
TVSOP – DGV
PD554A
PD554A
Reel of 2000
Reel of 2000
Reel of 125
PCA9554APWR
PCA9554ADGVR
PCA9554ADGV
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
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PCA9554A
REMOTE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
www.ti.com
SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
TERMINAL FUNCTIONS
NO.
QSOP (DBQ)
SOIC (DW),
SSOP (DB),
NAME
DESCRIPTION
QFN (RGT) AND
QFN (RGV)
TSSOP (PW), AND
TVSOP (DGV)
1
2
15
16
1
A0
A1
Address input. Connect directly to VCC or ground.
Address input. Connect directly to VCC or ground.
Address input. Connect directly to VCC or ground.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
Ground
3
A2
4
2
P0
5
3
P1
6
4
P2
7
5
P3
8
6
GND
P4
9
7
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
P-port input/output. Push-pull design structure.
Interrupt output. Connect to VCC through a pullup resistor.
Serial clock bus. Connect to VCC through a pullup resistor.
Serial data bus. Connect to VCC through a pullup resistor.
Supply voltage
10
11
12
13
14
15
16
8
P5
9
P6
10
11
12
13
14
P7
INT
SCL
SDA
VCC
FUNCTIONAL BLOCK DIAGRAM
13
Interrupt
Logic
LP Filter
INT
1
A0
2
A1
3
A2
14
P7−P0
SCL
2
Input
Filter
I C Bus
Control
Shift
Register
I/O
Port
15
8 Bits
SDA
Write Pulse
Read Pulse
16
V
Power-On
Reset
CC
8
GND
A. Pin numbers shown are for the DB, DBQ, DGV, DW, N, or PW package.
B. All I/Os are set to inputs at reset.
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PCA9554A
REMOTE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
www.ti.com
SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
Simplified Schematic of P0 to P7
Data From
Shift Register
Configuration
Output Port
Register Data
Register
V
CC
Data From
Shift Register
Q1
D
Q
FF
K
100 kW
Write Configuration
Pulse
D
C
Q
C
Q
FF
P0 to P7
GND
Write Pulse
Q
K
Q2
Output Port
Register
Input Port
Register
Input Port
Register Data
D
Q
FF
Read Pulse
C
K
Q
INT
Data From
Shift Register
Polarity
Register Data
D
C
Q
FF
Write Polarity
Pulse
Q
K
Polarity
Inversion
Register
A. At power-on reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high impedance input with a
weak pullup (100 kΩ typ) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address
byte is sent, MSB first, including the data direction bit /W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device
must not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 2).
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PCA9554A
REMOTE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
www.ti.com
SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 1. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 2. Bit Transfer
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PCA9554A
REMOTE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
www.ti.com
SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
1
2
8
9
Master
S
Start
Clock Pulse for
Condition
Acknowledgment
Figure 3. Acknowledgment on the I2C Bus
Interface Definition
BIT
BYTE
7 (MSB)
6
H
5
H
4
H
3
2
1
0 (LSB)
R/W
I2C slave address
Px I/O data bus
L
A2
P3
A1
P2
A0
P1
P7
P6
P5
P4
P0
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PCA9554A
REMOTE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
www.ti.com
SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
Device Address
Figure 4 shows the address byte for the PCA9554A.
Slave Address
1
0
1
1
A2 A1
R/W
A0
Hardware
Selectable
Fixed
Figure 4. PCA9554A Address
Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2
L
A1
L
A0
L
56 (decimal), 38 (hexadecimal)
57 (decimal), 39 (hexadecimal)
58 (decimal), 3A (hexadecimal)
59 (decimal), 3B (hexadecimal)
60 (decimal), 3C (hexadecimal)
61 (decimal), 3D (hexadecimal)
62 (decimal), 3E (hexadecimal)
63 (decimal), 3F (hexadecimal)
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read
is selected. A low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte that is
stored in the control register in the PCA9554A. Two bits of this command byte state the operation (read or write)
and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can
be written or read through the I2C bus. The command byte is sent only during a write transmission.
Once a command byte has been sent, the register that was addressed continues to be accessed by reads until
a new command byte has been sent.
0
0
0
0
0
0
B1 B0
Figure 5. Control Register Bits
Command Byte
CONTROL REGISTER BITS
COMMAND BYTE
(HEX)
POWER-UP
DEFAULT
REGISTER
PROTOCOL
B1
0
B0
0
0x00
0x01
0x02
0x03
Input Port Register
Output Port Register
Read byte
XXXX XXXX
1111 1111
0000 0000
1111 1111
0
1
Read/write byte
Read/write byte
Read/write byte
1
0
Polarity Inversion Register
Configuration Register
1
1
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REMOTE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
Register Descriptions
The Input Port Register (Register 0) reflects the incoming logic levels of the pins, regardless of whether the pin
is defined as an input or an output by the Configuration Register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to let the I2C device know that the
Input Port register will be accessed next.
Register 0 (Input Port Register) Table
BIT
I7
X
I6
X
I5
X
I4
X
I3
X
I2
X
I1
X
I0
X
DEFAULT
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Register 1 (Output Port Register) Table
BIT
O7
1
O6
1
O5
1
O4
1
O3
1
O2
1
O1
1
O0
1
DEFAULT
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained.
Register 2 (Polarity Inversion Register) Table
BIT
N7
0
N6
0
N5
0
N4
0
N3
0
N2
0
N1
0
N0
0
DEFAULT
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Register 3 (Configuration Register) Table
BIT
C7
1
C6
1
C5
1
C4
1
C3
1
C2
1
C1
1
C0
1
DEFAULT
Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9554A in a reset condition
until VCC has reached VPOR. At that point, the reset condition is released and the PCA9554A registers and
I2C/SMBus state machine will initialize to their default states. After that, VCC must be lowered to below 0.2 V and
then back up to the operating voltage for a power-reset cycle.
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REMOTE 8-BIT I2C AND SMBus I/O EXPANDER
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting; data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read
mode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the rising edge of the SCL signal. In a
Stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock
pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the
I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register.
INT has an open-drain structure and requires a pullup resistor to VCC
.
Bus Transactions
Data is exchanged between the master and PCA9554A through write and read commands.
Writes
Data is transmitted to the PCA9554A by sending the device address and setting the least-significant bit to a
logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission.
SCL
1
2
3
4
5
6
7
8
9
Slave Address
Command Byte
Data to Port
Data 1
S
0
1
1
1 A2 A1 A0
0
A
0
0
0
0
0
0
0
1
A
A
P
SDA
ACK From Slave
ACK From Slave
R/W ACK From Slave
Start Condition
Write to Port
Data Out
From Port
Data 1 Valid
t
pv
Figure 6. Write to Output Port Register
<br/>
SCL
1
2
3
4
5
6
7
8
0
9
Slave Address
Command Byte
Data to Register
Data
SDA
S
0
1
1
1
A2 A1 A0
A
0
0
0
0
0
0
1
1/0
A
A
P
Start Condition
R/W ACK From Slave
ACK From Slave
ACK From Slave
Data to
Register
Figure 7. Write to Configuration or Polarity Inversion Registers
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Reads
The bus master first must send the PCA9554A address with the least-significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again, but this time the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9554A (see Figure 8 and Figure 9). After
a restart, the value of the register defined by the command byte matches the register being accessed when the
restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limitation on the number of data bytes received in one read transmission, but when the final byte is received, the
bus master must not acknowledge the data.
ACK From
Master
ACK From
Slave
ACK From
Slave
ACK From
Slave
Data from Register
Data
Slave Address
Slave Address
Command Byte
A
S
A
0
1
1
1 A2 A1 A0
1
A
S
0
1
1
1 A2 A1 A0
0
A
R/W
R/W
NACK From
Master
Data from Register
Data
P
NA
Last Byte
Figure 8. Read From Register
<br/>
1
2
3
4
5
6
7
8
9
SCL
SDA
Data From Port
Data 1
Slave Address
Data From Port
Data 4
S
0
1
1
1
A2 A1 A0
R/W
0
A
P
A
NA
Start
Condition
NACK From
ACK From
Slave
ACK From
Master
Stop
Condition
Master
Read From
Port
Data Into
Port
Data 2
Data 3
Data 4
Data 5
t
ph
t
ps
INT
t
iv
t
ir
A. This figure assumes the command byte has previously been programmed with 00h.
B. Transfer of data can be stopped at any moment by a stop condition.
C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port. See Figure 8 for these details.
Figure 9. Read From Input Port Register
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)
6
V
VO
IIK
6
V
Input clamp current
VI < 0
–20
–20
±20
50
mA
mA
mA
mA
mA
mA
mA
IOK
IIOK
IOL
IOH
Output clamp current
VO < 0
Input/output clamp current
Continuous output low current
Continuous output high current
Continuous current through GND
Continuous current through VCC
VO < 0 or VO > VCC
VO = 0 to VCC
VO = 0 to VCC
–50
–250
160
82
ICC
DB package
DBQ package
DGV package
DW package
PW package
RGT package
RGV package
90
120
57
θJA
Package thermal impedance(3)
°C/W
°C
108
TBD
TBD
150
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
MIN
MAX
UNIT
VCC
VIH
Supply voltage
2.3
5.5
V
0.7 ×
VCC
SCL, SDA
5.5
High-level input voltage
V
A2–A0, P7–P0
SCL, SDA
A2–A0, P7–P0
P7–P0
2
5.5
–0.5 0.3 × VCC
VIL
Low-level input voltage
V
–0.5
0.8
–10
25
IOH
IOL
TA
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
P7–P0
–40
85
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Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
II = –18 mA
VCC
2.3 V to 5.5 V
VPOR
MIN
TYP(1)
MAX UNIT
VIK
Input diode clamp voltage
–1.2
V
VPOR Power-on reset voltage
VI = VCC or GND, IO = 0
1.5
1.65
V
2.3 V
1.8
2.6
3.1
4.1
1.7
2.5
3
3 V
IOH = –8 mA
4.5 V
4.75 V
2.3 V
VOH
P-port high-level output voltage(2)
V
3 V
IOH = –10 mA
VOL = 0.4 V
VOL = 0.5 V
4.5 V
4.75 V
2.3 V to 5.5 V
2.3 V
4
SDA
3
8
10
14
17
35
13
19
24
45
10
8
3 V
8
4.5 V
8
4.75 V
2.3 V
8
IOL
P port(3)
mA
10
10
10
10
3
3 V
VOL = 0.7 V
4.5 V
4.75 V
2.3 V to 5.5 V
INT
VOL = 0.4 V
SCL, SDA
A2–A0
P port
P port
±1
±1
II
VI = VCC or GND
2.3 V to 5.5 V
µA
IIH
IIL
VI = VCC
2.3 V to 5.5 V
2.3 V to 5.5 V
5.5 V
1
µA
µA
VI = GND
–100
175
90
104
50
VI = VCC, IO = 0, I/O = inputs,
fscl = 400 kHz, No load
3.6 V
2.7 V
20
65
Operating mode
5.5 V
60
150
40
VI = VCC, IO = 0, I/O = inputs,
fscl = 100 kHz, No load
3.6 V
15
2.7 V
8
20
ICC
µA
5.5 V
450
300
225
0.25
0.2
0.1
700
600
500
1
VI = GND, IO = 0, I/O = inputs,
fscl = 0 kHz, No load
3.6 V
2.7 V
Standby mode
5.5 V
VI = VCC, IO = 0, I/O = inputs,
fscl = 0 kHz, No load
3.6 V
0.9
0.8
2.7 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
1.5
1
Additional current in standby
mode
∆ICC
mA
Every LED I/O at VI = 4.3 V;
fscl = 0 kHz
5.5 V
CI
SCL
VI = VCC or GND
2.3 V to 5.5 V
4
5.5
8
5
6.5
9.5
pF
pF
SDA
P port
Cio
VIO = VCC or GND
2.3 V to 5.5 V
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC) and TA = 25°C.
(2) The total current sourced by all I/Os must be limited to 85 mA.
(3) Each I/O must be externally limited to a maximum of 25 mA, and the P port (P0 to P7) must be limited to a maximum current of 200 mA.
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
I2C Interface Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE
FAST MODE
I2C BUS
I2C BUS
UNIT
MIN
0
MAX
MIN
0
MAX
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
100
400 kHz
4
0.6
1.3
µs
µs
4.7
50
50
ns
ns
ns
ns
ns
ns
tsds
tsdh
ticr
250
0
100
0
(1)
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
300
(1)
(1)
ticf
tocf
I2C output fall time
10-pF to 400-pF bus
I2C bus free time between
stop and start
I2C start or repeated start
condition setup
I2C start or repeated start
condition hold
tbuf
tsts
4.7
4.7
4
1.3
0.6
0.6
µs
µs
µs
tsth
tsps
I2C stop condition setup
4
0.6
50
µs
tvd(data) Valid data time
SCL low to SDA output valid
300
ns
ACK signal from SCL low to
SDA (out) low
tvd(ack) Valid data time of ACK condition
0.3
3.45
400
0.1
0.9
µs
Cb
I2C bus capacitive load
400
ns
(1) Cb = Total capacitive load of one bus in pF
Switching Characteristics
over operating free-air temperature range (unless otherwise noted) (see Figure 11 and Figure 12)
STANDARD MODE
FAST MODE
I2C BUS
I2C BUS
MIN
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MAX
4
MIN
MAX
tiv
Interrupt valid time
Interrupt reset delay time
Output data valid
P port
SCL
INT
INT
4
4
µs
µs
ns
ns
µs
tir
4
tpv
tps
tph
SCL
P7–P0
SCL
200
200
Input data setup time
Input data hold time
P port
P port
100
1
100
1
SCL
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE
QUIESCENT SUPPLY CURRENT
vs
TEMPERATURE
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
VCC = 5 V
VCC = 5 V
fSCL = 400 kHz
I/Os unloaded
VCC = 3.3 V
VCC = 3.3 V
VCC = 2.5 V
VCC = 2.5 V
SCL = VCC
60
0
0
-40
-15
10
35
60
85
-40
-15
10
35
85
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
NUMBER OF I/Os HELD LOW
70
60
50
40
30
20
10
0
600
550
500
450
400
350
300
250
200
150
100
50
fSCL = 400 kHz
I/Os unloaded
VCC = 5 V
TA = –40°C
TA = 25°C
TA = 85°C
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0
1
2
3
4
5
6
7
8
VCC – Supply Voltage – V
Number of I/Os Held Low
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
I/O OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
vs
TEMPERATURE
30
25
20
15
10
5
300
275
VCC = 2.5 V
VCC = 2.5 V, ISINK = 10 mA
250
225
200
175
150
125
100
75
TA = –40°C
TA = 25°C
VCC = 5 V, ISINK = 10 mA
TA = 85°C
VCC = 2.5 V, ISINK = 1 mA
VCC = 5 V, ISINK = 1 mA
50
25
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-40
-15
10
35
60
85
VOL – Output Low Voltage – V
T
A – Free-Air Temperature – °C
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
I/O SINK CURRENT
vs
OUTPUT LOW VOLTAGE
60
55
50
45
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
VCC = 5 V
VCC = 3.3 V
TA = –40°C
TA = –40°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
VOL – Output Low Voltage – V
VOL – Output Low Voltage – V
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
I/O OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT
vs
vs
TEMPERATURE
OUTPUT HIGH VOLTAGE
275
250
225
200
175
150
125
100
75
35
30
25
20
15
10
5
VCC = 2.5 V
VCC = 2.5 V, IOL = 10 mA
TA = –40°C
TA = 25°C
VCC = 5 V, IOL = 10 mA
VCC = 2.5 V, IOL = 1 mA
TA = 85°C
VCC = 5 V, IOL = 1 mA
50
25
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-40
-15
10
35
60
85
(VCC – VOH) – Output High Voltage – V
TA – Free-Air Temperature – °C
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
I/O SOURCE CURRENT
vs
OUTPUT HIGH VOLTAGE
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
VCC = 3.3 V
VCC = 5 V
TA = –40°C
TA = –40°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 85°C
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
(VCC – VOH) – Output High Voltage – V
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
OUTPUT HIGH VOLTAGE
vs
SUPPLY VOLTAGE
6
TA = 25°C
5
4
IOH = –8 mA
3
IOH = –10 mA
2
1
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VCC – Supply Voltage – V
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION
V
CC
R
L
= 1 kΩ
SDA
DUT
C
L
= 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
(MSB)
Data
Bit 07
(MSB)
Data
Bit 10 Condition
(LSB)
Stop
R/W
Bit 0
(LSB)
Address
Bit 6
Address
Bit 1
ACK
(A)
(P)
t
scl
t
sch
0.7 × V
0.3 × V
CC
SCL
SDA
CC
t
icr
t
sts
t
PHL
t
icf
t
buf
t
t
sp
PLH
0.7 × V
0.3 × V
CC
CC
t
icf
t
icr
t
sdh
t
sps
t
sth
t
sds
Repeat
Start
Condition
Stop
Condition
Start or
Repeat
Start
Condition
VOLTAGE WAVEFORMS
BYTE
1
DESCRIPTION
2
I C address
2, 3
P-port data
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 10. I2C Interface Load Circuit and Voltage Waveforms
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
R
L
= 4.7 kΩ
INT
DUT
C
L
= 100 pF
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Slave
ACK
From Slave
Start
Condition
8 Bits
(One Data Bytes)
From Port
R/W
Slave Address
Data From Port
Data 2
S
0
1
1
1
A2 A1 A0
1
A
Data 1
A
1
P
1
2
3
4
5
6
7
8
A
A
t
ir
B
B
t
ir
INT
A
t
iv
t
sps
A
Data
Into
Port
Address
Data 1
Data 2
0.7 × V
0.3 × V
CC
0.7 × V
0.3 × V
CC
SCL
R/W
INT
A
CC
CC
t
iv
t
ir
0.7 × V
0.7 × V
0.3 × V
CC
CC
INT
1.5 V
P
n
0.3 × V
CC
CC
View A−A
A. CL includes probe and jig capacitance.
View B−B
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 11. Interrupt Load Circuit and Voltage Waveforms
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Pn
500 W
2 × V
DUT
CC
C
= 50 pF
L
500 W
(see Note A)
P-PORT LOAD CONFIGURATION
0.7 × V
CC
SCL
SDA
P0
A
P7
0.3 × V
CC
Slave
ACK
t
pv
(see Note B)
P
n
Last Stable Bit
Unstable
Data
WRITE MODE (R/W = 0)
0.7 × V
0.3 × V
CC
SCL
P0
A
P7
CC
t
ps
t
ph
0.7 × V
1.5 V
CC
P
n
0.3 × V
CC
READ MODE (R/W = 1)
A. CL includes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O pin output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 12. P-Port Load Circuit and Voltage Waveforms
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
R
L
= 1 kΩ
Pn
500 W
2 × V
SDA
DUT
CC
DUT
C
= 50 pF
L
500 W
C
L
= 50 pF
(see Note A)
(see Note A)
SDA LOAD CONFIGURATION
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 y V
CC
t
RESET
RESET
V /2
CC
t
REC
t
w
Pn
V /2
CC
t
RESET
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
C. All parameters and waveforms are not applicable to all devices.
Figure 13. Reset Load Circuits and Voltage Waveforms
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
APPLICATION INFORMATION
Figure 14 shows an application in which the PCA9554A can be used.
V
CC
(5 V)
2 kW
10 kW
10 kW
10 kW
V
CC
V
CC
Subsystem 1
(e.g., Temperature Sensor)
SDA
SCL
INT
SDA
P0
P1
Master
SCL
INT
Controller
GND
INT
P2
P3
RESET
Subsystem 2
(e.g., Counter)
PCA9554A
P4
A
P5
P6
P7
Controlled Device
(e.g., CBT Device)
A2
ENABLE
A1
A0
B
GND
ALARM
Subsystem 3
(e.g., Alarm System)
V
CC
A. Device address is configured as 0111000 for this example.
B. P0, P2, and P3 are configured as outputs.
C. P1, P4, and P5 are configured as inputs.
D. P6 and P7 are not used and have internal 100-kΩ pullup resistors to protect them from floating.
Figure 14. Typical Application
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SCPS127A–SEPTEMBER 2006–REVISED FEBRUARY 2007
APPLICATION INFORMATION (continued)
Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in
Figure 14. The LED acts as a diode so when the LED is off the I/O VIN is about 1.2 V less than VCC. ∆ICC in
Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC
.
For battery powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC when
the LED is off to minimize current consumption. Figure 15 shows a high value resistor in parallel with the LED.
Figure 16 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O
VIN at or above VCC and prevents additional supply current consumption when the LED is off.
V
CC
LED
100 kW
V
CC
LEDx
Figure 15. High-Value Resistor in Parallel With LED
5 V
3.3 V
LED
V
CC
LEDx
Figure 16. Device Supplied by a Lower Voltage
23
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2006
PACKAGING INFORMATION
Orderable Device
PCA9554ADB
Status (1)
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
16
16
16
16
16
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9554ADBG4
PCA9554ADBQR
PCA9554ADBR
PCA9554ADBRG4
SSOP
DB
DBQ
DB
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP/
QSOP
2500
TBD
Call TI
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SSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9554ADGV
PREVIEW
ACTIVE
TVSOP
TVSOP
DGV
DGV
16
16
125
TBD
Call TI
Call TI
PCA9554ADGVR
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9554ADGVRG4
PCA9554ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TVSOP
SOIC
DGV
DW
DW
PW
PW
PW
PW
16
16
16
16
16
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9554ADWR
PCA9554APW
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9554APWG4
PCA9554APWR
PCA9554APWRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9554ARGTR
PCA9554ARGVR
PREVIEW
PREVIEW
QFN
QFN
RGT
RGV
16
16
3000
2500
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2006
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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