PCA9517DG4_技术文档

PCA9517

www.ti.com

SCPS157B –DECEMBER 2007–REVISED MAY 2010

LEVEL-TRANSLATING I²C BUS REPEATER

Check for Samples: PCA9517

1

FEATURES

•

Two-Channel Bidirectional Buffer

I²C Bus and SMBus Compatible

•

Lockup-Free Operation

Accommodates Standard Mode and Fast Mode

I²C Devices and Multiple Masters

Operating Supply Voltage Range of

0.9 V to 5.5 V on A Side

•

Supports Arbitration and Clock Stretching

Across Repeater

Powered-Off High-Impedance I²C Pins

400-kHz Fast I²C Bus

•

Operating Supply Voltage Range of

2.7 V to 5.5 V on B Side

•

Voltage-Level Translation From 0.9 V to 5.5 V

and 2.7 V to 5.5 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Footprint and Function Replacement for

PCA9515A

•

ESD Protection Exceeds JESD 22

•

Active-High Repeater-Enable Input

Open-Drain I²C I/O

5.5-V Tolerant I²C and Enable Input Support

Mixed-Mode Signal Operation

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

1000-V Charged-Device Model (C101)

D PACKAGE

(TOP VIEW)

DGK PACKAGE

(TOP VIEW)

8

7

6

5

V_CCB

V_CCA

SCLA

SDAA

GND

1

2

3

4

V_CCA

V_CCB

1

2

3

4

8

7

6

5

SCLB

SDAB

EN

SCLA

SDAA

GND

SCLB

SDAB

EN

DESCRIPTION/ORDERING INFORMATION

This dual bidirectional I²C buffer is operational at 2.7 V to 5.5 V.

The PCA9517 is a BiCMOS integrated circuit intended for I²C bus and SMBus systems. It can also provide

bidirectional voltage-level translation (up-translation/down-translation) between low voltages (down to 0.9 V) and

higher voltages (2.7 V to 5.5 V) in mixed-mode applications. This device enables I²C and similar bus systems to

be extended, without degradation of performance even during level shifting.

The PCA9517 buffers both the serial data (SDA) and the serial clock (SCL) signals on the I²C bus, thus allowing

two buses of 400-pF bus capacitance to be connected in an I²C application. This device can also be used to

isolate two halves of a bus for voltage and capacitance.

The PCA9517 has two types of drivers—A-side drivers and B-side drivers. All inputs and I/Os are overvoltage

tolerant to 5.5 V, even when the device is unpowered (V_CCBand/or V_CCA= 0 V).

ORDERING INFORMATION

T_A

PACKAGES^{(1) (2)}

Tape and reel

ORDERABLE PART NUMBER

TOP-SIDE MARKING

SOIC – D

PCA9517DR

PD517

7EA

–40°C to 85°C

MSOP – DGK

PCA9517DGKR

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

PCA9517

SCPS157B –DECEMBER 2007–REVISED MAY 2010

www.ti.com

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

The B-side drivers operate from 2.7 V to 5.5 V and behave like the drivers in the PCA9515A. This side also

supports the standard low-level contention arbitration of the I²C bus and clock stretching. The output low level for

this internal buffer is approximately 0.5 V, but the input voltage must be 70 mV or more below the output low

level when the output internally is driven low. The higher-voltage low signal is called a buffered low. When the

B-side I/O is driven low internally, the low is not recognized as a low by the input. This feature prevents a lockup

condition from occurring when the input low condition is released.

This type of design on the B side prevents it from being used in series with the PCA9515A and another

PCA9517 (B side). This is because these devices do not recognize buffered low signals as a valid low and do

not propagate it as a buffered low again.

The A-side drivers operate from 0.9 V to 5.5 V and drive more current. They do not require the buffered low

feature (or the static offset voltage). This means that a low signal on the B side translates to a nearly 0-V low on

the A side, which accommodates smaller voltage swings of lower-voltage logic. The output pulldown on the

A side drives a hard low, and the input level is set at 0.3 V_CCAto accommodate the need for a lower low level in

systems where the low-voltage-side supply voltage is as low as 0.9 V.

The A side of two or more PCA9517s can be connected together to allow a star topography, with the A side on

the common bus. Also, the A side can be connected directly to any other buffer with static- or dynamic-offset

voltage. Multiple PCA9517s can be connected in series, A side to B side, with no buildup in offset voltage and

with only time-of-flight delays to consider.

The PCA9517 drivers are enabled when V_CCAis above 0.8 V and V_CCBis above 2.5 V.

The PCA9517 has an active-high enable (EN) input with an internal pullup to V_CCB, which allows the user to

select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It

should never change state during an I²C operation, because disabling during a bus operation hangs the bus, and

enabling part way through a bus cycle could confuse the I²C parts being enabled. The EN input should change

state only when the global bus and repeater port are in an idle state, to prevent system failures.

The PCA9517 includes a power-up circuit that keeps the output drivers turned off until V_CCBis above 2.5 V and

the V_CCAis above 0.8 V. V_CCBand V_CCAcan be applied in any sequence at power up. After power up and with

the EN high, a low level on the A side (below 0.3 V_CCA) turns the corresponding B-side driver (either SDA or

SCL) on and drives the B side down to approximately 0.5 V. When the A side rises above 0.3 V_CCA, the B-side

pulldown driver is turned off and the external pullup resistor pulls the pin high. When the B side falls first and

goes below 0.3 V_CCB, the A-side driver is turned on and the A side pulls down to 0 V. The B-side pulldown is not

enabled unless the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5 V, the

A-side driver turns off when the B-side voltage is above 0.7 V_CCB. If the B-side low voltage goes below 0.4 V, the

B-side pulldown driver is enabled, and the B side is able to rise to only 0.5 V until the A side rises above 0.3

V_CCA. Then the B side continues to rise, being pulled up by the external pullup resistor. V_CCAis only used to

provide the 0.3 V_CCAreference to the A-side input comparators and for the power-good-detect circuit. The

PCA9517 logic and all I/Os are powered by the V_CCBpin.

As with the standard I²C system, pullup resistors are required to provide the logic-high levels on the buffered

bus. The PCA9517 has standard open-collector configuration of the I²C bus. The size of these pullup resistors

depends on the system, but each side of the repeater must have a pullup resistor. The device is designed to

work with Standard mode and Fast mode I²C devices in addition to SMBus devices. Standard mode I²C devices

only specify 3 mA in a generic I²C system, where Standard mode devices and multiple masters are possible.

Under certain conditions, higher termination currents can be used.

2

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SCPS157B –DECEMBER 2007–REVISED MAY 2010

TERMINAL FUNCTIONS

NO.

1

NAME

V_CCA

SCLA

SDAA

GND

EN

DESCRIPTION

A-side supply voltage (0.9 V to 5.5 V)

2

Serial clock bus, A side. Connect to V_CCAthrough a pullup resistor.

Serial data bus, A side. Connect to V_CCAthrough a pullup resistor.

Supply ground

3

4

5

Active-high repeater enable input

6

SDAB

SCLB

V_CCB

Serial data bus, B side. Connect to V_CCBthrough a pullup resistor.

Serial clock bus, B side. Connect to V_CCBthrough a pullup resistor.

B-side and device supply voltage (2.7 V to 5.5 V)

7

8

Table 1. FUNCTION TABLE

INPUT

FUNCTION

EN

L

Outputs disabled

SDAA = SDAB

SCLA = SCLB

H

FUNCTIONAL BLOCK DIAGRAM

V

CCB

CCA

1

8

6

3

SDAA

SDAB

7

2

SCLA

SCLB

V

CCB

Pullup

Resistor

5

EN

4

GND

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PCA9517

SCPS157B –DECEMBER 2007–REVISED MAY 2010

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

7

UNIT

V_CCB

V_CCA

V_I

Supply voltage range

V

Supply voltage range

7

Enable input voltage range⁽²⁾

I²C bus voltage range⁽²⁾

Input clamp current

7

V_I/O

I_IK

7

V_I< 0

–50

±50

±100

150

mA

I_OK

Output clamp current

V_O< 0

Continuous output current

Continuous current through V_CCor GND

Storage temperature range

mA

°C

I_O

T_stg

–65

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

THERMAL IMPEDANCE

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

97

UNIT

D package

q_JA

Package thermal impedance⁽¹⁾

°C/W

DGK package

172

(1) The package thermal impedance is calculated in accordance with JESD 51-7.

RECOMMENDED OPERATING CONDITIONS

MIN

0.9⁽¹⁾

MAX

5.5

UNIT

V

V_CCA

V_CCB

Supply voltage, A-side bus

Supply voltage, B-side bus

2.7

V

SDAA, SCLA

SDAB, SCLB

EN

0.7 × V_CCA

0.7 × V_CCB

V_IH

High-level input voltage

Low-level input voltage

V

SDAA, SCLA

SDAB, SCLB

EN

–0.5 0.28 × V_CCA

–0.5⁽²⁾0.3 × V_CCB

V_IL

–0.5 0.3 × V_CCB

V_CCB= 2.7 V

V_CCB= 3 V

6

I_OL

T_A

Low-level output current

mA

°C

Operating free-air temperature

–40

85

(1) Low-level supply voltage

(2) V_ILspecification is for the first low level seen by the SDAB and SCLB lines. V_ILcis for the second and subsequent low levels seen by the

SDAB and SCLB lines.

4

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SCPS157B –DECEMBER 2007–REVISED MAY 2010

ELECTRICAL CHARACTERISTICS

V_CCB= 2.7 V to 5.5 V, GND = 0 V, T_A= –40°C to 85°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_I= –18 mA

V_CCB

MIN

TYP

MAX UNIT

V_IK

Input clamp voltage

2.7 V to 5.5 V

–1.2

V

I_OL= 100 mA or 6 mA,

V_ILA= V_ILB= 0 V

SDAB, SCLB

0.45

0.52

0.1

0.7

Low-level output

voltage

V_OL

2.7 V to 5.5 V

V

SDAA, SCLA I_OL= 6 mA

SDAB, SCLB

0.2

Low-level input voltage

V_OL– V_ILcbelow low-level output

voltage

2.7 V to 5.5 V

70

mV

V

SDA and SCL low-level

V_ILC

SDAB, SCLB

–0.5

0.4

1.5

input voltage contention

Both channels low,

SDAA = SCLA = GND and

SDAB = SCLB = open, or

SDAA = SCLA = open and

SDAB = SCLB = GND

I_CC

Quiescent supply current for V_CCA

1

4

mA

Both channels high,

SDAA = SCLA = V_CCAand

SDAB = SCLB = V_CCBand

EN = V_CCB

Both channels low,

SDAA = SCLA = GND and

SDAB = SCLB = open, or

SDAA = SCLA = open and

SDAB = SCLB = GND

I_CC

Quiescent supply current

5.5 V

mA

1.5

5

In contention,

SDAA = SCLA = GND and

SDAB = SCLB = GND

V_I= V_CCB

V_I= 0.2 V

V_I= V_CCB

V_I= 0.2 V

V_I= V_CCB

V_I= 0.2 V

±1

10

±1

10

±1

–30

10

7

SDAB, SCLB

SDAA, SCLA

EN

I_I

Input leakage current

2.7 V to 5.5 V

mA

–10

SDAB, SCLB

SDAA, SCLA

EN

High-level output

leakage current

I_OH

V_O= 3.6 V

mA

pF

V_I= 3 V or 0 V

3.3 V

0 V

6

C_I

Input capacitance

9

SCLA, SCLB V_I= 3 V or 0 V

SDAA, SDAB V_I= 3 V or 0 V

8

3.3 V

0 V

9

Input/output

capacitance

C_IO

8

TIMING REQUIREMENTS

over recommended operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

ns

t_su

t_h

Setup time, EN high before Start condition⁽¹⁾

Hold time, EN high after Stop condition⁽¹⁾

100

ns

(1) EN should change state only when the global bus and the repeater port are in an idle state.

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PCA9517

SCPS157B –DECEMBER 2007–REVISED MAY 2010

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I²C INTERFACE TIMING REQUIREMENTS

V_CCB= 2.7 V to 5.5 V, GND = 0 V, T_A= –40°C to 85°C (unless otherwise noted)

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

TEST CONDITIONS

MIN TYP⁽¹⁾MAX UNIT

SDAB, SCLB⁽²⁾SDAA, SCLA⁽²⁾

(see Figure 4) (see Figure 4)

SDAA, SCLA⁽³⁾SDAB, SCLB⁽³⁾

100

25

15

20

10

45

1

169 255

67 110

t_PLZ

t_PZL

t_TLH

t_THL

Propagation delay

ns

(see Figure 3)

V

_CCA≤ 2.7 V

68⁽⁴⁾110

79 130

(see Figure 2)

2.7 V ≤ V_CCA≤ 3 V

(see Figure 2)

SDAB, SCLB

SDAA, SCLA

Propagation delay

V_CCA≥ 3 V

103⁽⁵⁾300

118 230

(see Figure 2)

SDAA, SCLA⁽³⁾SDAB, SCLB⁽³⁾

(see Figure 3)

B side to A side

(see Figure 3)

6

30

Transition time

20%

80%

A side to B side

(see Figure 2)

20

1

31 170

V_CCA≤ 2.7 V

3⁽⁴⁾105

(see Figure 3)

2.7 V ≤ V_CCA≤ 3 V

(see Figure 2)

B side to A side

1

6

120

25⁽⁵⁾175

12 90

80%

20%

V_CCA≥ 3 V

1

(see Figure 3)

A side to B side

(see Figure 2)

1

(1) Typical values were measured with V_CCA= V_CCB= 2.7 V at T_A= 25°C, unless otherwise noted.

(2) The t_PLHdelay data from B to A side is measured at 0.5 V on the B side to 0.5 V_CCAon the A side when V_CCAis less than 2 V, and

1.5 V on the A side if V_CCAis greater than 2 V.

(3) The proportional delay data from A to B side is measured at 0.3 V_CCAon the A side to 1.5 V on the B side.

(4) Typical value measured with V_CCA= 0.9 V at T_A= 25°C

(5) Typical value measured with V_CCA= 5.5 V at T_A= 25°C

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SCPS157B –DECEMBER 2007–REVISED MAY 2010

PARAMETER MEASUREMENT INFORMATION

V_CC

R_L

V_IN

V_OUT

S1

(see Note A)

PULSE

GENERATOR

DUT

GND

R

T

C = 57 pF

L

(see Note B)

(see Note C)

TEST

S1

t_PLZ/t_PZL

V_CC

TEST CIRCUIT FOR OPEN-DRAIN OUTPUT

A. R_L= 167 Ω on the A side and 1.35 kΩ on the B side

B. R_Ttermination resistance should be equal to Z_OUTof pulse generators.

C. C_Lincludes probe and jig capacitance.

D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω,

slew rate ≥ 1 V/ns.

E. The outputs are measured one at a time, with one transition per measurement.

F. t_PLHand t_PHLare the same as t_pd

G. t_PLZand t_PHZare the same as t_dis

H. t_PZLand t_PZHare the same as t_en

.

Figure 1. Test Circuit

3 V

INPUT

1.5 V

0.1 V

t_PZL

80%

t_PLZ

80%

1.2 V

OUTPUT

0.6 V

20%

0.6 V

20%

V_OL

t_THL

t_TLH

Figure 2. Waveform 1 – Propagation Delay and Transition Times for B Side to A Side

V_CCA

INPUT

0.3 V_CCA

t_PZL

80%

20%

t_PLZ

3 V

80%

1.5 V

OUTPUT

1.5 V

20%

Figure 3. Waveform 2 – Propagation Delay and Transition Times for A Side to B Side

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SCPS157B –DECEMBER 2007–REVISED MAY 2010

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PARAMETER MEASUREMENT INFORMATION (continued)

INPUT

SDAB, SCLB

0.5 V

OUTPUT

50% is V_CCAis less than 2 V

SCLA, SDAA

1.5 V if V_CCAis greater than 2 V

t_PLH

Figure 4. Waveform 3

8

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SCPS157B –DECEMBER 2007–REVISED MAY 2010

APPLICATION INFORMATION

A typical application is shown in Figure 5. In this example, the system master is running on a 3.3-V I²C bus, and

the slave is connected to a 1.2-V bus. Both buses run at 400 kHz. Master devices can be placed on either bus.

The PCA9517 is 5-V tolerant, so it does not require any additional circuitry to translate between 0.9-V to 5.5-V

bus voltages and 2.7-V to 5.5-V bus voltages.

When the A side of the PCA9517 is pulled low by a driver on the I²C bus, a comparator detects the falling edge

when it goes below 0.3 V_CCAand causes the internal driver on the B side to turn on, causing the B side to pull

down to about 0.5 V. When the B side of the PCA9517 falls, first a CMOS hysteresis-type input detects the

falling edge and causes the internal driver on the A side to turn on and pull the A-side pin down to ground. In

order to illustrate what would be seen in a typical application, refer to Figure 7 and Figure 8. If the bus master in

Figure 5 were to write to the slave through the PCA9517, waveforms shown in Figure 7 would be observed on

the A bus. This looks like a normal I²C transmission, except that the high level may be as low as 0.9 V, and the

turn on and turn off of the acknowledge signals are slightly delayed.

On the B-side bus of the PCA9517, the clock and data lines would have a positive offset from ground equal to

the V_OLof the PCA9517. After the eighth clock pulse, the data line is pulled to the V_OLof the slave device, which

is very close to ground in this example. At the end of the acknowledge, the level rises only to the low level set by

the driver in the PCA9517 for a short delay, while the A-bus side rises above 0.3 V_CCAand then continues high. It

is important to note that any arbitration or clock stretching events require that the low level on the B-bus side at

the input of the PCA9517 (V_IL) be at or below 0.4 V to be recognized by the PCA9517 and then transmitted to

the A-bus side.

3.3 V

1.2 V

10 kW

V_CCA

10 kW

V_CCB

10 kW

SDA

SCL

SDA

SCL

SDAB

SDAA

SCLB

SCLA

BUS

PCA9517

EN

MASTER

400 kHz

SLAVE

400 kHz

BUS A

BUS B

Figure 5. Typical Application

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PCA9517

SCPS157B –DECEMBER 2007–REVISED MAY 2010

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V_CCA

V_CCB

10 kΩ

SDAA

SCLA

SDA

SCL

SDAB

SCLB

SDA

SCL

SLAVE

PCA9517

EN

BUS

MASTER

400 kHz

10 kΩ

SDAA

SCLA

SDAB

SCLB

SDA

SCL

PCA9517

EN

SLAVE

400 kHz

10 kΩ

SDAA

SCLA

SDAB

SCLB

SDA

SCL

SLAVE

400 kHz

PCA9517

EN

Figure 6. Typical Star Application

Multiple PCA9517 A sides can be connected in a star configuration, allowing all nodes to communicate with each

other.

V_CCB

10 kΩ

SDAA SDAB

10 kΩ

SDA

SCL

10 kΩ

SDAA SDAB

10 kΩ

SDAA

10 kΩ

SDA

SCL

10 kΩ

SDAB

SCLB

SCLA SCLB

SCLA

BUS

MASTER

PCA9517

EN

PCA9517

EN

PCA9517

EN

SLAVE

400 kHz

Figure 7. Typical Series Application

Multiple PCA9517s can be connected in series as long as the A side is connected to the B side. I²C bus slave

devices can be connected to any of the bus segments. The number of devices that can be connected in series is

limited by repeater delay/time-of-flight considerations on the maximum bus speed requirements.

10

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SCPS157B –DECEMBER 2007–REVISED MAY 2010

0.5 V/DIV

9th CLOCK PULSE — ACKNOWLEDGE

SCL

SDA

Figure 8. Bus A (0.9-V to 5.5-V Bus) Waveform

2 V/DIV

9th CLOCK PULSE — ACKNOWLEDGE

SCL

SDA

V_OLOF PCA9517

V_OLOF SLAVE

Figure 9. Bus B (2.7-V to 5.5-V Bus) Waveform

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PACKAGE OPTION ADDENDUM

www.ti.com

25-Feb-2009

PACKAGING INFORMATION

Orderable Device

PCA9517D

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PCA9517DG4

PCA9517DGKR

PCA9517DGKRG4

PCA9517DR

SOIC

MSOP

SOIC

D

DGK

D

75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PCA9517DRG4

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

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Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

PCA9517DGKR

PCA9517DR

MSOP

SOIC

DGK

D

8

2500

330.0

12.4

5.3

6.4

3.4

5.2

1.4

2.1

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

PCA9517DGKR

PCA9517DR

MSOP

SOIC

DGK

D

8

2500

358.0

346.0

335.0

346.0

35.0

29.0

Pack Materials-Page 2

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型号：	PCA9517DG4
厂家：	TEXAS INSTRUMENTS
描述：	LEVEL-TRANSLATING I2C BUS REPEATER 电平转换I2C总线中继器中继器
文件：	总17页 (文件大小：450K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA9517DG4 [TI]

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