P5LS10116ASPGEIQ1R [TI]
16/32-BIT RISC Flash Microcontroller; 16位/ 32位RISC闪存微控制器型号: | P5LS10116ASPGEIQ1R |
厂家: | TEXAS INSTRUMENTS |
描述: | 16/32-BIT RISC Flash Microcontroller |
文件: | 总101页 (文件大小:1144K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141–MARCH 2010
TMS570LS Series 16/32-BIT RISC Flash Microcontroller
Check for Samples: TMS570LS20216, TMS570LS20206, TMS570LS10216, TMS570LS10206, TMS570LS10116, TMS570LS10106
1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller
1.1 Features
12
• High-Performance Automotive Grade
• Communication Interfaces
Microcontroller for Safety Critical Applications
– Certified for use in SIL3 Applications
– Dual CPU’s running in Lockstep
– Three Multi-buffered Serial Peripheral
Interface (MibSPI) each with:
•
•
•
Four chip selects and one Enable pin
128 buffers with parity
One with parallel mode
– ECC on Flash and SRAM
– CPU and Memory BIST (Built-In Self Test)
– Error Signaling Module (ESM) w/ Error Pin
• ARM® Cortex™-R4F 32-Bit RISC CPU
– Two UART (SCI) interfaces with Local
Interconnect Network Interface (LIN 2.0)
– Three CAN (DCAN) Controller
– Efficient 1.6 DMIPS/MHz with 8-stage
pipeline
– Floating Point Unit with Single/Double
Precision
•
•
Two with 64 mailboxes, one with 32
Parity on mailbox RAM
– Dual Channel FlexRay™ Controller
– Memory Protection Unit (MPU)
– Open Architecture With Third-Party Support
• Operating Features
•
•
8K-Byte message RAM with parity
Transfer Unit with MPU and parity
• High-End Timer (nHET)
– Up to 160-MHz System Clock
– Core Supply Voltage (VCC): 1.5 V
– I/O Supply Voltage (VCCIO): 3.3 V
• Integrated Memory
– 1M-Byte or 2M-Byte Flash with ECC
– 128K-Byte or 160K-Byte RAM with ECC
• Multiple Communication interfaces including
Flexray, CAN, and LIN
– 32 Programmable I/O Channels
– 128 Words High-End Timer RAM with parity
– Transfer Unit with MPU and parity
• Two 12-Bit Multi-Buffered ADCs (MibADC)
– 24 total ADC Input channels
– Each has 64 Buffers with parity
• Trace and Calibration Interfaces
– Embedded Trace Module (ETMR4)
– Data Modification Module (DMM)
– RAM Trace Port (RTP)
• NHET Timer and 2x 12-bit ADC's
• External Memory Interface (EMIF)
– 16bit Data, 22bit Address, 4 Chip Selects
• Common TMS470/570 Platform Architecture
– Consistent Memory Map across the family
– Real-Time Interrupt (RTI) OS Timer
– Vectored Interrupt Module (VIM)
– Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
– Parity on Control Packet Memory
– Parameter Overlay Module (POM)
• On-Chip emulation logic including IEEE 1149.1
JTAG, Boundary Scan and ARM Coresight
components
• Full Development Kit Available
– Development Boards
– Code Composer Studio Integrated
Development Environment (IDE)
– HaLCoGen Code Generation Tool
– HET Assembler and Simulator
– nowFlash Flash Programming Tool
• Packages Supported
– Dedicated Memory Protection Unit (MPU)
• Frequency-Modulated Zero-Pin Phase-Locked
Loop (FMZPLL)-Based Clock Module
– Oscillator and PLL clock monitor
• Up to 115 Peripheral IO pins
– 16 Dedicated GIO - 8 w/ External Interrupts
– Programmable External Clock (ECLK)
1
– 144-Pin Quad Flatpack (PGE) [Green]
– 337-Pin Ball Grid Array (ZWT) [Green]
• Community Resources
– TI E2E Community
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
Copyright © 2010, Texas Instruments Incorporated
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
www.ti.com
1.2 Description
The TMS570LS series is a high performance automotive grade microcontroller family which has been
certified for use in IEC 61508 SIL3 safety systems. The safety architecture includes Dual CPUs in
lockstep, CPU and Memory Built-In Self Test (BIST) logic, ECC on both the Flash and the data SRAM,
parity on peripheral memories, and loop back capability on peripheral IOs.
The TMS570LS family integrates the ARM® Cortex™-R4F Floating Point CPU which offers an efficient 1.6
DMIPS/MHz, and has configurations which can run up to 160 MHz providing more than 250 DMIPS. The
TMS570LS series also provides different Flash (1MB or 2MB) and data SRAM (128KB or 160KB) options
with single bit error correction and double bit error detection.
The TMS570LS devices feature peripherals for real-time control-based applications, including up to 32
nHET timer channels and two 12-bit A to D converters supporting up to 24 inputs. There are multiple
communication interfaces including a 2-channel Flexray, 3 CAN controllers supporting 64 mailboxes each,
and 2 LIN/UART controllers.
With integrated SIL3 certified safety features and a wide choice of communication and control peripherals,
the TMS570LS series is an ideal solution for high performance real time control applications with safety
critical requirements.
The devices included in the TMS570LS series and described in this document are:
•
•
•
•
•
•
TMS570LS20216
TMS570LS20206
TMS570LS10216
TMS570LS10206
TMS570LS10116
TMS570LS10106
The TMS570LS series microcontrollers contain the following:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Dual TMS570 16/32-Bit RISC (ARM Cortex™-R4F) in Lockstep
Up to 2M-Byte Program Flash with ECC
Up to 160K-Byte Static RAM (SRAM) with ECC
Real-Time Interrupt (RTI) Operating System Timer
Vectored Interrupt Module (VIM)
Cyclic Redundancy Checker (CRC) with Parallel Signature Analysis (PSA)
Direct Memory Access (DMA) Controller
Frequency-Modulated Phase-Locked Loop (FMZPLL)-Based Clock Module With Prescaler
Three Multi-buffered Serial Peripheral Interfaces (MibSPI)
Two UARTs (SCI) with Local Interconnect Network Interfaces (LIN)
Three CAN Controllers (DCAN)
High-End Timer (NHET) with dedicated Transfer Unit (HTU)
Available FlexRay Controller with dedicated PLL and Transfer Unit (FTU)
External Clock Prescale (ECP) Module
Two 16-Channel 12-Bit Multi-Buffered ADCs (MibADC) - 8 shared channels between the two ADCs
System Bus Parity with Failure Detection
Error Signaling Module (ESM) with external error pin
Voltage Monitor (VMON) with out of range reset assertion
Embedded Trace Module (ETMR4)
Data Modification Module (DMM)
RAM Trace Port (RTP)
Parameter Overlay Module (POM)
2
TMS570LS Series 16/32-BIT RISC Flash Microcontroller
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Product Folder Link(s): TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116
TMS570LS10106
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141–MARCH 2010
•
•
•
16 Dedicated General-Purpose I/O (GIO) Pins for ZWT; 8 Dedicated GIO Pins for PGE
115 Total Peripheral I/Os for ZWT; 68 Total Peripheral I/Os for PGE
16-Bit External Memory Interface (EMIF)
The devices utilize the big-endian format where the most significant byte of a word is stored at the lowest
numbered byte and the least significant byte at the highest numbered byte.
The device memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
halfword, and word modes. The flash memory on this device is a nonvolatile, electrically erasable and
programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3V
supply input (same level as I/O supply) for all read, program and erase operations. When in pipeline
mode, the flash operates with a system clock frequency of up to 160 MHz.
The device has nine communication interfaces: three MibSPIs, two LIN/SCIs, three DCANs and one
FlexRay™ controller (optional). The SPI provides a convenient method of serial interaction for high-speed
communications between similar shift-register type devices. The LIN supports the Local Interconnect
standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero
(NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster
communication protocol that efficiently supports distributed real-time control with robust communication
rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and
harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or
multiplexed wiring. The FlexRay uses a dual channel serial, fixed time base multimaster communication
protocol with communication rates of 10 megabits per second (Mbps) per channel. A FlexRay Transfer
Unit (FTU) enables autonomous transfers of FlexRay data to and from main CPU memory. Transfers are
protected by a dedicated, built-in Memory Protection Unit (MPU).
The NHET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The NHET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O.. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer
Transfer Unit (HET-TU) provides features to transfer NHET data to or from main memory. A Memory
Protection Unit (MPU) is built into the HET-TU to protect against erroneous transfers.
The device has two 12-bit-resolution MibADCs with 24 total channels and 64 words of parity protected
buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Eight channels are shared between the two ADCs. There are three
separate groupings, two of which are triggerable by an external event. Each sequence can be converted
once when triggered or configured for continuous conversion mode.
The frequency-modulated phase-locked loop (FMZPLL) clock module contains a phase-locked loop, a
clock-monitor circuit, a clock-enable circuit, and a prescaler. The function of the FMZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The FMZPLL provides one of the six
possible clock source inputs to the global clock module (GCM). The GCM module provides system clock
(HCLK), real-time interrupt clock (RTICLK1), CPU clock (GCLK), NHET clock (VCLK2), DCAN clock
(AVCLK1), and peripheral interface clock (VCLK) to all other peripheral modules.
The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock on the ECLK pin. The ECLK frequency is a user-programmable ratio of the peripheral
interface clock (VCLK) frequency.
The Direct Memory Access Controller (DMA) has 16 channels, 32 control packets and parity protection on
its memory. The DMA provides memory to memory transfer capabilities without CPU interaction. A
Memory Protection Unit (MPU) is built into the DMA to protect memory against erroneous transfers.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or
external Error pin is triggered when a fault is detected.
Copyright © 2010, Texas Instruments Incorporated
TMS570LS Series 16/32-BIT RISC Flash Microcontroller
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Product Folder Link(s): TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116
TMS570LS10106
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
www.ti.com
The External Memory Interface (EMIF) provides a memory extension to asynchronous memories or other
slave devices.
Several interfaces are implemented to enhance the debugging capabilities of application code. In addition
to the built in ARM Cortex™-R4F CoreSight™ debug features, an External Trace Macrocell (ETM)
provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port
Module (RTP) is implemented to support high-speed output of RAM accesses by the CPU or any other
master. A Direct Memory Module (DMM) gives the ability to write external data into the device memory.
Both the RTP and DMM have no or only minimum impact on the program execution time of the application
code. A Parameter Overlay Module (POM) can re-route Flash accesses to the EMIF, thus avoiding the
re-programming steps necessary for parameter updates in Flash.
4
TMS570LS Series 16/32-BIT RISC Flash Microcontroller
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116
TMS570LS10106
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141–MARCH 2010
1.3 Functional Block Diagram
TRST
TMS
TCK
ETMDATA[31:0]
ETMTRACECTL
DAP
ETM
CCM-R4
ETMTRACECLKOUT
ETMTRACECLKIN
with
RTCK
TDI
TDO
ICEPick
RAM
160kB
with ECC
LIN1RX
LIN1TX
LIN2RX
LIN2TX
LIN1
LIN2
Cortex-R4F
with MPU
Flash
2.0MB
with ECC
P
O
M
V
CCP1
FLTP1
FLTP2
FRAYRX1
FRAYTX1
Cortex-R4F
with MPU
Flexray
8k Byte
STC
LBIST
FRAYTXEN1
FRAYRX2
FRAYTX2
32 Regions
Msg RAM
with Parity
FRAYTXEN2
NHET
128 Words
with Parity
DMA
DMMENA
DMMSYNC
DMMCLK
NHET[31:0]
16 Channels
1 Port
with Parity
Flexray HET TU
TU
8 DCP
with MPU
with Parity
DMM
DMMDATA[1:0]
DMMDATA[15:2]*
with MPU
with Parity
with MPU
RST
PORRST
TEST
ECLK
SYS
SCR1
ESM
SCR2
MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI1CLK
MiBSPI1
8 Transfer
Groups
128 Buffers
with Parity
ERROR
Primary SCR
MIBSPI1SCS[3:0]
MIBSPI1ENA
EMIFDQM[1:0]
EMIFDATA[15:0]
EMIFADD[21:0]
MiBSPI3
8 Transfer
Groups
128 Buffers
with Parity
MIBSPI3SIMO
MIBSPI3SOMI
MIBSPI3CLK
SCR
Periph Bridge
PCR
CRC
2 Channel
EMIFBADD[1:0]
EMIFCS[3:0]
EMIFWE
EMIF
MIBSPI3SCS[3:0]
MIBSPI3ENA
EMIFOE
MIBSPI5SIMO[3:0]*
MIBSPI5SOMI[3:0]*
MIBSPI5CLK*
MiBSPIP5
8 Transfer
Groups
MIBSPI5SCS[3:0]*
MIBSPI5ENA*
128 Buffers
with Parity
FMzPLL
OSC
Clock
Monitor
RTI
OSCIN
OSCOUT
DCAN1
64 Messages
with Parity
CAN1RX
CAN1TX
FPLL
for Flexray
VIM
64 Channel
with Parity
Kelvin_GND
DCAN2
64 Messages
with Parity
CAN2RX
CAN2TX
DCAN3
32 Messages
with Parity
CAN3RX
CAN3TX
MiBADC2
MiBADC1
RTP
64 Words
2 RAM blocks
Vcc
64 Words
with Parity
12Bit
VMON
64 Words
with Parity
12Bit
VccIO
GIOA[7:0]/INT[7:0]
GIOB[7:0]
GIO
Note:
Priorities
SCR : round robin
SCR1 : 1=DMA, 2=DMM, 3=DAP
SCR2 : round robin
* MIBSPIP5 pins are multiplexed
with DMMDATA[15:2] pins
Copyright © 2010, Texas Instruments Incorporated
TMS570LS Series 16/32-BIT RISC Flash Microcontroller
Submit Documentation Feedback
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Product Folder Link(s): TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116
TMS570LS10106
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
www.ti.com
1
TMS570LS Series 16/32-BIT RISC Flash
Microcontroller .......................................... 1
1.1 Features .............................................. 1
1.2 Description ........................................... 2
1.3 Functional Block Diagram ............................ 5
Device Overview ........................................ 7
2.1 Device Characteristics ............................... 7
2.2 Memory .............................................. 8
2.3 Pin Assignments .................................... 16
2.4 Terminal Functions ................................. 21
2.5 Device Support ..................................... 34
Reset / Abort Sources ................................ 36
3.1 Reset / Abort Sources .............................. 36
Peripherals .............................................. 39
4.1 Error Signaling Module (ESM) ...................... 39
4.2 Direct Memory Access (DMA) ...................... 42
5.1 Device Identification Code Register ................ 56
5.2 Die-ID Registers .................................... 58
5.3 PLL Registers ....................................... 59
Device Electrical Specifications .................... 60
6
6.1 Operating Conditions ............................... 60
2
6.2
Absolute Maximum Ratings Over Operating
Free-Air Temperature Range (unless otherwise
noted) ............................................... 60
6.3
6.4
Device Recommended Operating Conditions ...... 60
Electrical Characteristics Over Operating Free-Air
Temperature Range ................................ 61
7
Peripheral and Electrical Specifications .......... 66
7.1 Clocks .............................................. 66
7.2 ECLK Specification ................................. 69
7.3 RST And PORRST Timings ........................ 70
7.4 DAP - JTAG Scan Interface Timing ................ 72
7.5 Output Timings ..................................... 73
7.6 Input Timings ....................................... 74
3
4
4.3
High End Timer Transfer Unit (HET-TU) ........... 43
4.4 Vectored Interrupt Manager (VIM) .................. 44
4.5 MIBADC Event Trigger Sources .................... 46
4.6 MIBSPI .............................................. 47
7.7 Flash Timings ....................................... 75
7.8 SPI Master Mode Timing Parameters .............. 76
7.9 SPI Slave Mode Timing Parameters ............... 80
7.10 CAN Controller Mode Timings ...................... 84
7.11 Flexray Controller Mode Timings ................... 84
7.12 EMIF Timings ....................................... 85
7.13 ETM Timings ....................................... 87
7.14 RTP Timings ........................................ 88
7.15 DMM Timings ....................................... 90
7.16 MibADC ............................................. 91
4.7 ETM ................................................. 49
4.8 Debug Scan Chains ................................ 49
4.9 CCM ................................................ 51
4.10 LPM ................................................. 52
4.11 Voltage Monitor ..................................... 52
4.12 CRC ................................................ 52
4.13 System Module ..................................... 52
4.14 Debug ROM ........................................ 53
8
Mechanical Packaging and Orderable
Information .............................................. 97
8.1 Thermal Data ....................................... 97
8.2 Packaging Information .............................. 97
4.15 CPU Self Test Controller: STC / LBIST ............ 54
Device Registers ....................................... 56
5
6
Contents
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116
TMS570LS10106
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141–MARCH 2010
2 Device Overview
2.1 Device Characteristics
The table below shows the different configurations options offered in the TMS570LS series of devices:
Table 2-1. Characteristics of the TMS570LS Series Devices
Feature
TMS570LS20216
TMS570LS20206
TMS570LS10216
TMS570LS10206
TMS570LS10116
TMS570LS10106
Package
337
144 QFP
337
144 QFP
337
144 QFP
337
144 QFP
337
144 QFP
337
144 QFP
BGA
BGA
BGA
BGA
BGA
BGA
Type
(ZWT)
(PGE)
(ZWT)
(PGE)
(ZWT)
(PGE)
(ZWT)
(PGE)
(ZWT)
(PGE)
(ZWT)
(PGE)
Speed
160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz 160MHz 140MHz
Flash
Size
2MB
2MB
2MB
2MB
1MB
1MB
1MB
1MB
1MB
1MB
1MB
1MB
RAM Size 160KB
160KB
160KB
160KB
160KB
160KB
160KB
160KB
160KB
160KB
128KB
128KB
FlexRay
CAN
2ch
3
2ch
2
-
-
2ch
3
2ch
2
-
-
2ch
3
2ch
2
-
-
3
3
2
2
3
2
3
3
2
2
3
2
3
3
2
2
3
2
MibSPI
3
3
3
3
3
3
UART /
LIN
2
2
2
2
2
2
NHET
Channels
32
24
25
20
32
24
25
20
32
24
25
20
32
24
25
20
32
24
25
20
32
24
25
20
12 Bit
ADC
Channels
EMIF
GIO
16-bit
16
-
8
-
16-bit
16
-
8
-
16-bit
16
-
8
-
16-bit
16
-
8
-
16-bit
16
-
8
-
16-bit
16
-
8
-
ETM
RTP
DMM
32-bit
16-bit
16-bit
32-bit
16-bit
16-bit
32-bit
16-bit
16-bit
32-bit
16-bit
16-bit
32-bit
16-bit
16-bit
32-bit
16-bit
16-bit
-
-
-
-
-
-
-
-
-
-
-
-
Copyright © 2010, Texas Instruments Incorporated
Device Overview
7
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Product Folder Link(s): TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116
TMS570LS10106
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
www.ti.com
2.2 Memory
2.2.1 Memory Map
The memory map including all available Flash and RAM memory configurations for the device family are
shown in the Figure 2-1 figure below.
0xFFFFFFFF
SYSTEM Modules
0xFFF80000
0xFFF7FFFF
Peripherals
0xFF000000
0xFEFFFFFF
CRC
0xFE000000
RESERVED
CS3
0x6FFFFFFF
CS2
EMIF (256MB)
0x603FFFFF
0x60000000
CS1
CS0
0x60000000
0x204FFFFF
POM (4MB)
RESERVED
0x204FFFFF
0x2047FFFF
0x20400000
Flash - ECC(a)
RESERVED
(b)
(2MB Mirrored Image)
(1MB)
Flash - ECC
0x20400000
0x201FFFFF
RESERVED
0x201FFFFF
(a)
Flash (2MB)
RESERVED
0x200FFFFF
0x20000000
Flash (1MB)(b)
(Mirrored Image)
(Mirrored Image)
0x20000000
RESERVED
0x08427FFF
0x08401FFF
0x08400000
0x08427FFF
0x08400000
(c)
RESERVED
(128kB)
RAM - ECC
RAM - ECC(160kB)
(d)
RESERVED
0x08027FFF
0x0801FFFF
0x08027FFF
0x08000000
RESERVED
RAM (128kB)(d)
(c)
RAM (160kB)
0x08000000
RESERVED
RESERVED
0x004FFFFF
0x0047FFFF
0x00400000
0x004FFFFF
(a)
(2MB)
Flash-
ECC
(b)
(1MB)
Flash - ECC
RESERVED
0x00400000
0x001FFFFF
0x001FFFFF
0x000FFFFF
0x00000000
RESERVED
Flash (2MB)(a)
(b)
Flash (1MB)
0x00000000
(a) 2MB Flash Devices
(b) 1MB Flash Devices
( ) 160kB RAM Devices
c
(d) 128kB RAM Devices
Figure 2-1. Memory Map
8
Device Overview
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s): TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116
TMS570LS10106
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141–MARCH 2010
The Parameter Overlay memory space maps to the lower 4MB of the EMIF CS0 memory space. ECC
must be disabled by software via the CPU CP15 register if POM is used to overlay the program memory
to the EMIF space; otherwise ECC errors will be generated. The contents of memory connected to the
EMIF are not guaranteed after a power on reset. The addressable EMIF memory range is limited to the
lower 32MB of each EMIF chip select for 16bit memories, and to the lower 16MB of each EMIF chip select
for 8bit memories. The default EMIF data width is 16bit.
Copyright © 2010, Texas Instruments Incorporated
Device Overview
9
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Product Folder Link(s): TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116
TMS570LS10106
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
www.ti.com
2.2.2 Flash Memory
The F035 (130nm Flash Process) Flash memory is a nonvolatile electrically erasable and programmable
memory. The Flash has a state machine for simplifying the program and erase functions.
This device’s 2M-byte flash memory contains four 512K-byte memory arrays (or banks) consisting of 22
total sectors. 1M-byte versions of the device contain only the first two 512K-byte banks (Bank 0 and Bank
1) and have a total of 14 sectors. The bank and sector configurations are shown in Flash Memory Banks
and Sectors . When in pipeline mode, the Flash operates with a system clock frequency of up to 160MHz
(versus a system clock in non-pipeline mode of up to 36MHz). The flash in pipeline mode is capable of
accessing 128 bits at a time and provides two 64-bit pipelined words to the CPU. The minimum size for an
erase operation is one sector. A single program operation can program either one 32-bit word or one
16-bit half word at a time.
Table 2-2. Flash Memory Banks and Sectors
MEMORY ARRAYS (OR
Sector NO.
Segment
Low Address
High address
BANKS)
Bank 0: 512K Bytes
0
32K Bytes
32K Bytes
32K Bytes
8K Bytes
0x0000_0000
0x0000_8000
0x0001_0000
0x0001_8000
0x0001_A000
0x0001_C000
0x0002_0000
0x0003_0000
0x0004_0000
0x0006_0000
0x0000_7FFF
0x0000_FFFF
0x0001_7FFF
0x0001_9FFF
0x0001_BFFF
0x0001_FFFF
0x0002_FFFF
0x0003_FFFF
0x0005_FFFF
0x0007_FFFF
1
2
3
4
8K Bytes
BANK0 (512k Bytes)
5
16K Bytes
64K Bytes
64K Bytes
128K Bytes
128K Bytes
6
7
8
9
Bank 1: 512K Bytes
0
128K Bytes
128K Bytes
128K Bytes
128K Bytes
0x0008_0000
0x000A_0000
0x000C_0000
0x000E_0000
0x0009_FFFF
0x000B_FFFF
0x000D_FFFF
0x000F_FFFF
1
BANK1 (512k Bytes)
BANK2 (512k Bytes)
BANK3 (512k Bytes)
2
3
Bank 2: 512K Bytes
0
128K Bytes
128K Bytes
128K Bytes
128K Bytes
0x0010_0000
0x0012_0000
0x0014_0000
0x0016_0000
0x0011_FFFF
0x0013_FFFF
0x0015_FFFF
0x0017_FFFF
1
2
3
Bank 3: 512K Bytes
0
1
2
3
128K Bytes
128K Bytes
128K Bytes
128K Bytes
0x0018_0000
0x001A_0000
0x001C_0000
0x001E_0000
0x0019_FFFF
0x001B_FFFF
0x001D_FFFF
0x001F_FFFF
NOTE
The external flash pump voltage (VccP) is required for all flash operations (program, erase,
and read).
NOTE
After a system reset, pipeline mode is disabled (FRDCNTL[2:0] is a "000"). In other words,
the device powers up and comes out of reset in non-pipeline mode.
10
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SPNS141–MARCH 2010
2.2.3 System Modules Assignment
This table shows the memory map for the Cyclic Redundancy Check (CRC) module, the Cortex™-R4F
CoreSight™ debug module, and the System modules.
Table 2-3. System Modules Assignment
Frame Name
Address Range
Frame Start Address
0xFE00_0000
0xFFA0_0000
0xFFA0_1000
0xFFA0_2000
0xFFA0_3000
0xFFA0_4000
0xFFF8_0000
0xFFF8_2000
0xFFF8_3000
0xFFF8_7000
0xFFFF_E000
0xFFFF_E100
0xFFFF_E400
0xFFFF_E600
0xFFFF_E800
0xFFFF_F000
0xFFFF_F500
0xFFFF_F600
0xFFFF_F700
0xFFFF_F800
0xFFFF_F900
0xFFFF_FA00
0xFFFF_FC00
0xFFFF_FD00
0xFFFF_FE00
0xFFFF_FF00
Frame Ending Address
0xFEFF_FFFF
0xFFA0_0FFF
0xFFA0_1FFF
0xFFA0_2FFF
0xFFA0_3FFF
0xFFA0_4FFF
0xFFF8_0FFF
0xFFF8_2FFF
0xFFF8_3FFF
0xFFF8_7FFF
0xFFFF_E0FF
0xFFFF_E1FF
0xFFFF_E5FF
0xFFFF_E6FF
0xFFFF_E8FF
0xFFFF_F3FF
0xFFFF_F5FF
0xFFFF_F6FF
0xFFFF_F7FF
0xFFFF_F8FF
0xFFFF_F9FF
0xFFFF_FAFF
0xFFFF_FCFF
0xFFFF_FDFF
0xFFFF_FEFF
0xFFFF_FFFF
CRC
CoreSight Debug ROM Register
Cortex-R4F Debug Register
ETM-R4 Register
CoreSight TPIU Register
POM Register
DMA RAM
VIM RAM
RTP RAM
Flash Wrapper Register
PCR Register
Flexray PLL/STC CLK Register
PBIST Register
STC Register
EMIF Register
DMA Register
ESM Register
CCMR4 Register
DMM Register
RAM ECC even Register
RAM ECC odd Register
RTP Register
RTI Register
VIM Parity Register
VIM Register
System Register
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2.2.4 Peripheral Selects
The peripheral frame contains the memory map for the peripheral registers as well as the peripheral
memories. The first table shows the memory map for the peripheral module registers and following table
shows the memory map for the peripheral module memories.
Table 2-4. Peripheral Select Assignment
Peripheral Module
Address Range
Peripheral Selects
Base Address
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F400
0xFFF7_E500
0xFFF7_E400
0xFFF7_E000
0xFFF7_DE00
0xFFF7_DC00
0xFFF7_C800
0xFFF7_C200
0xFFF7_C000
0xFFF7_BC00
0xFFF7_B800
0xFFF7_A400
0xFFF7_A000
Ending Address
0xFFF7_FDFF
0xFFF7_F9FF
0xFFF7_F5FF
0xFFF7_E5FF
0xFFF7_E4FF
0xFFF7_E1FF
0xFFF7_DFFF
0xFFF7_DDFF
0xFFF7_CFFF
0xFFF7_C3FF
0xFFF7_C1FF
0xFFF7_BCFF
0xFFF7_B8FF
0xFFF7_A4FF
0xFFF7_A1FF
MIBSPIP5
MIBSPI3
MIBSPI1
LIN2
PS[0]
PS[1]
PS[2]
PS[6]
LIN1
DCAN3
DCAN2
DCAN1
Flexray
MIBADC2
MIBADC1
GIO
PS[7]
PS[8]
PS[12]+PS[13]
PS[15]
PS[16]
PS[17]
PS[22]
PS[23]
NHET
HET TU
Flexray TU
Table 2-5. Peripheral Memory Selects
Peripheral Module Memory
Address Range
Peripheral Selects
Base Address
0xFF0A0000
0xFF0C0000
0xFF0E0000
0xFF1A0000
0xFF1C0000
0xFF1E0000
0xFF3A0000
0xFF3E0000
0xFF460000
0xFF4E0000
0xFF500000
Ending Address
0xFF0BFFFF
0xFF0DFFFF
0xFF0FFFFF
0xFF1BFFFF
0xFF1DFFFF
0xFF1FFFFF
0xFF3BFFFF
0xFF3FFFFF
0xFF47FFFF
0xFF4FFFFF
0xFF51FFFF
MIBSPIP5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
DCAN3 RAM
DCAN2 RAM
DCAN1 RAM
MIBADC2 RAM
MIBADC1 RAM
NHET RAM
PCS[5]
PCS[6]
PCS[7]
PCS[13]
PCS[14]
PCS[15]
PCS[29]
PCS[31]
PCS[35]
PCS[39]
PCS[40]
HET TU RAM
Flexray TU RAM
12
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2.2.5 Memory Auto-Initialization
This device allows some of the on-chip memories to be initialized via the memory hardware initialization
control registers in the System module. The purpose of having the hardware initialization is to program the
memory arrays with error detection capability to a known state based on their error detection scheme
(odd/even parity or ECC). The MINITGCR register enables the memory initialization sequence, and the
MSINENA register selects the memories that are to be initialized. Please refer to the Architecture chapter
of the Technical Reference Manual (TRM) for more information.
The mapping of the different memories to the specific bits in the MSINENA register is shown in the
following table.
Table 2-6. Memory Initialization
Connecting Module
Address Range
RAM Select
Base Address
Ending Address
0x0801FFFF
RAM
0x08000000
0xFF0A0000
0xFF0C0000
0xFF0E0000
0xFF1A0000
0xFF1C0000
0xFF1E0000
0
12
11
7
MIBSPIP5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
DCAN3 RAM
DCAN2 RAM
DCAN1 RAM
Flexray RAM
MIBADC2 RAM
MIBADC1 RAM
NHET RAM
0xF0BFFFFF
0xFF0DFFFF
0xFF0FFFFF
0xFF1BFFFF
0xFF1DFFFF
0xFF1FFFFF
10
6
5
RAM is not visible
9
0xFF3A0000
0xFF3E0000
0xFF460000
0xFF4E0000
0xFFF80000
0xFFF82000
0xFF500000
0xFF3BFFFF
0xFF3FFFFF
0xFF47FFFF
0xFF4FFFFF
0xFFF80FFF
0xFFF82FFF
0xFF51FFFF
14
8
3
HET TU RAM
DMA RAM
4
1
VIM RAM
2
Flexray TU RAM
13
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2.2.6 PBIST RAM Self Test
The PBIST (Programmable Built-In Self Test) architecture provides a run-time-programmable memory
BIST engine for varying levels of test coverage across the device’s embedded RAM memory. The PBIST
architecture consists of a small CPU with an instruction set targeted specifically towards testing RAM
memories. This CPU includes both control and instruction registers necessary to execute the individual
memory algorithms. In order to minimize test load overhead, once an algorithm is loaded into the
instruction registers, it can be run on multiple memories of different sizes or types. The memory
configuration information and test algorithm code is stored in an on-chip ROM. The PBIST RAM groups
implemented on this device are shown in the following table. More information about memory self test can
be found in the PBIST chapter of the device TRM.
Table 2-7. PBIST RAM Grouping
RAM
Module
Memory RGS/RD
Test Pattern (Algorithm)
Group
Type
S
Triple
slow
read
Triple
fast read 13N[cycl
es]
March
Down 1A
Pre-
charge
Map
column
DTXN 2A
PMOS
open
1
2
PBIST
ROM
ROM
ROM
0/1
x
x
STC
13/1
x
x
ROM
3
4
5
6
DCAN1
DCAN2
DCAN3
ESRAM
SP
SP
SP
1/0..2
2/0..2
12600
12600
6360
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
3/0..2
SP,
multi-
4/21..22
266320
strobe w/
page
mode
7
8
9
MibSPI
VIM
SP
SP
5/0..5
Jun-00
7/0..1
50160
4200
8400
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
MibADC 2P, sync
write
async
read
10
11
12
13
DMA
NHET
HET TU
RTP
2P, sync
write
async
read
8/0..5
9/0..11
10/0..5
11/0..8
18960
25440
6480
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2P, sync
write
async
read
2P, sync
write
async
read
2P, sync
write
37800
async
read
14
15
Flexray
ESRAM
SP
12/0..7
20-Apr
175040
133160
x
x
x
x
x
x
x
x
x
x
SP,
multi-
strobe w/
page
mode
SP = Single Port RAM; 2P = Two Port RAM
14
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SPNS141–MARCH 2010
NOTE
•
•
•
The March13N test algorithm is recommended for application testing.
The maximum PBIST test execution speed is limited to 100MHz.
The supply current while performing PBIST self test is different than the device operating
mode current. These values can be found in the Icc section of the device electrical
specifications.
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2.3 Pin Assignments
2.3.1 PGE QFP Package Pinout (144 pin)
(TOP VIEW)
72
109
110
ADSIN[11]
NHET[7]
GIOA[4]/INT[4]
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
ADSIN[12]
ADSIN[13]
ADSIN[14]
ADSIN[15]
VCCAD
111
112
113
114
GIOA[5]/INT[5]
NHET[8]
NHET[15]
VCC
115
116
117
ADREFHI
ADREFLO
VSSAD
VSS
NHET[10]
NHET[11]
GIOA[0]/INT[0]
VCCIO
AD2IN[3]
AD2IN[2]
AD2IN[1]
118
119
120
121
VSSIO
NHET[4]
AD2IN[0]
AD2EVT
122
FLTP1
TEST
123
124
125
126
127
128
129
130
FLTP2
FRAYTX1
NHET[9]
NHET[2]
FRAYTXEN1
FRAYRX1
55
54
53
CAN2RX
CAN2TX
LIN1RX
LIN1TX
VSS
VCCP
52
51
50
FRAYTX2
FRAYTXEN2
FRAYRX2
GIOA[7]/INT[7]
CAN1TX
131
132
VCCIO
49
48
47
46
45
44
43
42
41
40
39
38
37
CAN1RX
NHET[6]
VCC
VSSIO 133
134
GIOA[1]/INT[1]
VCC
135
VSS
VSS 136
NHET[30] 137
NHET[14] 138
LIN2TX 139
NHET[20]
NHET[5]
NHET[24]
NHET[1]
NHET[3]
LIN2RX
140
141
142
143
144
GIOA[2]/INT[2]
VCCIO
VSSIO
VSS
NHET[16]
nERROR
GIOA[3]/INT[3]
VCC
Figure 2-2. PGE Pinout (144 pin) [Top View]
16
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SPNS141–MARCH 2010
2.3.2 ZWT BGA Package Pinout (337 ball)
C
H
A
B
D
E
F
G
J
K
L
NHET
[10]
MIBSPI5
CS[0]
MIBSPI5
SIMO[0]
NHET
[28]
DMM
DATA[0]
MIBSPI1
SIMO
MIBSPI1 MIBSPI5
ENA
CLK
TMS
TDO
19
18
17
VSS
VSS
19
18
17
NHET
[08]
MIBSPI5
SOMI[0]
NHET
[0]
DMM
DATA[1]
MIBSPI1
CLK
MIBSPI1 MIBSPI5
SOMI
ENA
VSS
TDI
TCK
RST
TRST
EMIF_
ADDR[21]
EMIF
_WE
MIBSPI5
SOM[1]
MIBSPI5 MIBSPI5
SIMO[2]
NHET
[31]
EMIF_
CS[1]
EMIF_
CS[0]
DMM
CLK
SIMO[3]
MIBSPI5
SOMI[3]
MIBSPI5
SOMI[2]
EMIF_
ADDR[20]
EMIF_
BA[1]
MIBSPI5
SIMO[1]
EMIF_
DATA[0]
EMIF_
DATA[1]
FRAY
TXEN1
DMM
ENA
DMM
SYNC
16
15
14
13
12
RTCK
16
15
14
13
12
EMIF_
EMIF_
ADDR[19] ADDR[18]
ETM
DATA[05] DATA[04] DATA[03] DATA[02] DATA[16] DATA[17]
ETM
ETM
ETM
ETM
ETM
ETM
DATA[06]
FRAY
RX1
FRAY
TX1
EMIF_
ADDR[16]
ETM
DATA[07]
NHET
[26]
EMIF_
ADDR[15]
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCC
VCC
VCCIO
ERROR
NHET
[17]
NHET
[19]
EMIF_
ADDR[15]
EMIF_
BA[0]
ETM
DATA[12]
NHET
[04]
EMIF_
ADDR[14]
ETM
DATA[13]
EMIF_
OE
ECLK
VSS
VSS
VSS
VSS
VCC
VSS
VSS
VSS
NHET
[14]
NHET
[30]
EMIF_
ADDR[13]
EMIF_
DQM[1]
ETM
DATA[14]
11
10
VCCIO
11
10
EMIF_
ADDR[12]
EMIF_
DQM[0]
ETM
DATA[15]
CAN1
TX
CAN1
RX
VCC
F
VCC
H
VSS
J
VSS
K
VSS
L
A
B
C
D
E
G
Figure 2-3. ZWT Package Pinout Top Left Quadrant (337 ball) [Top View]
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K
L
M
N
P
R
T
U
V
W
NHET
[28]
DMM
DATA[0]
ADS
IN[15]
AD2
IN[6]
AD1
IN[6]
ADS
IN[11]
CAN3
RX
AD1
EVT
19
18
17
VSSAD
VSSAD
19
18
17
NHET
[0]
AD1
IN[4]
AD1
IN[2]
ADS
IN[8]
ADS
IN[14]
ADS
IN[13]
DMM
DATA[1]
CAN3
TX
NC
VSSAD
EMIF_
CS[1]
EMIF_
CS[0]
EMIF_
CS[2]
EMIF_
CS[3]
AD1
IN[5]
AD1
IN[3]
ADS
IN[10]
AD1
IN[1]
ADS
IN[9]
NC
NC
ADS
IN[12]
EMIF_
DATA[0]
EMIF_
DATA[1]
EMIF_
DATA[2]
EMIF_
DATA[3]
AD2
IN[7]
AD2
IN[3]
ADREF
LO
16
15
14
13
12
VSSAD
VCCAD
16
15
14
13
12
ETM ETM
DATA[16] DATA [17]
ETM ETM
DATA[18] DATA[19]
AD2
IN[5]
AD2
IN[4]
ADREF
HI
NC
NC
NC
AD2
IN[2]
AD1
IN[7]
AD1
IN[0]
VCC
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCC
NC
NC
ETM
DATA[1]
AD2
IN[1]
AD2
IN[0]
AD2
EVT
ETM
DATA[0]
MIBSPI5
CS[3]
RTP
ENA
LIN1
TX
LIN1
RX
VCC
VSS
VSS
VSS
VSS
VSS
ETM
TRACE
CTL
RTP
DATA[1]
RTP
DATA[0]
RTP
SYNC
RTP
CLK
11
10
11
10
ETM
TRACE
CLKOUT
RTP
DATA[2]
RTP
DATA[3]
MIBSPI3
CS[0]
GIOB[3]
W
VCC
P
VSS
K
VSS
L
VCC
M
N
R
T
U
V
Figure 2-4. ZWT Package Pinout Top Right Quadrant (337 ball) [Top View]
18
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SPNS141–MARCH 2010
A
B
C
D
E
F
G
H
J
K
L
EMIF_
DQM[0]
ETM_
DATA[15]
EMIF_
ADDR[12]
10
9
CAN1TX
10
9
VCC
VCC
VSS
VSS
VSS
CAN1RX
NHET
[27]
FRAY
EMIF_
ADDR[5]
ETM
DATA[8]
EMIF_
ADDR[11]
VCC
VCCP
VCCIO
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VSS
TXEN2
FRAY
RX2
EMIF_ EMIF_
ADDR[10] ADDR[4]
ETM
DATA[9]
8
FRAY
TX2
8
EMIF_
ADDR[9] ADDR[3] DATA[10]
EMIF_
ETM
LIN2
RX
LIN2
TX
7
6
5
4
3
7
6
5
4
3
GIOA
[4]
MIBSPI5
CS[1]
EMIF_
EMIF_
ADDR[8] ADDR[2] DATA[11]
ETM
VCCIO
ETM
VCCIO
ETM
VCC
ETM
VCCIO
FLTP2
VCCIO
FLTP1
VCC
ETM
EMIF_
ADDR[7] ADDR[1] DATA[20]
GIOA
[5]
ETM
GIOA
[0]
EMIF_
DATA[21] DATA[22]
DATA[23] DATA[24]
EMIF_
EMIF_
EMIF_
EMIF_
EMIF_
NHET
[21]
NHET
[16]
NHET
[12]
EMIF_
EMIF_
NHET
[23]
ADDR[6] ADDR[0]
DATA[4]
DATA[5]
DATA[6]
DATA[7]
DATA[8]
NHET
[22]
NHET
[11]
GIOA
[6]
MIBSPI1
CS[3]
NHET
[29]
MIBSPI1
CS[1]
MIBSPI3
NC
CS[3]
MIBSPI1
CS[2]
NC
NC
KELVIN
GND
GIOA
NC
[1]
GIOB
[6]
GIOB
[1]
GIOB
[5]
CAN2
TX
GIOB
[2]
MIBSPI3
CS[2]
VSS
2
1
NC
2
1
NHET
[18]
GIOB
[7]
GIOA
NC
[2]
GIOA
[3]
GIOB
[4]
CAN2
RX
OSCOUT
L
VSS
A
OSCIN
K
VSS
B
C
D
E
F
G
H
J
Figure 2-5. ZWT Package Pinout Bottom Left Quadrant (337 ball) [Top View]
Copyright © 2010, Texas Instruments Incorporated
Device Overview
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TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
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L
N
P
R
T
U
V
W
K
M
ETM
TRACE
CLKOUT
RTP
DATA[2]
RTP
DATA[3]
MIBSPI3
CS[0]
GIOB[3]
10
9
VSS
VSS
VCC
VCC
10
9
RTP
DATA[4]
RTP
DATA[4]
RTP
DATA[5]
MIBSPI3
CLK
MIBSPI3
ENA
VSS
VCC
VSS
VSS
VSS
VSS
VCCIO
VCCIO
VCCIO
ETM EMIF_
DATA[31] DATA[15]
RTP
DATA[6]
MIBSPI3
SOMI
MIBSPI3
SIMO
8
8
ETM EMIF_
DATA[30] DATA[14]
RTP
DATA[7]
NHET
[9]
7
6
5
4
3
7
6
5
4
3
PORRST
ETM EMIF_
DATA[29] DATA[13]
RTP
DATA[8]
NHET
[5]
MIBSPI5
CS[2]
VCC
ETM
VCC
ETM
VCCIO
ETM
VCCIO
ETM
VCCIO
ETM
ETM
EMIF_
RTP
DATA[9]
MIBSPI3
CS[1]
NHET
[2]
DATA[23] DATA[24] DATA[25] DATA[26] DATA[27] DATA[28] DATA[12]
EMIF_
DATA[7]
EMIF_
DATA[8]
EMIF_
DATA[9]
EMIF_ EMIF_
DATA[10] DATA[11]
RTP
DATA[11]
RTP
DATA[19]
NC
NC
VSS
RTP
NC
NHET
[25]
RTP
DATA[14]
RTP
NHET
[6]
NC
NC
NC
NC
DATA[13] DATA[12]
GIOB
[1]
GIOB
[0]
NHER
[13]
NHET
[20]
MIBSPI1
CS[0]
RTP
DATA[15]
NHET
KELVIN
GND
2
1
TEST
[1]
VSS
2
1
GIOA
[7]
NHET
[15]
NHET
[24]
NHET
[7]
NHET
OSCIN
K
OSCOUT
L
NC
R
VSS
[3]
VSS
W
N
P
T
U
V
M
Figure 2-6. ZWT Package Pinout Bottom Right Quadrant (337 ball) [Top View]
20
Device Overview
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TMS570LS10106
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TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141–MARCH 2010
2.4 Terminal Functions
This following table describes the pins on the device.
Table 2-8. Terminal Functions
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
Type
Description
Name
337
144
337
144
HIGH-END TIMER (NHET)
NHET[0]
K18
V2
105
42
K18
V2
105
42
Timer input capture or output compare.
The applicable NHET pins can be
programmed as general-purpose
input/output (GIO) pins. NHET pins are
high-resolution.
NHET[1]
NHET[2]
W5
U1
56
W5
U1
56
NHET[3]
41
41
The high-resolution (HR) SHARE feature
allows even HR pins to share the next
higher odd HR pin structures. The next
higher odd HR pin structure is always
implemented, even if the next higher odd
HR pad and/or pin itself is not. The HR
sharing is independent of whether or not
the odd pin is available externally. If an
odd pin is available externally and
shared, then the odd pin can only be
used as a general-purpose I/O.
NHET[4]
B12
V6
121
44
B12
V6
121
44
NHET[5]
NHET[6]
W3
T1
48
W3
T1
48
NHET[7]
109
112
57
109
112
57
NHET[8]
E18
V7
E18
V7
NHET[9]
NHET[10]
NHET[11]
NHET[12]
NHET[13]
NHET[14]
NHET[15]
NHET[16]
NHET[17]
NHET[18]
NHET[19]
NHET[20]
NHET[21]
NHET[22]
NHET[23]
NHET[24]
NHET[25]
NHET[26]
NHET[27]
NHET[28]
NHET[29]
NHET[30]
NHET[31]
D19
E3
116
117
8
D19
E3
116
117
8
NHET[0] provides SPI clock when used
for SPI emulation.
B4
B4
Each NHET pin is equipped with an input
suppression filter that can be used to
eliminate the sampling of pulses that are
smaller than a programmable duration
GIOA[0]/INT[0] is also connected to the
NHET Pin Disable input of the NHET
module.
NHET pins can be programmed as a
GIO pins when not used as NHET
functional pins.
N2
26
N2
26
A11
N1
138
113
142
A11
N1
138
program
mable
IPD
113
3.3V I/O 2mA - z
142
A4
A4
(20mA)
A13
J1
A13
J1
10
10
B13
P2
B13
P2
45
11
9
45
11
9
H4
H4
B3
B3
J4
12
43
J4
12
43
P1
P1
M3
A14
A9
M3
A14
A9
K19
A3
106
137
K19
A3
106
137
B11
J17
B11
J17
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TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
www.ti.com
Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
Type
Description
Name
337
144
337
144
GENERAL-PURPOSE I/O (GIO)
General-purpose input/output pin.
GIOA[0]/INT[0] is an interrupt-capable
pin. GIOA[0]/INT[0] is also connected to
the NHET Pin Disable input of the NHET
module.
GIOA[0]/INT0
A5
118
A5
118
GIOA[1]/INT1
GIOA[2]/INT2
GIOA[3]/INT3
GIOA[4]/INT4
GIOA[5]/INT5
GIOA[6]/INT6
GIOA[7]/INT7
GIOB[0]
C2
C1
E1
A6
B5
H3
M1
M2
K2
F2
134
141
144
110
111
27
C2
C1
E1
A6
B5
H3
M1
M2
K2
F2
134
141
144
110
111
General-purpose input/output
pins.GIOA[7:1]/INT[7:1] are
interrupt-capable pins.
Program
mable
IPD
27
51
3.3V I/O 2mA - z
51
(20mA)
GIOB[1]
GIOB[2]
GIOB[3]
W10
G1
G2
J2
W10
G1
G2
J2
General-purpose input/output pins.
GIOB[4]
GIOB[5]
GIOB[6]
GIOB[7]
F1
F1
Flexray Controller (FLEXRAY)
NOTE: Devices with out the FlexRay option should leave all FlexRay pins unconnected (NC)
Program
mable
IPD
FRAYRX1
A15
126
3.3V I
3.3V O
3.3V I
Flexray data receive (channel 1) pin
(20mA)
FRAYTX1
B15
B16
124
125
8mA
8mA
Flexray data transmit (channel 1) pin
Flexray transmit enable (channel 1) pin
FRAYTXEN1
Program
mable
IPD(20m
A)
FRAYRX2
A8
131
Flexray data receive (channel 2) pin
FRAYTX2
B8
B9
129
130
8mA
8mA
Flexray data transmit (channel 2) pin
Flexray transmit enable (channel 2) pin
3.3V O
FRAYTXEN2
CAN Controller (DCAN1)
CAN1TX
CAN1RX
A10
B10
50
49
A10
B10
50
Program CAN1 transmit pin or GIO pin
mable
3.3V I/O 2mA - z
49
IPU
CAN1 receive pin or GIO pin
(20mA)
CAN Controller (DCAN2)
CAN2TX
CAN2RX
H2
H1
54
55
H2
H1
54
Program CAN2 transmit pin or GIO pin
mable
3.3V I/O 2mA - z
55
IPU
CAN2 receive pin or GIO pin
(20mA)
CAN Controller (DCAN3)
CAN3TX
CAN3RX
M18
M19
M18
M19
program CAN3 transmit pin or GIO pin
mable
3.3V I/O 2mA - z
IPU
CAN3 receive pin or GIO pin
(20mA)
22
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TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141–MARCH 2010
Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
337 144
Type
Description
Name
337
144
Serial Communications Interface (SCI)/Local Interconnect Network (LIN1)
LIN1RX
LIN1TX
W12
V12
53
W12
53
Program LIN1 data receive pin or GIO pin
mable
3.3V I/O 2mA - z
IPU
52
V12
52
LIN1 data transmit pin or GIO pin
(20mA)
Serial Communications Interface (SCI)/Local Interconnect Network (LIN2)
LIN2RX
LIN2TX
A7
B7
140
A7
140
Program LIN2 data receive pin or GIO pin
mable
3.3V I/O 2mA - z
IPU
139
B7
139
LIN2 data transmit pin or GIO pin
(20mA)
Multibuffered Serial Peripheral Interface (MIBSPI1)
MIBSPI1 slave chip select pins or GIO
pins
MIBSPI1CLK
F18
17
F18
17
4mA
MIBSPI1CS[0]
MIBSPI1CS[1]
MIBSPI1CS[2]
MIBSPI1CS[3]
MIBSPI1ENA
R2
F3
23
24
25
R2
F3
23
24
25
2mA - z
MIBSPI1 clock pin or GIO pin
Program
mable
IPU
G3
J3
G3
J3
3.3V I/O
(20µA)
G19
218
14
G19
218
14
2mA - z
4mA
MIBSPI1 enable pin or GIO pin
MIBSPI1 data stream - Slave in/master
out pin or GIO pin
MIBSPI1SIMO
MIBSPI1SOMI
F19
G18
F19
G18
MIBSPI1 data stream - Slave out/master
in pin or GIO pin
13
13
Multibuffered Serial Peripheral Interface (MIBSPI3)
MIBSPI3 slave chip select pins or GIO
pins
MIBSPI3CLK
V9
3
7
V9
3
7
4mA
MIBSPI3CS[0]
MIBSPI3CS[1]
MIBSPI3CS[2]
MIBSPI3CS[3]
MIBSPI3ENA
V10
V5
V10
V5
2mA - z
MIBSPI3 clock pin or GIO pin
MIBSPI3 enable pin or GIO pin
Program
mable
IPU
B2
B2
3.3V I/O
C3
W9
C3
W9
(20mA)
6
4
6
4
2mA - z
4mA
MIBSPI3 data stream - Slave in/master
out pin or GIO pin
MIBSPI3SIMO
MIBSPI3SOMI
W8
V8
W8
V8
MIBSPI3 data stream - Slave out/master
in pin or GIO pin
5
5
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TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
www.ti.com
Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
337 144
Type
Description
Name
337
144
Multibuffered Serial Peripheral Interface - Parallel (MIBSPIP5)
MIBSPI5CLK/DM
MDATA[4]
MIBSPI5 clock pin or GIO pin;
multiplexed with DMMDATA[4] pin
H19
E19
B6
91
92
93
H19
E19
B6
91
92
93
4mA
MIBSPI5CS[0]/DM
MDATA[5]
MIBSPI5CS[1]/DM
MDATA[6]
MIBSPI5 slave chip select pins or GIO
pins; multiplexed with DMMDATA pins
MIBSPI5CS[2]/DM
MDATA[2]
W6
W6
2mA - z
MIBSPI5CS[3]/DM
MDATA[3]
T12
H18
J19
E16
H17
G17
J18
E17
H16
G16
T12
H18
J19
E16
H17
G17
J18
E17
H16
G16
MIBSPI5ENA/DM
MDATA[7]
MIBSPI5 enable pin or GIO pin;
multiplexed with DMMDATA[7] pin
94
95
94
95
MIBSPI5SIMO[0]/
DMMDATA[8]
Program
mable
IPU
3.3V I/O
DMMDATA[9]/MIB
SPI5SIMO[1]
96
96
MIBSPI5 data stream - Slave in/master
out pins or GIO pins; multiplexed with
DMMDATA pins
(20mA)
MIBSPI5SIMO[2]/
DMMDATA[10]
97
97
MIBSPI5SIMO[3]/
DMMDATA[11]
98
98
4mA
MIBSPI5SOMI[0]/
DMMDATA[12]
99
99
MIBSPI5SOMI[1]/
DMMDATA[13]
100
101
102
100
101
102
MIBSPI5 data stream - Slave out/master
in pins or GIO pins; multiplexed with
DMMDATA pins
MIBSPI5SOMI[2]/
DMMDATA[14]
MIBSPI5SOMI[3]/
DMMDATA[15]/
Multibuffered Analog-To-Digital Converter (MIBADC1)
Program
mable
IPD
AD1EVT
N19
84
N19
84
3.3V I/O 2 mA - z
MibADC1 event input pin or GIO pin
(20mA)
AD1IN[0]
AD1IN[1]
AD1IN[2]
AD1IN[3]
AD1IN[4]
AD1IN[5]
AD1IN[6]
AD1IN[7]
W14
V17
V18
T17
U18
R17
T19
V14
83
82
81
80
79
78
77
76
W14
V17
V18
T17
U18
R17
T19
V14
83
82
81
80
79
78
77
76
3.3V I
MibADC1 analog input pins
24
Device Overview
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TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
www.ti.com
SPNS141–MARCH 2010
Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
337 144
Type
Description
Name
337
144
Multibuffered Analog-To-Digital Converter (MIBADC2)
Program
mable
IPD
AD2EVT
W13
59
W13
59
3.3V I/O 2 mA - z
MibADC2 event input pin or GIO pin
(20mA)
AD2IN[0]
AD2IN[1]
AD2IN[2]
AD2IN[3]
AD2IN[4]
AD2IN[5]
AD2IN[6]
AD2IN[7]
V13
U13
U14
U16
U15
T15
R19
R16
60
61
62
63
V13
U13
U14
U16
U15
T15
R19
R16
60
61
62
63
3.3 V I
MibADC2 analog input pins
Multibuffered Analog-To-Digital Converter - shared signals (MIBADC1, MIBADC2)
ADSIN[8]
P18
W17
U17
U19
T16
T18
R18
P19
75
74
73
72
71
70
69
68
P18
W17
U17
U19
T16
T18
R18
P19
75
74
73
72
71
70
69
68
ADSIN[9]
ADSIN[10]
ADSIN[11]
ADSIN[12]
ADSIN[13]
ADSIN[14]
ADSIN[15]
MibADC1, MibADC2 shared analog input
pins
3.3 V I
3.3-V
REF
MibADC1, MibADC2 module
high-voltage reference input
ADREFHI
ADREFLO
VCCAD
V15
V16
W15
66
65
V15
V16
W15
66
65
GND
REF
MibADC1, MibADC2 module low-voltage
reference input
3.3-V
PWR
MibADC1, MibADC2 analog supply
voltage
67
64
67
64
VSSAD
VSSAD
VSSAD
VSSAD
V19
W16
W18
W19
V19
W16
W18
W19
MibADC1, MibADC2 analog ground
reference
GND
Oscillator (OSC)
Oscillator input connection pin or
external clock input pin
OSCIN
K1
20
21
K1
20
21
1.5VI
OSCOUT
L1
L2
L1
L2
1.5V O
GND
Oscillator ouptut connection pin
Kelvin_GND for oscillator
Kelvin_GND
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TMS570LS10106
TMS570LS20216, TMS570LS20206, TMS570LS10216
TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
www.ti.com
Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
Type
Description
Name
337
144
337
144
System Module (SYS)
Power on Reset Pin. External power
supply monitor circuitry must assert a
power-on reset on this pin.
PORRST
W7
28
W7
28
3.3V I
Active Low Bidirectional Reset pin. An
external device can assert a device reset
on this pin.
The output buffer on this pin is
implemented as an open drain (drives
low only).
IPD
(100µA)
RST
B17
85
B17
85
4mA
8mA
3.3V I/O
To ensure an external reset is not
arbitrarily generated, TI recommends
that an external pullup resistor is
connected to this pin.
IPD
External Clock Prescaler module output
ECLK
TCK
A12
B18
88
30
A12
B18
88
30
(20µA) pin or GIO pin
Tset/Debug (T/D)
3.3V I
IPD
JTAG test clock pin. Clocks the JTAG
(100mA) debug logic.
RTCK
TDI
A16
A17
C18
35
34
33
A16
A17
C18
35
34
33
3.3V O
JTAG return test clock pin. (JTAG)
JTAG test data in pin.
JTAG test data out pin.
TDO
8 mA
3.3V I/O
JTAG serial input pin for controlling the
state of the CPU test access port (TAP)
controller.
TMS
C19
D18
36
29
C19
D18
36
29
IPU
(100mA)
JTAG test hardware reset to TAP. IEEE
Standard 1149-1 (JTAG) Boundary-Scan
Logic
TRST
3.3V I
Test enable pin. Reserved for internal TI
use only. For proper operation, this pin
must be connected to ground, e.g. using
a external resistor.
TEST
U2
58
U2
58
Error Signaling Module (ESM)
IPD
(20mA)
ERROR
B14
143
B14
143
3.3V I/O
8mA
Error Signaling pin
Flash
Flash Test Pad 1 pin. For proper
operation this pin must connect only to a
test pad or not be connected at all [no
connect (NC)]. The test pad must not be
exposed in the final product where it
might be subjected to an ESD event.
FLTP1
J5
122
J5
122
Flash Test Pad 2 pin. For proper
operation this pin must connect only to a
test pad or not be connected at all [no
connect (NC)]. The test pad must not be
exposed in the final product where it
might be subjected to an ESD event.
FLTP2
VCCP
H5
F8
123
128
H5
F8
123
128
Flash pump voltage supply (3.3 V). This
pin is required for Flash read, program
and erase operations.
3.3V
PWR
26
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TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141–MARCH 2010
Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
Type
Description
Name
337
144
337
144
RAM Trace Port Module (RTP)
RTPDATA[0]
RTPDATA[1]
RTPDATA[2]
RTPDATA[3]
RTPDATA[4]
RTPDATA[5]
RTPDATA[6]
RTPDATA[7]
RTPDATA[8]
RTPDATA[9]
RTPDATA[10]
RTPDATA[11]
RTPDATA[12]
RTPDATA[13]
RTPDATA[14]
RTPDATA[15]
RTPENA
V11
U11
T10
U10
T9
V11
U11
T10
U10
T9
U9
U8
U7
U6
U5
U4
T4
U9
U8
U7
U6
U5
U4
T4
RAM Trace Port Output Data Signal pins
or GIO pins
8mA
Program
mable
IPU
3.3V I/O
(20mA)
V3
V3
U3
T3
U3
T3
T2
T2
U12
U12
2mA - z
8mA
Packet Handshake Signal pin or GIO pin
Packet Synchronization Signal pin or
GIO pin
RTPSYNC
RTPCLK
T11
T11
W11
W11
Packet Clock Signal pin or GIO pin
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TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
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Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
Type
Description
Name
337
144
337
144
Data Modification Module (DMM)
DMMDATA[0]
DMMDATA[1]
L19
L18
L19
L18
DMM Data pins or GIO pins
DMMDATA[2]/MIB
SPI5CS[2]
2mA - z
W6
T12
H19
E19
B6
W6
T12
H19
E19
B6
DMMDATA[3]/MIB
SPI5CS[3]
DMMDATA[4]/MIB
SPI5CLK
4mA
DMMDATA[5]/MIB
SPI5CS[0]
DMMDATA[6]/MIB
SPI5CS[1]
2mA - z
DMMDATA[7]/MIB
SPI5ENA
H18
J19
E16
H17
G17
J18
E17
H16
G16
H18
J19
E16
H17
G17
J18
E17
H16
G16
DMMDATA[8]/MIB
SPI5SIMO[0]
Program
mable
IPU
DMM Data pins or GIO pins; multiplexed
with MIBSPI5 pins
DMMDATA[9]/MIB
SPI5SIMO[1]
3.3V I/O
(20mA)
DMMDATA[10]/MI
BSPI5SIMO[2]
DMMDATA[11]/MI
BSPI5SIMO[3]
4mA
DMMDATA[12]/MI
BSPI5SOMI[0]
DMMDATA[13]/MI
BSPI5SOMI[1]
DMMDATA[14]/MI
BSPI5SOMI[2]
DMMDATA[15]/MI
BSPI5SOMI[3]
DMMENA
DMMSYNC
DMMCLK
F16
J16
F17
F16
J16
F17
8mA
DMM Handshake pin or GIO pin
DMM Synchronization pin or GIO pin
DMM Clock input pin or GIO pin
2mA - z
28
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TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141–MARCH 2010
Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
337 144
Type
Description
Name
337
144
External Memory Interface Module (EMIF)
EMIFBADD[0]
EMIFBADD[1]
EMIFDATA[0]
EMIFDATA[1]
EMIFDATA[2]
EMIFDATA[3]
EMIFDATA[4]
EMIFDATA[5]
EMIFDATA[6]
EMIFDATA[7]
EMIFDATA[8]
EMIFDATA[9]
EMIFDATA[10]
EMIFDATA[11]
EMIFDATA[12]
EMIFDATA[13]
EMIFDATA[14]
EMIFDATA[15]
EMIFADD[0]
EMIFADD[1]
EMIFADD[2]
EMIFADD[3]
EMIFADD[4]
EMIFADD[5]
EMIFADD[6]
EMIFADD[7]
EMIFADD[8]
EMIFADD[9]
EMIFADD[10]
EMIFADD[11]
EMIFADD[12]
EMIFADD[13]
EMIFADD[14]
EMIFADD[15]
EMIFADD[16]
EMIFADD[17]
EMIFADD[18]
EMIFADD[19]
EMIFADD[20]
EMIFADD[21]
EMIFCS[0]
D13
D16
K16
L16
M16
N16
E4
D13
D16
K16
L16
M16
N16
E4
3.3V I/O
8mA
EMIF Byte Address pins
F4
F4
G4
G4
Program
mable
IPU
K4
K4
3.3V I/O
8mA
EMIF Data pins
L4
L4
(20mA)
M4
N4
M4
N4
P4
P4
T5
T5
T6
T6
T7
T7
T8
T8
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
C4
C4
C5
C5
C6
C6
C7
C7
C8
C8
3.3V I/O
8mA
EMIF Address pins
C9
C9
C10
C11
C12
C13
D14
C14
D15
C15
C16
C17
L17
K17
M17
N17
C10
C11
C12
C13
D14
C14
D15
C15
C16
C17
L17
K17
M17
N17
EMIFCS[1]
3.3V I/O
8mA
EMIF Chip Select pins
EMIFCS[2]
EMIFCS[3]
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Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
Type
Description
Name
EMIFWE
337
D17
D12
D10
D11
144
337
D17
D12
D10
D11
144
3.3V I/O
8mA
8mA
EMIF Write Enable pin
EMIFOE
3.3V I/O
EMIF Output Enable pin
EMIFDQM[0]
EMIFDQM[1]
3.3V I/O
8mA
EMIF Byte Enable pins
30
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TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141–MARCH 2010
Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
Type
Description
Name
337
144
337
144
Embedded Trace Module (ETM)
ETMDATA[0]
ETMDATA[1]
ETMDATA[2]
ETMDATA[3]
ETMDATA[4]
ETMDATA[5]
ETMDATA[6]
ETMDATA[7]
ETMDATA[8]
ETMDATA[9]
ETMDATA[10]
ETMDATA[11]
ETMDATA[12]
ETMDATA[13]
ETMDATA[14]
ETMDATA[15]
ETMDATA[16]
ETMDATA[17]
ETMDATA[18]
ETMDATA[19]
ETMDATA[20]
ETMDATA[21]
ETMDATA[22]
ETMDATA[23]
ETMDATA[24]
ETMDATA[25]
ETMDATA[26]
ETMDATA[27]
ETMDATA[28]
ETMDATA[29]
ETMDATA[30]
ETMDATA[31]
ETMTRACECTL
R12
R13
J15
H15
G15
F15
E15
E14
E9
R12
R13
J15
H15
G15
F15
E15
E14
E9
E8
E8
E7
E7
E6
E6
E13
E12
E11
E10
K15
L15
M15
N15
E5
E13
E12
E11
E10
K15
L15
M15
N15
E5
3.3V O
8mA
ETM Trace Data output pins
F5
F5
G5
G5
K5
K5
L5
L5
M5
M5
N5
N5
P5
P5
R5
R5
R6
R6
R7
R7
R8
R8
R11
R11
ETM Control pin
3.3V O
3.3V I
8mA
ETMTRACECLKO
UT
R10
R9
R10
R9
ETM Clock output pin
IPU
(20mA)
ETMTRACECLKIN
ETM Clock input pin
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TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
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Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
337 144
Type
Description
Name
337
144
Supply Voltage Digital I/O (3.3V) and Core (1.5V)
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCC
F6
F7
1
F6
F7
1
15
15
F11
F12
F13
F14
G6
40
F11
F12
F13
F14
G6
40
90
90
108
119
132
108
119
132
G14
H6
G14
H6
H14
J6
H14
J6
Digital I/O supply pins
Note: All VccIO pads are connected to
the BGA packages through the package
substrate. There is not a direct ball to
bond pad connection for this supply.
L14
M6
L14
M6
3.3V
PWR
M14
N6
M14
N6
N14
P6
N14
P6
P7
P7
P8
P8
P9
P9
P12
P13
P14
P12
P13
P14
F9
F10
H10
J14
K6
19
31
F9
F10
H10
J14
K6
19
31
VCC
VCC
37
37
VCC
47
47
VCC
87
87
Digital Core supply pins
VCC
K8
104
114
135
K8
104
114
135
Note: All Vcc pads are connected to the
BGA packages through the package
substrate. There is not a direct ball to
bond pad connection for this supply.
1.5V
PWR
VCC
K12
K14
L6
K12
K14
L6
VCC
VCC
VCC
M10
P10
P11
M10
P10
P11
VCC
VCC
VCC
32
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TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141–MARCH 2010
Table 2-8. Terminal Functions (continued)
Terminal
Internal
pullup/p
ulldown
TMS570LSXXX16
TMS570LSXXX06
Type
Description
Name
337
144
337
144
Supply Ground
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
A2
2
A1
A2
2
16
16
A18
A19
B1
22
A18
A19
B1
22
32
32
38
38
B19
H8
39
B19
H8
39
46
46
H9
86
H9
86
H11
H12
J8
89
H11
H12
J8
89
103
107
115
120
127
133
136
103
107
115
120
127
133
136
J9
J9
J10
J11
J12
K9
J10
J11
J12
K9
K10
K11
L8
K10
K11
L8
Digital supply ground reference pins
Note: All Vss pads are connected to the
BGA packages through the package
substrate.
GND
L9
L9
L10
L11
L12
M8
M9
M11
M12
V1
L10
L11
L12
M8
M9
M11
M12
V1
W1
W2
V4
W1
W2
V4
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SPNS141–MARCH 2010
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2.5 Device Support
2.5.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g.,TMS570LS20216ASPGEQQ1). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications.
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PGE), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz.
34
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TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141–MARCH 2010
Full Part #
TMS
S
570
5
LS 20
LS 20
2
2
16
16
A
A
S
S
PGE
PGE
Q
Q
Q1
Q1
R
R
Orderable Part #
Prefix: TM
S = Fully TMS Qualified
P = TMP Prototype
X = TMX Samples
Core Technology:
5 = 570 Cortex R4
Architecture:
LS = Lockstep CPUs
Flash Memory Size:
20 = 2MB
10 = 1MB
RAM Memory Size:
2 = 160kB
1 = 128kB
Peripheral Set:
16 = Flexray
06 = No Flexray
Die Revision:
Blank = Initial Die
A = 1st Die Revision
B = 2nd Die Revision
Technology/Core Voltage:
S = F035 (130nm), 1.5 V nominal core voltage
Package Type:
PGE = 144p QFP Package [Green]
ZWT = 337p BGA Package [Green]
Temperature Range:
I = -40...+85oC
T = -40...+105oC
Q = -40...+125oC
Quality Designator:
Q1 = Automotive
Shipping Options:
R = Tape and Reel
A. For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com).
Figure 2-7. Device Numbering Conventions(A)
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TMS570LS10206, TMS570LS10116, TMS570LS10106
SPNS141–MARCH 2010
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3 Reset / Abort Sources
3.1 Reset / Abort Sources
The device Resets and Aborts are handled as shown in the following table. The table shows the source of
the error, the system mode, the type of error response and the corresponding Error Signaling Module
(ESM) channel. Only standard ARM exception handlers and ESM errors are used.
Table 3-1. Reset / Abort Sources
Error Source
System Mode
Error Response
ESM Hookup group channel
1) CPU transactions
Precise write error (Strongly
Ordered)
User/Privilege
User/Privilege
User/Privilege
User/Privilege
User/Privilege
Precise Abort (CPU)
Precise Abort (CPU)
Imprecise Abort (CPU)
n/a
n/a
n/a
n/a
n/a
Precise read error (Device or
Normal)
Imprecise write error (Device or
Normal)
Illegal instruction
Undefined Instruction Trap
(CPU)(1)
MPU access violation
Abort (CPU)
2) SRAM
B0 Tightly Coupled Memory
(TCM) (even) ECC single error
(correctable)
User/Privilege
User/Privilege
ESM
1.26
B0 TCM (even) ECC double error
(non-correctable)
Abort (CPU), ESM => nERROR
ESM => NMI
ESM => nERROR
3.3
B0 TCM (even) uncorrectable
error (i.e. redundant address
decode)
User/Privilege
2.6
B0 TCM (even) address bus
parity error
User/Privilege
User/Privilege
User/Privilege
ESM => NMI
ESM
2.1
B1 TCM (odd) ECC single error
(correctable)
1.28
B1 TCM (odd) ECC double error
(non-correctable)
Abort (CPU), ESM => nERROR
ESM => nERROR
3.5
B1 TCM (odd) uncorrectable
error (i.e. redundant address
decode)
User/Privilege
ESM => NMI
ESM => NMI
2.8
B1 TCM (odd) address bus parity
error
User/Privilege
2.12
3) Flash with ECC INTEGRATED INTO CPU
ECC single error (correctable)
User/Privilege
User/Privilege
ESM
1.6
2.4
ECC double error
(non-correctable)
Abort (CPU), ESM => nERROR
ESM => nERROR
3.7
Uncorrectable error (i.e.
redundant address tag,
redundant syndrome
compare, address bus parity,
etc.)
User/Privilege
ESM => NMI
4) DMA transactions
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the Code reaches the execute stage of
the CPU.
36
Reset / Abort Sources
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TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141–MARCH 2010
Table 3-1. Reset / Abort Sources (continued)
Error Source
System Mode
Error Response
ESM Hookup group channel
External imprecise error on read
(Illegal transaction with ok
response)
User/Privilege
ESM
1.5
External imprecise error on write
(Illegal transaction with ok
response)
User/Privilege
ESM
1.13
Memory access permission
violation
User/Privilege
User/Privilege
ESM
ESM
1.2
1.3
Memory parity error
5) DMM transactions
External imprecise error on read
(Illegal transaction with ok
response)
User/Privilege
User/Privilege
ESM
ESM
1.5
External imprecise error on write
(Illegal transaction with ok
response)
1.13
6) AHB-AP transactions
External imprecise error on read
(Illegal transaction with ok
response)
User/Privilege
User/Privilege
ESM
ESM
1.5
External imprecise error on write
(Illegal transaction with ok
response)
1.13
7) HET TU
NCNB (Strongly Ordered)
transaction with slave error
response
User/Privilege
Interrupt => VIM
n/a
External imprecise error (Illegal
transaction with ok response)
User/Privilege
User/Privilege
User/Privilege
Interrupt => VIM
ESM
n/a
1.9
1.8
Memory access permission
violation
Memory parity error
8) NHET
ESM
Memory parity error
9) MibSPI
User/Privilege
ESM
1.7
MibSPI1 memory parity error
MibSPI3 memory parity error
MibSPIP5 memory parity error
10) MibADC
User/Privilege
User/Privilege
User/Privilege
ESM
ESM
ESM
1.17
1.18
1.24
MibADC1 memory parity error
MibADC2 memory parity error
11) DCAN
User/Privilege
User/Privilege
ESM
ESM
1.19
1.1
DCAN1 memory parity error
DCAN2 memory parity error
DCAN3 memory parity error
12) PLL
User/Privilege
User/Privilege
User/Privilege
ESM
ESM
ESM
1.21
1.23
1.22
PLL slip error
User/Privilege
User/Privilege
ESM
ESM
1.1
13) Clock monitor
Clock monitor interrupt
14) CCM
1.11
Self test failure
User/Privilege
User/Privilege
ESM
1.31
2.2
Compare failure
ESM => NMI
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Reset / Abort Sources
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Table 3-1. Reset / Abort Sources (continued)
Error Source
15) Flexray
System Mode
User/Privilege
User/Privilege
Error Response
ESM Hookup group channel
Memory parity error
ESM
1.12
n/a
16) Flexray TU
NCNB (Strongly Ordered)
transaction with slave error
response
Interrupt => VIM
External imprecise error (Illegal
transaction with ok response)
User/Privilege
User/Privilege
User/Privilege
Interrupt => VIM
ESM
n/a
Memory access permission
violation
1.16
1.14
Memory parity error
17) VIM
ESM
Memory parity error
18) voltage monitor
VMON out of voltage range
19) CPU Selftest (LBIST)
CPU Selftest (LBIST) error
User/Privilege
n/a
ESM
Reset
ESM
1.15
n/a
User/Privilege
1.27
n/a
20) errors reflected in the SYSESR register
Power-Up Reset; VCC out of
voltage range
n/a
Reset
Oscillator fail / PLL slip(2)
Watchdog time limit exceeded
CPU Reset
n/a
n/a
n/a
n/a
n/a
Reset
Reset
Reset
Reset
Reset
n/a
n/a
n/a
n/a
n/a
Software Reset
External Reset
(2) Oscillator fail/PLL slip can be configured in the system register PLLCTL1 to generate a reset.
38
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4 Peripherals
4.1 Error Signaling Module (ESM)
The Error Signaling Module (ESM) is used to indicate a severe device failure via interrupts and the
external ERROR pin. The error pin is normally used by an external device to either reset the controller
and/or keep the system in a fail safe state.
The ESM module consists of three error groups with 32 inputs each. The generation of the interrupts and
the activation of the ERROR Pin is shown in the following table. The next table shows the ESM error
sources and their corresponding group and channel numbers.
Table 4-1. ESM Groups
Error Group
Group1
Interrupt, Level
maskable, low/high
non-maskable, high
none, none
Influence on Error pin
configurable
fixed
Group2
Group3
fixed
Table 4-2. ESM Assignments
ERROR Sources
Group
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Channels
Reserved
MibADC2 - parity
0
1
DMA - MPU
2
DMA - parity
3
Reserved
4
DMA/DMM/AHB-AP - imprecise read error
Flash (ATCM) - correctable error
NHET - parity
5
6
7
HET TU - parity
8
HET TU - MPU
9
PLL - slip
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Clock Monitor - interrupt
Flexray - parity
DMA/DMM/AHB-AP - imprecise write error
Flexray TU - parity
VIM RAM - parity
Flexray TU - MPU
MibSPI1 - parity
MibSPI3 - parity
MibADC1 - parity
Reserved
DCAN1 - parity
DCAN3 - parity
DCAN2 - parity
MibSPIP5 - parity
Reserved
RAM even bank (B0TCM) - correctable error
CPU - selftest
RAM odd bank (B1TCM) - correctable error
Reserved
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Table 4-2. ESM Assignments (continued)
ERROR Sources
Group
Group1
Group1
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Channels
30
31
0
Reserved
CCM-R4 - selftest
Reserved
Reserved
1
CCM-R4 - compare
2
Reserved
3
Flash (ATCM) - uncorrectable error
4
Reserved
5
RAM even bank (B0TCM) - uncorrectable error
6
Reserved
7
RAM odd bank (B1TCM) - uncorrectable error
8
Reserved
9
RAM even bank (B0TCM) - address bus parity error
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
Reserved
RAM odd bank (B1TCM) - address bus parity error
Reserved
Reserved
Reserved
Flash (ATCM) - ECC live lock detect
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
Reserved
2
RAM even bank (B0TCM) - ECC uncorrectable error
3
Reserved
4
RAM odd bank (B1TCM) - ECC uncorrectable error
5
Reserved
6
Flash (ATCM) - ECC uncorrectable error
7
Reserved
Reserved
Reserved
Reserved
Reserved
8
9
10
11
12
40
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Table 4-2. ESM Assignments (continued)
ERROR Sources
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Group
Channels
13
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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4.2 Direct Memory Access (DMA)
The direct-memory access (DMA) controller transfers data to and from any specified location in the device
memory map. The DMA supports data transfer for both on-chip memories and peripherals.
The DMA controller on this device supports 16 channels and 32 request lines. Each of the 32 DMA
requests are assigned by default to one of the 32 available channels. For DMA requests multiplexed
between multiple sources, the DMA controller cannot differentiate between the multiple sources and the
user has to ensure that multiple sources are not enabled at the same time. Please refer to the DMA
Specification in the TRM for more details.
The DMA request configuration is shown in the following table.
Table 4-3. DMA Request Line Connection
Modules
MIBSPI1
DMA Request Sources
MIBSPI1[1](1)
DMA Request
DMAREQ[0]
DMAREQ[1]
DMAREQ[2]
DMAREQ[3]
DMAREQ[4]
DMAREQ[5]
DMAREQ[6]
DMAREQ[7]
DMAREQ[8]
DMAREQ[9]
DMAREQ[10]
DMAREQ[11]
DMAREQ[12]
DMAREQ[13]
DMAREQ[14]
DMAREQ[15]
DMAREQ[16]
MIBSPI1
MIBSPI1[0](2)
Reserved
Reserved
Reserved
Reserved
MIBSPI1 / MIBSPI3 / DCAN2
MIBSPI1 / MIBSPI3 / DCAN2
MIBSPIP5 / DCAN1
MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3
MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2
MIBSPIP5[2] / DCAN1 IF2
MIBADC1 / MIBSPIP5
MIBSPI1 / MIBSPI3 / DCAN1
MIBSPI1 / MIBSPI3 / DCAN2
MIBADC1 / MIBSPIP5
MIBADC1 / MIBSPIP5
RTI / MIBSPI1 / MIBSPI3
RTI / MIBSPI1 / MIBSPI3
MIBADC2 / MIBSPI3 / MIBSPIP5
MIBSPI3 / MIBSPIP5
MIBADC2 / MIBSPI1 / MIBSPI3 / DCAN1
MIBADC1 event / MIBSPIP5[3]
MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1
MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1
MIBADC1 G1 / MIBSPIP5[4]
MIBADC1 G2 / MIBSPIP5[5]
RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6]
RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7]
MIBADC2 event / MIBSPI3[1]* / MIBSPIP5[6]
MIBSPI3[0]† / MIBSPIP5[7]
MIBADC2 G1 / MIBSPI1[8] / MIBSPI3[8] / DCAN1
IF3
MIBADC2 / MIBSPI1 / MIBSPI3 / DCAN3
MIBADC2 G2 / MIBSPI1[9] / MIBSPI3[9] / DCAN3
IF1
DMAREQ[17]
RTI / MIBSPIP5
RTI / MIBSPIP5
RTI DMAREQ2 / MIBSPIP5[8]
RTI DMAREQ3 / MIBSPIP5[9]
DMAREQ[18]
DMAREQ[19]
DMAREQ[20]
DMAREQ[21]
DMAREQ[22]
DMAREQ[23]
DMAREQ[24]
DMAREQ[25]
DMAREQ[26]
DMAREQ[27]
DMAREQ[28]
DMAREQ[29]
DMAREQ[30]
DMAREQ[31]
LIN2 / NHET / DCAN3
LIN2 / NHET / DCAN3
MIBSPI1 / MIBSPI3 / MIBSPIP5
MIBSPI1 / MIBSPI3 / MIBSPIP5
NHET / MIBSPIP5
LIN2 receive / NHET DMAREQ[4] / DCAN3 IF2
LIN2 transmit / NHET DMAREQ[5] / DCAN3 IF3
MIBSPI1[10] / MIBSPI3[10] / MIBSPIP5[10]
MIBSPI1[11] / MIBSPI3[11] / MIBSPIP5[11]
NHET DMAREQ[6] / MIBSPIP5[12]
NHET / MIBSPIP5
NHET DMAREQ[7] / MIBSPIP5[13]
CRC / MIBSPI1 / MIBSPI3
CRC / MIBSPI1 / MIBSPI3
LIN1 / MIBSPIP5
CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12]
CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13]
LIN1 receive / MIBSPIP5[14]
LIN1 / MIBSPIP5
LIN1 transmit / MIBSPIP5[15]
MIBSPI1 / MIBSPI3 / MIBSPIP5
MIBSPI1 / MIBSPI3 / MIBSPIP5
MIBSPI1[14] / MIBSPI3[14] / MIBSPIP5[1]*
MIBSPI1[15] / MIBSPI3[15] / MIBSPIP5[0]†
(1) SPI1, SPI3, SPI5 receive in standard SPI/compatibility mode
(2) SPI1, SPI3, SPI5 transmit in standard SPI/compatibility mode
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4.3 High End Timer Transfer Unit (HET-TU)
The High End Timer Transfer Unit (HET-TU) is a local Direct Memory Access (DMA) module. It is
specifically designed to transfer High End Timer (NHET) data to (or from) the CPU data SRAM . The HET
software controls which HET instructions generate transfer requests to the transfer unit. More information
about the NHET and the HET-TU can be found in the technical reference manual (TRM). The HET-TU
supports 8 channels.
The HET-TU request assignment is shown in the following table.
Table 4-4. NHET Request Line Connection
Modules
NHET
NHET
NHET
NHET
NHET
NHET
NHET
NHET
Request Source
HTUREQ[0]
HTUREQ[1]
HTUREQ[2]
HTUREQ[3]
HTUREQ[4]
HTUREQ[5]
HTUREQ[6]
HTUREQ[7]
HET TRANSFER UNIT Request
HET TU DCP[0]
HET TU DCP[1]
HET TU DCP[2]
HET TU DCP[3]
HET TU DCP[4]
HET TU DCP[5]
HET TU DCP[6]
HET TU DCP[7]
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4.4 Vectored Interrupt Manager (VIM)
The Vectored Interrupt Manager (VIM) provides hardware assistance for prioritizing and controlling the
many interrupt sources present on the device. Interrupt requests originating from the device modules (i.e.,
SPI, LIN, SCI, etc.) are assigned to channels within the 64-channel VIM. Programming multiple interrupt
sources to the same VIM channel effectively shares the VIM channel between sources. The VIM request
channels are maskable so that individual channels can be selectively disabled. All interrupt requests can
be programmed in the VIM to be of either type:
•
•
•
Fast interrupt request (FIQ)
Normal interrupt request (IRQ)
Non maskable interrupt (NMI) - Programmable via CPU CP15 register setting
The VIM prioritizes interrupts, whose precedence of request channels decrease with ascending channel
order in the VIM (0 [highest] and 64[lowest] priority). For VIM default mapping, channel priorities, and their
associated modules see the table below. More information on the VIM can be found in the technical
reference manual (TRM).
Table 4-5. Interrupt Request Assignments
Modules
ESM
Interrupt Sources
ESM High level interrupt (NMI)
(NMI)
Default VIM Interrupt Request
0
Reserved
RTI
1
RTI compare interrupt 0
RTI compare interrupt 1
RTI compare interrupt 2
RTI compare interrupt 3
RTI overflow interrupt 0
RTI overflow interrupt 1
RTI timebase
2
RTI
3
RTI
4
RTI
5
RTI
6
RTI
7
RTI
8
GIO
GIO interrupt A
9
NHET
NHET level 1 interrupt
HET TU level 1 interrupt
MIBSPI1 level 0 interrupt
LIN1 level 0 interrupt
MIBADC1 event group interrupt
MIBADC1 sw group 1 interrupt
DCAN1 level 0 interrupt
Reserved
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
HET TU
MIBSPI1
LIN1 (incl. SCI)
MIBADC1
MIBADC1
DCAN1
Reserved
Flexray
CRC
Flexray level 0 interrupt
CRC Interrupt
ESM
ESM Low level interrupt
Software interrupt (SSI)
PMU Interrupt
SYSTEM
CPU
GIO
GIO interrupt B
NHET
NHET level 2 interrupt
HET TU level 2 interrupt
MIBSPI1 level 1 interrupt
LIN1 level 1 interrupt
MIBADC1 sw group 2 interrupt
DCAN1 level 1 interrupt
Reserved
HET TU
MIBSPI1
LIN1 (incl. SCI)
MIBADC1
DCAN1
Reserved
MIBADC1
MIBADC1 magnitude interrupt
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Table 4-5. Interrupt Request Assignments (continued)
Modules
Flexray
Interrupt Sources
Flexray level 1 interrupt
FTCA interrupt
Default VIM Interrupt Request
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
DMA
DMA
LFSA interrupt
DCAN2
DCAN2 level 0 interrupt
DMM level 0 interrupt
MIBSPI3 level 0 interrupt
MIBSPI3 level 1 interrupt
HBCA interrupt
DMM
MIBSPI3
MIBSPI3
DMA
DMA
BTCA interrupt
Reserved
DCAN2
Reserved
DCAN2 level 1 interrupt
DMM level 1 interrupt
DCAN1 IF3 interrupt
DCAN3 level 0 interrupt
DCAN2 IF3 interrupt
FPU interrupt
DMM
DCAN1
DCAN3
DCAN2
FPU
Flexray TU
LIN2 (incl. SCI)
MIBADC2
MIBADC2
Flexray
Flexray TU Transfer Status interrupt
LIN2 level 0 interrupt
MIBADC2 event group interrupt
MIBADC2 sw group 1 interrupt
Flexray T0C interrupt
MIBSPIP5 level 0 interrupt
LIN2 level 1 interrupt
DCAN3 level 1 interrupt
MIBSPIP5 level 1 interrupt
MIBADC2 sw group 2 interrupt
Flexray TU Error interrupt
MIBADC2 magnitude interrupt
DCAN3 IF3 interrupt
Reserved
MIBSPIP5
LIN2 (incl. SCI)
DCAN3
MIBSPIP5
MIBADC2
Flexray TU
MIBADC2
DCAN3
Reserved
Flexray
Flexray T1C interrupt
Reserved
Reserved
Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry.
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4.5 MIBADC Event Trigger Sources
All three conversion groups can be configured for event-triggered operation, providing up to three event
triggered groups.
The trigger source and polarity can be selected individually for group 1, group 2 and the event group from
the options identified in the first table following for MibADC1 and in the second table following for
MibADC2.
Table 4-6. MIBADC1 Event Trigger Sources
Event #
SOURCE SELECT BITS for G1, G2 or
EVENT (G1SRC[2:0], G2SRC[2:0] or
EVSRC[2:0])
Hookup
1
2
3
4
5
6
7
8
0
AD1EVT
NHET[8]
1
10
NHET[10]
RTI compare 0
NHET[17]
NHET[19]
GIOB[0]
11
100
101
110
111
GIOB[1]
NOTE
The Trigger is present, even if the pin is not available.
Table 4-7. MIBADC2 Event Trigger Sources
Event #
SOURCE SELECT BITS for G1, G2 or
EVENT (G1SRC[2:0], G2SRC[2:0] or
EVSRC[2:0])
Hookup
1
2
3
4
5
6
7
8
0
AD2EVT
NHET[8]
1
10
NHET[10]
RTI compare 0
NHET[17]
NHET[19]
GIOB[0]
11
100
101
110
111
GIOB[1]
NOTE
The Trigger is present, even if the pin is not available.
The application can generate the trigger condition using these signals by configuring the corresponding
device pins as input pins and driving them from an external source, or by configuring them as output pins
and driving them by software. The pin doesn't have to be present on the package to be able to be used as
a trigger.
The interrupt request signals (RTI compare 0) are driven HIGH when the interrupt condition occurs. So if
the ADC is required to be triggered on the interrupt being asserted, select the rising edge for this trigger
source. The ADC can be still triggered using the falling edge on the interrupt line. In this case, the falling
edge occurs when the interrupt line is deasserted.
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4.6 MIBSPI
4.6.1 MIBSPI Event Trigger Sources
The Multi-buffered Serial Peripheral Interfaces (MIBSPIs) have a programmable buffer memory that
enables data transmission to be completed without CPU intervention. The buffers are combined in
different Transfer Groups (TGs) that can be triggered by external events such as I/O activity, timers or by
the internal tick counter. The internal tick counter supports the periodic trigger of events. Each buffer of the
MibSPI can be associated with different DMA channels in different TGs, allowing the user to move data
between internal memory and an external slave with minimal CPU interaction.
Table 4-8. MIBSPI1 Event Trigger Sources
Event
TGxCTRL TRIGSRC[3:0]
Hookup
No trigger source
GIOA[0]
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
0
1
10
GIOA[1]
11
GIOA[2]
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
NHET[8]
NHET[10]
NHET[12]
NHET[14]
NHET[16]
NHET[18]
Internal Tick counter
Table 4-9. MIBSPI3 Event Trigger Sources
Event
TGxCTRL TRIGSRC[3:0]
Hookup
No trigger source
GIOA[0]
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
0
1
10
GIOA[1]
11
GIOA[2]
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
NHET[8]
NHET[10]
NHET[12]
NHET[14]
NHET[16]
NHET[18]
Internal Tick counter
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Table 4-10. MIBSPI5 Event Trigger Sources
Event
TGxCTRL TRIGSRC[3:0]
Hookup
No trigger source
GIOA[0]
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
0
1
10
GIOA[1]
11
GIOA[2]
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
NHET[8]
NHET[10]
NHET[12]
NHET[14]
NHET[16]
NHET[18]
Internal Tick counter
4.6.2 MIBSPIP5/DMM Pin Multiplexing
The multiplexing of MIBSPIP5 and DMM pins are controlled by the status of the MIBSPIP5 module and
the DMM module. The pins will have DMM functionality if the DMM module is enabled and the MIBSPIP5
module is disabled; if the MIBSPIP5 is enabled the pins will have MIBSPI functionality, regardless of the
DMM module status. DMMCLK, DMMSYNC, DMMENA and DMMDATA[1:0] are always functional
independent of the MIBSPIP5 configuration because they are not multiplexed. The related pin numbers
can be found in the MIBSPI5 and the DMM section of the Terminal Functions chapter. The following table
shows the MIBSPI5 and DMM Data pin multiplexing.
Table 4-11. MIBSPIP5 Pin Multiplexing
MIBSPIP5 enabled
MIBSPI5CLK
DMM enabled &MIBSPIP5 disabled
DMMDATA[4]
MIBSPI5CS[0]
DMMDATA[5]
MIBSPI5CS[1]
DMMDATA[6]
MIBSPI5CS[2]
DMMDATA[2]
MIBSPI5CS[3]
DMMDATA[3]
MIBSPI5ENA
DMMDATA[7]
MIBSPI5SIMO[0]
MIBSPI5SIMO[1]
MIBSPI5SIMO[2]
MIBSPI5SIMO[3]
MIBSPI5SOMI[0]
MIBSPI5SOMI[1]
MIBSPI5SOMI[2]
MIBSPI5SOMI[3]
DMMDATA[8]
DMMDATA[9]
DMMDATA[10]
DMMDATA[11]
DMMDATA[12]
DMMDATA[13]
DMMDATA[14]
DMMDATA[15]
48
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4.7 ETM
The device contains an ARM Cortex™-R4F External Trace Macrocell (ETM-R4) with a 32bit data port. The
ETM-R4 module is connected to a Test Port Interface Unit (TPIU) with a 32bit data bus. The ETM-R4 is
CoreSight compliant and follows the ARM ETM v3 specification; for more details see ARM CoreSight™
ETM-R4 TRM specification Revr0p0. The ETM-R4 supports "half rate clocking" only.
The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The
selection is done by the EXTCTRLOUT[1:0] control bits of the TPIU; the default is '00'.
Table 4-12. ETMTRACECLKIN Selection
EXTCTRLOUT[1:0]
TPIU/TRACECLKIN
tied-low
0
1
VCLK
10
11
ETMTRACECLKIN
tied-zero
4.8 Debug Scan Chains
The device contains an ICEPICK module to access the debug scan chains. Debug scan chain #0 handles
the access to the CPU, to the ETM-R4 (External Trace Macrocell), to the POM (Parameter Overlay
Module) and to the TPIU (Test Port Interface Unit). Debug scan chain #1 handles the access to the Ram
Trace Port (RTP) and the Data Modification Module (DMM) which each incorporate a dedicated TAP (Test
Access Port) controller. Each module is selected via its scan chain number. The IcePick scan ID is
0x80206D05, which is the same number as the device ID.
DAP
CPU
ETM
POM
TPIU
CoreSight
debug scan chain #0
TDI
RTP
RTP TAP
0
1
TDO
DMM
DMM TAP
debug scan chain #1
Boundary
Scan
boundary scan interface
Figure 4-1. Debug Scan Chains
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4.8.1 JTAG
The 32bit JTAG ID code for this device is 0x0B7B302F.
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4.9 CCM
4.9.1 Dual Core Implementation
The microcontroller has two Cortex-R4 cores, where the output signals of both CPUs are compared in the
CCM-R4 (Core Compare Module). To avoid common mode impacts the signals of the CPUs to be
compared are delayed in a different way as shown in the following figure..
CCM-R4
1.5cycle delay
CCM-R4
Compare
Compare
Error
CPU1CLK
CPU 2
CPU 1
1.5cycle delay
CPU2CLK
Figure 4-2. Dual Core Implementation
4.9.2 CCM-R4
To avoid an erroneous CCM-R4 compare error, the application software must ensure that the CPU
registers of both CPUs are initialized with the same values before the 1st function call or other operation
that pushes the CPU registers onto the stack. All CCM-R4 error forcing test modes are limited to 100MHz
HCLK speed.
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4.10 LPM
TMS570 Platform devices support multiple low power modes. These different modes allow the user to
trade-off the amount of current consumption during low power mode versus functionality and wake-up
time.
Supported Low Power modes on this devices are Doze, Snooze and Sleep; for detailed description please
refer to the Architecture section of the Technical Reference Manual.
4.11 Voltage Monitor
A voltage monitor has been implemented on this device. The purpose of this voltage monitor is to
eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies. It
also reduces the risk of corrupting memory or glitches on I/O pins during power-up, power-down or brown
outs. The voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the
device is held in reset when the voltage supplies are out of range. The voltage monitor thresholds can be
found in the Vmon section of the device electrical specifications.
When the voltage monitor detects a low voltage on the I/O supply, it will assert a reset. When the voltage
monitor detects a low voltage on the core supply, it asynchronously makes all output pins high impedance,
and asserts a reset. The voltage monitor is disabled when the device is in halt mode.
The voltage monitor has three filter functions:
•
•
•
It rejects short low-going glitches on the PORRST pin
It rejects noise on the VCCIO supply
It rejects noise on the VCC supply
Please note that such glitches on VCC and VCCIO could still corrupt the system depending on many
factors. The width of noise that can be filtered by the voltage monitor on the VCC and VCCIO supplies is
shown in the table below. The duration of glitches that will be filtered on the PORRST pin can be found in
Table 7-5, Timing Requirements for PORRST.
Table 4-13. VMON Supply Glitch Filter Capability
Parameter
Min
Max
1us
1us
Width of glitch on VCC that can be filtered out
Width of glitch on VCCIO that can be filtered out
250ns
300ns
4.12 CRC
MCRC Controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the
integrity of memory system. A signature representing the contents of the memory is obtained when the
contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to
calculate the signature for a set of data and then compare the calculated signature value against a
pre-determined good signature value. MCRC controller provides up to four channels to perform CRC
calculation on multiple memories in parallel and can be used on any memory system. Channel 1 can also
be put into data trace mode. In data trace mode, MCRC controller compresses each data being read
through the CPU read data bus.
When using the MCRC module in PSA mode while ECC is enabled, bus masters (e.g. FTU, HTU, DMA or
CPU) should not write to the data RAM (TCRAM) to avoid corrupting the PSA value.
4.13 System Module
The system module access modes and access rights are shown in the following table.
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Table 4-14. System Module Access
Domain
Module
Access Mode Used by Module
Access Rights Required to
Access the Module RAMS
System
System
VIM
RTP
DMA
HTU
FTU
n/a
n/a
privilege mode (RWP)
privilege mode (RWP)
privilege mode (RWP)
privilege mode (RWP)
user & privilege mode (RW)
System
user mode
Peripheral
Peripheral
privilege mode
user & privilege mode
4.14 Debug ROM
The Debug ROM stores the location of the components on the Debug APB bus.
Table 4-15. Debug ROM Table
Address
Components Table
0x000
Description
Value
pointer to Cortex-R4
ETM
0x00001003
0x00002003
0x00003003
0x00004003
0x00000000
0x000
0x000
TPIU
0x000
POM
0x001
end of table
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4.15 CPU Self Test Controller: STC / LBIST
The CPU Self Test Controller (STC) is used to test the ARM CPU core using a Deterministic Logic BIST
(LBIST) Controller as the test engine. The STC has the capability of dividing the complete test run into
smaller independent test sets (intervals). The test coverage and number of test execution cycles for each
test interval is shown in the table below.
The maximum clock rate for the STC / LBIST is:
•
•
•
53.333MHz when HCLK = 160MHz / VCLK = 80MHz on BGA package
50MHz when HCLK = 100MHz / VCLK = 100MHz on QFP and BGA packages
46.666MHz when HCLK = 140MHz / VCLK = 70MHz on QFP and BGA packages
In order to achieve the proper clock rate during CPU self test a STC clock divider has been implemented.
The clock divider is set by the CLKDIV bits in STCCLKDIV register in the secondary system module frame
at location 0xFFFF E108. The default value of the CPU Self Test LBIST clock divider is set to divide-by-1’.
NOTE
The supply current while performing CPU self test is different than the device operating
mode current. These values can be found in the Icc section of the device electrical
specifications.
Table 4-16. STC/LBIST Test Coverage and Duration
Intervals
0
Test Coverage
0
Test Cycles
0
1
57,14
65,82
70,56
73,56
76,06
78,07
79,62
80,92
82,1
1555
2
3108
3
4661
4
6214
5
7767
6
9320
7
10873
12426
13979
15532
17085
18638
20191
21744
23297
24850
26403
27956
29509
31062
32615
34168
35721
37274
38827
40380
41933
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
82,94
83,76
84,51
85,12
85,62
86,19
86,56
86,97
87,33
87,67
88,01
88,31
88,58
88,87
89,11
89,34
89,59
89,82
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Table 4-16. STC/LBIST Test Coverage and Duration (continued)
Intervals
Test Coverage
90,05
Test Cycles
43486
28
29
30
31
32
90,26
45039
90,46
46592
90,64
48145
90,84
49698
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5 Device Registers
5.1 Device Identification Code Register
The device identification code register identifies several aspects of the device including the silicon version.
The details of the device identification code register are shown in Figure 11. The device identification code
register value for this device is:
•
•
Rev 0 = 0x80206D05
Rev A = 0x80206D0D
Figure 5-1. Device ID Bit Allocation Register
31
CP-15
R-1
30
29
13
28
27
26
25
24
23
22
21
20
19
3
18
17
16
16
UNIQUE ID
R-00000 0000 10000
R-0
15
14
12
11
10
9
8
7
6
5
4
2
1
1
0
0
1
TECH
I/O
PERIP
FLASH ECC
R-10
RAM
ECC
VERSION
VOLT HERA
AGE
L
PARIT
Y
R-0
R-0
R-1
R-1
R-1
R-1
R-0
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device dependent
Table 5-1. Device ID Bit Allocation Register Field Descriptions
Bit
Field
Value Description
31
CP15
Indicates the presence of coprocessor 15
CP15 not present
0
1
1
CP15 present
30-17 UNIQUE ID
16-13 TECH
Silicon version (revision) bits This bitfield holds a unique number for a dedicated device configuration
(die).
Process technology on which the device is manufactured.
0000 C05
0001 F05
0010 C035
0011 F035
Others Reserved
12
11
I/O
VOLTAGE
I/O voltage of the device.
I/O are 3.3v
0
1
I/O are 5v
PERIPHERA
L PARITY
Peripheral Parity
0
1
No parity on peripherals
Parity on peripherals
10-9
FLASH ECC
Flash ECC
00
01
10
11
No error detection/correction
Program memory with parity
Program memory with ECC
Reserved
8
RAM ECC
Indicates if RAM memory ECC is present.
No ECC implemented
ECC implemented
0
1
56
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Table 5-1. Device ID Bit Allocation Register Field Descriptions (continued)
Bit
7-3
2-0
Field
Value Description
Revision of the Device.
The platform family ID is always 0b101
REVISION
101
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5.2 Die-ID Registers
The two registers (DIEIDL and DIEIDH) form a 64-bit number that contains information about the device’s
die lot number, wafer number and X, Y wafer coordinates. The die identification information will vary from
unit to unit. This information is programmed by TI as part of the initial device test procedure. The data
format of the Die-ID registers is shown here.
Figure 5-2. DIEIDL Register (Location: 0xFFFF FF7C)
31
15
30
14
29
13
28
12
27
26
25
9
24
8
23
7
22
6
21
20
19
WAFER #
R-D
18
17
1
16
0
LOT (LOWER 10 BITS)
R-D
11
10
5
4
3
2
Y WAFER COORDINATES
R-D
X WAFER COORDINATES
R-D
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device dependent
Figure 5-3. DIEIDH Register (Location: 0xFFFF FF80)
31
15
30
14
29
13
28
12
27
26
25
24
23
22
21
20
19
18
2
17
1
16
0
RESERVED
R-D
11
10
9
8
7
6
5
4
3
RESERVED
LOT # (UPPER 14 BITS)
R-D
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device dependent
58
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5.3 PLL Registers
The default values for the PLL (Phase Locked Loop) control registers are shown in this section. PLLCTL1
and PLLCTL2 are used to configure PLL1 (F035 FMzPLL) and PLLCTL3 is used to configure PLL2 (F035
FPLL).
Figure 5-4. PLLCTL1 Register (Location: 0xFFFF FF70)
31
30
29
28
27
26
25
23
223
RESERVED
R-0
21
20
19
18
17
1
16
0
ROS
BPOS[1:0]
R/WP-01
PLLDIV[4:0]
R/WP-111
ROF
REFCLKDIV[5:0]
R/WP-000010
R/WP-
0
R/WP-
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
PLLMUL[15:0]
R/WP-01011111000000000101
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device specific
Figure 5-5. PLLCTL2 Register (Location: 0xFFFF FF74)
31
30
29
28
12
27
26
25
24
23
22
21
20
19
18
17
16
FMEN
A
SPREADINGRATE[8:0]
RESV
EWADJ[8:4]
R/WP-
0
R/WP-111111111
R-0
R/WP-00000
2
15
14
13
11
10
9
8
7
6
5
4
3
1
0
BWADJ[3:0]
R/WP-0111
ODPLL
R/WP-001
SPR_AMOUNT[8:0]
R/WP-000000000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D = device specific
NOTE
There are several combinations of the modulation depth and modulation frequency that are
not allowed. Valid settings for this device include the following: TBD
Figure 5-6. PLLCTL3 Register (Location: 0xFFFF E100)
31
15
30
14
29
13
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
OSC
DIV
RESERVED
R/W-000000000
R/WP-
0
R/W-000000
12
11
10
9
PLL_MUL[3:0]
R/WP-011
8
7
6
5
4
3
2
1
0
RESERVED
R/W-000000
RESERVED
R/W-00000
PLL_DIV [2:0]
R/WP 111
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device specific
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Device Registers
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6 Device Electrical Specifications
6.1 Operating Conditions
6.2 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless
otherwise noted)(1)
(2)
Supply voltage ranges
VCC
- 0.3 V to 2.1V
VCCIO, VCCAD, VCCP (Flash pump) (see Note 1) - 0.3 V to 4.1V
Input voltage range
Input clamp current
All input pins
- 0.3 V to 4.1 V
±20 mA
IIK(VI<0 or VI> VCCIO
)
All pins except AD1IN[7:0], AD2IN[7:0],
ADSIN[15:8]
IIK (VI<0 or VI>VCCAD
)
AD1IN[7:0], AD2IN[7:0], ADSIN[15:8]
±10 mA
total
±40 mA
Operating free-air temperature
ranges, TA
A version
T version
Q version
- 40°C to 85°C
- 40°C to 105°C
- 40°C to 125°C
-40°C to 150°C
Operating junction temperature range,
TJ
Storage temperature range, Tstg
- 65°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
(2) All voltage values are with respect to their associated grounds.
6.3 Device Recommended Operating Conditions(1)
MIN
1.35
NOM
1.5
MAX
1.65
Unit
V
VCC
Digital logic supply voltage (Core)
Digital logic supply voltage (I/O)
MibADC supply voltage
VCCIO
VCCAD
VCCP
VSS
3
3
3
3.3
3.3
3.3
0
3.6
3.6
3.6
V
V
Flash pump supply voltage
Digital logic supply ground
MibADC supply ground
V
V
VSSAD
TA
-0.1
-40
-40
-40
-40
0.1
85
V
Operating free-air temperature
A version
T version
Q version
°C
°C
°C
°C
105
125
150
TJ
Operating junction temperature
(1) All voltages are with respect to VSS except VCCAD is with respect to VSSAD
.
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6.4 Electrical Characteristics Over Operating Free-Air Temperature Range(1)
Parameter
Test Conditions
MIN
0.15
-0.3
2
TYP
MAX
Unit
V
Vhys
VIL
Input hysteresis
Low-level input voltage All inputs(2)
0.8
V
VIH
High-level input voltage All inputs
VCCIO
0.3
+
V
VOL
Low-level output voltage
High-level output voltage
IOL = IOL MAX
IOL = 50 µA
0.2 VCCIO
0.2
V
V
VOH
IOH = IOH MAX
IOH = 50 µA
0.8 VCCIO
VCCIO
0.2
-
VILoscin
VIHoscin
VMON
Low-level input voltage OSCIN
High-level input voltage OSCIN
-0.3
0.2 VCC
VCC + 0.3
1.35
V
V
V
0.8 VCC
1.1
Voltage monitoring
threshold
VCC low
1.2
2
VCC high
VCCIO low
1.7
2.38
2.0
2.4
3.0
IIC
II
Input clamp current
VI < VSSIO - 0.3 or VI
> VCCIO + 0.3
-2
2
mA
µA
Input current (I/O pins) IIL Pulldown
VI = VSS
-1
5
1
IIH Pulldown 20 mA VI = VCCIO
40
IIH Pulldown 100
VI = VCCIO
40
195
mA
IIL Pullup 20 mA
IIL Pullup 100 mA
IIH Pullup
VI = VSS
-40
-195
-1
-5
-40
1
VI = VSS
VI = VCCIO
All other pins
No pullup or pulldown
-1
1
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) This does not apply to PORRST pin.
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(1)
Electrical Characteristics Over Operating Free-Air Temperature Range
(continued)
Parameter
Test Conditions
MIN
TYP
MAX
Unit
IOL
Low-level output
current
TDO
VOL = VOL MAX
8
mA
TDI
TMS
RTCK
ECLK
FRAYRX1
FRAYTX1
FRAYTXEN1
FRAYRX2
FRAYTX2
FRAYTXEN2
DMMENA
ETMTRACECTL
ETMTRACECLKO
UT
ETMDATA[31:0]
RTPSYNC
RTPCLK
RTPDATA[15:0]
DMMENA
EMIFWE
EMIFOE
EMIFCS[3:0]
EMIFDATA[15:0]
EMIFADD[21:0]
EMIFBADD[1:0]
EMIFDQM[1:0]
ERROR
IOL
Low-level output
current
RST
VOL = VOL MAX
4
mA
MIBSPI1CLK
MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI3CLK
MIBSPI3SIMO
MIBSPI3SOMI
MIBSPI5CLK
MIBSPI5SIMO[3:0]
MIBSPI5SOMI[3:0]
DMMDATA[15:8]
DMMDATA[4]
All other output
pins
2
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SPNS141–MARCH 2010
(1)
Electrical Characteristics Over Operating Free-Air Temperature Range
(continued)
Parameter
Test Conditions
MIN
TYP
MAX
Unit
IOH
High-level output
current
TDO
VOH = VOH MIN
-8
mA
TDI
TMS
RTCK
ECLK
FRAYRX1
FRAYTX1
FRAYTXEN1
FRAYRX2
FRAYTX2
FRAYTXEN2
DMMENA
ETMTRACECTL
ETMTRACECLKO
UT
ETMDATA[31:0]
RTPSYNC
RTPCLK
RTPDATA[15:0]
DMMENA
EMIFWE
EMIFOE
EMIFCS[3:0]
EMIFDATA[15:0]
EMIFADD[21:0]
EMIFBADD[1:0]
EMIFDQM[1:0]
ERROR
IOH
High-level output
current
RST
VOH = VOH MIN
-4
mA
MIBSPI1CLK
MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI3CLK
MIBSPI3SIMO
MIBSPI3SOMI
MIBSPI5CLK
MIBSPI5SIMO[3:0]
MIBSPI5SOMI[3:0]
DMMDATA[15:8]
DMMDATA[4]
All other output
pins
-2
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Device Electrical Specifications
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(1)
Electrical Characteristics Over Operating Free-Air Temperature Range
(continued)
Parameter
Test Conditions
MIN
TYP
MAX
Unit
(3)
ICC
VCC Digital supply
current (Operating
mode)
All packages
HCLK = 100MHz,
VCLK = 100MHz
350
mA
HCLK = 140MHz,
VCLK= 70MHz
390
430
450
500
550
320
400
35
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
BGA packages
All packages
HCLK = 160MHz,
VCLK = 80MHz
VCC Digital supply
current (CPU selftest
mode: LBIST)
LBIST (STC) CLK =
46.666MHz
LBIST (STC) CLK =
50.0MHz
BGA packages
All packages
LBIST (STC) CLK =
53.333MHz
VCC Digital supply
current (Mem selftest
mode: PBIST)
HCLK=80MHz,
VCLK=40MHz
HCLK=100MHz,
VLCK=100MHz
VCC Digital supply current (doze mode)
VCC Digital supply current (snooze mode)
VCC Digital supply current (sleep mode)
OSCIN = 6 MHz, VCC
= 1.65 V(4)
All frequencies, VCC
1.65 V(4)
=
30
All frequencies, VCC
1.65 V(4)
=
10
ICCIO
ICCAD
ICCP
VCCIO Digital supply current (operating mode) No DC load, VCCIO
3.6 V(5)
=
=
=
=
15
VCCIO Digital supply current (doze mode)
VCCIO Digital supply current (snooze mode)
VCCIO Digital supply current (sleep mode)
VCCAD supply current (operating mode)
VCCAD supply current (doze mode)
VCCAD supply current (snooze mode)
VCCAD supply current (sleep mode)
VCCP pump supply current
No DC load, VCCIO
3.6 V(5)
100
100
100
30
No DC load, VCCIO
3.6 V(5)
No DC load, VCCIO
3.6 V(5)
All frequencies, VCCAD
= 3.6 V
All frequencies, VCCAD
= 3.6 V(6)
10
All frequencies, VCCAD
= 3.6 V(6)
10
All frequencies, VCCAD
= 3.6 V(6)
10
VCCP = 3.6 V read
operation
25
VCCP = 3.6 V
program(7)
90
VCCP = 3.6 V erase
90
5
mA
mA
VCCP = 3.6 V doze
mode(6)
VCCP = 3.6 V snooze
mode(6)
5
5
mA
mA
pF
VCCP = 3.6 V sleep
mode(6)
CI
Input capacitance(8)
2
(3) Typical values are at Vcc=1.5V and maximum values are at Vcc=1.65V
(4) For Flash banks/pumps in sleep mode.
(5) I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO - 0.2 V.
(6) For Flash banks/pumps in sleep mode.
(7) This assumes reading from one bank while programming the same bank.
(8) The maximum input capacitance CI of the Flexray RX pin(s) is 10pF.
64
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SPNS141–MARCH 2010
(1)
Electrical Characteristics Over Operating Free-Air Temperature Range
(continued)
Parameter
Test Conditions
MIN
TYP
MAX
Unit
CO
Output capacitance
3
pF
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7 Peripheral and Electrical Specifications
7.1 Clocks
7.1.1 PLL And Clock Specifications
Table 7-1. Timing Requirements For PLL Circuits Enabled Or Disabled
MIN
5
MAX
Unit
MHz
ns
f(OSC)
Input clock frequency
20
tc(OSC)
Cycle time, OSCIN
50
15
15
20
1.5
tw(OSCIL)
tw(OSCIH)
f(OSCRST)
f(OSCRST)
Pulse duration, OSCIN low
Pulse duration, OSCIN high
OSC FAIL frequency - upper level
OSC FAIL frequency - lower level
ns
ns
50
5
MHz
MHz
7.1.2 External Reference Resonator/Crystal Oscillator Clock Option
The oscillator is enabled by connecting the appropriate fundamental 5–20 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in section (a) of the figure below. The
oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled
during leakage test measurement and HALT mode.
NOTE
TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load
capacitors will best tune their resonator/crystal to the microcontroller device for optimum
start-up and operation over temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.5V clock signal to the OSCIN pin and leaving
the OSCOUT pin unconnected (open) as shown in section (b) of the figure below.
(see Note B)
OSCIN
OSCOUT
OSCIN
OSCOUT
Kelvin_GND
C1
C2
External
Clock Signal
(toggling 0-1.5V)
(see Note A)
Crystal
(a)
(b)
Figure 7-1. Recommended Crystal/Clock Connection
NOTE
In figure (a), The values of C1 and C2 should be provided by the resonator/crystal vendor.
In figure (b), Kelvin_GND should not be connected to any other GND.
66
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SPNS141–MARCH 2010
7.1.3 LPO And Clock Detection
The LPOCLKDET module consists of a clock monitor (CLKDET) and 2 low power oscillators (LPO) - a low
frequency (LF) and a high frequency {HF) oscillator. The CLKDET is a supervisor circuit for an externally
supplied clock signal. In case the externally supplied clock frequency falls out of a frequency window, the
clock detector flags this condition and switches to the HF LPO clock (limp mode). The OSCFAIL flag and
clock switch-over remain, regardless of the behavior of the oscillator clock signal. The only way OSCFAIL
can be cleared (and re-enable OSCIN as the clock source) is a power-on-reset.
Table 7-2. LPO And Clock Detection
Parameter
MIN
1.5
Type
MAX
5
Unit
MHz
MHz
MHz
MHz
kHz
Invalid frequency
lower threshold
upper threshold
20
50
Limp mode frequency (HFosc)
HFosc frequency
TBD
TBD
TBD
10
10
80
TBD
TBD
TBD
LFosc frequency
lower-
upper-
threshold
guaranteed fail
guaranteed pass
guaranteed fail
threshold
f[MHz]
1.5
5.0
20.0
50.0
Figure 7-2. LPO And Clock Detection
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7.1.4 Switching Characteristics Over Recommended Operating Conditions For Clocks
Table 7-3. Switching Characteristics Over Recommended Operating Conditions For Clocks
Parameter
Test Conditions
MIN
MAX
160
36
Unit
MHz
MHz
MHz
MHz
MHz
f(HCLK)
f(HCLK)
f(GCLK)
HCLK - System clock frequency (BGA packages) Pipeline mode enabled
Pipeline mode disabled
HCLK - System clock frequency (144pin QFP
package)
Pipeline mode enabled
Pipeline mode disabled
140
36
GCLK - CPU clock frequency (ratio GCLK :
HCLK = 1:1)
f(HCLK)
f(RTICLK)
f(VCLK)
f(VCLK2)
f(AVCLK1)
RTICLK - clock frequency
f(VCLK)
100
MHz
MHz
MHz
MHz
VCLK - Primary peripheral clock frequency
VCLK2 - Secondary peripheral clock frequency
f(VCLK)
f(VCLK)
AVCLK1 - Primary asynchronous peripheral clock
frequency
f(AVCLK2)
AVCLK2 - Secondary asynchronous peripheral
clock frequency
f(VCLK)
80
MHz
MHz
MHz
(1)
f(ECLK)
ECLK - External clock output frequency for ECP
Module
f(PROG/ERASE)
System clock frequency - Flash
programming/erase
f(HCLK)
(1) (ECLK) = f(VCLK) / N, where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the System
module. Pipeline mode enabled or disabled is determined by the FRDCNTL[2:0].
7.1.4.1 Timing - Wait States
RAM
0
Address Waitstates
0MHz
0MHz
f(HCLK)
f(HCLK)
Data Waitstates
0
Flash
0
1
Address Waitstates
0MHz
0MHz
f(HCLK)
f(HCLK)
100MHz
2
Data Waitstates
0
1
3
36MHz
72MHz
108MHz
Figure 7-3. Wait States
NOTE
If FMzPLL frequency modulation is enabled, special care must be taken to ensure that the
maximum system clock frequency f(HCLK) and peripheral clock frequency f(VCLK) are not
exceeded. The speed of the device clocks may need be derated to accommodate the
modulation depth when FMzPLL frequency modulation is enabled.
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SPNS141–MARCH 2010
7.2 ECLK Specification
7.2.1 Switching Characteristics Over Recommended Operating Conditions For External
Clocks
Table 7-4. Switching Characteristics Over Recommended Operating Conditions For External Clocks(1)(2)
NO.
Parameter
Pulse duration, ECLK
Test Conditions
MIN
MAX
Unit
3
4
tw(EOL)
under all prescale
factor combinations (X
and N)
0.5tc(ECL
K) – tf
ns
low
tw(EOH)
Pulse duration, ECLK
high
under all prescale
factor combinations (X
and N)
0.5tc(ECL
K) – tr
ns
(1) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the VBUS interface clock divider ratio determined by the CLKCNTL.[19:16] bits in the
SYS module.
(2) N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the System module.
4
ECLK
3
Figure 7-4. ECLK Timing Diagram
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7.3 RST And PORRST Timings
7.3.1 Timing Requirements For PORRST
Table 7-5. Timing Requirements For PORRST
NO.
MIN
MAX
Unit
V
VCCPORL
VCCPORH
VCC low supply level when PORRST must be active during power up
0.5
VCC high supply level when PORRST must remain active during power up
and become active during power down
1.35
V
VCCIOPORL
VCCIOPORH
VIL(PORRST)
VCCIO / VCCP low supply level when PORRST must be active during
power up
1.1
V
V
VCCIO / VCCP high supply level when PORRST must remain active during
power up and become active during power down
3
Low-level input voltage of PORRST VCCIO > 2.5V
Low-level input voltage of PORRST VCCIO < 2.5V
0.2 VCCIO
0.5
V
V
3
tsu(PORRST)
Setup time, PORRST active before VCCIO and VCCP > VCCIOPORL during
power up
0
ms
6
7
8
9
th(PORRST)
tsu(PORRST)
th(PORRST)
th(PORRST)
tf(PORRST)
Hold time, PORRST active after VCC > VCCPORH
1
8
ms
ms
ms
ms
ns
Setup time, PORRST active before VCC <= VCCPORH during power down
Hold time, PORRST active after VCCIO and VCCP > VCCIOPORH
Hold time, PORRST active after VCC < VCCPORL
1
0
Filter time PORRST, pulses less than MIN will be filtered out, pulses
greater than MAX are guaranteed to generate a reset
30
150
150
tf(RST)
Filter time RST, pulses less than MIN will be filtered out, pulses greater
than MAX are guaranteed to generate a reset
40
ns
3.3 V
V
V
CCIOPORH
V
/ V
CCP
CCIOPORH
CCIO
8
1.5 V
V
V
CCPORH
CC
V
CCPORH
7
6
6
7
V
V
CCIOPORL
CCIOPORL
V
V
CCPORL
CCPORL
V
(1.5 V)
CC
3
9
V
V
IL(PORRST)
V
V
V
V
IL
IL
IL(PORRST)
IL
IL
PORRST
Figure 7-5. PORRST Timing Diagram
NOTE
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage;
this is just an exemplary drawing. All requirements are to ensure PORRST is active when
VCCIO or VCC is out of the normal operating range.
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SPNS141–MARCH 2010
7.3.2 Switching Characteristics Over Recommended Operating Conditions For RST
Table 7-6. Switching Characteristics Over Recommended Operating Conditions For RST(1)
Parameter
Valid time, RST active after PORRST inactive
Valid time, RST active (all others)
MIN
MAX
Unit
tv(RST)
1048c(OSC)
8tc(VCLK)
ns
(1) Specified values do NOT include rise/fall times. For rise and fall timings, see the switching characteristics for output timings versus load
capacitance table.
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7.4 DAP - JTAG Scan Interface Timing
7.4.1 JTAG clock specification 12-MHz and 50-pF load on TDO output
Table 7-7. JTAG Scan Interface Timing
NO.
MIN
MAX
Unit
MHz
MHz
ns
f(TCK)
TCK frequency (at HCLKmax)
12
f(RTCK)
RTCK frequency (at TCKmax and HCLKmax)
Delay time, TCK to RTCK
10
1
2
3
4
5
td(TCK -RTCK)
tsu(TDI/TMS - RTCKr)
th(RTCKr -TDI/TMS)
th(RTCKr -TDO)
td(RTCKf -TDO)
20
10
Setup time, TDI, TMS before RTCK rise (RTCKr)
Hold time, TDI, TMS after RTCKr
15
0
ns
ns
Hold time, TDO after RTCKr
0
ns
Delay time, TDO valid after RTCK fall (RTCKf)
ns
TCK
RTCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 7-6. JTAG timing
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SPNS141–MARCH 2010
7.5 Output Timings
7.5.1 Switching Characteristics For Output Timings Versus Load Capacitance ©L)
Table 7-8. Switching Characteristics For Output Timings Versus Load Capacitance ©L)
Parameter
MIN
MAX
2.5
5
Unit
tr
tf
tr
tf
tr
tf
8mA pins
8mA pins
4mA pins
4mA pins
2mA-z pins
2mA-z pins
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
ns
9
12
2.5
5
ns
ns
ns
ns
ns
9
12
7
13
21
29
7
13
21
29
10
17
25
35
10
17
25
35
tr
tf
VCCIO
80%
80%
Output
20%
20%
0
Figure 7-7. CMOS-Level Outputs
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7.6 Input Timings
7.6.1 Timing Requirements For Input Timings(1)
Table 7-9. Timing Requirements For Input Timings
MIN
tc(VCLK) + 10(1)
MAX
Unit
ns
tpw
Input minimum pulse width
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(1) The timing shown above is only valid for pin used in GIO mode
tpw
VCCIO
80%
80%
Input
20%
20%
0
Figure 7-8. CMOS-Level Inputs
74
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SPNS141–MARCH 2010
7.7 Flash Timings
Table 7-10. Timing Requirements For Program Flash
MIN
NOM
MAX
300
74
Unit
µs
s
tprog(32-bit)
tprog(Total)
Full word (32-bit) programming time
33
17
17
2M-byte programming
time(1)
-40°C to 125°C
0°C to 60C, for first 25
cycles
25
s
tprog ECC(16-bit)
tprog ECC(total)
ECC programming time
33
4.3
4.3
300
15
7
µs
s
Total ECC bit
programming time
(256k-byte)
-40°C to 125°C
0°C to 60°C, for first 25
cycles
s
terase(sector)
Sector erase time
(including compaction)
-40°C to 125°C
2
15
10
s
s
0°C to 60°C, for first 25
cycles
1.5
terase(bank)
Bank erase time (including Bank 0
7.5
5.5
5.5
5.5
20
12
s
compaction),0C to 60C,
for first 25 cycles
Bank 1
s
Bank 2
Bank 3
12
s
s
12
twec
Write/erase cycles at TA = 125°C with 15 year Data
Retention requirement
1000
cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time.
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7.8 SPI Master Mode Timing Parameters
7.8.1 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)
Table 7-11. SPI Master Mode External Timing Parameters(1)(2)(3)
NO.
1
MIN
MAX
Unit
ns
(4)
tc(SPC)M
Cycle time, SPICLK
50
256tc(VCLK)
2(5)
tw(SPCH)M
tw(SPCL)M
tw(SPCL)M
tw(SPCH)M
td(SPCH-SIMO)M
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 3 – tr
0.5tc(SPC)M – 3 – tf
0.5tc(SPC)M – 3 – tf
0.5tc(SPC)M – 3 – tr
0.5tc(SPC)M – 10
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
ns
3(5)
4(5)
ns
ns
Delay time, SPISIMO valid before SPICLK low
(clock polarity = 0)
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
th(SPCL-SOMI)M
th(SPCH-SOMI)M
tC2TDELAY
Delay time, SPISIMO valid before SPICLK high
(clock polarity = 1)
0.5tc(SPC)M – 10
5(5)
6(5)
7(5)
8(6)
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5tc(SPC)M – tf(SPC)
-5
ns
ns
ns
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5tc(SPC)M – tr(SPC)
-5
Setup time, SPISOMI before SPICLK low (clock
polarity = 0)
tf(SPC)
tr(SPC) + 4
10
Setup time, SPISOMI before SPICLK high (clock
polarity = 1)
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
10
Setup time CS active until SPICLK high (clock
polarity = 0)
C2TDELAY*tc(VCLK)
2*tc(VCLK) - tf(SPICS)
tr(SPC)
+
ns
ns
ns
+
Setup time CS active until SPICLK low (clock
polarity = 1)
C2TDELAY*tc(VCLK)
2*tc(VCLK) - tf(SPICS)
tf(SPC)
+
+
9(6)
tT2CDELAY
Hold time SPICLK low CS until inactive (clock
polarity = 0)
0.5*tc(SPC)M
T2CDELAY*tc(VCLK)
tc(VCLK)
tf(SPC) + tr(SPICS)
+
+
+
-
Hold time SPICLK high until CS inactive (clock
polarity = 1)
0.5*tc(SPC)M
T2CDELAY*tc(VCLK)
tc(VCLK)
tr(SPC) + tr(SPICS)
+
ns
-
10
11
tSPIENA
SPIENAn Sample point
(C2TDELAY+1)*tc(VCLK) (C2TDELAY+1)*tc(VCLK)
- tf(SPICS)
ns
ns
tSPIENAW
SPIENAn Sample point from write to buffer
(C2TDELAY+2)*tc(VCLK)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)\
(3) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 50 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register
bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 50 ns. The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY are programmed in the SPIDELAY register
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TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141–MARCH 2010
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
6
7
Master In Data
Must Be Valid
SPISOMI
Figure 7-9. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPICSn
Master Out Data Is Valid
8
9
10
11
SPIENAn
Figure 7-10. SPI Master Mode Chip Select timing (CLOCK PHASE = 0)
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SPNS141–MARCH 2010
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7.8.2 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(7)(8)(9)
Table 7-12. SPI Master Mode External Timing Parameters
NO.
MIN
MAX
Unit
ns
(1)
1
tc(SPC)M
Cycle time, SPICLK
50
256tc(VCLK)
2(2) tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 3 – tr
0.5tc(SPC)M – 3 – tf
0.5tc(SPC)M – 3 – tr
0.5tc(SPC)M – 3 – tf
0.5tc(SPC)M – 15
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
ns
tw(SPCL)M
3(2) tw(SPCL)M
tw(SPCH)M
4(2) tv(SIMO-SPCH)M
ns
ns
Valid time, SPICLK high after SPISIMO data
valid(clock polarity = 0)
tv(SIMO-SPCL)M
5(2) tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
Valid time, SPICLK low after SPISIMO data valid
(clock polarity = 1)
0.5tc(SPC)M – 15
Valid time, SPISIMO data valid after SPICLK
high(clock polarity = 0)
0.5tc(SPC)M – tr(SPC)
ns
ns
ns
Valid time, SPISIMO data valid after SPICLK
low(clock polarity = 1)
0.5tc(SPC)M – tf(SPC)
6(2) tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
7(2) tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
Setup time, SPISOMI before SPICLK high (clock
polarity = 0)
4
4
6
6
Setup time, SPISOMI before SPICLK low (clock
polarity = 1)
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
8(3) tC2TDELAY
Setup time CS active until SPICLK high (clock
polarity = 0)
0.5*tc(SPC)M
+
ns
ns
C2TDELAY*tc(VCLK)
2*tc(VCLK) - tf(SPICS)
tr(SPC)
+
+
Setup time CS active until SPICLK low (clock
polarity = 1)
0.5*tc(SPC)M +
C2TDELAY*tc(VCLK)
2*tc(VCLK) - tf(SPICS)
tf(SPC)
+
+
9(3) tT2CDELAY
Hold time SPICLK low CS until inactive (clock
polarity = 0)
T2CDELAY*tc(VCLK)
+
ns
ns
ns
ns
tc(VCLK) - tf(SPC) + tr(SPICS)
T2CDELAY*tc(VCLK)
tc(VCLK) - tr(SPC) + tr(SPICS)
Hold time SPICLK high until CS inactive (clock
polarity = 1)
+
10
11
tSPIENA
SPIENAn Sample Point
(C2TDELAY+1)*tc(VCLK) (C2TDELAY+1)*tc(VCLK)
- tf(SPICS)
tSPIENAW
SPIENAn Sample point from write to buffer
(C2TDELAY+2)*tc(VCLK)
(7) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(8) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(9) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(1) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 50 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register
bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 50 ns. The external load on the SPICLK pin must be less than 60pF.
(2) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(3) C2TDELAY and T2CDELAY are programmed in the SPIDELAY register
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TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141–MARCH 2010
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Data Valid
Master Out Data Is Valid
SPISIMO
SPISOMI
6
7
Master In Data
Must Be Valid
Figure 7-11. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPICS
Master Out Data Is Valid
8
9
10
11
SPIENA
Figure 7-12. SPI Master Mode Chip Select timing (CLOCK PHASE = 1)
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SPNS141–MARCH 2010
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7.9 SPI Slave Mode Timing Parameters
7.9.1 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input,
SPISIMO = input, and SPISOMI = output)(4)(5)(6)(7)
Table 7-13. SPI Slave Mode External Timing Parameters
NO.
MIN
MAX
Unit
ns
1
tc(SPC)S
Cycle time, SPICLK(1)
50
256tc(VCLK)
2(2) tw(SPCH)S
tw(SPCL)S
3(2) tw(SPCL)S
tw(SPCH)S
4(2) td(SPCH-SOMI)S
td(SPCL-SOMI)S
5(2) tH(SPCH-SOMI)S
tH(SPCL-SOMI)S
Pulse duration, SPICLK high(clock polarity = 0)
0.5tc(SPC)S –
0.25tc(VCLK)
0.5tc(SPC)S +
0.25tc(VCLK)
ns
Pulse duration, SPICLK low(clock polarity = 1)
Pulse duration, SPICLK low(clock polarity = 0)
Pulse duration, SPICLK high(clock polarity = 1)
0.5tc(SPC)S –
0.25tc(VCLK)
0.5tc(SPC)S +
0.25tc(VCLK)
0.5tc(SPC)S –
0.25tc(VCLK)
0.5tc(SPC)S +
0.25tc(VCLK)
ns
ns
ns
ns
ns
0.5tc(SPC)S –
0.25tc(VCLK)
0.5tc(SPC)S +
0.25tc(VCLK)
Delay time, SPISOMI valid after SPICLK high
(clock polarity = 0)
trf(SOMI) + 15
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1)
trf(SOMI) + 15
Hold time, SPISOMI data valid after SPICLK high
(clock polarity =0)
0
Hold time, SPISOMI data valid after SPICLK low
(clock polarity =1)
0
6(2) tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
7(2) th(SPCL-SIMO)S
th(SPCH-SIMO)S
Setup time, SPISIMO before SPICLK low(clock
polarity = 0)
4
Setup time, SPISIMO before SPICLK high(clock
polarity = 1)
4
Hold time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
6
Hold time, SPISIMO data valid after S PICLK high
(clock polarity = 1)
6
8
td(SPCL-SENAH)S
td(SPCH-SENAH)S
td(SCSL-SENAL)S
Delay time, SPIENAn high after last SPICLK low
(clock polarity = 0)
1.5tc(VCLK)
1.5tc(VCLK)
2.5tc(VCLK)+tr(ENAn)
2.5tc(VCLK)+tr(ENAn)
tf(ENAn)+6
ns
ns
Delay time, SPIENAn high after last SPICLK high
(clock polarity = 1)
9
Delay time, SPIENAn low after SPICSn low (if new
data has been written to the SPI buffer)
(4) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(5) If the SPI is in slave mode, the following must be true: tc(SPC)S >= (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(6) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(7) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(1) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S >= (PS +1)tc(VCLK) >= 50 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) >= 50 ns.
(2) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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SPNS141–MARCH 2010
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI Data Is Valid
SPISOMI
SPISIMO
6
7
SPISIMO Data
Must Be Valid
Figure 7-13. SPI Slave Mode External Timing (CLOCK PHASE = 0)
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
8
SPIENAn
SPICSn
9
Figure 7-14. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)
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SPNS141–MARCH 2010
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7.9.2 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input,
SPISIMO = input, and SPISOMI = output)(3)(4)(5)(6)
Table 7-14. SPI Slave Mode External Timing Parameters
NO.
1
MIN
MAX
Unit
ns
tc(SPC)S
Cycle time, SPICLK(1)
50
256tc(VCLK)
2(2)
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S –
0.25tc(VCLK)
0.5tc(SPC)S +
0.25tc(VCLK)
ns
tw(SPCL)S
tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S –
0.25tc(VCLK)
0.5tc(SPC)S +
0.25tc(VCLK)
3(2)
4(2)
5(2)
6(2)
7(2)
8
0.5tc(SPC)S –
0.25tc(VCLK)
0.5tc(SPC)S +
0.25tc(VCLK)
ns
ns
ns
ns
ns
0.5tc(SPC)S –
0.25tc(VCLK)
0.5tc(SPC)S +
0.25tc(VCLK)
td(SOMI-
SPCL)S
Delay time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
trf(SOMI)+15
td(SOMI-
SPCH)S
tH(SPCL-
SOMI)S
Delay time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
trf(SOMI)+15
Hold time, SPISOMI data valid after SPICLK high
(clock polarity =0)
0
tH(SPCH-
SOMI)S
Hold time, SPISOMI data valid after SPICLK low
(clock polarity =1)
0
tsu(SIMO-
SPCH)S
tsu(SIMO-
SPCL)S
Setup time, SPISIMO before SPICLK high (clock
polarity = 0)
4
Setup time, SPISIMO before SPICLK low (clock
polarity = 1)
4
tv(SPCH-
SIMO)S
High time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
6
tv(SPCL-
SIMO)S
High time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
6
td(SPCH-
SENAH)S
td(SPCL-
SENAH)S
td(SCSL-
SENAL)S
td(SCSL-
SOMI)S
Delay time, SPIENAn high after last SPICLK high
(clock polarity = 0)
1.5tc(VCLK)
1.5tc(VCLK)
2.5tc(VCLK)+tr(ENAn)
2.5tc(VCLK)+tr(ENAn)
tf(ENAn)+6
ns
Delay time, SPIENAn high after last SPICLK low
(clock polarity = 1)
9
Delay time, SPIENAn low after SPICSn low (if new
data has been written to the SPI buffer)
ns
ns
10
Delay time, SOMI valid after SPICSn low (if new data
has been written to the SPI buffer)
trf(SOMI)+6
(3) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(4) If the SPI is in slave mode, the following must be true: tc(SPC)S >= (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(5) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(6) For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
(1) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S >= (PS +1)tc(VCLK) >= 50 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) >= 50 ns.
(2) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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TMS570LS10206, TMS570LS10116, TMS570LS10106
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SPNS141–MARCH 2010
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Data Valid
SPISOMI Data Is Valid
SPISOMI
SPISIMO
6
7
SPISIMO Data
Must Be Valid
Figure 7-15. SPI Slave Mode External Timing (CLOCK PHASE = 1)
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
8
SPIENAn
SPICSn
9
10
SPISOMI
Slave Out Data Is Valid
Figure 7-16. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)
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SPNS141–MARCH 2010
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7.10 CAN Controller Mode Timings
7.10.1 Dynamic Characteristics For The CANnTX And CANnRX Pins
Table 7-15. Dynamic Characteristics For The CANnTX And CANnRX Pins
Parameter
MIN
MAX
15
Unit
ns
td(CANnTX)
td(CANnRX)
Delay time, transmit shift register to CANnTX pin(1)
Delay time, CANnRX pin to receive shift register
5
ns
(1) These values do not include rise/fall times of the output buffer.
7.11 Flexray Controller Mode Timings
7.11.1 Jitter Timing
Table 7-16. Jitter Timing
Parameter
MIN
98
MAX
102
Unit
ns
tTx1bit
clock jitter and signal symmetry
FlexRay BSS (byte start sequence) to BSS
average over 10000 samples
tTx10bit
999
999.5
-
1001
1000.5
2.5
ns
tTx10bitAvg
tRxAsymDelay
ns
delay difference between rise and fall from Rx pin to
sample point in FlexRay core
ns
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SPNS141–MARCH 2010
7.12 EMIF Timings
Table 7-17. EMIF Read/Write Mode Switching Characteristics(1)(2)
NO
Parameter
Description
Reads and Writes
MIN
MAX
Unit
1
td(TURNAROUND) Turn around time
(TA + 1) * E -
TBD
(TA + 1) * E +
TBD
ns
Reads
2
3
tc(EMRCYCLE)
EMIF read cycle time
(RS + RST +
RH + TA +4) *
E - TBD
(RS + RST +
RH + TA +4) *
E - TBD
ns
tsu(EMCSL-EMOEL) Output setup time, EMIFCS[3:0] low to EMIFOE
low (SS=0)
(RS +1) * E -
TBD
(RS +1) * E +
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output setup time, EMIFCS[3:0] low to EMIFOE
low (SS=1)
TBD
TBD
4
th(EMOEH-EMCSH) Output hold time, EMIFOE high to EMIFCS[3:0]
high (SS=0)
(RH +1) * E -
TBD
(RH +1) * E +
TBD
Output hold time, EMIFOE high to EMIFCS[3:0]
high (SS=1)
TBD
TBD
5
6
tsu(EMBAV-EMOEL) Output setup time, EMIFBADD[1:0] valid to
EMIFOE low
(RS +1) * E -
TBD
(RS +1) * E +
TBD
th(EMOEH-EMBAIV) Output hold time, EMIFOE high to
EMIFBADD[1:0] invalid
(RH +1) * E -
TBD
(RH +1) * E +
TBD
7
tsu(EMAV-EMOEL) Output setup time, EMIFADD[21:0] valid to
EMIFOE low
(RS +1) * E -
TBD
(RS +1) * E +
TBD
8
th(EMOEH-EMAIV) Output hold time, EMIFOE high to EMIFADD[21:0]
invalid
(RH +1) * E -
TBD
(RH +1) * E +
TBD
9
tw(EMOEL)
EMIFOE active low width
(RST +1) * E - (RST +1) * E +
TBD
TBD
10
11
tsu(EMDV-EMOEH) Setup time, EMIFD[15:0] valid before EMIFOE
high
TBD
th(EMOEH-EMDV)
Hold time, EMIFD[15:0] valid after EMIFOE high
TBD
Writes
12
13
tc(EMWCYCLE)
EMIF write cycle time
(WS + WST +
WH + TA +4) * WH + TA +4) *
(WS + WST +
ns
E - TBD
E - TBD
tsu(EMCSL-EMWEL) Output setup time, EMIFCS[3:0] low to EMIFWE
low (SS=0)
(WS +1) * E -
TBD
(WS +1) * E +
TBD
ns
ns
ns
ns
ns
ns
ns
ns
Output setup time, EMIFCS[3:0] low to EMIFWE
low (SS=1)
TBD
TBD
14
th(EMWEH-EMCSH) Output hold time, EMIFWE high to EMIFCS[3:0]
high (SS=0)
(WH +1) * E -
TBD
(WH +1) * E +
TBD
Output hold time, EMIFWE high to EMIFCS[3:0]
high (SS=1
TBD
TBD
15
16
17
18
19
tsu(EMBAV-EMWEL) Output setup time, EMIFBADD[1:0] valid to
EMIFWE low
(WS +1) * E -
TBD
(WS +1) * E +
TBD
th(EMWEH-EMBAIV) Output hold time, EMIFWE high to EMBADD[1:0]
invalid
(WH +1) * E -
TBD
(WH +1) * E +
TBD
tsu(EMAV-EMWEL) Output setup time, EMIFADD[21:0] valid to
EMIFWE low
(WS +1) * E -
TBD
(WS +1) * E +
TBD
th(EMWEH-EMAIV) Output hold time, EMIFWE high to
EMIFADD[21:0] invalid
(WH +1) * E -
TBD
(WH +1) * E +
TBD
tw(EMWEL)
EMIFWE active low width
(WST +1) * E - (WST +1) * E +
TBD TBD
(1) RS = Read setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold, TA = Turn Around,
SS= Strobe Select Mode
(2) E = VCLK period in ns.
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(1) (2)
Table 7-17. EMIF Read/Write Mode Switching Characteristics
(continued)
NO
Parameter
Description
MIN
MAX
Unit
20
tsu(EMDV-ENWEL) Output setup time, EMIFD[15:0] valid to EMIFWE
low
(WS +1) * E -
TBD
(WS +1) * E +
TBD
ns
21
th(EMWEH-EMDIV) Output hold time, EMIFD[15:0] valid after
EMIFWE high
(WH +1) * E -
TBD
(WH +1) * E +
TBD
ns
7.12.1 Read Timing (Asynchronous RAM)
2
1
EMIFCS[3:0]
EMIFR/W
EMIFBADD[1:0]
EMIFADD[21:0]
3
5
7
8
6
4
9
EMIFOE
11
10
EMIFD[15:0]
EMIFWE
Figure 7-17. Asynchronous Memory Read Timing for EMIF
7.12.2 Write Timing (Asynchronous RAM)
12
1
EMIFCS[3:0]
EMIFBADD[1:0]
EMIFADD[21:0]
13
15
17
16
18
14
19
EMIFWE
20
21
EMIFD[15:0]
EMIFOE
Figure 7-18. Asynchronous Memory Write Timing for EMIF
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7.13 ETM Timings
7.13.1 ETMTRACECLK Timing
t(ETM)
l
t(ETM)
t(ETM)
t(ETM)
h
f
r
t(ETM)
cyc
Figure 7-19. ETMTRACECLK Timing
Table 7-18. ETMTRACECLK Timing
Parameter
f(ETM)cyc
t(ETM)cyc
t(ETM)l
Minimum
Maximum
Description
Clock frequency
45MHz
22.22ns
2ns
Clock period
Low pulse width
t(ETM)h
t(ETM)r
2ns
High pulse width
Clock and data rise time
Clock and data fall time
3ns
t(ETM)f
3ns
7.13.2 ETMDATA Timing
ETMTRACECLK
ETMDATA
t(ETM)
t(ETM)
t(ETM)
t(ETM)
ho
su
ho
su
Figure 7-20. ETMDATA Timing
Table 7-19. ETMDATA Timing
Parameter
t(ETM)su
t(ETM)ho
Minimum
Maximum
2.5ns
Description
Data setup time
Data hold time
1.5ns
Note: The ETMTRACECLK and ETMDATA timing is based on a 50pF load.
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7.14 RTP Timings
7.14.1 RTPCLK Timing
t(RTP)
l
t
t
t(RTP)
f
r
h
t(RTP)
cyc
Figure 7-21. RTPCLK Timing
Table 7-20. RTPCLK Timing
Parameter
Minimum
Description
t(RTP)cyc
tc(HCLK)
Clock period (depending on HCLK divide
ratio)
t(RTP)h
t(RTP)l
(t(RTP)cyc/2) - ((tr+tf)/2)
(t(RTP)cyc/2) - ((tr+tf)/2)
High pulse width (depending on HCLK divide
ratio and load on pin)
Low pulse width (depending on HCLK divide
ratio and load on pin)
7.14.2 RTPDATA Timing
td(RTPSYNC) t(RTPSYNC)valid
RTPSYNC
RTPCLK
RTPDATA
td(RTPDATA) t(RTPDATA)valid
Figure 7-22. RTPDATA Timing
Table 7-21. RTPDATA Timing
Parameter
td(RTPSYNC)
t(RTP)svalid
Minimum
3ns
Description
RTP SYNC delay time
RTP SYNC valid
2ns
td(RTPDATA)
t(RTP)dvalid
3ns
RTP DATA delay time
SYNC hold time
2ns
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7.14.3 RTPENABLE Timing
t
t
t
(RTP)disable
(RTP)enable
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
HCLK
RTPCLK
RTPENA
RTPSYNC
RTPDATA
d1
d2
d3
d4
Divide by 1
d5
d6
d7
d8
Figure 7-23. RTPENABLE Timing
Table 7-22. RTPENABLE Timing
Parameter
Minimum
3tc(HCLK) + tr(RTPSYNC) + 12ns
Maximum
Description
t(RTP)disable
time RTPENA must go high
before what would be the next
RTPSYNC, to guarantee
delaying the next packet
t(RTP)enable
4tc(HCLK) + tr(RTPSYNC)
5tc(HCLK) + tr(RTPSYNC) + 12ns
time after RTPENA goes low
before a packet that has been
halted, resumes
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7.15 DMM Timings
7.15.1 DMMCLK Timing
t(DMM)
l
t
t
r
t(DMM)
h
f
t(DMM)
cyc
Figure 7-24. DMMCLK Timing
Table 7-23. DMMCLK Timing
Parameter
Minimum
Description
t(DMM)cyc
tc(HCLK * 2
Clock period (depending on HCLK divide
ratio)
t(DMM)h
t(DMM)l
(t(DMM)cyc/2) - ((tr+tf)/2)
(t(DMM)cyc/2) - ((tr+tf)/2)
High pulse width (depending on HCLK divide
ratio)
Low pulse width (depending on HCLK divide
ratio)
7.15.2 DMMDATA Timing
t(DMM)
t(DMM)
sho
ssu
DMMSYNC
DMMCLK
DMMDATA
t(DMM)
t(DMM)
dho
dsu
Figure 7-25. DMMDATA Timing
Table 7-24. DMMDATA Timing
Parameter
t(DMM)ssu
t(DMM)sho
t(DMM)dsu
t(DMM)dho
Minimum
2 ns
Description
SYNC active to clk falling edge setup time
clk falling edge to SYNC deactive hold time
DATA to clk falling edge setup time
clk falling edge to DATA hold time
3ns
2ns
3ns
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7.15.3 DMMENA Timing
HCLK
DMMCLK
DMMSYNC
DMMDATA
DMMENA
D00
D01
D10
D11
D20
D21
D30
D31
D40
D41
D50
Figure 7-26. DMMENA Timing
The above figure shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode,
data width = 8, portwidth = 4) where none of the packets received by the DMM are sent out, leading to
filling up of the internal buffers. The DMMENA signal is shown asserted, after the first two packets have
been received and synchronized to the HCLK domain. Here, the DMM has the capacity to accept packets
D4, D5, D6, D7. Packet D8 would result in an overflow. Once DMMENA is asserted, the DMM expects to
stop receiving packets after 4 HCLK cycles; once DMMENA is de-asserted, the DMM can handle packets
immediately (after 0 HCLK cycles).
7.16 MibADC
7.16.1 MibADC
The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could
be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are
given with respect to ADREFLO unless otherwise noted.
Table 7-25. MibADC
Resolution
12 bits (4096 values)
Assured
Monotonic
Output conversion fcode
00h to FFFh [00 for VAI ≤ADREFLO; FFF for VAI ≥ ADREFHI]
7.16.2 MibADC Recommended Operating Conditions
Table 7-26. MibADC Recommended Operating Conditions(1)
MIN
MAX
3.6
UNIT
V
ADREFHI
ADREFLO
VAI
A-to-D high-voltage reference source
A-to-D low-voltage reference source
Analog input voltage
3
0
ADREFLO
-2
0.3
V
ADREFHI
2
V
IAIC
Analog input clamp current(2)
mA
(VAI < VSSAD – 0.3 or VAI > VCCAD
0.3)
+
(1) For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
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7.16.3 Operating Characteristics Over Full Ranges Of Recommended Operating Conditions
Table 7-27. Operating Characteristics Over Full Ranges Of Recommended Operating Conditions(1)
Parameter
Rmux
Description/Conditions
Min
TYP
Max
250
250
Unit
Ω
Analog input mux on-resistance
Rsamp
ADC sample switch
on-resistance
150
Ω
Cmux
Csamp
IAIL
Input mux capacitance
ADC sample capacitance
Analog input leakage current
ADREFHI input current
16
13
200
5
pF
pF
nA
mA
V
11
12
Input leakage per ADC input pin
ADREFHI = 3.6 V, ADREFLO = VSSAD
ADREFHI - ADREFLO
–200
IADREFHI
CR
Conversion range over which
3
3.6
specified accuracy is maintained
EDNL
EINL
Differential nonlinearity error
Difference between the actual step width and the
ideal value.
±2
LSB
LSB
Integral nonlinearity error
Maximum deviation from the best straight line
through the MibADC. MibADC transfer
± 2
characteristics, excluding the quantization error.
ETOT
Total error/Absolute accuracy
Maximum value of the difference between an
analog value and the ideal midstep value.
± 4
LSB
(1) 1 LSB = (ADREFHI – ADREFLO)/ 212 for the MibADC
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7.16.4 MibADC Input Model
External
Internal
Mux
Switch
Rmux
Rs0
ADIN[0]
Vsrc0
I
AIL
Mux
Switch
Rmux
Rs1
ADIN[1]
Vsrc1
I
AIL
Mux
Switch
Sample
Switch
Rmux
Cmux
Rsamp
RsX
To ADC
Comparator
ADIN[X]
VsrcX
Csamp
I
AIL
Figure 7-27. MibADC Input Equivalent Circuit
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7.16.5 MibADC Timings
Table 7-28. MibADC Timings
Min
33
NOm
MAX
Unit
ns
tc(ADCLK)
td(SH)
Cycle time, MibADC clock
Delay time, sample and hold time
200
400
600
ns
td©)
Delay time, conversion time
ns
(1)
td(SHC)
Delay time, total sample/hold and conversion time
ns
(1) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the
prescale settings.
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7.16.6 MibADC Nonlinearity Error
The differential nonlinearity error shown in the figure below (sometimes referred to as differential linearity)
is the difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
0 ... 101
0 ... 100
0 ... 011
Differential
1 LSB
Linearity Error (1/2 LSB)
0 ... 010
Differential Linearity
0 ... 001
1 LSB
Error (–1/2 LSB)
0 ... 000
0
1
2
3
4
5
Analog Input Value (LSB)
Figure 7-28. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in the figure below (sometimes referred to as linearity error) is the
deviation of the values on the actual transfer function from a straight line.
0 ... 111
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(– 1/2 LSB)
At Transition
011/100
(–1/2 LSB)
0 ... 011
0 ... 010
0 ... 001
End-Point Lin. Error
At Transition
001/010 (– 1/4 LSB)
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
Figure 7-29. Integral Nonlinearity (INL) Error
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7.16.7 MibADC Total Error
The absolute accuracy or total error of an MibADC as shown in the figure below is the maximum value of
the difference between an analog value and the ideal midstep value.
0 ... 111
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
0 ... 011
0 ... 010
(–1 1/4 LSB)
Total Error
At Step
0 ... 001
0 ... 000
0 ... 001 (1/2 LSB)
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
Figure 7-30. Absolute Accuracy (Total) Error
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8 Mechanical Packaging and Orderable Information
The following table(s) show the thermal resistance for the PBGA-ZWT and PQFP-PGE mechanical
packages.
8.1 Thermal Data
8.1.1 PGE (S-PQFP-G144) plastic Quad Flat Pack
Table 8-1. PGE (S-PQFP-G144) Thermal Resistance Characteristics
PARAMETER
RQJA
°C / W
45
5
RQJC
8.1.2 ZWT (S-PBGA-N337) Plastic ball grid array
Table 8-2. ZWT (S-PBGA-N337) Thermal Resistance Characteristics
PARAMETER
RQJA
°C / W
TBD
RQJC
TBD
8.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). The data is subject to change without notice and without revision of this document.
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PACKAGE OPTION ADDENDUM
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5-Mar-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
X5LS20216ASPGEQQ1
X5LS20216ASZWTQQ1
ACTIVE
ACTIVE
LQFP
PGE
144
337
1
1
TBD
TBD
Call TI
Call TI
Call TI
Call TI
NFBGA
ZWT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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amplifier.ti.com
dataconverter.ti.com
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interface.ti.com
logic.ti.com
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www.ti.com/energy
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Microcontrollers
RFID
power.ti.com
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microcontroller.ti.com
www.ti-rfid.com
Security
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RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
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