OPA863SIDBVR [TI]
单通道低功耗 110MHz 12V 轨到轨输入和输出电压反馈放大器 | DBV | 6 | -40 to 125;
| 型号： | OPA863SIDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单通道低功耗 110MHz 12V 轨到轨输入和输出电压反馈放大器 | DBV | 6 | -40 to 125 放大器 |
| 文件： | 总54页 (文件大小：3346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA863, OPA2863, OPA4863
ZHCSMO3J –JUNE 2020 –REVISED JUNE 2023
OPAx863 低功耗、110MHz、轨到轨输入/输出、电压反馈运算放大器
1 特性
3 说明
• 宽带宽
– 单位增益带宽：110MHz (AV = 1V/V)
– 增益带宽积：50 MHz
• 低功耗
OPAx863 器件是单位增益稳定的低功耗、轨到轨输入/
输出、电压反馈运算放大器，旨在于 2.7V 至 12.6V 的
电源电压范围内运行。OPAx863 每通道仅消耗 700µA
的电流，提供的增益带宽积为 50MHz，压摆率为
105V/µs，电压噪声密度为5.9nV/√Hz。
– 静态电流：700 µA/通道（典型值）
– 断电模式：1.5 µA（最大值，VS= 3V）
– 电源电压：2.7V 至12.6V
• 输入电压噪声：5.9 nV/√Hz
• 压摆率：105 V/µs
• 轨到轨输入和输出
• HD2/HD3：在20 kHz (2VPP) 时为–129dBc/–
138dBc
由 2.7V 电源供电的轨到轨输入级适用于便携式电池供
电型应用。轨到轨输入级可在整个输入共模电压范围内
很好地匹配增益带宽积和噪声，从而在宽输入动态范围
内实现出色的性能。OPAx863 具有断电 (PD) 模式，
PD 静态电流 (IQ) 为 1.5µA（最大值），并在 6.5µs
（电源电压为3V）时间内开启或关闭。
OPAx863 包括过载功率限制功能，可限制输出饱和时
IQ 的增加，从而避免电池供电的功率敏感型系统中出
现过度功率耗散。输出级具有短路保护功能，使得此类
器件可适应恶劣的环境。
• 工作温度范围：
–40°C 至+125°C
• 其他特性：
– 过载功率限制
– 输出短路保护
• 高精度版：OPAx863A
器件信息(1)(2)
器件型号
OPA863
通道数
封装
DBV（SOT-23，5)
DBV（SOT-23，6）
DGK（VSSOP，8）
RUN（WQFN，10）
D（SOIC，8）
2 应用
单通道
• 低功耗SAR 和Δ-ΣADC 驱动器
• ADC 基准缓冲器
• 低侧电流检测
• 光电二极管TIA 接口
• 电感式传感
• 超声波流量计
• 多功能打印机
• MDAC 输出缓冲器
• 增益和有源滤波器级
OPA2863
OPA4863
双通道
四通道
PW（TSSOP，14）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 有关相关产品，请参阅器件比较
-20
HD2, VOUT = 2 VPP
HD3, VOUT = 2 VPP
HD2, VOUT = 4 VPP
HD3, VOUT = 4 VPP
CF
LED
Driver
-40
RF
-60
VCC
OPAx863
VOUT
ID
œ
LED
-80
-100
-120
-140
-160
To
ADC
Photo-
Diode
+
GND
VEE
œVBIAS
Transimpedance Amplifier Circuit
Switching
Circuit
RF
ISH
To comparator
for fault detection
VCC
1k
10k
100k
1M
10M
RG
Frequency (Hz)
OPAx863
œ
RSH
VOUT
GND
+
To MCU/
ADC
RG
G = 1V/V 时的失真性能
GND
VREF
Low-side Current Sensing
使用OPAx863 的应用电路
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS982
OPA863, OPA2863, OPA4863
ZHCSMO3J –JUNE 2020 –REVISED JUNE 2023
www.ti.com.cn
Table of Contents
8.1 Overview...................................................................22
8.2 Functional Block Diagram.........................................22
8.3 Feature Description...................................................23
8.4 Device Functional Modes..........................................24
9 Application and Implementation..................................26
9.1 Application Information............................................. 26
9.2 Typical Applications.................................................. 26
9.3 Power Supply Recommendations.............................30
9.4 Layout....................................................................... 30
10 Device and Documentation Support..........................32
10.1 Documentation Support.......................................... 32
10.2 接收文档更新通知................................................... 32
10.3 支持资源..................................................................32
10.4 Trademarks.............................................................32
10.5 静电放电警告.......................................................... 32
10.6 术语表..................................................................... 32
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information: OPA863.................................... 7
7.5 Thermal Information: OPA2863.................................. 7
7.6 Thermal Information: OPA4863.................................. 7
7.7 Electrical Characteristics: VS = 10 V ..........................8
7.8 Electrical Characteristics: VS = 3 V........................... 11
7.9 Typical Characteristics: VS = 10 V............................ 13
7.10 Typical Characteristics: VS = 3 V............................ 18
7.11 Typical Characteristics: VS = 3 V to 10 V................ 20
8 Detailed Description......................................................22
Information.................................................................... 32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision I (December 2022) to Revision J (June 2023)
Page
• 将OPA4863 PW（TSSOP，14）封装的状态从预发布更改为量产并添加了相关内容.....................................1
Changes from Revision H (August 2022) to Revision I (December 2022)
Page
• 将DBV（SOT23，5）封装的状态从预发布 更改为量产...................................................................................1
Changes from Revision G (July 2022) to Revision H (August 2022)
Page
• Changed the status of the RUN Package, from: preview to: production ........................................................... 3
Changes from Revision F (April 2022) to Revision G (July 2022)
Page
• 向特性 部分添加了 OPAx863A 信息...................................................................................................................1
• 向数据表添加了DBV（SOT23，5）封装...........................................................................................................1
• Changed the status of the D Package, from: preview to: production .................................................................3
• Updated the Output Voltage vs Load Current and Output Voltage vs Load Current figures to show typical
device performance.......................................................................................................................................... 13
Changes from Revision E (November 2021) to Revision F (April 2022)
Page
• 向数据表添加了 D（SOIC，8）封装和RUN（WQFN，10）封装.....................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBOS982
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ZHCSMO3J –JUNE 2020 –REVISED JUNE 2023
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5 Device Comparison Table
VOLTAGE NOISE
IQ / CHANNEL GBWP SLEW RATE
DEVICE
±VS (V)
AMPLIFIER DESCRIPTION
(mA)
0.70
2.7
(MHz)
(V/µs)
(nV/√Hz)
OPA2863
LMH6643
OPAx810
OPAx837
±6.3
±6.4
50
105
5.9
17
Unity-gain stable RRIO Bipolar Amplifier
Unity-gain stable NRI/RRO Bipolar Amplifier
Unity-gain stable RRIO FET-Input Amplifier
Unity-gain stable NRI/RRO Bipolar Amplifier
65
130
±13.5
±2.7
3.6
70
200
6.3
4.7
0.6
50
105
Decompensated Gain of 6 V/V stable CMOS
Amplifier
OPAx607
±2.75
0.9
50
24
3.8
6 Pin Configuration and Functions
VOUT
VS+
VOUT
VS-
VS+
1
2
3
5
4
1
2
3
6
5
VS-
PD
VIN+
VIN-
VIN+
VIN-
4
图6-1. OPA863 DBV Package,
6-Pin SOT-23
图6-2. OPA863 DBV Package,
5-Pin SOT-23
(Top View)
(Top View)
表6-1. Pin Functions: OPA863
PIN
NO.
TYPE(1)
DESCRIPTION
NAME
DBV
DBV
(SOT-23, 5) (SOT-23, 6)
Power down.
PD
5
I
—
Low = disabled, high = normal operation (pin must be driven).
VIN+
VIN–
VOUT
VS–
VS+
3
4
1
2
5
3
4
1
2
6
I
Noninverting input pin
I
Inverting input pin
O
P
P
Output pin
Negative power-supply pin
Positive power-supply pin
(1) I = input, O = output, and P = power.
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English Data Sheet: SBOS982
OPA863, OPA2863, OPA4863
ZHCSMO3J –JUNE 2020 –REVISED JUNE 2023
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VS+
10
VOUT1
1
VS+
8
7
6
5
VOUT1
VIN1-
1
2
3
4
VOUT2
9
8
VIN1-
2
VOUT2
VIN2-
VIN2+
PD2
VIN1+
3
VIN2-
VIN2+
VIN1+
7
6
VS-
4
PD1
5
VS-
图6-3. OPA2863 D Package, 8-Pin SOIC
and DGK Package, 8-Pin VSSOP,
(Top View)
图6-4. OPA2863 RUN Package,
10-Pin WQFN
(Top View)
表6-2. Pin Functions: OPA2863
PIN
NO.
TYPE(1)
DESCRIPTION
D (SOIC),
DGK
(VSSOP)
NAME
RUN
(WQFN)
Amplifier 1 power down.
Low = disabled, high = normal operation (pin must be driven).
PD1
PD2
4
6
I
I
—
—
Amplifier 2 power down.
Low = disabled, high = normal operation (pin must be driven).
2
3
6
5
1
7
4
8
2
3
I
I
Amplifier 1 inverting input pin
Amplifier 1 noninverting input pin
Amplifier 2 inverting input pin
Amplifier 2 noninverting input pin
Amplifier 1 output pin
VIN1–
VIN1+
VIN2–
VIN2+
VOUT1
VOUT2
VS–
8
I
7
I
1
O
O
P
P
9
Amplifier 2 output pin
5
Negative power-supply pin
Positive power-supply pin
VS+
10
(1) I = input, O = output, and P = power.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBOS982
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VOUT1
VIN1-
VIN1+
VS+
VOUT4
13 VIN4-
1
2
3
14
VIN4+
VS-
12
4
5
6
7
11
10
9
VIN2+
VIN2-
VIN3+
VIN3-
VOUT3
8
VOUT2
图6-5. OPA4863 PW Package,
14-Pin TSSOP
(Top View)
表6-3. Pin Functions: OPA4863
PIN
TYPE(1)
DESCRIPTION
NAME
VIN1–
VIN1+
VIN2–
VIN2+
VIN3–
VIN3+
VIN4–
VIN4+
VOUT1
VOUT2
VOUT3
VOUT4
VS–
NO.
2
I
I
Amplifier 1 inverting input pin
Amplifier 1 noninverting input pin
Amplifier 2 inverting input pin
Amplifier 2 noninverting input pin
Amplifier 3 inverting input pin
Amplifier 3 noninverting input pin
Amplifier 4 inverting input pin
Amplifier 4 noninverting input pin
Amplifier 1 output pin
3
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
P
P
7
Amplifier 2 output pin
8
Amplifier 3 output pin
14
11
4
Amplifier 4 output pin
Negative power-supply pin
Positive power-supply pin
VS+
(1) I = input, O = output, and P = power.
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English Data Sheet: SBOS982
OPA863, OPA2863, OPA4863
ZHCSMO3J –JUNE 2020 –REVISED JUNE 2023
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage
13
0.1
VS– to VS+
Supply turn-on/off maximum dV/dt, DBV-6 and D packages
V/µs
V
VI
VID
II
Input voltage
VS+ + 0.5
±1
VS– –0.5
Differential input voltage
Continuous input current(2)
Continuous output current(3)
Continuous power dissipation
Maximum junction temperature
Operating free-air temperature
Storage temperature
V
±10
mA
mA
IO
±30
See Thermal Information
150
TJ
°C
°C
°C
TA
125
150
–40
–65
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Continuous input current limit for both the ESD diodes to supply pins and amplifier differential input clamp diode. The differential input
clamp diode limits the voltage across it to 1 V with this continuous input current flowing through it.
(3) Long-term continuous current for electromigration limits.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
10
MAX
12.6
125
UNIT
V
Total supply voltage
Ambient temperature
VS+ –VS–
TA
25
°C
–40
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English Data Sheet: SBOS982
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7.4 Thermal Information: OPA863
OPA863
THERMAL METRIC(1)
DBV (SOT-23)
UNIT
5 PINS
6 PINS
161.8
73.9
RθJA
Junction-to-ambient thermal resistance
168.3
64.3
40.6
14.2
40.3
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ΨJT
YJB
Junction-to-board thermal resistance
42.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
21.2
42.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: OPA2863
OPA2863
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
180.3
D (SOIC)
8 PINS
120.0
63.3
RUN (WQFN)
10 PINS
110.2
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
67.5
66.8
101.9
63.2
43.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
9.8
17.2
2.9
YJB
100.1
62.5
43.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Thermal Information: OPA4863
OPA4863
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
99.5
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
27.6
56.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
4.4
YJB
55.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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Product Folder Links: OPA863 OPA2863 OPA4863
English Data Sheet: SBOS982
OPA863, OPA2863, OPA4863
ZHCSMO3J –JUNE 2020 –REVISED JUNE 2023
www.ti.com.cn
7.7 Electrical Characteristics: VS = 10 V
at VS+ = 5 V, VS– = –5 V, G = 1 V/V, RF = 0 Ωfor G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ
referenced to mid-supply, input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
GBWP
LSBW
Small-signal bandwidth
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
VOUT = 20 mVPP, G = 1, < 1 dB peaking
110
50
MHz
MHz
MHz
MHz
V/µs
ns
VOUT = 2 VPP
17
VOUT = 20 mVPP
15
SR
105
9
VOUT = 2–V step, G = –1
VOUT = 200–mV step
Rise, fall time
Settling time to 0.1%
Settling time to 0.01%
Overshoot/undershoot
57
ns
%
VOUT = 2–V step
70
1
VOUT = 2–V step
70
G = –1, 0.5 V overdrive beyond supplies
G = 1, 0.5 V overdrive beyond supplies
Overdrive recovery time
ns
100
–129
–138
–107
–125
5.9
HD2
HD3
HD2
HD3
eN
Second-order harmonic distortion
Third-order harmonic distortion
Second-order harmonic distortion
Third-order harmonic distortion
Input voltage noise
f = 20 kHz, VOUT = 2 VPP
f = 100 kHz, VOUT = 2 VPP
dBc
dBc
Flatband, 1/f corner at 25 Hz
Flatband, 1/f corner at 2 kHz
f = 1 MHz
nV/√Hz
pA/√Hz
iN
Input current noise
0.4
Closed-loop output impedance
Channel-to-channel crosstalk
0.2
Ω
f = 1 MHz, VOUT = 2 VPP, OPA2863
dBc
–124
DC PERFORMANCE
AOL
VOS
Open-loop voltage gain
VOUT = ±2.5 V
110
128
dB
Input-referred offset voltage
±0.4
1.3
3.5
mV
–1.3
TA = –40°C to +125°C,
D, DBV-5, RUN and DGK packages
±1
–3.5
±1
±1
4
4.4
TA = –40°C to +125°C, PW package
TA = 0°C to +85°C, DBV-6 package
TA = –40°C to +125°C, DBV-6 package
TA ≅ 25°C
–4
–4.4
–4.9
Input offset voltage drift
µV/°C
µA
±1
4.9
0.3
0.73
1.2
Input bias current
TA = –40°C to +85°C
1.6
TA = –40°C to +125°C
Input bias current drift
Input offset current
±3
7.6 nA/°C
TA = –40°C to +125°C
±10
30
nA
–30
INPUT
Input common-mode voltage range
Common-mode rejection ratio
VS++0.2
V
VS––0.2
CMRR
100
120
650 || 0.8
200 || 0.5
dB
VCM = VS––0.2 V to VS+ –1.6 V
Input impedance common-mode
Input impedance differential mode
MΩ|| pF
kΩ|| pF
OUTPUT
VS–+0.14
VS–+0.2
TA ≅ 25°C
VOL
Output voltage, low
V
VS–+0.15 VS–+0.22
TA = –40°C to +125°C
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English Data Sheet: SBOS982
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7.7 Electrical Characteristics: VS = 10 V (continued)
at VS+ = 5 V, VS– = –5 V, G = 1 V/V, RF = 0 Ωfor G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ
referenced to mid-supply, input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA ≅ 25°C
VS+–0.2 VS+–0.14
VS+–0.2 VS+–0.15
VOH
Output voltage, high
V
TA = –40°C to +125°C
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www.ti.com.cn
7.7 Electrical Characteristics: VS = 10 V (continued)
at VS+ = 5 V, VS– = –5 V, G = 1 V/V, RF = 0 Ωfor G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ
referenced to mid-supply, input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Linear output drive (sourcing/
sinking)
VOUT = ±2.5 V, ΔVOS < 1 mV
25
30
mA
OPA863 and OPA2863(1)
Short-circuit current
45
mA
POWER SUPPLY
700
120
970
TA ≅ 25°C
IQ
Quiescent current per amplifier
µA
dB
1280
TA = –40°C to +125°C
ΔVS = ±2 V(2)
PSRR
Power-supply rejection ratio
100
3.5
POWER DOWN (Pin Must be Driven)
Enable voltage threshold
4.5
V
V
Specified on above VS+ –0.5 V
Specified off below VS+ –1.5 V
Disable voltage threshold
Power-down quiescent current per
channel
2
3.3
50
µA
PD ≤VS+ –1.5 V
Power-down pin bias current
Turn-on time delay
2
6
nA
µs
µs
Turn-off time delay
4.5
AUXILIARY INPUT STAGE
Gain-bandwidth product
Input voltage noise
50
6
MHz
nV/√Hz
pA/√Hz
mV
Flatband, 1/f corner at 25 Hz
Flatband, 1/f corner at 100 Hz
Input current noise
0.4
Input-referred offset voltage
±0.15
0.2
1.3
0.6
1.3
–1.3
TA ≅ 25°C
Input bias current
µA
0.2
TA = –40°C to +125°C
VCM = 4.1 V to 5.2 V
ΔVS = ±0.6 V
Common-mode rejection ratio
Power supply rejection ratio
100
100
120
120
dB
dB
(1) Change in input offset voltage from no-load condition.
(2) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.
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English Data Sheet: SBOS982
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7.8 Electrical Characteristics: VS = 3 V
at VS+ = 3 V, VS– = 0 V, G = 1, RF = 0 Ωfor G =1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected
to 1 V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
GBWP
LSBW
Small-signal bandwidth
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate
VOUT = 20 mVPP, G = 1
97
50
MHz
MHz
MHz
MHz
V/µs
ns
VOUT = 1 VPP
26
VOUT = 20 mVPP
10
SR
105
10
VOUT = 1–V step, Gain = –1
VOUT = 200–mV step
Rise, fall time
Settling time to 0.1%
Settling time to 0.01%
Overshoot
58
ns
%
VOUT = 1–V step
VOUT = 1–V step
90
2
Undershoot
16
95
G = –1, 0.5V overdrive beyond supplies
Overdrive recovery time
ns
G = 1, 0.5V overdrive beyond supplies
100
–123
–132
–109
–129
6
HD2
HD3
HD2
HD3
eN
Second-order harmonic distortion
Third-order harmonic distortion
Second-order harmonic distortion
Third-order harmonic distortion
Input voltage noise
f = 20 kHz, VOUT = 1 VPP
f = 100 kHz, VOUT = 1 VPP
dBc
dBc
Flatband, 1/f corner at 25 Hz
Flatband, 1/f corner at 2 kHz
f = 1 MHz
nV/√Hz
pA/√Hz
iN
Input current noise
0.4
Closed-loop output impedance
Channel-to-channel crosstalk
0.2
Ω
f = 1 MHz, VOUT = 1 VPP, OPA2863
dBc
–127
DC PERFORMANCE
AOL
VOS
Open-loop voltage gain
VOUT = 1 V to 2 V
104
123
dB
Input-referred offset voltage
±0.4
1.3
3.5
mV
–1.3
TA = –40°C to +125°C,
D, DBV-5, RUN, and DGK packages
±1
–3.5
±1
±1
4
4.4
5
TA = –40°C to +125°C, PW package
TA = 0°C to +85°C, DBV-6 package
TA = –40°C to +125°C, DBV-6 package
TA ≅ 25°C
–4
–4.4
–5
Input offset voltage drift
μV/°C
±1
0.3
0.73
1.2
1.56
Input bias current
µA
TA = –40°C to +85°C
TA = –40°C to +125°C
Input bias current drift
Input offset current
±3
7.4 nA/°C
TA = –40°C to +125°C
±10
30
nA
–30
INPUT
Input common-mode voltage range
Common-mode rejection ratio
VS++0.2
V
VS––0.2
CMRR
94
115
360 || 0.9
200 || 0.5
dB
VCM = VS––0.2 V to VS+ –1.6 V
Input impedance common-mode
Input impedance differential mode
MΩ|| pF
kΩ|| pF
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7.8 Electrical Characteristics: VS = 3 V (continued)
at VS+ = 3 V, VS– = 0 V, G = 1, RF = 0 Ωfor G =1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected
to 1 V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VS–+ 0.13 VS–+ 0.15
VS–+ 0.13 VS–+ 0.16
TA ≅ 25°C
VOL
Output voltage, low
Output voltage, high
V
V
TA = –40°C to +125°C
TA ≅ 25°C
VS+–0.15 VS+–0.13
VS+–0.15 VS+–0.13
VOH
TA = –40°C to +125°C
Linear output drive (sourcing/
sinking)
VOUT = ±0.7 V, ΔVOS < 1 mV
23
33
45
mA
mA
OPA863 and OPA2863(1)
Short-circuit current
POWER SUPPLY
690
120
910
TA ≅ 25°C
IQ
Quiescent current per amplifier
µA
dB
1180
TA = –40°C to +125°C
ΔVS = ±1 V(2)
PSRR
Power-supply rejection ratio
100
1.5
POWER DOWN (Pin Must be Driven)
Enable voltage threshold
2.5
V
V
Specified on above VS+ –0.5 V
Specified off below VS+ –1.5 V
Disable voltage threshold
Power-down quiescent current per
channel
0.8
1.5
50
µA
PD ≤VS+ –1.5 V
Power-down pin bias current
Turn-on time delay
1
6.5
5
nA
µs
µs
Turn-off time delay
AUXILIARY INPUT STAGE
Gain-bandwidth product
Input voltage noise
50
6
MHz
nV/√Hz
pA/√Hz
mV
Flatband, 1/f corner at 25 Hz
Flatband, 1/f corner at 100 Hz
Input current noise
0.4
Input-referred offset voltage
±0.15
0.2
1.3
0.6
1.2
–1.3
TA ≅ 25°C
Input bias current
µA
0.4
TA = –40°C to +125°C
VCM = 2.1 V to 3.2 V
ΔVS = ±0.6 V
Common-mode rejection ratio
Power supply rejection ratio
100
100
120
115
dB
dB
(1) Change in input offset voltage from no-load condition.
(2) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.
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English Data Sheet: SBOS982
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7.9 Typical Characteristics: VS = 10 V
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩfor other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
3
0
3
0
-3
-3
-6
-6
-9
-9
-12
-15
-18
-21
-12
-15
-18
-21
G = 1 V/V
G = -1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
RL = 2 k
RL = 500
100k
1M
10M
100M
100k
1M
10M
Frequency (Hz)
100M
Frequency (Hz)
VOUT = 20 mVPP
图7-1. Small-Signal Frequency Response vs Gain
VOUT = 20 mVPP
图7-2. Small-Signal Frequency Response vs Output Load
6
1
3
0
0.5
0
-3
-6
-9
No CL
CL = 2.2 pF
CL =4.7 pF
CL = 10 pF, Rs = 200
CL = 10 pF, G = 2 V/V
-0.5
G = 1 V/V
G = 2 V/V
-1
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
VOUT = 20 mVPP
VOUT = 20 mVPP
图7-3. Frequency Response vs Load Capacitance
图7-4. Small-Signal Response Flatness vs Gain
3
0
6
3
0
-3
-6
-9
-3
-6
VOUT = 20 mVPP
VOUT = 200 mVPP
VOUT = 500 mVPP
VOUT = 1 VPP
VOUT = 2 VPP
VOUT = 4 VPP
TA = 25°C
TA = 125°C
TA = −45 °C
-9
VOUT = 8 VPP
-12
100k
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
VOUT = 20 mVPP
.
图7-5. Frequency Response vs Ambient Temperature
图7-6. Frequency Response vs Output Voltage
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7.9 Typical Characteristics: VS = 10 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩfor other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
3
3
0
0
-3
-3
-6
-9
-6
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
-9
TA = 25°C
TA = 125 °C
TA = −45 °C
-12
100k
100k
1M
10M
Frequency (Hz)
100M
1M
10M
100M
Frequency (Hz)
VOUT = 2 VPP
VOUT = 2 VPP
图7-7. Large-Signal Frequency Response vs Gain
图7-8. Frequency Response vs Ambient Temperature
-20
-20
HD2, G = 1 V/V
HD3, G = 1 V/V
HD2, G = 2 V/V
HD3, G = 2 V/V
HD2, VOUT = 2 VPP
HD3, VOUT = 2 VPP
HD2, VOUT = 4 VPP
HD3, VOUT = 4 VPP
-40
-60
-40
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
1k
10k
100k
Frequency (Hz)
1M
10M
1k
10k
100k
Frequency (Hz)
1M
10M
G = 1 V/V
VOUT = 2 VPP
图7-9. Harmonic Distortion vs Frequency
图7-10. Harmonic Distortion vs Gain
0.15
6
4
0.1
0.05
0
2
0
-0.05
-0.1
-0.15
-2
-4
-6
Time (200 ns/div)
Time (50 ns/div)
.
.
图7-11. Small-Signal Transient Response
图7-12. Large-Signal Transient Response
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English Data Sheet: SBOS982
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7.9 Typical Characteristics: VS = 10 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩfor other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
6
6
4
4
2
2
0
0
-2
-4
-6
-2
-4
-6
Input
Output
Input x -1 V/V
Output
Time (100 ns/div)
Time (100 ns/div)
Gain = 1 V/V
Gain = –1 V/V
图7-13. Input Overdrive Recovery
图7-14. Output Overdrive Recovery
1200
900
600
300
0
1000
750
500
250
0
-250
-500
-750
-1000
-300
-600
-6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
-5.5 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
Measured for 10 units
图7-15. Input Offset Voltage vs Input Common-Mode Voltage
图7-16. Input Bias Current vs Input Common-Mode Voltage
6
50
40
30
20
4
2
10
Sourcing
Sourcing
Sinking
Sinking
0
0
-10
-20
-30
-40
-50
-2
-4
-6
-40
-20
0
20
40
60
80
100 120 140
0
5
10
15
20
25
30
35
Ambient Temperature (°C)
Output Current (mA)
Output saturated and then short-circuited to opposite supply
图7-17. Output Voltage vs Load Current
图7-18. Output Short-Circuit Current vs Ambient Temperature
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7.9 Typical Characteristics: VS = 10 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩfor other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
20000
9000
18000
8000
16000
7000
14000
6000
12000
5000
10000
4000
8000
3000
6000
2000
4000
1000
2000
0
0
Quiescent Current per Channel (A)
μ= 678 μA, σ= 13 μA
Input Bias Current (nA)
μ= 251 nA, σ= 5.6 nA
图7-19. Quiescent Current Distribution
图7-20. Input Bias Current Distribution
6
5
4
3
2
1
0
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
Input Offset Drift (μV/°C)
μ
Input Offset Voltage ( V)
35 units, μ=-0.26 μV/°C, σ= 0.49 μV/°C, DGK package
μ= 209 μV, σ= 193 μV
图7-22. Input Offset Voltage Drift Distribution
图7-21. Input Offset Voltage Distribution
7
6
5
4
3
2
1
0
0.9
0.85
0.8
0.75
0.7
0.65
0.6
0.55
-40
-20
0
20
40
60
80
100 120 140
Ambient Temperature (°C)
Input Offset Drift (V/C)
35 units
32 units, μ= −0.02 μV/°C, σ= 0.98 μV/°C, DBV-6 package
图7-23. Input Offset Voltage Drift Distribution
图7-24. Quiescent Current vs Ambient Temperature
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7.9 Typical Characteristics: VS = 10 V (continued)
at VS+ = 5 V, VS– = –5 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩfor other gains, CL = 1 pF, RL = 2 kΩreferenced
to mid-supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
700
650
600
550
500
450
400
350
300
250
200
150
100
50
100
75
50
25
0
-25
-50
-75
-100
-125
-150
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (°C)
Ambient Temperature (°C)
35 units
Normalized to 25°C values, 35 units, DGK package
图7-25. Input Bias Current vs Ambient Temperature
图7-26. Input Offset Voltage vs Ambient Temperature
8
6
8
VPD
VOUTx10
6
4
4
2
2
0
0
-2
-4
-2
-4
-6
-8
-6
-8
VPD
VOUTx10
Time (2.5 s/div)
Time (2.5 s/div)
.
.
图7-27. Turn-On Time to DC Input
图7-28. Turn-Off Time to DC Input
8000
6000
4000
2000
0
2.8
2.4
2
1.6
1.2
0.8
0.4
0
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
-60 -40 -20
0
20
40
60
80 100 120 140
Power-Down Quiescent Current (A)
Ambient Temperature (C)
.
μ= 1.86 μA, σ= 0.076 μA
图7-30. Power-Down IQ vs Ambient Temperature
图7-29. Power-Down Quiescent Current Distribution
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7.10 Typical Characteristics: VS = 3 V
at VS+ = 3 V, VS– = 0 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected to 1
V, G = 1 V/V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
3
0
-3
-6
-9
-12
G = 1 V/V
-15
-18
-21
G = -1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
100k
1M
10M
Frequency (Hz)
100M
VOUT = 20 mVPP
VOUT = 1 VPP
图7-31. Small-Signal Frequency Response vs Gain
图7-32. Harmonic Distortion vs Frequency
0.15
1
0.1
0.05
0
0.5
0
-0.5
-1
-0.05
-0.1
-0.15
Time (200 ns/div)
Time (50 ns/div)
.
.
图7-33. Small-Signal Transient Response
图7-34. Large-Signal Transient Response
1000
1000
750
500
800
600
400
200
0
250
0
-250
-500
-750
-1000
-200
-400
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
Measured for 10 units
.
图7-35. Input Offset Voltage vs Input Common-Mode Voltage
图7-36. Input Bias Current vs Input Common-Mode Voltage
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7.10 Typical Characteristics: VS = 3 V (continued)
at VS+ = 3 V, VS– = 0 V, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩconnected to 1
V, G = 1 V/V, input and output VCM = 1 V, and TA ≅ 25°C (unless otherwise noted)
3
2.5
2
60
40
20
0
Sourcing
Sinking
Sourcing
Sinking
1.5
1
-20
-40
-60
0.5
0
-40
-20
0
20
40
60
80
100 120 140
0
5
10
15
20
25
30
35
40
Ambient Temperature (°C)
Output Current (mA)
.
Output saturated and then short-circuited to other supply
图7-37. Output Voltage vs Load Current
图7-38. Output Short-Circuit Current vs Ambient Temperature
6
4
2
0
6
4
2
0
-2
-4
-6
-2
-4
VPD
VOUTx10
VPD
VOUTx10
-6
Time (2.5 s/div)
Time (2.5 s/div)
.
.
图7-39. Turn-On Time to DC Input
图7-40. Turn-Off Time to DC Input
5000
4000
3000
2000
1000
0
1
0.8
0.6
0.4
0.2
0
-60 -40 -20
0
20
40
60
80 100 120 140
Ambient Temperature (C)
Power-Down Quiescent Current (A)
μ= 0.64 μA, σ= 0.056 μA
.
图7-42. Power-Down IQ vs Ambient Temperature
图7-41. Power-Down Quiescent Current Distribution
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7.11 Typical Characteristics: VS = 3 V to 10 V
at VOUT = 2 VPP, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced to mid-
supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
3
3
0
0
-3
-3
-6
-6
-9
-9
VS = 10 V
VS = 5 V
VS = 3 V
VS = 10 V
VS = 5 V
VS = 3 V
-12
-12
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
100M
Frequency (Hz)
VOUT = 20 mVPP
图7-43. Frequency Response vs Supply Voltage
VOUT = 1 VPP
图7-44. Frequency Response vs Supply Voltage
100
10
Main Stage
Auxiliary Stage
10
1
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10
100
1k
10k
100k
1M
Frequency (Hz)
D401
.
.
图7-45. Input Voltage Noise Density vs Frequency
图7-46. Input Current Noise Density vs Frequency
140
140
PSRR−
PSRR+
120
100
80
60
40
20
0
120
100
80
60
40
20
-20
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
.
.
图7-47. Common-Mode Rejection Ratio vs Frequency
图7-48. Power Supply Rejection Ratio vs Frequency
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English Data Sheet: SBOS982
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7.11 Typical Characteristics: VS = 3 V to 10 V (continued)
at VOUT = 2 VPP, RF = 0 Ωfor Gain = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩreferenced to mid-
supply, G = 1 V/V, input and output referenced to mid-supply, and TA ≅ 25°C (unless otherwise noted)
100
80
60
40
20
0
135
120
105
90
210
180
150
120
90
Magnitude
Phase
75
60
60
45
30
30
0
15
-30
-60
-90
0
-15
1
10
100
1k
10k 100k
1M
10M 100M
1
10
100
1k
10k 100k
1M
10M 100M
Frequency (Hz)
Frequency (Hz)
.
Small-signal response
图7-49. Open-Loop Output Impedance vs Frequency
图7-50. Open-Loop Gain and Phase vs Frequency
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
HD2, VS = 10 V
HD3, VS = 10 V
HD2, VS = 5 V
HD3, VS = 5 V
-120
-140
Ch-A to Ch-B
Ch-B to Ch-A
-140
100k
-160
1k
1M
10M
100M
10k
100k
Frequency (Hz)
1M 10M
Frequency(Hz)
DGK package
VOUT = 2 VPP
图7-52. Crosstalk vs Frequency
图7-51. Harmonic Distortion vs Supply Voltage
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8 Detailed Description
8.1 Overview
The OPAx863 devices are low-power, 50‑MHz, rail-to-rail input and output (RRIO), bipolar, voltage-feedback
operational amplifiers with a voltage noise density of 5.9 nV/√Hz and 1/f noise corner at 25 Hz. The OPAx863
work with a wide-supply voltage range of 2.7 V to 12.6 V, and consume only 700 μA quiescent current. The
OPAx863 operate with a 2.7 V supply, are RRIO capable, consume low-power, and offer a power-down mode,
which makes them great amplifiers for 3.3‑V or lower-voltage applications that require excellent ac performance.
The main and auxiliary input stages of the amplifier are matched for gain bandwidth product (GBW), noise, and
offset voltage and designed for applications that require wide dynamic input range and good SNR.
The device includes an overload power limit feature which limits the increase in quiescent current with over-
driven and saturated outputs to either of the supply rails. For more details of this overload power limit feature,
see 节8.3.2.1. The amplifier's output is protected against short-circuit fault conditions.
The OPAx863 feature a power-down mode (PD) with a PD quiescent current of 1.5 µA (maximum) with a 3‑V
supply, with turn-on and turn-off time within less than 6.5 µs.
8.2 Functional Block Diagram
PD
VS+
OPAx863
Auxiliary
NPN-
+
–
Stage
VIN+
EN
Output
Short-Circuit
Protection
CC
Main
PNP-
Stage
VOUT
+
–
Overload
Power
EN
Limiting
–
–
+
VIN–
VS+ –1.6 V
VS–
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8.3 Feature Description
8.3.1 Input Stage
The OPAx863 include a rail-to-rail input stage. The main stage differential pair using PNP bipolar transistors
operates for common-mode input voltages from VS– – 0.2 V to VS+ – 1.6 V. The amplifier inputs transition into
the auxiliary stage using NPN transistors for common-mode input voltages from VS+ –1.6 V till VS+ + 0.2 V. The
PNP and NPN input stages offer a gain-bandwidth product of 50 MHz and a voltage noise density of 6.3 nV/√
Hz. The offset voltage for the two input stages is matched to lie within the device specifications. The auxiliary
NPN input stage does not use the slew-boost circuit during large-signal transient response. The input bias
current for the PNP and NPN input stages is opposite in polarity, which adds an additional offset based on the
values of the gain-setting and feedback resistors. A common-mode input voltage transition between these input
stages causes a crossover distortion that must be considered in high-frequency applications requiring excellent
linearity. Limit the common-mode input voltage to VS+ – 1.6 V (maximum) for main-stage operation across
process and ambient temperature.
The OPAx863 are bipolar amplifiers; therefore, the two inputs are protected with antiparallel back-to-back diodes
between the inputs, which limits the maximum input differential voltage to 1 V. The amplifier is slew limited, and
the two inputs are pulled apart up to 1 V when the antiparallel diodes begin to conduct in very fast input or output
transient conditions. Make sure to use gain-setting and feedback resistors large enough to limit the current
through these diodes in such conditions.
8.3.2 Output Stage
The OPAx863 feature a rail-to-rail output stage with possible signal swing from VS– + 0.2 V to VS+ – 0.2 V.
Violating the output headroom of either supply causes output signal clipping and introduces distortion.
The OPAx863 integrate an output short-circuit protection circuit that makes the device rugged for use in real-
world applications.
8.3.2.1 Overload Power Limit
The OPAx863 include overload power limiting that limits the increase in device quiescent current with output
saturated to either of the supplies. Typically, when an amplifier output saturates, the two inputs are pulled apart,
which can enable the slew-boost circuit. The input differential voltage is an error voltage in negative feedback
that the amplifier core nullifies by engaging the slew-boost circuit and driving the output stage deeper into
saturation. After the input to an amplifier attains a value large enough to saturate the output, any further increase
in this input excitation results in a finite input differential voltage. As the output stage transistor is pushed deeper
into saturation, the base-to-collector current gain (hFE) drops with an increase in the base and collector current,
and an increase in the device quiescent current. This increase in quiescent current can cause a catastrophic
failure in multichannel, high-gain, high-density front-end designs, and reduce operating lifetime in portable,
battery-powered systems.
The OPAx863 overload power limiting includes an intelligent output saturation-detection circuit that limits the
device quiescent current to 2.2-mA per channel under dc overload conditions. This increase in quiescent current
is smaller with ac input or output and output saturation duration for only a fraction of the overall signal time
period. 表 8-1 compares the increase in quiescent current with 50‑mV input overdrive for OPAx863 devices and
other voltage-feedback amplifiers without overload power limit.
表8-1. Quiescent Current With Saturated Outputs
INCREASE IN IQ FROM
INPUT DIFFERENTIAL
VOLTAGE
QUIESCENT CURRENT
DURING OVERLOAD
DEVICE
STEADY-STATE
CONDITION
OPAx863 with overload power limit
50 mV
50 mV
1.1 mA
1.57 ×
3.43 ×
Competitor amplifier without overload power limit
1.96 mA
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8.3.3 ESD Protection
As 图 8-1 shows, all device pins are protected with internal ESD protection diodes to the power supplies. These
diodes provide moderate protection to input overdrive voltages greater than the supplies. The protection diodes
typically support 10-mA continuous input and output currents. Use series current limiting resistors if input
voltages exceeding the supply voltages occur at the amplifier inputs, which makes sure that the current through
the ESD diodes remains within the rated value. OPAx863 is a bipolar amplifier; therefore, the two inputs are
protected with antiparallel, back-to-back diodes between the inputs that limits the maximum input differential
voltage to approximately 1 V. Make sure to use gain-setting and feedback resistors large enough to limit the
current through these diodes in fast slewing conditions.
VS+
Power Supply
ESD Cell
VIN+
PD
+
œ
VOUT
VIN-
VS-
图8-1. Internal ESD Protection
8.4 Device Functional Modes
8.4.1 Power-Down Mode
The OPAx863 includes a power-down mode for low-power standby operation with a quiescent current of only 1.5
μA (maximum) with a 3-V supply and high output impedance. Many low-power systems are active for only a
small time interval when the parameters of interest are measured and remain in low-power standby mode for a
majority of the time and an overall small average power consumption. The OPAx863 enables such a low-power
operation with quick turn-on within less than 6.5 μs. See the Electrical Characteristics tables for power-down pin
control thresholds.
Always drive PD pin to avoid false triggering and oscillations. If power-down mode is not used, then connect the
PD pin to VS+. For applications that need power-down mode, use an external pull-up resistor from the PD pin to
VS+ (driven with an open-collector power-down control logic).
VS+
RPU
1 M
CPU
1 nF
OPAx863
Control
Logic
PD
VS–
图8-2. Power Down Control
图 8-2 shows the choice of value of the pull-up resistor RPU, which impacts the current consumption in power-
down mode. Using a large RPU reduces power consumption, but increases the noise at the PD pin, which can
cause the amplifier to power down. A 1‑nF capacitor can be used in parallel with RPU to avoid coupling of
external noise and false triggering. For the case of the PD pin driven to VS-, the IPU current through RPU is given
as:
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ꢃ
ꢄ
− ꢃ
ꢄ−
ꢀꢁꢂ
ꢅꢁꢂ
(1)
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The OPAx863 are classic voltage-feedback amplifiers with two high-impedance inputs and a low-impedance
output. These devices have a GBW of 50 MHz, 5.9 nV/√Hz of noise, RRIO capability, and precision
performance consuming only 700 µA quiescent current per channel These features make the OPAx863 an
excellent choice for use in low-side current sensing, ADC input driver, and reference buffering with fast settling,
buffers, high gain and filter circuits. The overload power limit makes the OPAx863 truly low-power in high-gain,
multichannel systems limiting any increase in quiescent current during output overload conditions.
9.2 Typical Applications
9.2.1 Low-Side Current Sensing
Power converters use current-mode feedback control for excellent transient response and multiphase load
sharing. Inverter stages control the phase currents for torque control in motor drives. As a result of the simplicity
and low-cost, many of these topologies use difference-amplifier-based, low-side current sensing. 图 9-1 shows
the use of the OPAx863 in a difference amplifier circuit for low-side current sensing.
300V
3.3V
Switching
Circuit
TLV3201
VTH
+
12kΩ
Interrupt
œ
ISH
3.3V
3.3V
MCU
600Ω
600Ω
OPAx863
VOUT
250Ω
œ
RSH
ADS7056
Digital I/O
+
220pF
12kΩ
GND
1.65V
图9-1. Low-Side Current Sensing in Power Converters
9.2.1.1 Design Requirements
表9-1. Design Requirements
PARAMETER
DESIGN REQUIREMENT
Shunt resistor
Input current
10 mΩ
15 APP
Output voltage
3 VPP
50 kHz
Switching frequency
Data acquisition
1 MSPS with 0.1% accuracy
10 Vpk
Input voltage due to ground bounce
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9.2.1.2 Detailed Design Procedure
In a difference amplifier circuit, the output voltage is given by:
4(
81 =
+5*45* + 84'(
4)
(2)
For lowest system noise, small values of RF and RG are preferred. The smallest value of RG is limited by the
input transient voltage (10 V here) seen by the circuit, and is given by:
8
+0(I=T .) F 8& F 8
5
4) =
+
&(I=T .)
(3)
Where,
• VIN(maximum) is the maximum input transient voltage seen by the circuit.
• VD is the forward voltage drop of ESD diodes at the amplifier input.
• ID(maximum) is the maximum current rating of the ESD diodes at the amplifier input.
For a difference amplifier gain of 20 V/V, an RF of 12 kΩ and RG of 600 Ω are used. With a clock frequency of
40 MHz and the ADS7056 sampling at 1 MSPS, the available acquisition time for amplifier output settling is 550
ns. 图 9-2 shows the simulation results for the circuit in 图 9-1. The worst-case peak-to-peak input transient
condition is simulated. The output of the OPAx863 device settles to within 0.1% accuracy within 543 ns. If using
a slower clock frequency with the ADC is desired, then the acquisition time reduces with the same sampling rate,
which degrades measurement accuracy. Alternatively, the sampling rate can be reduced to recover the required
acquisition time and 0.1% accuracy.
9.2.1.3 Application Curves
4
3.5
3
1.2
1.1
1
2.5
2
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
1
0.5
0
-0.5
-1
VIN x 20
OPAx863 O/P
S/H Voltage
% Error
-1.5
-2
Time (150 ns/div)
D805
图9-2. 0.1% Settling Performance
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9.2.2 Front-End Gain and Filtering
C2
D1
RBIAS
R2
-VBIAS
VS+
C1
D2
R1
RISO
œ
VS+
œ
+
CSH
RP
+
VS-
VS-
High-Gain Band Pass Filter
High-Speed Peak Detector
图9-3. High-Gain Narrow Bandpass Filter and Peak Detector Circuit
Ultrasonic signaling is used for proximity and obstacle detection, level sensing, sonars, and so forth. Such signal
chains detect the amplitude of received ultrasonic signal at a particular center frequency. 图 9-3 shows a high-
gain narrow bandpass filter and peak detector circuit using any of the OPAx863 devices. The signal at the
frequency of interest is filtered out, gained, and peak detected to report the amplitude at the output of this circuit.
The phase information is lost in this circuit. The OPAx863 devices are used with the 50-MHz GBW to add a
single-stage gain and filtering, and the peak detection capability is easily made with the RRIO capability of these
amplifiers.
9.2.3 Low-Power SAR ADC Driver and Reference Buffer
图 9-4 shows the use of the OPAx863 as a SAR ADC input driver and reference buffer driving the ADS7945.
sensors, which are used for interface with the physical environment, exhibit high output impedance, and cannot
drive SAR ADC inputs directly. A wide-GBW amplifier, such as the OPAx863, is needed to charge the switching
capacitors at the SAR ADC input, and quickly settle to the required accuracy within the given acquisition time.
The ADC core draws transient current from the reference input during the conversion (digitization) phase, which
must be driven with a wide-GBW amplifier to offer fast settling and maintain a stable reference voltage for
excellent digitization performance. The OPAx863 reference buffer is used in a composite loop with the OPA378
precision amplifier because of limitations in precision performance of wide-GBW amplifiers. The precision
amplifier maintains low-offset output, whereas the OPAx863 devices provide the output drive and fast-settling
performance.
RF
RG
6 V
5 V
5 V
–
RS
AVDD
DVDD
Sensor
OPAx863
+
ZOUT
ADS7945
14-bit
CCB
2 MSPS
VREF
5 V
12 V
6 V
–
OPA378
+
–
REF5050
5.0 V
Reference
RFILT
OPAx863
+
CFILT
图9-4. OPAx863 as Low-Power SAR ADC Driver
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9.2.4 Variable Reference Generator Using MDAC
High-speed amplifiers can be used as a voltage buffer at MDAC output to generate a fast-settling variable
reference voltage. 图9-5 shows a representative circuit using DAC8801 and OPAx863.
VDD
RFB
+6 V
IOUT
VREF
–
+
DAC8801
VOUT
OPAx863
6 V
图9-5. Variable Reference Generator Using MDAC and OPAx863
9.2.5 Clamp-On Ultrasonic Flow Meter
图 9-6 shows how ultrasonic flow meters measure the rate of flow of a liquid using transit-time difference (t12–
t21), which depends on the flow rate. 图 9-6 shows a representative schematic for a non-intrusive ultrasonic flow
meter using the OPAx863 and 12-V transducer excitation. The OPAx863 are used for the forward path as a
unity-gain buffer for 12-V pulsed transducer excitation at NODE 1. At the same time, the receiver circuit at NODE
2 (which also uses the OPAx863) first provides an ac-gain followed by a dc-level shift to lead to the PGA, ADC,
and processor within the MSP430™ microcontroller.
NODE 2 and NODE 1 use similar transmit and receive circuits (discussed previously) for the reverse path. The
OPAx863 wide GBW of 50 MHz introduces minimal phase-delay and low-noise for excellent flow rate
measurement. The amplifier stays in power-down mode for a majority of the time in battery-powered systems.
This configuration results in very small average system-level power consumption and prolonged battery lifetime
with the 1.5‑µA (maximum) power-down mode quiescent current with a 3-V supply. The transmit and receive
signal chains are connected to the same point at the respective node transducers. Therefore, the OPAx863 12.6-
V supply voltage capability enables 12-V transducer excitation without any damage to the front-end, or a need
for external switches, thus enabling a more compact solution. These specifications make the OPAx863 an
excellent choice for flow measurements in large diameter pipes and non-intrusive flow meters. The TIDM-02003
reference design discusses an ultrasonic gas flow sensing subsystem which uses high-speed amplifiers for front-
end amplification.
NODE-1
CFilt
NODE-2
3.3 V
CG
RG
RF
12 V
3.3 V
RISO
œ
12 V
R‘
12 V
MSP430FR6043
ADC
VTX
CAC2
+
OPAx863
12 V
0 V
œ
R
Processor
PGA
+
OPAx863
VRX
t12
CAC1
R‘
R
Transmitter
TRX2
TRX1
VTX
Receiver
12 V
VRX
0 V
Receiver
Transmitter
t21
图9-6. Non-Intrusive Ultrasonic Flow Meter
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9.3 Power Supply Recommendations
The OPAx863 is intended to operate on supplies ranging from 2.7 V to 12.6 V. The OPAx863 devices operate on
single-sided supplies, split and balanced bipolar supplies, or unbalanced bipolar supplies. Operating from a
single supply has numerous advantages. The dc errors, due to the –PSRR term, can be minimized with the
negative supply at ground. Typically, ac performance improves slightly at 10-V operation with minimal increase in
supply current. Minimize the distance (< 0.1 in) from the power supply pins to high-frequency, 0.01-µF
decoupling capacitors. A larger capacitor (2.2 µF typical) is used along with a high-frequency, 0.01-µF supply-
decoupling capacitor at the device supply pins. Only the positive supply has these capacitors for single-supply
operation. Use these capacitors from each supply to ground when a split-supply is used. If necessary, place the
larger capacitors further from the device and share these capacitors among several devices in the same area of
the printed circuit board (PCB). An optional supply decoupling capacitor across the two power supplies (for split-
supply operation) reduces second harmonic distortion.
9.4 Layout
9.4.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier (like the OPAx863) requires careful attention to
board layout parasitics and external component types. The OPA2863 DGK Evaluation Module user's guide can
be used as a reference when designing the circuit board. Recommendations that optimize performance includes
the following:
1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability on the noninverting input and can react with the source
impedance to cause unintentional band-limiting. Open a window around the signal I/O pins in all of the
ground and power planes around those pins to reduce unwanted capacitance. Otherwise, ground and power
planes must be unbroken elsewhere on the board.
2. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency 0.01-µF decoupling
capacitors. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the
supply pins. These capacitors can be placed somewhat farther from the device and shared among several
devices in the same area of the PCB.
3. Careful selection and placement of external components preserves the high-frequency performance
of the OPAx863. Resistors must be a low reactance type. Surface-mount resistors work best and allow a
tighter overall layout. Other network components, such as noninverting input termination resistors, must also
be placed close to the package. Keep resistor values as low as possible and consistent with load-driving
considerations. Lowering the resistor values keeps the resistor noise terms low and minimizes the effect of
the parasitic capacitance. Lower resistor values, however, increase the dynamic power consumption
because RF and RG become part of the amplifier output load network.
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9.4.1.1 Thermal Considerations
The OPAx863 does not require heat sinking or airflow in most applications. The maximum allowed junction
temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction
temperature to exceed 150°C.
Operating junction temperature (TJ) is given by,
TJ = TA + PD x RƟJA
(4)
where
• TA is the ambient temperature
• PD is the total power dissipation internal to the amplifier
• RƟJA is the junction-to-ambient thermal resistance
The total power dissipation PD = PDQ + PDL
where
• PDQ = (VS+ ‐VS-) x IQ, is the power dissipation due to the amplifier quiescent current
• PDL(max) = VS 2 / (4 × RL), is the internal power dissipation due to the output load current
As a worst-case example, compute the maximum TJ using an OPA2863-DGK (VSSOP package) configured as a
unity gain buffer, operating on ±6-V supplies at an ambient temperature of 25°C and driving a grounded 500-Ω
load.
PD = 12 V × 2 mA + 62 / (4 × 500 Ω) = 42 mW
(5)
Maximum TJ = 25°C + (0.042 W × 180.3°C/W) = 33°C, which is much less than the maximum allowed junction
temperature of 150°C.
9.4.2 Layout Example
VS+
Representative schematic of a
single channel
CBYP
RS
+
t
CBYP
VS-
RF
RG
Ground and power plane exist on inner
layers.
Ground and power plane removed
from inner layers. Ground fill on outer
layers also removed
CBYP
RS
Place series output resistors close
to output pin to minimize
parasitic capacitance
1
2
8
7
RF
RS
Place bypass capacitors
close to power pins
RG
RF
Place gain and feedback resistors close
to pins to minimize stray capacitance
3
4
6
5
RG
Place bypass capacitors
close to power pins
Remove GND and Power plane under
output and inverting pins to minimize
stray PCB capacitance
CBYP
图9-7. Layout Recommendation for Dual-Channel DGK Package
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, OPA2863ADGK Evaluation Module user's guide
• Texas Instruments, Single-Supply Op Amp Design Techniques application report
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
MSP430™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBOS982
32
Submit Document Feedback
Product Folder Links: OPA863 OPA2863 OPA4863
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2863DR
OPA2863IDGKR
OPA2863RUNR
OPA4863PWR
OPA863DBVR
OPA863SIDBVR
XOPA4863IPWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
QFN
D
8
8
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
O2863D
Samples
Samples
Samples
Samples
Samples
Samples
Samples
DGK
RUN
PW
NIPDAUAG
NIPDAUAG
NIPDAU
SN
2FJ4
10
14
5
O263
TSSOP
SOT-23
SOT-23
TSSOP
OPA4863
2QS5
O863
DBV
DBV
PW
6
SN
14
2000
TBD
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jun-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2863 :
Automotive : OPA2863-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2863DR
OPA2863IDGKR
OPA2863RUNR
OPA4863PWR
OPA863DBVR
OPA863SIDBVR
SOIC
VSSOP
QFN
D
8
8
3000
2500
3000
3000
3000
3000
330.0
330.0
180.0
330.0
178.0
178.0
12.4
12.4
8.4
6.4
5.3
2.2
6.9
3.3
3.3
5.2
3.4
2.2
5.6
3.2
3.2
2.1
1.4
1.2
1.6
1.4
1.4
8.0
8.0
4.0
8.0
4.0
4.0
12.0
12.0
8.0
Q1
Q1
Q2
Q1
Q3
Q3
DGK
RUN
PW
10
14
5
TSSOP
SOT-23
SOT-23
12.4
9.0
12.0
8.0
DBV
DBV
6
9.0
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2863DR
OPA2863IDGKR
OPA2863RUNR
OPA4863PWR
OPA863DBVR
OPA863SIDBVR
SOIC
VSSOP
QFN
D
8
8
3000
2500
3000
3000
3000
3000
356.0
366.0
213.0
356.0
180.0
190.0
356.0
364.0
191.0
356.0
180.0
190.0
35.0
50.0
35.0
35.0
18.0
30.0
DGK
RUN
PW
10
14
5
TSSOP
SOT-23
SOT-23
DBV
DBV
6
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RUN 10
2 X 2, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4228249/A
www.ti.com
PACKAGE OUTLINE
RUN0010B
WQFN - 0.8 mm max height
S
C
A
L
E
5
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
2.1
1.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
SYMM
5
(0.2) TYP
4
6
SYMM
2X 1.5
6X 0.5
9
1
0.3
0.2
10X
10
PIN 1 ID
0.1
C A B
0.6
10X
0.05
0.4
4226925/A 08/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RUN0010B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10
SEE SOLDER MASK
DETAIL
10X (0.7)
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226925/A 08/2021
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RUN0010B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
10X (0.7)
10
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
SYMM
(1.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
4226925/A 08/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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