OPA858 [TI]
具有 FET 输入的 5.5GHz 增益带宽积、解补偿跨阻放大器;
| 型号： | OPA858 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 FET 输入的 5.5GHz 增益带宽积、解补偿跨阻放大器 放大器 |
| 文件： | 总37页 (文件大小：2852K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
OPA858 5.5GHz 增益带宽积、7V/V 增益稳定型 FET 输入放大器
1 特性
3 说明
1
•
高增益带宽积：5.5GHz
解补偿，增益 ≥ 7V/V（稳定）
超低偏置电流 MOSFET 输入：10pA
低输入电压噪声：2.5nV/√Hz
压摆率：2000V/µs
OPA858 是一款具有 CMOS 输入的低噪声运算放大
器，适用于宽带跨阻和电压放大器 应用。当将该器件
配置为跨阻放大器 (TIA) 时，5.5GHz 增益带宽积
(GBWP) 可为 需要 在数十至数百千欧范围内的跨阻增
益下实现高闭环带宽的应用提供支持。
•
•
•
•
•
低输入电容：
下图展示了当将 OPA858 配置为 TIA 时，该放大器的
带宽和噪声性能与光电二极管电容的函数关系。计算总
噪声时所依据的带宽范围为：从直流到左轴上计算得出
的 f-3dB 频率。OPA858 封装 具有 反馈引脚 (FB)，可
简化输入和输出之间的反馈网络连接。
–
–
共模：0.6pF
差动：0.2pF
•
宽输入共模范围：
–
–
与正电源相差 1.4V
包括负电源
OPA858 经过优化，可用于光学飞行时间 (ToF) 系
统，下图所示系统便是一个例子，其中 OPA858 是与
TDC7201 时数转换器搭配使用。OPA858 可搭配高速
模数转换器 (ADC) 和用以驱动该 ADC 的差动输出放
大器（如 THS4541 或 LMH5401），用于高分辨率激
光雷达系统。
•
•
•
•
•
TIA 配置下的输出摆幅为 2.5VPP
电源电压范围：3.3V 至 5.25V
静态电流：20.5mA
采用 8 引脚 WSON 封装
温度范围：–40 至 +125°C
2 应用
器件信息(1)
•
•
•
•
•
•
•
•
•
高速跨阻放大器
器件型号
OPA858
封装
WSON (8)
封装尺寸（标称值）
激光测距
2.00mm × 2.00mm
激光雷达接收器
液位变送器（光学）
光学时域反射法 (OTDR)
分布式温度检测
3D 扫描仪
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
飞行时间 (ToF) 系统
自主驾驶系统
空白
高速飞行时间接收器
光电二极管电容与带宽和噪声
CF
450
400
350
300
250
200
150
100
50
110
100
90
RF
VBIAS
f-3dB, RF = 10 kW
f-3dB, RF = 20 kW
IRN, RF = 10 kW
IRN, RF = 20 kW
Rx
Lens
5 V
TLV3501
+
œ
3.5 V
+
OPA858
Stop 2
Start 2
VREF
œ
80
CF
RF
70
TDC7201
(Time-to-
Digital
VBIAS
60
5 V
Converter)
TLV3501
+
œ
50
3.5 V
+
OPA858
Stop 1
Start 1
40
VREF
œ
30
0
20
20
Tx
Lens
0
2
4
6
8
10
12
14
16
18
MSP430
ꢀController
Pulsed Laser
Diode
Photodiode capacitance (pF)
D209
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS629
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ............................................... 22
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Example .................................................... 25
13 器件和文档支持 ..................................................... 27
13.1 接收文档更新通知 ................................................. 27
13.2 社区资源................................................................ 27
13.3 商标....................................................................... 27
13.4 静电放电警告......................................................... 27
13.5 术语表 ................................................................... 27
14 机械、封装和可订购信息....................................... 28
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics .......................................... 5
7.6 Typical Characteristics ............................................. 7
Parameter Measurement Information ................ 14
8.1 Parameter Measurement Information ..................... 14
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (April 2018) to Revision A
Page
•
已更改 将器件状态从“预告信息”更改为“生产数据” ................................................................................................................. 1
2
Copyright © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
5 Device Comparison Table
MINIMUM STABLE
GAIN
VOLTAGE NOISE
INPUT
CAPACITANCE (pF)
GAIN BANDWIDTH
(GHz)
DEVICE
INPUT TYPE
(nV/√Hz)
OPA858
OPA855
LMH6629
CMOS
Bipolar
Bipolar
7 V/V
7 V/V
2.5
0.8
0.8
5.7
5.5
8
0.98
0.69
10 V/V
4
6 Pin Configuration and Functions
DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
FB
NC
INœ
IN+
1
2
3
4
8
7
6
5
PD
VS+
OUT
VSœ
Thermal
Pad
Not to scale
NC - no internal connection
Pin Functions
PIN
I/O
DESCRIPTION
NAME
FB
NO.
1
I
I
Feedback connection to output of amplifier
Inverting input
IN–
3
IN+
4
I
Noninverting input
NC
2
—
O
Do not connect
OUT
6
Amplifier output
Power down connection. PD = logic low = power off mode; PD = logic high = normal
operation
PD
8
I
VS–
5
7
—
—
—
Negative voltage supply
VS+
Positive voltage supply
Thermal pad
Connect the thermal pad to VS–
Copyright © 2018, Texas Instruments Incorporated
3
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.5
UNIT
VS
Total supply voltage (VS+ – VS–
)
VIN+, VIN–
VID
Input voltage
(VS–) – 0.5
(VS–) – 0.5
(VS+) + 0.5
1
V
Differential input voltage
Output voltage
VOUT
IIN
IOUT
TJ
(VS+) + 0.5
±10
Continuous input current
Continuous output current(2)
Junction temperature
Operating free-air temperature
Storage temperature
mA
°C
±100
150
TA
125
TSTG
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Long-term continuous output current for electromigration limits.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VS
Total supply voltage (VS+ – VS–
)
3.3
5
5.25
V
7.4 Thermal Information
OPA858
THERMAL METRIC(1)
DSG (WSON)
8 PINS
80.1
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
100
45
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.8
ψJB
45.2
RθJC(bot)
22.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
7.5 Electrical Characteristics
VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced
to midsupply, and TA = 25℃ (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
AC PERFORMANCE
SSBW
LSBW
GBWP
Small-signal bandwidth
Large-signal bandwidth
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
Slew rate (10% - 90%)
Rise time
VOUT = 100 mVPP
1.2
600
5.5
130
2000
0.3
0.3
8
GHz
MHz
GHz
MHz
V/µs
ns
C
VOUT = 2 VPP
C
C
C
C
C
C
C
C
C
C
SR
tr
VOUT = 2-V step
VOUT = 100-mV step
VOUT = 100-mV step
VOUT = 2-V step
tf
Fall time
ns
Settling time to 0.1%
Settling time to 0.001%
Overshoot or undershoot
Overdrive recovery
ns
VOUT = 2-V step
3000
7%
200
88
ns
VOUT = 2-V step
2x output overdrive (0.1% recovery)
f = 10 MHz, VOUT = 2 VPP
f = 100 MHz, VOUT = 2 VPP
f = 10 MHz, VOUT = 2 VPP
f = 100 MHz, VOUT = 2 VPP
f = 1 MHz
ns
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
dBc
C
C
64
86
dBc
68
en
Input-referred voltage noise
2.5
0.15
nV/√Hz
C
C
ZOUT
Closed-loop output impedance
f = 1 MHz
Ω
DC PERFORMANCE
AOL
Open-loop voltage gain
72
–5
75
±0.8
±2
dB
mV
A
A
B
A
A
VOS
Input offset voltage
Input offset voltage drift
Input bias current
TA = 25°C
5
ΔVOS/ΔT
IBN, IBI
IBOS
TA = –40°C to +125°C
TA = 25°C
µV/°C
pA
±0.4
±0.01
5
5
Input offset current
TA = 25°C
pA
VCM = ±0.5 V, referenced to
midsupply
CMRR
Common-mode rejection ratio
70
90
dB
A
INPUT
Common-mode input resistance
Common-mode input capacitance
Differential input resistance
1
0.62
1
GΩ
pF
GΩ
pF
V
C
C
C
C
A
A
A
B
CCM
CDIFF
VIH
Differential input capacitance
0.2
1.9
0
Common-mode input range (high) CMRR > 66 dB, VS+ = 3.3 V
1.7
3.4
VIL
Common-mode input range (low)
CMRR > 66 dB, VS+ = 3.3 V
CMRR > 66 dB
0.4
0.4
V
3.6
3.4
VIH
Common-mode input range (high)
V
V
TA = –40°C to +125°C, CMRR > 66
dB
CMRR > 66 dB
0
A
B
VIL
Common-mode input range (low)
TA = –40°C to +125°C, CMRR > 66
dB
0.35
OUTPUT
VOH
Output voltage (high)
Output voltage (high)
Output voltage (low)
TA = 25°C, VS+ = 3.3 V
TA = 25°C
2.3
2.4
4.1
V
V
V
A
A
B
A
3.95
VOH
VOL
TA = –40°C to +125°C
TA = 25°C, VS+ = 3.3 V
3.9
1.05
1.15
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and
simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
Copyright © 2018, Texas Instruments Incorporated
5
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
Electrical Characteristics (continued)
VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced
to midsupply, and TA = 25℃ (unless otherwise noted)
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
TA = 25°C
1.05
1.2
80
1.15
A
VOL
Output voltage (low)
V
TA = –40°C to +125°C
B
A
B
RL = 10 Ω, AOL > 60 dB
65
85
Linear output drive (sink and
source)
mA
mA
TA = –40°C to +125°C, RL = 10 Ω,
AOL > 60 dB
64
ISC
Output short-circuit current
105
A
POWER SUPPLY
VS
IQ
IQ
IQ
IQ
IQ
Operating voltage
3.3
18
5.25
24
V
A
A
A
A
B
B
Quiescent current
Quiescent current
Quiescent current
Quiescent current
Quiescent current
VS+ = 5 V
20.5
20
mA
mA
mA
mA
mA
VS+ = 3.3 V
VS+ = 5.25 V
TA = 125°C
TA = –40°C
17.5
18
23.5
24
21
24.5
18.5
Positive power-supply rejection
ratio
PSRR+
PSRR–
74
70
84
80
dB
A
Negative power-supply rejection
ratio
POWER DOWN
Disable voltage threshold
Amplifier OFF below this voltage
Amplifier ON above this voltage
0.65
1
1.5
70
V
V
A
A
A
A
C
C
Enable voltage threshold
Power-down quiescent current
PD bias current
1.8
140
200
µA
µA
ns
ns
70
Turnon time delay
Time to VOUT = 90% of final value
13
Turnoff time delay
120
6
版权 © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
7.6 Typical Characteristics
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
3
0
4
2
0
-2
-3
-4
-6
-6
-8
Gain = +7 V/V
Gain = +10 V/V
Gain = +20 V/V
Gain = -7 V/V
-9
-10
-12
VS = 5 V
VS = 3.3 V
-12
1M
10M
100M
1G
5G
1M
10M
100M
Frequency (Hz)
1G
5G
Frequency (Hz)
D100
D102
VOUT = 100 mVPP; see 图 43 and 图 44 for circuit configuration
VOUT = 100 mVPP
图 1. Small-Signal Frequency Response vs Gain
图 2. Small-Signal Frequency Response vs Supply Voltage
3
2
1
0
0
-3
-6
-1
-2
-3
-4
-5
-6
-7
-8
TA = -40èC
TA = 0èC
TA = 25èC
TA = 85èC
TA = 125èC
-9
RL = 200 W
RL = 400 W
RL = 100 W
-12
1M
10M
100M
Frequency (Hz)
1G
5G
1M
10M
100M
Frequency (Hz)
1G
D103
D104
VOUT = 100 mVPP
VOUT = 100 mVPP
图 3. Small-Signal Frequency Response vs Output Load
图 4. Small-Signal Frequency Response vs Ambient
Temperature
4
2
4
2
0
0
-2
-4
-6
-2
-4
-6
-8
-8
RS = 24 W, C L = 10 pF
Gain = 7 V/V
Gain = 10 V/V
Gain = 20 V/V
Gain = -7 V/V
RS = 10 W, C L = 47 pF
RS = 5.6 W, C L = 100 pF
RS = 1.8 W, C L = 1 nF
-10
-12
-10
-12
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
D105
D106
VOUT = 100 mVPP; see 图 45 for circuit configuration
VOUT = 2 VPP
图 6. Large-Signal Frequency Response vs Gain
图 5. Small-Signal Frequency Response vs Capacitive Load
版权 © 2018, Texas Instruments Incorporated
7
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
Typical Characteristics (接下页)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
0.4
0.3
0.2
0.1
0
4
2
0
-2
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-4
-6
-8
-10
-12
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
5G
D107
D108
VOUT = 2 VPP
VS = 3.3 V
VOUT = 1 VPP
图 7. Large-Signal Response for 0.1-dB Gain Flatness
100
图 8. Large-Signal Frequency Response
90
75
60
45
30
15
0
45
Gain = 7 V/V
Gain = 20 V/V
AOL magnitude (dB)
AOL phase (è)
0
-45
10
1
-90
-135
-180
-225
-270
0.1
-15
1M
10M
100M
10k
100k
1M
10M
100M
1G
10G
Frequency (Hz)
Frequency (Hz)
D109
D500
Small-Signal Response
图 9. Closed-Loop Output Impedance vs Frequency
Small-Signal Response
图 10. Open-Loop Magnitude and Phase vs Frequency
100
10
1
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1k
10k
100k
1M
10M
100M
-40
-20
0
20
40
60
80
100 120 140
Frequency (Hz)
Ambient Temperature (èC)
D111
D112
Frequency = 10 MHz
图 11. Voltage Noise Density vs Frequency
图 12. Voltage Noise Density vs Ambient Temperature
版权 © 2018, Texas Instruments Incorporated
8
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
Typical Characteristics (接下页)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
-40
-40
-50
HD2, VOUT = 0.5 VPP
HD2, VOUT = 1 VPP
HD2, VOUT = 2 VPP
HD2, VOUT = 2.5 VPP
HD3, VOUT = 0.5 VPP
HD3, VOUT = 1 VPP
HD3, VOUT = 2 VPP
HD3, VOUT = 2.5 VPP
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D113
D114
图 13. Harmonic Distortion (HD2) vs Output Swing
图 14. Harmonic Distortion (HD3) vs Output Swing
-40
-50
-40
-50
HD2, RL = 100 W
HD2, RL = 200 W
HD2, RL = 400 W
HD3, RL = 100 W
HD3, RL = 200 W
HD3, RL = 400 W
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D115
D116
VOUT = 2 VPP
VOUT = 2 VPP
图 15. Harmonic Distortion (HD2) vs Output Load
图 16. Harmonic Distortion (HD3) vs Output Load
-40
-50
-40
-50
HD2, G = -7 V/V
HD2, G = 7 V/V
HD2, G = 20 V/V
HD3, G = -7 V/V
HD3, G = 7 V/V
HD3, G = 20 V/V
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D117
D118
VOUT = 2 VPP
VOUT = 2 VPP
图 17. Harmonic Distortion (HD2) vs Gain
图 18. Harmonic Distortion (HD3) vs Gain
版权 © 2018, Texas Instruments Incorporated
9
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
Typical Characteristics (接下页)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
80
1.25
1
Input
Output
Input
Output
60
0.75
0.5
40
20
0.25
0
0
-0.25
-0.5
-0.75
-1
-20
-40
-60
-80
-1.25
Time (5 ns/div)
Time (5 ns/div)
D119
D120
Average Rise and Fall Time (10% - 90%) = 450 ps
Average Rise and Fall Time (10% - 90%) = 750 ps
图 19. Small-Signal Transient Response
图 20. Large-Signal Transient Response
3
2
80
60
Measured Output
Ideal Output
40
1
20
0
0
-20
-40
-60
-80
-1
-2
RS = 24 W, CL = 10 pF
RS = 10 W, CL = 47 pF
RS = 5.6 W, CL = 100 pF
RS = 1.8 W, CL = 1 nF
-3
0
10
20
30
40
50
60
70
80
90 100
Time (5 ns/div)
Time (ns)
D121
D122
2x Output Overdrive
图 22. Output Overload Response
图 21. Small-Signal Transient Response vs Capacitive Load
5
4.5
4
5
4.5
4
Power Down (PD)
Output
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
Power Down (PD)
0.5
0.5
0
Output
0
Time (5 ns/div)
Time (5 ns/div)
D123
D124
VS+ = 5 V, VS– = Ground
VS+ = 5 V, VS– = Ground
图 23. Turnon Transient Response
图 24. Turnoff Transient Response
10
版权 © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
Typical Characteristics (接下页)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
100
80
60
40
20
0
100
80
60
40
20
0
PSRR-
PSRR+
-20
-40
-20
10k
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
D125
D126
Small-Signal Response
Small-Signal Response
图 25. Common-Mode Rejection Ratio vs Frequency
图 26. Power Supply Rejection Ratio vs Frequency
23
22.5
22
26
25
24
23
22
21
20
19
18
21.5
21
20.5
20
Unit 1 (VS = 3.3 V)
Unit 1 (VS = 5 V)
Unit 2 (VS = 3.3 V)
Unit 2 (VS = 5 V)
19.5
19
Unit1
Unit2
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25
-40
-20
0
20
40
60
80
100
120
Total Supply Voltage (V)
Ambient Temperature (èC)
D160
D161
2 Typical Units
2 Typical Units
图 27. Quiescent Current vs Supply Voltage
图 28. Quiescent Current vs Ambient Temperature
85
80
75
70
65
1.5
1.2
0.9
0.6
0.3
0
Unit 1
Unit 2
Unit 3
-0.3
-0.6
-0.9
-1.2
-1.5
-40
-20
0
20
40
60
80
100 120 140
3
3.25 3.5
3.75
4
4.25 4.5
4.75
5
5.25
Ambient Temperature (èC)
D162
Total Supply Voltage (V)
D163
30 Units Tested
3 Typical Units
图 29. Quiescent Current (Amplifier Disabled) vs Ambient
图 30. Offset Voltage vs Supply Voltage
Temperature
版权 © 2018, Texas Instruments Incorporated
11
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
Typical Characteristics (接下页)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
4
3.5
3
0.8
0.6
0.4
0.2
0
Unit 1
Unit 2
Unit 3
2.5
2
1.5
1
-0.2
-0.4
-0.6
-0.8
0.5
0
-0.5
-1
-1.5
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
-40
-20
0
20
40
60
80
100 120 140
Common-Mode Voltage (V)
Ambient Temperature (èC)
D165
D164
VS = 3.3 V
3 Typical Units
µ = 1 µV/°C
σ = 2.2 µV/°C
28 Units Tested
图 32. Offset Voltage vs Input Common-Mode Voltage
图 31. Offset Voltage vs Ambient Temperature
3
2.5
2
2
Unit 1
Unit 2
Unit 3
1.6
1.2
0.8
0.4
0
1.5
1
0.5
0
-0.4
-0.8
-1.2
-1.6
-2
-0.5
-1
TA = -40èC
TA = 25èC
TA = 125èC
-1.5
-2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
0.4 0.8 1.2 1.6
2
2.4 2.8 3.2 3.6
4
Common-Mode Voltage (V)
Common-Mode Voltage (V)
D166
D167
VS = 5 V
3 Typical Units
图 33. Offset Voltage vs Input Common-Mode Voltage
图 34. Offset Voltage vs Input Common-Mode Voltage vs
Ambient Temperature
4
3
2.5
Unit 1
Unit 2
Unit 3
2
1.5
1
2
1
0.5
0
0
-0.5
-1
-1
-2
-3
-4
-1.5
-2
Unit 1
Unit 2
Unit 3
-2.5
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
Output Voltage (V)
Output Voltage (V)
D168
D169
VS = 3.3 V
3 Typical Units
VS = 5 V
3 Typical Units
图 35. Offset Voltage vs Output Swing
图 36. Offset Voltage vs Output Swing
12
版权 © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
Typical Characteristics (接下页)
VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA =
25°C (unless otherwise noted)
1.5
1000
100
10
1
0.5
0
1
-0.5
-1
0.1
TA = -40èC
TA = 25èC
TA = 125èC
Unit 1
Unit 2
Unit 3
-1.5
0.01
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
-40
-20
0
20
40
60
80
100
120 140
Output Voltage (V)
Ambient Temperature (èC)
D170
D171
3 Typical Units
图 37. Offset Voltage vs Output Swing vs Ambient
图 38. Input Bias Current vs Ambient Temperature
Temperature
4000
5
0
3500
3000
2500
2000
1500
1000
500
-5
-10
-15
-20
-25
-30
0
0
0.5
1
1.5
2
2.5
3
3.5
4
Common-Mode Voltage (V)
D140
D172
Quiescent Current (mA)
µ = 20.35 mA
σ = 0.2 mA
4555 units tested
图 39. Input Bias Current vs Input Common-Mode Voltage
图 40. Quiescent Current Distribution
1750
1500
1250
1000
750
500
250
0
1200
1000
800
600
400
200
0
D142
D141
Offset Voltage (mV)
Input Bias Current (pA)
µ = –0.28 mV
σ = 0.8 mV
4555 units tested
µ = –0.1 pA
σ = 0.39 pA
4555 units tested
图 41. Offset Voltage Distribution
图 42. Input Bias Current Distribution
版权 © 2018, Texas Instruments Incorporated
13
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
8 Parameter Measurement Information
8.1 Parameter Measurement Information
The various test setup configurations for the OPA858 are shown below
GND
50 ꢀ
2.5 V
50 ꢀ
50-ꢀ
Source
169 ꢀ
+
50-ꢀ
Measurement
System
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
RG
453 ꢀ
GND
GND
GND
RG values depend on gain configuration
图 43. Noninverting Configuration
2.5 V
169 ꢀ
+
50-ꢀ
Measurement
System
GND
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
50 ꢀ
50-ꢀ
Source
GND
64 ꢀ
453 ꢀ
GND
220 ꢀ
GND
图 44. Inverting Configuration (Gain = –7 V/V)
GND
50 ꢀ
2.5 V
50 ꢀ
50-ꢀ
Source
RS
1 kꢀ
+
50-ꢀ
Measurement
System
œ
50 ꢀ
CL
53.6 ꢀ
Þ2.5 V
75 ꢀ
453 ꢀ
GND
GND
GND
GND
图 45. Capacitive Load Driver Configuration
14
版权 © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
9 Detailed Description
9.1 Overview
The ultra-wide, 5.5-GHz gain bandwidth product (GBWP) of the OPA858, combined with the broadband voltage
noise of 2.5 nV/√Hz, produces a viable amplifier for wideband transimpedance applications, high-speed data
acquisition systems, and applications with weak signal inputs that require low-noise and high-gain front ends.
The OPA858 combines multiple features to optimize dynamic performance. In addition to the wide, small-signal
bandwidth, the OPA858 has 600 MHz of large signal bandwidth (VOUT = 2 VPP) and a slew rate of 2000 V/µs.
The OPA858 is offered in a 2-mm × 2-mm, 8-pin WSON package that features a feedback (FB) pin for a simple
feedback network connection between the amplifiers output and inverting input. Excess capacitance on an
amplifiers input pin can reduce phase margin causing instability. This problem is exacerbated in the case of very
wideband amplifiers like the OPA858. To reduce the effects of stray capacitance on the input node, the OPA858
pinout features an isolation pin (NC) between the feedback and inverting input pins that increases the physical
spacing between them thereby reducing parasitic coupling at high frequencies. The OPA858 also features a very
low capacitance input stage with only 0.8-pF of total input capacitance.
9.2 Functional Block Diagram
The OPA858 is a classic, voltage feedback operational amplifier (op amp) with two high-impedance inputs and a
low-impedance output. Standard application circuits are supported, like the two basic options shown in 图 46 and
图 47. The DC operating point for each configuration is level-shifted by the reference voltage (VREF), which is
typically set to midsupply in single-supply operation. VREF is typically connected to ground in split-supply
applications.
VSIG
VS+
(1 + RF / RG) × VSIG
VREF
VIN
+
VOUT
VREF
œ
RG
VSœ
RF
VREF
图 46. Noninverting Amplifier
VS+
œ(RF / RG) × VSIG
VREF
+
VSIG
VOUT
VREF
VREF
VIN
œ
RG
VSœ
RF
图 47. Inverting Amplifier
版权 © 2018, Texas Instruments Incorporated
15
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
9.3 Feature Description
9.3.1 Input and ESD Protection
The OPA858 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown
voltages are low for these small geometry devices, and as a result, all device pins are protected with internal
ESD protection diodes to the power supplies as 图 48 shows. There are two antiparallel diodes between the
inputs of the amplifier that clamp the inputs during an overrange or fault condition.
VS+
Power Supply
ESD Cell
VIN+
+
VOUT
œ
VINÞ
FB
VSÞ
图 48. Internal ESD Structure
9.3.2 Feedback Pin
The OPA858 pin layout is optimized to minimize parasitic inductance and capacitance, which is critical in high-
speed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The FB pin is
separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin must be
left floating. There are two advantages to this pin layout:
1. A feedback resistor (RF) can connect between the FB and IN– pin on the same side of the package (see 图
49) rather than going around the package.
2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN– pins by
increasing the physical separation between the pins.
FB
NC
INœ
IN+
PD
1
2
3
4
8
7
6
5
VS+
OUT
VSœ
RF
œ
+
图 49. RF Connection Between FB and IN– Pins
16
版权 © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
Feature Description (接下页)
9.3.3 Wide Gain-Bandwidth Product
图 10 shows the open-loop magnitude and phase response of the OPA858. Calculate the gain bandwidth product
of any op amp by determining the frequency at which the AOL is 60 dB and multiplying that frequency by a factor
of 1000. The second pole in the AOL response occurs before the magnitude crosses 0 dB, and the resultant
phase margin is less than 0°. This indicates instability at a gain of 0 dB (1 V/V). Amplifiers that are not unity-gain
stable are known as decompensated amplifiers. Decompensated amplifiers typically have higher gain-bandwidth
product, higher slew rate, and lower voltage noise, compared to a unity-gain stable amplifier with the same
amount of quiescent power consumption.
图 50 shows the open-loop magnitude (AOL) of the OPA858 as a function of temperature. The results show
minimal variation over temperature. The phase margin of the OPA858 configured in a noise gain of 7 V/V (16.9
dB) is close to 55° across temperature. Similarly 图 51 shows the AOL magnitude of the OPA858 as a function of
process variation. The results show the AOL curve for the nominal process corner and the variation one standard
deviation from the nominal. The simulated results suggest less than 1° of phase margin difference within a
standard deviation of process variation when the amplifier is configured in a gain of 7 V/V.
One of the primary applications for the OPA858 is as a high-speed transimpedance amplifier (TIA), as 图 59
shows. The low-frequency noise gain of a TIA is 0 dB (1 V/V). At high frequencies the ratio of the total input
capacitance and the feedback capacitance set the noise gain. To maximize the TIA closed-loop bandwidth, the
feedback capacitance is typically smaller than the input capacitance, which implies that the high-frequency noise
gain is greater than 0 dB. As a result, op amps configured as TIAs are not required to be unity-gain stable, which
makes a decompensated amplifier a viable option for a TIA. What You Need To Know About Transimpedance
Amplifiers – Part 1 and What You Need To Know About Transimpedance Amplifiers – Part 2 describe
transimpedance amplifier compensation in greater detail.
90
75
60
45
30
15
0
90
75
60
45
30
15
0
AOL at -40èC
AOL at 25èC
AOL at +125èC
AOL (-1 s)
AOL (Typ.)
AOL (+1 s)
-15
-15
100k
1M
10M
100M
1G
10G
100k
1M
10M
100M
1G
10G
Frequency (Hz)
Frequency (Hz)
D204
D205
图 50. Open-Loop Gain vs Temperature
图 51. Open-Loop Gain vs Process Variation
9.3.4 Slew Rate and Output Stage
In addition to wide bandwidth, the OPA858 features a high slew rate of 2000 V/µs . The slew rate is a critical
parameter in high-speed pulse applications with narrow sub 10-ns pulses such as Optical Time-Domain
Reflectometry (OTDR) and LIDAR. The high slew rate of the OPA858 implies that the device accurately
reproduces a 2-V, sub-ns pulse edge as seen in 图 20. The wide bandwidth and slew rate of the OPA858 make it
an ideal amplifier for high-speed, signal-chain front ends.
图 52 shows the open-loop output impedance of the OPA858 as a function of frequency. To achieve high slew
rates and low output impedance across frequency, the output swing of the OPA858 is limited to approximately 3
V. The OPA858 is typically used in conjunction with high-speed pipeline ADCs and flash ADCs that have limited
input ranges. Therefore, the OPA858 output swing range coupled with the class-leading voltage noise
specification maximizes the overall dynamic range of the signal chain.
版权 © 2018, Texas Instruments Incorporated
17
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
Feature Description (接下页)
20
18
16
14
12
10
8
6
4
2
0
10k
100k
1M
10M
100M
1G
10G
Frequency (Hz)
D601
图 52. Open-Loop Output Impedance (ZOL) vs Frequency
9.3.5 Current Noise
The input impedance of CMOS and JFET input amplifiers at low frequencies exceed several GΩs. However, at
higher frequencies, the transistors parasitic capacitance to the drain, source, and substrate reduces the
impedance. The high impedance at low frequencies eliminates any bias current and the associated shot noise. At
higher frequencies, the input current noise increases (see 图 53) as a result of capacitive coupling between the
CMOS gate oxide and the underlying transistor channel. This phenomenon is a natural artifact of the construction
of the transistor and is unavoidable.
100p
10p
1p
100f
10f
1f
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
D607
图 53. Input Current Noise (IBN and IBI) vs Frequency
18
版权 © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
9.4 Device Functional Modes
9.4.1 Split-Supply and Single-Supply Operation
The OPA858 can be configured with single-sided supplies or split-supplies as shown in 图 63. Split-supply
operation using balanced supplies with the input common-mode set to ground eases lab testing because most
signal generators, network analyzers, spectrum analyzers, and other lab equipment typically reference inputs and
outputs to ground. Split-supply operation is preferred in systems where the signals swing around ground.
However, the system requires two supply rails. In split-supply operation, the thermal pad must be connected to
the negative supply.
Newer systems use a single power supply to improve efficiency and reduce the cost of the extra power supply.
The OPA858 can be used with a single positive supply (negative supply at ground) with no change in
performance if the input common-mode and output swing are biased within the linear operation of the device. To
change the circuit from a split-supply to a single-supply configuration, level shift all the voltages by half the
difference between the power supply rails. In this case, the thermal pad must be connected to ground.
9.4.2 Power-Down Mode
The OPA858 features a power-down mode to reduce the quiescent current to conserve power. 图 23 and 图 24
show the transient response of the OPA858 as the PD pin toggles between the disabled and enabled states.
The PD disable and enable threshold voltages are with reference to the negative supply. If the amplifier is
configured with the positive supply at 3.3 V and the negative supply at ground, then the disable and enable
threshold voltages are 0.65 V and 1.8 V, respectively. If the amplifier is configured with ±1.65-V supplies, then
the disable and enable threshold voltages are at –1 V and 0.15 V, respectively. If the amplifier is configured with
±2.5-V supplies, then the threshold voltages are at –1.85 V and –0.7 V.
图 54 shows the switching behavior of a typical amplifier as the PD pin is swept down from the enabled state to
the disabled state. Similarly 图 55 shows the switching behavior of a typical amplifier as the PD pin is swept up
from the disabled state to the enabled state. The small difference in the switching thresholds between the down
sweep and the up sweep is due to the hysteresis designed into the amplifier to increase its immunity to noise on
the PD pin.
25
20
15
10
5
25
20
15
10
5
TA = -40èC
TA = 25èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 125èC
0
0
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Power Down Voltage (V)
Power Down Voltage (V)
D200
D201
图 54. Switching Threshold (PD Pin Swept from HIGH to
图 55. Switching Threshold (PD Pin Swept from LOW to
LOW)
HIGH)
Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When the
amplifier is configured as a noninverting amplifier, the feedback (RF) and gain (RG) resistor network form a
parallel load to the output of the amplifier. To protect the input stage of the amplifier, the OPA858 uses internal,
back-to-back protection diodes between the inverting and noninverting input pins as 图 48 shows. When the
differential voltage between the input pins of the amplifier exceeds a diode voltage drop, an additional low-
impedance path is created between the inputs.
版权 © 2018, Texas Instruments Incorporated
19
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Using the OPA858 as a Transimpedance Amplifier
The OPA858 design has been optimized to meet the industry's growing demand for wideband, low-noise
photodiode amplifiers. The closed-loop bandwidth of a transimpedance amplifier is a function of the following:
1. The total input capacitance. This includes the photodiode capacitance, input capacitance of the amplifier
(common-mode and differential capacitance) and any stray capacitance from the PCB.
2. The op amp gain bandwidth product (GBWP), and,
3. The transimpedance gain RF.
5 V
OPA858
+
œ
100 V
+
3.4 V
GND
œ
GND
RF
CF
图 56. Transimpedance Amplifier Circuit
图 56 shows the OPA858 configured as a TIA with the avalanche photodiode (APD) reverse biased such that its
cathode is tied to a large positive bias voltage. In this configuration the APD sources current into the op amp
feedback loop so that the output swings in a negative direction relative to the input common-mode voltage. To
maximize the output swing in the negative direction, the OPA858 common-mode is set close to the positive limit,
1.6 V from the positive supply rail.
The feedback resistance RF and the input capacitance form a zero in the noise gain that results in instability if left
unchecked. To counteract the effect of the zero, a pole is inserted by adding the feedback capacitor (CF.) into the
noise gain transfer function. The Transimpedance Considerations for High-Speed Amplifiers application report
discusses theories and equations that show how to compensate a transimpedance amplifier for a particular gain
and input capacitance. The bandwidth and compensation equations from the application report are available in a
Microsoft Excel ™ calculator. What You Need To Know About Transimpedance Amplifiers – Part 1 provides a
link to the calculator.
20
版权 © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
Application Information (接下页)
450
110
100
90
350
300
250
200
150
100
50
120
f-3dB, CF = 1 pF
f-3dB, RF = 10 kW
400
350
300
250
200
150
100
50
f-3dB, RF = 20 kW
IRN, RF = 10 kW
IRN, RF = 20 kW
f-3dB, CF = 2 pF
IRN, CF = 1 pF
100
IRN, CF = 2 pF
80
80
70
60
40
20
60
50
40
30
0
20
0
0
2
4
6
8
10
12
14
16
18
20
10
100
Photodiode capacitance (pF)
Feedback Resistance (kW)
D209
D210
图 57. Bandwidth and Noise Performance vs Photodiode
图 58. Bandwidth and Noise Performance vs Feedback
Capacitance
Resistance
The equations and calculators in the application report and blog posts referenced above are used to model the
bandwidth (f-3dB) and noise (IRN) performance of the OPA858 configured as a TIA. The resultant performance is
shown in 图 57 and 图 58. The left side Y-axis shows the closed-loop bandwidth performance, while the right
side of the graph shows the integrated input referred noise. The noise bandwidth to calculate IRN, for a fixed RF
and CPD is set equal to the f–3dB frequency.
图 57 shows the amplifier performance as a function of photodiode capacitance (CPD) for RF = 10 kΩ and 20 kΩ.
Increasing CPD decreases the closed-loop bandwidth. It is vital to reduce any stray parasitic capacitance from the
PCB to maximize bandwidth. The OPA858 is designed with 0.8 pF of total input capacitance to minimize the
effect on system performance.
图 58 shows the amplifier performance as a function of RF for CPD = 1 pF and 2 pF. Increasing RF results in
lower bandwidth. To maximize the signal-to-noise ratio (SNR) in an optical front-end system, maximize the gain
in the TIA stage. Increasing RF by a factor of "X" increases the signal level by "X", but only increases the resistor
noise contribution by "√X", thereby improving SNR.
版权 © 2018, Texas Instruments Incorporated
21
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
10.2 Typical Application
The high GBWP, low input voltage noise and high slew rate of the OPA858 makes the device a viable wideband,
high input impedance voltage amplifier.
2.5 V
169 ꢀ
+
50-ꢀ
Measurement
System
GND
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
50 ꢀ
50-ꢀ
Source
226 ꢀ
453 ꢀ
GND
GND
62 ꢀ
Supply decoupling not shown
GND
GND
图 59. OPA858 in a Gain of –2V/V (No Noise Gain Shaping)
2.5 V
169 ꢀ
+
50-ꢀ
Measurement
System
GND
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
50 ꢀ
50-ꢀ
Source
226 ꢀ
453 ꢀ
GND
GND
2.7 pF
GND
62 ꢀ
Supply decoupling not shown
0.5 pF
GND
GND
图 60. OPA858 in a Gain of –2V/V (With Noise Gain Shaping)
10.2.1 Design Requirements
Design a high-bandwidth, high-gain, voltage amplifier with the design requirements listed in 表 1. An inverting
amplifier configuration is chosen here; however, the theory is applicable to a noninverting configuration as well.
In an inverting configuration the signal gain and noise gain transfer functions are not equal, unlike the
noninverting configuration.
表 1. Design Requirements
TARGET BANDWIDTH
(MHz)
FEEDBACK RESISTANCE
FREQUENCY
PEAKING (dB)
SIGNAL GAIN (V/V)
(Ω)
> 750
–2
453
< 2
10.2.2 Detailed Design Procedure
The OPA858 is compensated to have less than 1 dB of peaking in a gain of 7 V/V. Using the device in lower
gains results in increased peaking and potential instability. 图 59 shows the OPA858 configured in a signal gain
of –2 V/V. The DC noise gain (1/β) of the amplifier is affected by the 62-Ω termination resistor and the 50-Ω
source resistor and is given by 公式 1. At higher frequencies the noise gain is affected by reactive elements such
as inductors and capacitors. These include both discrete board components as well as printed circuit board
(PCB) parasitics.
≈
∆
«
’
1
453 W
Noise Gain =
= 1+
= 2.79 V/V = 5.04 dB
∆
÷
÷
b
226 W + 62 W || 50 W
◊
(1)
22
版权 © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
The stability and phase margin of the amplifier depend on the loop gain of the amplifier, which is the product of
the AOL and the feedback factor (β) of the amplifier. The β of a negative-feedback loop system is the portion of
the output signal that is fed back to the input, and in the case of an amplifier is the inverse of the noise gain. The
noise gain of the amplifier at high frequencies can be increased by adding an input capacitor and a feedback
capacitor as 图 60 shows. If done carefully, increasing 1/β improves the phase margin just as any amplifier is
more stable in a high gain configuration versus a unity-gain buffer configuration. The modified network with the
added capacitors alters the high-frequency noise gain, but does not alter the signal gain. The AN-1604
Decompensated Operational Amplifiers application report provides a detailed analysis of noise gain-shaping
techniques for decompensated amplifiers and shows how to choose external resistors and capacitor values.
图 61 shows the uncompensated frequency response of the OPA858 configured as shown in 图 59. Without any
added noise gain shaping components, the OPA858 shows approximately 13 dB of peaking.
图 62 shows the noise gain compensated frequency response of the OPA858 configured as shown in 图 60. The
noise gain shaping elements reduce the peaking to less than 1.5 dB. The 2.7-pF input capacitor, the input
capacitance of the amplifier, the gain resistor, and the feedback resistor create a zero in the noise gain at a
frequency f, as 公式 2 shows.
1
f =
2p R || R
C
IN
F
G
where
•
•
•
RF is the feedback resistor
RG is the input or gain resistor (includes the effect of the source and termination resistor)
CIN is the total input capacitance, which includes the external 2.7-pF capacitor, the amplifier input capacitance,
and any parasitic PCB capacitance.
(2)
The zero in 公式 2 increases the noise gain at higher frequencies, which is important when compensating a
decompensated amplifier. However, the noise gain zero reduces the loop gain phase which results in a lower
phase margin. To counteract the phase reduction due to the noise gain zero, add a pole to the noise gain curve
by inserting the 0.5-pF feedback capacitor. The pole occurs at a frequency shown in 公式 3. The noise gain pole
and zero locations must be selected so that the rate-of-closure between the magnitude curves of AOL and 1/β is
approximately 20 dB. To ensure this, the noise gain pole must occur before the 1/β magnitude curve intersects
the AOL magnitude curve. In other words, the noise gain pole must occur before |AOL| = |1/β|. The point at which
the two curves intersect is known as the loop gain crossover frequency.
1
f =
2pRFCF
where
•
CF is the feedback capacitor (includes any added PCB parasitic)
(3)
For more information on op amp stability, watch the TI Precision Lab series on stability video.
10.2.3 Application Curves
16
12
8
4
0
-4
-8
4
-12
-16
-20
-24
-28
-32
0
-4
-8
-12
-16
Simulated Response
Measured Response
Simulated Response
Measured Response
1M
10M
100M
1G
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
D206
D207
VOUT = 100 mVPP
VOUT = 100 mVPP
图 61. Gain = –2 V/V, Uncompensated Frequency
图 62. Gain = –2 V/V, Compensated Frequency Response
Response
版权 © 2018, Texas Instruments Incorporated
23
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
11 Power Supply Recommendations
The OPA858 operates on supplies from 3.3 V to 5.25 V. The OPA858 operates on single-sided supplies, split
and balanced bipolar supplies, and unbalanced bipolar supplies. Because the OPA858 does not feature rail-to-
rail inputs or outputs, the input common-mode and output swing ranges are limited at 3.3-V supplies.
a) Single supply configuration
VS+
VS+
+
2
0.1 …F
6.8 …F
RG
75 ꢀ
RF
453 ꢀ
œ
50-Ω Source
+
VI
200 ꢀ
RT
49.9 ꢀ
VS+
2
VS+
2
b) Split supply configuration
VS+
+
0.1 …F
6.8 …F
RG
RF
75 ꢀ
453 ꢀ
œ
50-Ω Source
+
VI
200 ꢀ
+
RT
49.9 ꢀ
0.1 …F
6.8 …F
VSœ
图 63. Split and Single Supply Circuit Configuration
24
版权 © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
12 Layout
12.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA858 requires careful attention to
board layout parasitics and external component types. Recommendations that optimize performance include:
1. Minimize parasitic capacitance from the signal I/O pins to AC ground. Parasitic capacitance on the output
and inverting input pins can cause instability. To reduce unwanted capacitance, TI recommends cutting out
the power and ground traces underneath the signal input and output pins. Otherwise, ground and power
planes must be unbroken elsewhere on the board. When configuring the amplifier as a TIA, if the required
feedback capacitor is under 0.15 pF, consider using two series resistors, each of half the value of a single
resistor in the feedback loop to minimize the parasitic capacitance from the resistor.
2. Minimize the distance (less than 0.25") from the power-supply pins to high-frequency bypass capacitors. Use
high quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three
times greater than the amplifiers maximum power supplies to ensure that there is a low-impedance path to
the amplifiers power-supply pins across the amplifiers gain bandwidth specification. At the device pins, do
not allow the ground and power plane layout to be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between the pins and the decoupling capacitors. The
power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF)
decoupling capacitors, effective at lower frequency, must be used on the supply pins. These are placed
further from the device and are shared among several devices in the same area of the PC board.
3. Careful selection and placement of external components preserves the high-frequency performance
of the OPA858 . Use low-reactance resistors. Surface-mount resistors work best and allow a tighter overall
layout. Never use wirewound resistors in a high-frequency application. Because the output pin and inverting
input pin are the most sensitive to parasitic capacitance, always position the feedback and series output
resistor, if any, as close to the output pin as possible. Place other network components (such as noninverting
input termination resistors) close to the package. Even with a low parasitic capacitance shunting the external
resistors, high resistor values create significant time constants that can degrade performance. When
configuring the OPA858 as a voltage amplifier, keep resistor values as low as possible and consistent with
load driving considerations. Decreasing the resistor values keeps the resistor noise terms low and minimizes
the effect of the parasitic capacitance. However, lower resistor values increase the dynamic power
consumption because RF and RG become part of the output load network of the amplifier.
12.2 Layout Example
Representative schematic
Connect PD to VS+ to enable the
amplifier
VS+
1
2
8
7
CBYP
RS
+
NC (Pin 2) isolates the IN- and FB
pins thereby reducing capacitive
coupling
œ
Thermal
Pad
CBYP
RF
CBYP
Place gain and feedback resistors
close to pins to minimize stray
capacitance
VS-
RF
3
4
6
5
RS
RG
RG
CBYP
Connect the thermal pad to the
negative supply pin
Ground and power plane exist on
inner layers.
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
Place bypass capacitor
close to power pins
图 64. Layout Recommendation
版权 © 2018, Texas Instruments Incorporated
25
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
Layout Example (接下页)
When configuring the OPA858 as a transimpedance amplifier additional care must be taken to minimize the
inductance between the avalanche photodiode (APD) and the amplifier. Always place the photodiode on the
same side of the PCB as the amplifier. Placing the amplifier and the APD on opposite sides of the PCB
increases the parasitic effects due to via inductance. APD packaging can be quite large which often requires the
APD to be placed further away from the amplifier than ideal. The added distance between the two device results
in increased inductance between the APD and op amp feedback network as shown in 图 65. The added
inductance is detrimental to a decompensated amplifiers stability since it isolates the APD capacitance from the
noise gain transfer function. The noise gain is given by 公式 4. The added PCB trace inductance between the
feedback network increases the denominator in 公式 4 thereby reducing the noise gain and the phase margin. In
cases where a leaded APD in a TO can is used inductance should be further minimized by cutting the leads of
the TO can as short as possible.
The layout shown in 图 65 can be improved by following some of the guidelines shown in 图 66. The two key
rules to follow are:
•
Add an isolation resistor RISO as close as possible to the inverting input of the amplifier. Select the value of
RISO to be between 10 Ω and 20 Ω. The resistor dampens the potential resonance caused by the trace
inductance and the amplifiers internal capacitance.
•
Close the loop between the feedback elements (RF and CF) and RISO as close to the APD pins as possible.
This ensures a more balanced layout and reduces the inductive isolation between the APD and the feedback
network.
≈
’
÷
ZF
Noise Gain = 1+
∆
ZIN ◊
«
where
•
•
ZF is the total impedance of the feedback network.
ZIN is the total impedance of the input network.
(4)
Vbias
Vbias
CF
RF
APD
Package
APD
Package
FB
NC
INœ
IN+
FB
NC
INœ
IN+
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
PD
PD
RF
VS+
VS+
CF
Close the loop close
to APD pins
Thermal
Pad
Thermal
Pad
OUT
OUT
Trace inductance isolates
APD capacitance from the
amplifier noise gain
RISO
VSœ
VSœ
Place RISO close to INœ
图 65. Non-Ideal TIA Layout
图 66. Improved TIA Layout
26
版权 © 2018, Texas Instruments Incorporated
OPA858
www.ti.com.cn
ZHCSI18A –APRIL 2018–REVISED JULY 2018
13 器件和文档支持
13.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.3 商标
E2E is a trademark of Texas Instruments.
is a trademark of ~Microsoft Corporation.
13.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
版权 © 2018, Texas Instruments Incorporated
27
OPA858
ZHCSI18A –APRIL 2018–REVISED JULY 2018
www.ti.com.cn
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
28
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA858IDSGR
OPA858IDSGT
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
X858
X858
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
OTHER QUALIFIED VERSIONS OF OPA858 :
Automotive : OPA858-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Jul-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA858IDSGR
OPA858IDSGT
WSON
WSON
DSG
DSG
8
8
3000
250
180.0
180.0
8.4
8.4
2.3
2.3
2.3
2.3
1.15
1.15
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Jul-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA858IDSGR
OPA858IDSGT
WSON
WSON
DSG
DSG
8
8
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
OPA858-Q1_V01
OPA858-Q1 5.5-GHz Gain Bandwidth Product, Gain of 7-V/V Stable, FET Input Amplifier
TI
OPA858QDSGRQ1
OPA858-Q1 5.5-GHz Gain Bandwidth Product, Gain of 7-V/V Stable, FET Input Amplifier
TI
©2020 ICPDF网 联系我们和版权申明