OPA820-HT [TI]
UNITY-GAIN STABLE, LOW-NOISE, VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER; 单位增益稳定，低噪声，电压反馈运算放大器
| 型号： | OPA820-HT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | UNITY-GAIN STABLE, LOW-NOISE, VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER |
| 文件： | 总30页 (文件大小：516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA820-HT
www.ti.com
SBOS587 –DECEMBER 2011
UNITY-GAIN STABLE, LOW-NOISE, VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER
Check for Samples: OPA820-HT
1
FEATURES
•
High Bandwidth
(240 MHz at 25°C and 100 MHz at 210°C, G = 2)
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
•
•
•
High Output Current
(±110 mA at 25°C and 50 mA at 210°C)
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Low Input Noise
(2.5 nV/√Hz at 25°C and 4.5 nV/√Hzat 210°C)
Available in Extreme (–55°C/210°C)
Temperature Range(1)
Low Supply Current
(5.6 mA at 25°C and 6.8 mA at 210°C)
•
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Flexible Supply Voltage:
–
–
Dual ±2.5 V to ±5 V
Single +5 V
Texas Instruments high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures. All devices are characterized
and qualified for 1000 hour continuous
operating life at maximum rated temperature.
APPLICATIONS
•
•
Downhole Drilling
Extreme Temperature Application
(1) Custom temperature ranges available
DESCRIPTION
The OPA820 provides a wideband, unity-gain stable, voltage-feedback amplifier with a very low input noise
voltage and high output current using a low 6.8-mA supply current. The OPA820 complements this high-speed
operation with excellent DC precision in a low-power device. A worst-case input offset voltage of ±3.5 mV and an
offset current of ±700 nA give excellent absolute DC precision for pulse amplifier applications.
Minimal input and output voltage swing headroom allow the OPA820 to operate on a single 5-V supply with >
2VPP output swing. While not a rail-to-rail (RR) output, this swing will support most emerging analog-to-digital
converter (ADC) input ranges with lower power and noise than typical RR output op amps.
The OPA820 is characterized for operation from –55°C to 210°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OPA820-HT
SBOS587 –DECEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BARE DIE INFORMATION
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
BOND PAD
THICKNESS
DIE THICKNESS
BACKSIDE FINISH
15 mils.
Silicon with backgrind
Floating
TiW/AlCu (0.5%)
1100 nm
1094µm
CIC60311
69µm
654µm
0
45µm
0
Table 1. Bond Pad Coordinates in Microns
DISCRIPTION
Inverting Input
NonInverting Input
Output
PAD NUMBER
X MIN
27
Y MIN
439
125
27
X MAX
125
Y MAX
537
1
2
3
4
5
27
125
125
831
831
831
929
125
-VS
233
439
929
331
+VS
929
537
ORDERING INFORMATION(1)
ORDERABLE PART NUMBER
OPA820SKD3
TA
PACKAGE(2)
TOP-SIDE MARKING
–55°C to 210°C
KGD (bare die)
NA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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SBOS587 –DECEMBER 2011
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
UNIT
V
Supply voltage, VS– to VS+
±6.5
±1.2
±VS
50
Differential input voltage, VID
V
Input common-mode voltage range
Maximum continuous operating current at 210°C
Internal power dissipation
V
mA
See Thermal Characteristic specifications
Junction temperature, TJ
210
°C
Operating Free-air Temperature Range, TA
Storage Temperature Range, TSTG
Lead temperature (soldering, 10 s)
–55 to 210
–65 to 210
300
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
xxxx
100000
10000
1000
100
160
170
180
190
200
210
220
Continuous T (°C)
J
A. See datasheet for absolute maximum and minimum recommended operating conditions.
B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
C. The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wear out for the specific device process and design characteristics.
Figure 1. OPA820-HT Operating Life Derating Chart
Copyright © 2011, Texas Instruments Incorporated
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SBOS587 –DECEMBER 2011
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ELECTRICAL CHARACTERISTICS: VS = ±5 V
RF = 402 Ω, RL = 100 Ω, and G = 2, unless otherwise noted.
-55°C to 125°C
210°C
TEST
PARAMETER
AC PERFORMANCE
Small-Signal Bandwidth
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
LEVEL(1)
G = 1, VO = 0.1VPP, RF = 0 Ω
G = 2, VO = 0.1VPP
G = 10, VO = 0.1VPP
G ≥ 20
800
240
30
MHz
MHz
MHz
MHz
C
C
C
C
100
202
Gain Bandwidth Product
150
270
38
Bandwidth for 0.1dB Gain
Flatness
G = 2, VO = 0.1VPP
MHz
C
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
VO = 0.1VPP, RF = 0 Ω
G = 2, VO = 2VPP
0.5
85
dB
MHz
V/µs
ns
C
C
C
C
G = 2, 2-V Step
240
10.5
22
185
11.5
28
Rise and Fall Time
G = 2, VO = 0.2-V Step
0.02%
Settling Time to
0.1%
G = 2, VO = 2-V Step
ns
C
18
25
Harmonic Distortion
2nd harmonic
G = 2, f = 1 MHz, VO = 2VPP
RL = 200 Ω
-85
-90
-79
-77
-90
-78
-98
4.5
dBc
dBc
C
C
C
C
C
C
C
C
RL = 500 Ω
-81
-88
-100
2.9
3
3rd harmonic
RL = 200 Ω
-95
dBc
RL = 500 Ω
-110
2.5
dBc
Input Voltage Noise
Input Current Noise
Differential Gain
f > 100 kHz
nV/√Hz
pA/√Hz
%
f > 100 kHz
1.7
G = 2, PAL, VO = 1.4VPP, RL = 150 Ω
G = 2, PAL, VO = 1.4VPP, RL = 150 Ω
0.01
0.03
Differential Phase
°
DC PERFORMANCE(2)
Open-Loop Voltage Gain
VO = 0 V, Input-Referred
VCM = 0 V
59
62
±1.8
7
52
57
±1.8
7
dB
mV
A
A
C
C
C
C
C
(AOL
)
Input Offset Voltage
±3.5
±3.5
Average input offset
voltage drift
VCM = 0 V
μV/°C
μA
Input Bias Current
VCM = 0 V
39
39
Average input bias
current drift
VCM = 0 V
50
50
nA/°C
nA
Input Offset Current
VCM = 0 V
±700
50
±700
50
Inverting Input Bias Current
Drift
VCM = 0 V
nA/°C
(1) Test levels: (A) 100% tested. (B) Limits set by characterization and simulation. (C) Typical value only for information.
(2) Current is considered positive out-of-node. VCM is the input common-mode voltage.
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SBOS587 –DECEMBER 2011
ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)
RF = 402 Ω, RL = 100 Ω, and G = 2, unless otherwise noted.
-55°C to 125°C
210°C
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
LEVEL(1)
INPUT
Common-Mode Input Range
(CMIR)(3)
±3.9
±3.2
V
A
A
Common-Mode Rejection
Ratio
VCM = 0 V, Input-Referred
73
71
dB
Input Impedance
Differential mode
Common mode
OUTPUT
VCM = 0 V
VCM = 0 V
18 || 0.8
6 || 1
kΩ || pf
C
MΩ || pf
No Load
RL = 100 Ω
±3.5
±3.5
±3.7
±3.6
±90
±3.4
±3.4
Output Voltage Swing
V
A
Short-Circuit Output Current
Output Shorted to Ground
±50
mA
C
C
Closed-Loop Output
Impedance
G = 2, f ≤ 100 kHz
0.04
Ω
POWER SUPPLY
Maximum Operating
Voltage
V
±5
±5
A
Maximum Quiescent
Current
VS = ±5 V
VS = ±5 V
6.6
6.8
mA
mA
dB
A
A
A
Minimum Quiescent Current
5
5
Power-Supply Rejection
Ratio (±PSRR)
Input Referred
62
61
(3) Tested < 3 dB below minimum specified CMRR at ±CMIR limits.
Copyright © 2011, Texas Instruments Incorporated
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SBOS587 –DECEMBER 2011
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ELECTRICAL CHARACTERISTICS: VS = 5 V
RF = 402 Ω, RL = 100 Ω, and G = 2, unless otherwise noted.
-55°C to 125°C
210°C
TEST
PARAMETER
AC PERFORMANCE
Small-Signal Bandwidth
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
LEVEL(1)
G = 1, VO = 0.1VPP, RF = 0 Ω
G = 2, VO = 0.1VPP
G = 10, VO = 0.1VPP
G ≥ 20
800
240
30
MHz
MHz
MHz
MHz
C
C
C
C
100
202
Gain Bandwidth Product
150
270
38
Bandwidth for 0.1dB Gain
Flatness
G = 2, VO = 0.1VPP
MHz
C
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
VO = 0.1VPP, RF = 0 Ω
G = 2, VO = 2VPP
0.5
85
dB
MHz
V/µs
ns
C
C
C
C
G = 2, 2-V Step
240
10.5
22
185
11.5
28
Rise and Fall Time
G = 2, VO = 0.2-V Step
0.02%
Settling Time to
0.1%
G = 2, VO = 2-V Step
ns
C
18
24
Harmonic Distortion
2nd harmonic
G = 2, f = 1 MHz, VO = 2VPP
RL = 200 Ω
-85
-90
-95
-110
2.5
-76
-75
-92
-91
4.5
dBc
dBc
C
C
C
C
C
C
RL = 500 Ω
3rd harmonic
RL = 200 Ω
dBc
RL = 500 Ω
dBc
Input Voltage Noise
Input Current Noise
f > 100 kHz
nV/√Hz
pA/√Hz
f > 100 kHz
1.7
G = 2, PAL, VO = 1.4VPP, RL = 150
Differential Gain
0.01
0.03
%
C
C
Ω
G = 2, PAL, VO = 1.4VPP, RL = 150
Differential Phase
°
Ω
DC PERFORMANCE(2)
Open-Loop Voltage Gain
VO = 0 V, Input-Referred
VCM = 0 V
60
65
1.8
7
58
64
1.8
7
dB
mV
A
A
C
C
C
C
C
(AOL
)
Input Offset Voltage
3.5
3.5
Average input offset
voltage drift
VCM = 0 V
μV/°C
μA
Input Bias Current
VCM = 0 V
39
39
Average input bias
current drift
VCM = 0 V
50
50
nA/°C
nA
Input Offset Current
VCM = 0 V
±700
50
±700
50
Inverting Input Bias Current
Drift
VCM = 0 V
nA/°C
(1) Test levels: (A) 100% tested. (B) Limits set by characterization and simulation. (C) Typical value only for information.
(2) Current is considered positive out-of-node. VCM is the input common-mode voltage.
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SBOS587 –DECEMBER 2011
ELECTRICAL CHARACTERISTICS: VS = 5 V (continued)
RF = 402 Ω, RL = 100 Ω, and G = 2, unless otherwise noted.
-55°C to 125°C
210°C
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
LEVEL(1)
INPUT
Common-Mode Input Range
(CMIR)(3)
3.9
72
3.2
70
V
A
A
Common-Mode Rejection
Input Impedance
Differential mode
Common mode
OUTPUT
VCM = 0 V, Input-Referred
dB
VCM = 0 V
VCM = 0 V
18 || 0.8
6 || 1.0
kΩ || pf
C
MΩ || pf
No Load
RL = 100 Ω
3.4
3.4
3.7
3.6
±60
3.4
3.4
Output Voltage Swing
V
A
Short-Circuit Output Current
Output Shorted to Ground
±37
mA
C
C
Closed-Loop Output
Impedance
G = 2, f ≤ 100 kHz
0.04
Ω
POWER SUPPLY
Maximum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
5
5
V
A
A
A
VS = ±5 V
VS = ±5 V
5.8
6.5
mA
mA
3.8
62
4
Power-Supply Rejection
Ratio (±PSRR)
Input Referred
61
dB
C
(3) Tested < 3 dB below minimum specified CMRR at ±CMIR limits.
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SBOS587 –DECEMBER 2011
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TYPICAL CHARACTERISTICS: VS = ±5 V
RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted.
NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE
INVERTING SMALL−SIGNAL FREQUENCY RESPONSE
3
0
3
0
G = +1
RF = 0 W
−
G =
G =
1
−
2
G = +5
−
−
3
6
9
3
6
9
G = +2
−
5
G =
−
−
−
−
G = +10
−
G = 10
−
12
−
15
−
18
−
12
−
15
−
18
VO = 0.1VPP
RL = 100 W
See Figure 1
VO = 0.1VPP
RL = 100 W
See Figure 2
1M
10M
100M
1G
1
10
Frequency (MHz)
100
500
Frequency (Hz)
NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE
VO = 0.5VPP
INVERTING LARGE−SIGNAL FREQUENCY RESPONSE
VO = 0.5VPP
9
6
3
0
3
0
−
−
−
3
6
9
VO = 1VPP
VO = 2VPP
VO = 1VPP
VO = 2VPP
−
−
−
3
6
9
VO = 4VPP
VO = 4VPP
−
12
15
18
G = +2
RL = 100
See Figure 1
−
1
G =
Ω
−
−
RL = 100 W
See Figure 2
−
12
1
10
100
500
1
10
100
500
Frequency (MHz)
Frequency (MHz)
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
0.4
0.3
2.0
0.4
0.3
2.0
G = −1
See Figure 2
Large Signal 1V
Right Scale
1.5
1.5
0.2
1.0
0.2
1.0
0.1
0.5
0.1
0.5
Small Signal 100 mV
Left Scale
Small Signal 100 mV
Left Scale
0
0
0
0
−0.1
−0.2
−0.3
−0.4
−0.5
−1.0
−1.5
−2.0
−0.1
−0.2
−0.3
−0.4
−0.5
−1.0
−1.5
−2.0
Large Signal 1V
Right Scale
G = +2
See Figure 1
Time (10 ns/div)
Time (10ns/div)
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SBOS587 –DECEMBER 2011
TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted.
1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
HARMONIC DISTORTION vs LOAD RESISTANCE
−
−
−
−
−
75
80
85
90
95
−
−
−
−
−
−
70
75
80
85
90
95
VO = 2VPP
f = 1MHz
RL = 200 W
VO = 2VPP
G = +2V/V
G = +2V/V
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
3rd−Harmonic
−
−
100
105
See Figure 1
5.5
See Figure 1
−
100
2.5
3.0
3.5
4.0
4.5
5.0
6.0
10
10
100
1k
Supply Voltage ( VS)
Ω
Resistance (
)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
f = 1MHz
HARMONIC DISTORTION vs FREQUENCY
VO = 2VPP
−
−
−
−
−
75
80
−
−
−
−
−
−
−
−
60
65
70
75
80
85
90
95
RL = 100 W
RL = 200 W
2nd−Harmonic
G = +2V/V
G = +2V/V
85
90
2nd−Harmonic
95
−
−
−
100
105
110
3rd−Harmonic
3rd−Harmonic
−
100
105
See Figure 1
0.1
See Figure 1
10
−
1
0.1
1
Output Voltage (VPP
)
Frequency (MHz)
HARMONIC DISTORTION vs NONINVERTING GAIN
HARMONIC DISTORTION vs INVERTING GAIN
−
−
−
−
−
−
−
−
−
−
−
−
70
75
80
85
90
95
70
75
80
85
90
95
f = 1MHz
f = 1MHz
RL = 200 W
VO = 2VPP
RL = 200 W
VO = 2VPP
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
3rd−Harmonic
−
100
105
110
−
−
See Figure 2
See Figure 1
10
−
100
1
1
| |
Gain ( V/V )
Gain (V/V)
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TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted.
TWO−TONE, 3RD−ORDER
INPUT VOLTAGE AND CURRENT NOISE
100
INTERMODULATION INTERCEPT
50
45
40
35
30
25
20
15
PI
PO
OPA820
50 W
200 W
402 W
402 W
10
√
Voltage Noise (2.5nV/ Hz)
√
Current Noise (1.7pA/ Hz)
1
10
100
1k
10k
100k
1M
10M
0
5
10
15
20
25
30
Frequency (Hz)
Frequency (MHz)
RECOMMENDED RS vs CAPACITIVE LOAD
0dB Peaking Targeted
FREQUENCY RESPONSE vs CAPACITIVE LOAD
CL = 10pF
100
8
7
6
5
4
3
2
1
0
CL = 22pF
CL = 47pF
CL = 100pF
10
RS
VI
VO
(1)
OPA820
50Ω
CL
Ω
1k
402Ω
−
1
2
3
Ω
NOTE: (1) 1k is optional.
402Ω
−
−
1
1
10
100
1000
1
10
100
400
Capacitive Load (pF)
Frequency (MHz)
CMRR AND PSRR vs FREQUENCY
CMRR
OPEN−LOOP GAIN AND PHASE
90
80
70
60
50
40
30
20
10
0
80
0
70
60
50
40
30
20
10
0
−20
20 log (AOL
)
−40
−60
+PSRR
−80
∠A OL
−100
−120
−140
−160
−180
−
PSRR
−10
100
1k
10k
100k
1M
10M 100M
1G
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
10
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SBOS587 –DECEMBER 2011
TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
5
CLOSED−LOOP OUTPUT IMPEDANCE vs FREQUENCY
10
1W Internal
Output Current
4
Power Limit
Limit
3
RL = 100Ω
2
1
1
0
Ω
RL = 25
RL = 50Ω
−
1
2
3
4
5
0.1
0.01
−
−
−
−
Output Current
Limit
1W Internal
Power Limit
−
−
−
50
150
100
0
50
100
150
1k
10k
100k
1M
10M
100M
IO (mA)
Frequency (Hz)
INVERTING OVERDRIVE RECOVERY
NONINVERTING OVERDRIVE RECOVERY
Input Right Scale
5
4
3
2
1
0
5
4
3
2
1
0
8
6
4
2
0
4
3
2
1
0
−
−
−
−
Input
Right Scale
Output Left Scale
Output
−
1
−
2
−
3
−
4
−
5
−
−
−
−
−
1
2
3
4
5
−
−
−
−
2
4
6
8
1
2
3
4
Left Scale
RL = 100Ω
RL = 100Ω
−
G = 1V/V
G = +2V/V
See Figure 1
See Figure 2
Time (40ns/div)
Time (40ns/div)
COMMON−MODE INPUT RANGE AND OUTPUT SWING
vs SUPPLY VOLTAGE
6
COMPOSITE VIDEO dG/dP
dG Negative Video
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
0.40
0.36
0.32
0.28
0.24
0.20
0.16
0.12
0.08
0.04
0
G = +2V/V
5
4
3
2
1
0
+VIN
−
VIN
+VOUT
dP Negative Video
dP Positive Video
−
VOUT
dG Positive Video
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1
2
3
4
Video Loads
Supply Voltage ( VS)
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TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted.
TYPICAL INPUT OFFSET VOLTAGE DISTRIBUTION
COMMON−MODE AND DIFFERENTIAL
INPUT IMPEDANCE
2500
2000
1500
1000
500
−
µ
Mean = 30 V
10M
µ
Standard Deviation = 80 V
Common−Mode Input Impedance
Total Count = 6115
1M
100k
Differential Input Impedance
10k
1k
0
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
µ
Input Offset Voltage ( V)
TYPICAL INPUT OFFSET CURRENT DISTRIBUTION
2000
1800
1600
1400
1200
1000
800
Mean = 26nA
Standard Deviation = 57nA
Total Count = 6115
600
400
200
0
Input Offset Current (nA)
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TYPICAL CHARACTERISTICS: VS = 5 V
RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted.
NONINVERTING SMALL−SIGNAL FREQUENCY RESPONSE
INVERTING SMALL−SIGNAL FREQUENCY RESPONSE
3
0
3
0
−
−
G =
G =
1
2
G = +1
G = +2
−
−
3
6
9
3
6
9
−
5
G =
G = +5
G = +10
−
−
−
−
−
G = 10
−
12
−
15
−
18
−
12
−
15
−
18
VO = 0.1VPP
Ω
VO = 0.1VPP
Ω
RL = 100
See Figure 4
RL = 100
See Figure 3
1M
10M
100M
1G
1
10
Frequency (MHz)
100
500
Frequency (Hz)
NONINVERTING LARGE−SIGNAL FREQUENCY RESPONSE
VO = 0.5VPP
INVERTING LARGE−SIGNAL FREQUENCY RESPONSE
VO = 0.5VPP
9
6
3
0
3
0
VO = 1VPP
−
−
−
3
6
9
VO = 2VPP
VO = 1VPP
VO = 2VPP
VO = 4VPP
VO = 4VPP
−
−
−
3
6
9
−
12
15
18
−
G =
RL = 100
See Figure 4
1
G = +2V/V
Ω
−
−
Ω
RL = 100
See Figure 3
−
12
1
10
100
600
1
10
100
500
Frequency (MHz)
Frequency (MHz)
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
2.9
4.5
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
4.5
G = −1
See Figure 4
Large Signal 1V
Right Scale
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Small Signal 100mV
Left Scale
Small Signal 100mV
Left Scale
Large Signal 1V
Right Scale
G = +2
See Figure 3
Time (10ns/div)
Time (10ns/div)
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TYPICAL CHARACTERISTICS: VS = 5 V (continued)
RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs FREQUENCY
−
−
−
−
−
−
−
−
−
75
80
85
90
95
60
70
80
90
f = 1MHz
VO = 2VPP
G = +2V/V
G = +2V/V
RL = 200Ω
O = 2VPP
2nd−Harmonic
2nd−Harmonic
V
3rd−Harmonic
3rd−Harmonic
−
100
110
−
100
105
See Figure 3
See Figure 3
0.1
−
−
100
1k
10
10
1
10
Ω
Resistance (
)
Frequency (MHz)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
VO = 2VPP
HARMONIC DISTORTION vs NONINVERTING GAIN
−
−
−
70
80
90
−
−
−
−
60
70
80
90
f = 1MHz
RL = 200Ω
f = 1MHz
VO = 2VPP
G = +2V/V
RL = 200Ω
2nd−Harmonic
2nd−Harmonic
3rd−Harmonic
3rd−Harmonic
−
100
110
−
100
110
See Figure 3
0.1
See Figure 3
−
−
1
Output Voltage Swing (VPP
1
10
)
Gain (V/V)
TWO−TONE, 3RD−ORDER
HARMONIC DISTORTION vs INVERTING GAIN
INTERMODULATION INTERCEPT
−
−
−
−
−
−
70
75
80
85
90
95
40
35
30
25
20
15
f = 1MHz
RL = 200Ω
O = 2VPP
+5V
806Ω
µ
0.01
F
PI
V
PO
OPA820
806Ω
57.6Ω
2nd−Harmonic
200Ω
402Ω
402Ω
0.01µF
3rd−Harmonic
See Figure 4
−
100
1
0
5
10
15
20
25
30
| |
Gain ( V/V )
Frequency (MHz)
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TYPICAL CHARACTERISTICS: VS = 5 V (continued)
RF = 402 Ω, RL = 100 Ω, G = 2 and TA = 25°C unless otherwise noted.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
CL = 10pF
100
8
7
6
5
4
3
2
1
0
0dB Peaking Targeted
CL = 22pF
CL = 47pF
CL = 100pF
10
+5V
806Ω
806Ω
µ
F
0.01
RS
V
I
VO
(1)
OPA820
57.6Ω
CL
1kΩ
402Ω
−
1
2
3
NOTE: (1) 1kΩis optional.
402Ω
µ
0.01
F
−
−
1
1
10
100
1000
1
10
100
300
Capacitive Load (pF)
Frequency (MHz)
TYPICAL INPUT OFFSET VOLTAGE DISTRIBUTION
TYPICAL INPUT OFFSET CURRENT DISTRIBUTION
3500
3000
2500
2000
1500
1000
500
2000
1800
1600
1400
1200
1000
800
− µ
Mean = 490 V
µ
Standard Deviation = 90 V
Mean = 43nA
Standard Deviation = 50nA
Total Count = 6115
Total Count = 6115
600
400
200
0
0
Input Offset Voltage (mV)
Input Offset Current (nA)
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APPLICATION INFORMATION
Wideband Voltage-Feedback Operation
The combination of speed and dynamic range offered by the OPA820 is easily achieved in a wide variety of
application circuits, providing that simple principles of good design practice are observed. For example, good
power-supply decoupling, as shown in Figure 2, is essential to achieve the lowest possible harmonic distortion
and smooth frequency response.
Proper PC board layout and careful component selection will maximize the performance of the OPA820 in all
applications, as discussed in the following sections of this data sheet.
Figure 2 shows the gain of +2 configuration used as the basis for most of the typical characteristics. Most of the
curves were characterized using signal sources with 50-Ω driving impedance and with measurement equipment
presenting 50-Ω load impedance. In Figure 2, the 50-Ω shunt resistor at the VI terminal matches the source
impedance of the test generator while the 50-Ω series resistor at the VO terminal provides a matching resistor for
the measurement equipment load. Generally, data sheet specifications refer to the voltage swings at the output
pin (VO in Figure 2). The 100-Ω load, combined with the 804-Ω total feedback network load, presents the
OPA820 with an effective load of approximately 90 Ω in Figure 2.
+5V
+VS
+
µ
0.1 F
2.2µF
50Ω Source
VIN
50Ω Load
RS
50Ω
VO
50Ω
OPA820
RF
402Ω
RG
402Ω
0.1µF
2.2µF
+
−
VS
−5V
Figure 2. Gain of +2, High-Frequency Application and Characterization Circuit
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Wideband Inverting Operation
Operating the OPA820 as an inverting amplifier has several benefits and is particularly useful when a matched
50-Ω source and input impedance is required. Figure 3 shows the inverting gain of −1 circuit used as the basis of
the inverting mode typical characteristics.
+5V
+
µ
0.1 F
µ
2.2 F
50Ω Load
Ω
50
VO
RT
205Ω
µ
0.01 F
OPA820
RG
402Ω
RF
402Ω
50Ω Source
VI
RM
Ω
57.6
0.1µF
2.2µF
+
−
5V
Figure 3. Inverting G = −1 Specifications and Test Circuit
In the inverting case, just the feedback resistor appears as part of the total output load in parallel with the actual
load. For the 100-Ω load used in the typical characteristics, this gives a total load of 80 Ω in this inverting
configuration. The gain resistor is set to get the desired gain (in this case 402 Ω for a gain of −1) while an
additional input matching resistor (RM) can be used to set the total input impedance equal to the source if
desired. In this case, RM = 57.6 Ω in parallel with the 402-Ω gain setting resistor gives a matched input
impedance of 50 Ω. This matching is only needed when the input needs to be matched to a source impedance,
as in the characterization testing done using the circuit of Figure 3.
The OPA820 offers extremely good DC accuracy as well as low noise and distortion. To take full advantage of
that DC precision, the total DC impedance looking out of each of the input nodes must be matched to get bias
current cancellation. For the circuit of Figure 32, this requires the 205-Ω resistor shown to ground on the
noninverting input. The calculation for this resistor includes a DC-coupled 50-Ω source impedance along with RG
and RM. Although this resistor will provide cancellation for the bias current, it must be well decoupled (0.01 μF in
Figure 3) to filter the noise contribution of the resistor and the input current noise.
As the required RG resistor approaches 50 Ω at higher gains, the bandwidth for the circuit in Figure 3 will far
exceed the bandwidth at that same gain magnitude for the noninverting circuit of Figure 2. This occurs due to the
lower noise gain for the circuit of Figure 3 when the 50-Ω source impedance is included in the analysis. For
instance, at a signal gain of −10 (RG = 50 Ω, RM = open, RF = 499 Ω) the noise gain for the circuit of Figure 3 will
be 1 + 499 Ω/(50 Ω + 50 Ω) = 6 as a result of adding the 50-Ω source in the noise gain equation. This gives
considerable higher bandwidth than the noninverting gain of +10. Using the 240-MHz gain bandwidth product for
the OPA820, an inverting gain of −10 from a 50-Ω source to a 50-Ω RG gives 55-MHz bandwidth, whereas the
noninverting gain of +10 gives 30 MHz.
Wideband Single-Supply Operation
Figure 4 shows the AC-coupled, single 5-V supply, gain of +2 V/V circuit configuration used as a basis for the
5 V only Electrical and Typical Characteristics. The key requirement for single-supply operation is to maintain
input and output signal swings within the useable voltage ranges at both the input and the output. The circuit of
Figure 4 establishes an input midpoint bias using a simple resistive divider from the 5-V supply (two 806-Ω
resistors) to the noninverting input. The input signal is then AC-coupled into this midpoint voltage bias. The input
voltage can swing to within 0.9 V of the negative supply and 0.5 V of the positive supply, giving a 3.6VPP input
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signal range. The input impedance matching resistor (57.6 Ω) used in Figure 4 is adjusted to give a 50-Ω input
match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is
AC-coupled, giving the circuit a DC gain of +1. This puts the input DC bias voltage (2.5 V) on the output as well.
On a single 5-V supply, the output voltage can swing to within 1.3 V of either supply pin while delivering more
than 80-mA output current giving 2.4-V output swing into 100 Ω (5.6-dBm maximum at the matched load).
Figure 5 shows the AC-coupled, single 5-V supply, gain of −1 V/V circuit configuration used as a basis for the
5 V only Typical Characteristic curves. In this case, the midpoint DC bias on the noninverting input is also
decoupled with an additional 0.01-μF decoupling capacitor. This reduces the source impedance at higher
frequencies for the noninverting input bias current noise. This 2.5-V bias on the noninverting input pin appears on
the inverting input pin and, since RG is DC blocked by the input capacitor, will also appear at the output pin.
The single-supply test circuits of Figure 4 and Figure 4 show 5-V operation. These same circuits can be used
over a singlesupply range of 5 V to 12 V. Operating on a single 12-V supply, with the Absolute Maximum Supply
voltage specification of 13 V, gives adequate design margin for the typical ±5% supply tolerance.
+5V
+VS
+
µ
0.1 F
µ
6.8 F
50ΩSource
VI
Ω
Ω
806
µ
0.01 F
DIS
100Ω
VO
VS/2
OPA820
Ω
57.6
806
RF
402Ω
RG
Ω
402
µ
0.01 F
Figure 4. AC-Coupled, G = +2 V/V, Single-Supply Specifications and Test Circuit
+5V
+VS
+
µ
0.1 F
µ
6.8 F
806Ω
806Ω
DIS
VO
Ω
100
µ
0.01 F
VS/2
OPA820
RG
RF
µ
0.01 F
Ω
402
402Ω
VI
Figure 5. AC-Coupled, G = −1 V/V, Single-Supply Specifications and Test Circuit
Buffering High-Performance ADCs
To achieve full performance from a high dynamic range ADC, considerable care must be exercised in the design
of the input amplifier interface circuit. The example circuit on the front page shows a typical AC-coupled interface
to a very high dynamic range converter. This AC-coupled example allows the OPA820 to be operated using a
signal range that swings symmetrically around ground (0 V). The 2VPP swing is then level-shifted through the
blocking capacitor to a midscale reference level, which is created by a well-decoupled resistive divider off the
converter’s internal reference voltages. To have a negligible effect (1 dB) on the rated spurious-free dynamic
range (SFDR) of the converter, the amplifier’s SFDR should be at least 18 dB greater than the converter. The
OPA820 has minimal effect on the rated distortion of the ADS850, given its 79-dB SFDR at 2VPP, 1 MHz. The
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> 90-dB (< 1MHz) SFDR for the OPA820 in this configuration implies a < 3-dB degradation (for the system) from
the converter’s specification. For further SFDR improvement with the OPA820, a differential configuration is
suggested.
Successful application of the OPA820 for ADC driving requires careful selection of the series resistor at the
amplifier output, along with the additional shunt capacitor at the ADC input. To some extent, selection of this RC
network will be determined empirically for each converter. Many high performance CMOS ADCs, such as the
ADS850, perform better with the shunt capacitor at the input pin. This capacitor provides low source impedance
for the transient currents produced by the sampling process. Improved SFDR is often obtained by adding this
external capacitor, whose value is often recommended in this converter data sheet. The external capacitor, in
combination with the built-in capacitance of the ADC input, presents a significant capacitive load to the OPA820.
Without a series isolation resistor, an undesirable peaking or loss of stability in the amplifier may result.
Since the DC bias current of the CMOS ADC input is negligible, the resistor has no effect on overall gain or
offset accuracy. Refer to the typical characteristic RS vs Capacitive Load to obtain a good starting value for the
series resistor. This will ensure flat frequency response to the ADC input. Increasing the external capacitor value
will allow the series resistor to be reduced. Intentionally bandlimiting using this RC network can also be used to
limit noise at the converter input.
Video Line Driving
Most video distribution systems are designed with 75-Ω series resistors to drive a matched 75-Ω cable. In order
to deliver a net gain of 1 to the 75-Ω matched load, the amplifier is typically set up for a voltage gain of +2,
compensating for the 6-dB attenuation of the voltage divider formed by the series and shunt 75-Ω resistors at
either end of the cable.
The circuit of Figure 2 applies to this requirement if all references to 50-Ω resistors are replaced by 75-Ω values.
Often, the amplifier gain is further increased to 2.2, which recovers the additional DC loss of a typical long cable
run. This change would require the gain resistor (RG) in Figure 2 to be reduced from 402 Ω to 335 Ω. In either
case, both the gain flatness and the differential gain/phase performance of the OPA820 will provide exceptional
results in video distribution applications. Differential gain and phase measure the change in overall small-signal
gain and phase for the color sub-carrier frequency (3.58 MHz in NTSC systems) versus changes in the
large-signal output level (which represents luminance information in a composite video signal). The OPA820, with
the typical 150-Ω load of a single matched video cable, shows less than 0.01%/0.01° differential gain/phase
errors over the standard luminance range for a positive video (negative sync) signal. Similar performance would
be observed for multiple video signals, as shown in Figure 6.
Ω
335
Ω
402
Ω
75 Transmission Line
Ω
75
Ω
75
Ω
75
VOUT
VOUT
VOUT
OPA820
Video
Input
Ω
Ω
Ω
75
75
75
Ω
75
High output current drive capability allows three
Ω
back−terminated 75 transmission lines to be simultaneously driven.
Figure 6. Video Distribution Amplifier
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Single Operational Amplifier Differential Amplifier
The voltage-feedback architecture of the OPA820, with its high common-mode rejection ratio (CMRR), will
provide exceptional performance in differential amplifier configurations. Figure 7 shows a typical configuration.
The starting point for this design is the selection of the RF value in the range of 200 Ω to 2 kΩ. Lower values
reduce the required RG, increasing the load on the V2 source and on the OPA820 output. Higher values increase
output noise as well as the effects of parasitic board and device capacitances. Following the selection of RF, RG
must be set to achieve the desired inverting gain for V2. Remember that the bandwidth will be set approximately
by the gain bandwidth product (GBP) divided by the noise gain (1 + RF/RG). For accurate differential operation
(that is, good CMRR), the ratio R2/R1 must be set equal to RF/RG.
+5V
Power−supply decoupling not shown.
R1
V1
50Ω
RF
R2
VO
=
(V1 −
V2)
OPA820
RG
R2 RF
=
R1 RG
when
RG
RF
V2
−
5V
Figure 7. High-Speed, Single Differential Amplifier
Usually, it is best to set the absolute values of R2 and R1 equal to RF and RG, respectively; this equalizes the
divider resistances and cancels the effect of input bias currents. However, it is sometimes useful to scale the
values of R2 and R1 in order to adjust the loading on the driving source, V1. In most cases, the achievable
low-frequency CMRR will be limited by the accuracy of the resistor values. The 85-dB CMRR of the OPA820
itself will not determine the overall circuit CMRR unless the resistor ratios are matched to better than 0.003%. If it
is necessary to trim the CMRR, then R2 is the suggested adjustment point.
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DAC Transimpedance Amplifier
High-frequency digital-to-analog converters (DACs) require a low-distortion output amplifier to retain their SFDR
performance into real-world loads. See Figure 8 for a single-ended output drive implementation. In this circuit,
only one side of the complementary output drive signal is used. The diagram shows the signal output current
connected into the virtual ground-summing junction of the OPA820, which is set up as a transimpedance stage or
I-V converter. The unused current output of the DAC is connected to ground. If the DAC requires its outputs to
be terminated to a compliance voltage other than ground for operation, then the appropriate voltage level may be
applied to the non-inverting input of the OPA820.
VO = ID RF
OPA820
High−Speed
DAC
RF
CF
CD
ID
→
GBP Gain Bandwidth
Product (Hz) for the OPA820.
ID
Figure 8. Wideband, Low-Distortion DAC Transimpedance Amplifier
The DC gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance (CD) will produce a
zero in the noise gain for the OPA820 that may cause peaking in the closed-loop frequency response. CF is
added across RF to compensate for this noise-gain peaking. To achieve a flat transimpedance frequency
response, this pole in the feedback network should be set to:
1
GBP
4pR
=
2pRFC
F
F
C
D
(1)
which will give a corner frequency f−3dB of approximately:
GBP
f
- 3dB =
4pRFC
D
(2)
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Active Filters
Most active filter topologies will have exceptional performance using the broad bandwidth and unity-gain stability
of the OPA820. Topologies employing capacitive feedback require a unity-gain stable, voltage-feedback op amp.
Sallen-Key filters simply use the operational amplifier as a noninverting gain stage inside an RC network. Either
current- or voltage-feedback op amps may be used in Sallen-Key implementations.
Figure 9 shows an example Sallen-Key low-pass filter, in which the OPA820 is set up to deliver a low-frequency
gain of +2. The filter component values have been selected to achieve a maximally-flat Butterworth response
with a 5-MHz, −3-dB bandwidth. The resistor values have been slightly adjusted to compensate for the effects of
the 240-MHz bandwidth provided by the OPA820 in this configuration. This filter may be combined with the ADC
driver suggestions to provide moderate (2-pole) Nyquist filtering, limiting noise, and out-of-band harmonics into
the input of an ADC. This filter will deliver the exceptionally low harmonic distortion required by high SFDR ADCs
such as the ADS850 (14-bit, 10 MSPS, 82-dB SFDR).
C1
150pF
+5V
R1
R2
Ω
Ω
505
124
V1
C2
VO
OPA820
100pF
RF
Ω
402
Power−supply
decoupling not shown.
−
5V
RG
Ω
402
Figure 9. 5-MHz Butterworth Low-Pass Active Filter
Another type of filter, a high-Q bandpass filter, is shown in Figure 10. The transfer function for this filter is:
R
3
+ R
4
S
1
V
OUT
R1R
4
C
1
=
R
3
V
IN
S2 + S
+
R1C
1
R
2R
4R
5
C1C
2
(3)
(4)
with
2
R
3
wO
=
R
2R
4R
5
C1C
2
and
wO
1
=
C
Q
R
1
1
(5)
(6)
For the values chosen in Figure 10:
wO
≃
; 1MHz
fO
=
2p
and Q = 100.
See Figure 11 for the frequency response of the filter shown in Figure 10.
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R3
500Ω
OPA820
R4
500Ω
C2
R5
1000pF
Ω
158
R2
R1
15.8k
158Ω
VOUT
Ω
OPA820
VIN
C1
1000pF
Figure 10. High-Q 1-MHz Bandpass Filter
6
0
−
6
−
12
−
18
−
24
−
30
−
36
−
42
−
48
−
54
−
60
−
66
−
72
100k
1M
10M
Frequency (Hz)
100M
Figure 11. High-Q 1-MHz Bandpass Filter Frequency Response
DESIGN-IN TOOLS
Macromodels and Applications Support
Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the
OPA820 and its circuit designs. This is particularly true for video and RF amplifier circuits where parasitic
capacitance and inductance can play a major role on circuit performance. A SPICE model for the OPA820 is
available through the TI web page (www.ti.com). The applications department is also available for design
assistance. These models predict typical small-signal AC, transient steps, DC performance, and noise under a
wide variety of operating conditions. The models include the noise terms found in the electrical specifications of
the data sheet. These models do not attempt to distinguish between the package types in their small-signal AC
performance.
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OPERATING SUGGESTIONS
Optimizing Resistor Values
Since the OPA820 is a unity-gain stable, voltage-feedback operational amplifier, a wide range of resistor values
may be used for the feedback and gain-setting resistors. The primary limits on these values are set by dynamic
range (noise and distortion) and parasitic capacitance considerations. Usually, the feedback resistor value should
be between 200 Ω and 1 kΩ. Below 200 Ω, the feedback network will present additional output loading which can
degrade the harmonic distortion performance of the OPA820. Above 1 kΩ, the typical parasitic capacitance
(approximately 0.2 pF) across the feedback resistor may cause unintentional band limiting in the amplifier
response. A direct short is suggested as a feedback for AV = +1 V/V.
A good rule of thumb is to target the parallel combination of RF and RG (see Figure 2) to be less than about
200 Ω. The combined impedance RF||RG interacts with the inverting input capacitance, placing an additional pole
in the feedback network, and thus a zero in the forward response. Assuming a 2-pF total parasitic on the
inverting node, holding RF||RG < 200 Ω will keep this pole above 400 MHz. By itself, this constraint implies that
the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed
by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest.
In the inverting configuration, an additional design consideration must be noted. RG becomes the input resistor
and therefore the load impedance to the driving source. If impedance matching is desired, RG may be set equal
to the required termination value. However, at low inverting gains, the resulting feedback resistor value can
present a significant load to the amplifier output. For example, an inverting gain of 2 with a 50-Ω input matching
resistor (= RG) would require a 100-Ω feedback resistor, which would contribute to output loading in parallel with
the external load. In such a case, it would be preferable to increase both the RF and RG values, and then achieve
the input matching impedance with a third resistor to ground (see Figure 3). The total input impedance becomes
the parallel combination of RG and the additional shunt resistor.
Bandwidth vs Gain
Voltage-feedback operational amplifiers exhibit decreasing closed-loop bandwidth as the signal gain is increased.
In theory, this relationship is described by the GBP shown in the specifications. Ideally, dividing GBP by the
noninverting signal gain (also called the noise gain, or NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90°, as it does in high-gain configurations. At low signal
gains, most amplifiers will exhibit a more complex response with lower phase margin. The OPA820 is optimized
to give a maximally-flat, 2nd-order Butterworth response in a gain of 2. In this configuration, the OPA820 has
approximately 64° of phase margin and will show a typical −3-dB bandwidth of 240 MHz. When the phase
margin is 64°, the closed-loop bandwidth is approximately √2 greater than the value predicted by dividing GBP
by the noise gain.
Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the
predicted value of (GBP/NG). At a gain of +10, the 30-MHz bandwidth shown in the Electrical Characteristics
agrees with that predicted using the simple formula and the typical GBP of 280 MHz.
Output Drive Capability
The OPA820 has been optimized to drive the demanding load of a doubly-terminated transmission line. When a
50-Ω line is driven, a series 50 Ω into the cable and a terminating 50-Ω load at the end of the cable are used.
Under these conditions, the cable impedance will appear resistive over a wide frequency range, and the total
effective load on the OPA820 is 100 Ω in parallel with the resistance of the feedback network. The electrical
characteristics show a ±3.6-V swing into this load—which will then be reduced to a ±1.8-V swing at the
termination resistor. The ±75-mA output drive over temperature provides adequate current drive margin for this
load. Higher voltage swings (and lower distortion) are achievable when driving higher impedance loads.
A single video load typically appears as a 150-Ω load (using standard 75-Ω cables) to the driving amplifier. The
OPA820 provides adequate voltage and current drive to support up to three parallel video loads (50-Ω total load)
for an NTSC signal. With only one load, the OPA820 achieves an exceptionally low 0.01%/0.03° dG/dP error.
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Driving Capacitive Loads
One of the most demanding, and yet very common, load conditions for an operational amplifier is capacitive
loading. A high-speed, high open-loop gain amplifier like the OPA820 can be very susceptible to decreased
stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. In simple
terms, the capacitive load reacts with the open-loop output resistance of the amplifier to introduce an additional
pole into the loop and thereby decrease the phase margin. This issue has become a popular topic of application
notes and articles, and several external solutions to this problem have been suggested. When the primary
considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response,
but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from
the capacitive load pole, thus increasing the phase margin and improving stability.
The Typical Characteristics show the recommended RS vs Capacitive Load and the resulting frequency response
at the load. The criterion for setting the recommended resistor is maximum bandwidth, flat frequency response at
the load. Since there is now a passive low-pass filter between the output pin and the load capacitance, the
response at the output pin itself is typically somewhat peaked, and becomes flat after the roll-off action of the RC
network. This is not a concern in most applications, but can cause clipping if the desired signal swing at the load
is very close to the amplifier’s swing limit. Such clipping would be most likely to occur in pulse response
applications where the frequency peaking is manifested as an overshoot in the step response.
Parasitic capacitive loads greater than 2 pF can begin to degrade the performance of the OPA820. Long PC
board traces, unmatched cables, and connections to multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to
the OPA820 output pin (see the Board Layout section).
Distortion Performance
The OPA820 is capable of delivering an exceptionally low distortion signal at high frequencies and low gains.
The distortion plots in the Typical Characteristics show the typical distortion under a wide variety of conditions.
Most of these plots are limited to 100-dB dynamic range. The OPA820 distortion does not rise above −90 dBc
until either the signal level exceeds 0.9 V and/or the fundamental frequency exceeds 500 kHz. Distortion in the
audio band is ≤ −100 dBc.
Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd-harmonic will dominate
the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load
impedance improves distortion directly. Remember that the total load includes the feedback network—in the
noninverting configuration this is the sum of RF + RG, whereas in the inverting configuration this is just RF (see
Figure 2). Increasing the output voltage swing increases harmonic distortion directly. Increasing the signal gain
will also increase the 2nd-harmonic distortion. Again, a 6-dB increase in gain will increase the 2nd- and
3rd-harmonic by 6 dB even with a constant output power and frequency. Finally, the distortion increases as the
fundamental frequency increases because of the roll-off in the loop gain with frequency. Conversely, the
distortion will improve going to lower frequencies down to the dominant open-loop pole at approximately
100 kHz. Starting from the −85-dBc 2nd-harmonic for 2VPP into 200 Ω, G = +2 distortion at 1 MHz (from the
Typical Characteristics), the 2nd-harmonic distortion will not show any improvement below 100 kHz and will then
be:
−100 dB − 20 log (1 MHz/100 kHz) = −105 dBc
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Noise Performance
The OPA820 complements its low harmonic distortion with low input noise terms. Both the input-referred voltage
noise and the two input-referred current noise terms combine to give a low output noise under a wide variety of
operating conditions. Figure 12 shows the operational amplifier noise analysis model with all the noise terms
included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz
or pA/√Hz.
ENI
EO
OPA820
RS
IBN
ERS
RF
√
4kTRS
√
4kTRF
IBI
RG
4kT
RG
−
4kT = 1.6E 20J
at 290 K
Figure 12. Operational Amplifier Noise Analysis Model
The total output spot noise voltage is computed as the square root of the squared contributing terms to the
output noise voltage. This computation is adding all the contributing noise powers at the output by superposition,
then taking the square root to get back to a spot noise voltage. Equation 7 shows the general form for this output
noise voltage using the terms presented in Figure 12.
EO
=
[E2NI + (IBN
RS
)2 + 4kTR
S
]NG2 + (IBI
RF
)2 + 4kTR
NG
F
(7)
Dividing this expression by the noise gain (NG = 1 + RF/RG) will give the equivalent input referred spot noise
voltage at the noninverting input, as shown in Equation 8.
2
I
BI
R
F
4kTR
F
æ
ö
EN
=
E2NI + (IBN
RS
)2 + 4kTR
S
+
+
ç
÷
NG
NG
è
ø
(8)
Evaluating these two equations for the OPA820 circuit presented in Figure 2 will give a total output spot noise
voltage of 6.44 nV/√Hz and an equivalent input spot noise voltage of 3.22 nV/√Hz.
DC Offset Control
The OPA820 can provide excellent DC signal accuracy because of its high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset voltage and bias current offset errors. To take full
advantage of this low input offset voltage, careful attention to input bias current cancellation is also required. The
high-speed input stage for the OPA820 has a moderately high input bias current (9 μA typ into the pins) but with
a very close match between the two input currents—typically 100-nA input offset current. The total output offset
voltage may be considerably reduced by matching the source impedances looking out of the two inputs. For
example, one way to add bias current cancellation to the circuit of Figure 2 would be to insert a 175-Ω series
resistor into the noninverting input from the 50-Ω terminating resistor. When the 50-Ω source resistor is
DC-coupled, this will increase the source impedance for the noninverting input bias current to 200 Ω. Since this is
now equal to the impedance looking out of the inverting input (RF||RG), the circuit will cancel the gains for the
bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term
at the output. Using a 402-Ω feedback resistor, this output error will now be less than ±0.4 μA × 402 Ω = ±160 μV
at 25°C.
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SBOS587 –DECEMBER 2011
Thermal Analysis
The OPA820 will not require heatsinking or airflow in most applications. Maximum desired junction temperature
would set the maximum allowed internal power dissipation as described below. In no case should the maximum
junction temperature be allowed to exceed 210°C.
Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the
sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.
Quiescent power is simply the specified no-load supply current times the total supply voltage across the part.
PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a
maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies).
Under this worst-case condition, PDL = VS2/(4 × RL), where RL includes feedback network loading.
Note that it is the power in the output stage and not in the load that determines internal power dissipation.
Board Layout
Achieving optimum performance with a high-frequency amplifier such as the OPA820 requires careful attention to
board layout parasitics and external component types. Recommendations that will optimize performance include:
a. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause instability: on the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the
signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground
and power planes should be unbroken elsewhere on the board.
b. Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1-μF decoupling
capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. The power-supply connections should always be decoupled with these capacitors.
Larger (2.2-μF to 6.8-μF) decoupling capacitors, effective at lower frequency, should also be used on the
main supply pins. These may be placed somewhat farther from the device and may be shared among
several devices in the same area of the PC board.
c. Careful selection and placement of external components will preserve the high-frequency
performance of the OPA820. Resistors should be a very low reactance type. Surface-mount resistors work
best and allow a tighter overall layout. Metal-film and carbon composition, axially leaded resistors can also
provide good high-frequency performance. Again, keep their leads and PC board trace length as short as
possible. Never use wire-wound type resistors in a high-frequency application. Since the output pin and
inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series
output resistor, if any, as close as possible to the output pin. Other network components, such as
noninverting input termination resistors, should also be placed close to the package. Where double-side
component mounting is allowed, place the feedback resistor directly under the package on the other side of
the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the
external resistors, excessively high resistor values can create significant time constants that can degrade
performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the
resistor. For resistor values > 1.5 kΩ, this parasitic capacitance can add a pole and/or a zero below 500 MHz
that can effect circuit operation. Keep resistor values as low as possible consistent with load-driving
considerations. It has been suggested here that a good starting point for design would be to set RG||RF = 200
Ω. Using this setting will automatically keep the resistor noise terms low, and minimize the effect of their
parasitic capacitance.
d. Connections to other wideband devices on the board may be made with short direct traces or
through onboard transmission lines. For short connections, consider the trace and the input to the next
device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably
with ground and power planes opened up around them. Estimate the total capacitive load and set RS from
the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5 pF) may not need an
RS since the OPA820 is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase
margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques
(consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is
normally not necessary onboard, and in fact, a higher impedance environment will improve distortion as
shown in the distortion versus load plots. With a characteristic board trace impedance defined based on
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board material and trace dimensions, a matching series resistor into the trace from the output of the OPA820
is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the
terminating impedance will be the parallel combination of the shunt resistor and input impedance of the
destination device; this total effective impedance should be set to match the trace impedance. If the 6-dB
attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated
at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as
shown in the plot of RS vs Capacitive Load. This will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the destination device is low, there will be some signal
attenuation due to the voltage divider formed by the series output into the terminating impedance.
e. Socketing a high-speed part like the OPA820 is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network,
which can make it almost impossible to achieve a smooth, stable frequency response. Best results are
obtained by soldering the OPA820 onto the board.
Input and ESD Protection
The OPA820 is built using a very high-speed complementary bipolar process. The internal junction breakdown
voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power
supplies, as shown in Figure 13.
+VCC
External
Pin
−
VCC
Figure 13. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection
diodes can typically support 30-mA continuous current. Where higher currents are possible (for example, in
systems with ±15-V supply parts driving into the OPA820), current-limiting series resistors should be added into
the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance
and frequency response. Figure 14 shows an example protection circuit for I/O voltages that may exceed the
supplies.
+5V
50Ω Source
174Ω
Power−supply
decoupling not shown.
V1
50Ω
D1
D2
OPA820
VO
50Ω
RF
50Ω
301Ω
RG
301Ω
−
5V
D1 = D2 IN5911 (or equivalent)
Figure 14. Gain of +2 With Input Protection
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PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
OPA820SKGD3
ACTIVE
XCEPT
KGD
0
400
TBD
Call TI
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA820-HT :
Catalog: OPA820
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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