OPA818IDRGT [TI]
2.7GHz、13V、解补偿 7V/V FET 输入运算放大器 | DRG | 8 | -40 to 125;
| 型号： | OPA818IDRGT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.7GHz、13V、解补偿 7V/V FET 输入运算放大器 | DRG | 8 | -40 to 125 放大器 运算放大器 |
| 文件： | 总32页 (文件大小：1096K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA818
ZHCSJO8 –MAY 2019
OPA818 2.7GHz、13V、7V/V 稳定增益、FET 输入运算放大器
1 特性
3 说明
1
•
高速:
OPA818 是一款解补偿（稳定增益 = 7V/V）电压反馈
运算放大器，具有低噪声结型场效应管 (JFET) 输入
级，它将高增益带宽与 6V 至 13V 的宽电源电压范围
集于一身，适用于高速、宽动态范围的 应用。此放大
器使用德州仪器 (TI) 专有的高速硅锗 (SiGe) 工艺制
造，性能明显高于其他高速 FET 输入放大器。快速压
摆率 (1400V/µs) 可提供更高的大信号带宽和低失真。
–
–
–
–
增益带宽积：2.7GHz
带宽 (G = 7V/V)：790MHz
大信号带宽 (2VPP)：400MHz
压摆率：1400V/µs
•
•
解补偿增益：7V/V（稳定）
低噪声：
–
–
输入电压噪声：2.2nV/√Hz
OPA818 具有 2.7GHz 的增益带宽、较低的 2.4pF 总
输入电容和 2.2nV/√Hz 的噪声，因此用途非常广泛，
宽带 TIA 光电二极管放大器可用在光学测试和通信设
备以及很多医疗、科技和工业仪器中。OPA818 可使
用 TIA 配置实现 85MHz 以上的信号带宽、20kΩ 的
TIA 增益 (RF)、0.5pF 的光电二极管电容 (CD) 和宽输
出摆幅。具有皮安级输入偏置电流的解补偿低噪声架构
也非常适合具有可变或较高源阻抗的高增益测试和测量
应用 。尽管在增益 ≥ 7V/V 时通常保持稳定，但也可以
利用噪声增益整形技术将 OPA818 用于具有较低增益
的 应用 。
输入电流噪声：2.5 fA/√Hz (f = 10kHz)
•
•
输入偏置电流：4pA（典型值）
低输入电容：
–
–
共模：1.9pF
差分模式：0.5pF
•
低失真（G = 7V/V，RL = 1kΩ，VO = 2VPP）：
–
–
1MHz 时的 HD2、HD3：-90dBc、-96dBc
50MHz 时的 HD2、HD3：-57dBc、-72dBc
•
•
•
•
•
宽电源电压范围：6V 至 13V
输出摆幅：8VPP (VS = 10V)
电源电流：27.7mA
OPA818 采用带有裸露散热垫的 8 引脚 WSON 封装。
此器件可在 -40°C 至 +85°C 的工业温度范围内正常运
行。
关断电源电流：27µA
温度范围：-40°C 至 +85°C
器件信息(1)
2 应用
•
•
•
•
•
•
•
宽带跨阻放大器 (TIA)
器件型号
OPA818
封装
WSON (8)
封装尺寸（标称值）
3.00mm × 3.00mm
晶圆扫描设备
光学通信模块
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
光学时域反射法 (OTDR)
高速高增益数据采集
测试和测量前端
光电二极管电容与 3dB 带宽间的关系
90
RF = 20 kW
80
70
60
50
40
30
20
10
0
RF = 50 kW
RF = 100 kW
RF = 500 kW
医学和化学分析器
高速光学前端
CF
VBIAS
100 kꢀ
RF1
+5 V
œ
RG1
+
VCM
ADC
VREF1
0
2
4
6
8
10
12
14
16
18
20
+
œ
Photodiode Capacitance, CD (pF)
D100
-5 V
RG2
VREF2
RF2
OPA818
THS4520
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS940
OPA818
ZHCSJO8 –MAY 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 13
Power Supply Recommendations...................... 16
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: VS = ±5 V......................... 5
6.6 Typical Characteristics: VS = ±5 V............................ 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 20
11.1 接收文档更新通知 ................................................. 20
11.2 社区资源................................................................ 20
11.3 商标....................................................................... 20
11.4 静电放电警告......................................................... 20
11.5 Glossary................................................................ 20
12 机械、封装和可订购信息....................................... 20
12.1 Package Option Addendum .................................. 21
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2019 年 5 月
*
初始发行版。
2
Copyright © 2019, Texas Instruments Incorporated
OPA818
www.ti.com.cn
ZHCSJO8 –MAY 2019
5 Pin Configuration and Functions
DRG Package
8-Pin WSON With Thermal Pad
Top View
PD
FB
VS+
OUT
NC
1
2
3
4
8
7
6
5
INÞ
IN+
Þ
VSÞ
+
NC - no internal connection
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
WSON
FB
2
3
4
6
7
1
5
8
Output
Input
Input
—
Feedback resistor connection (optional)
Inverting input
IN–
IN+
NC
Noninverting input
No connect (no internal connection to die)
Output of amplifier
OUT
PD
Output
Input
Power
Power
Power down
VS–
VS+
Negative power supply
Positive power supply
Electrically isolated from the die. Recommended connection to a heat spreading plane,
typically GND.
Thermal pad
—
Copyright © 2019, Texas Instruments Incorporated
3
OPA818
ZHCSJO8 –MAY 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
13.5
±5
UNIT
Voltage
Voltage
Supply voltage, (VS+) – (VS–)
Differential input voltage
V
V
V
Common-mode input voltage
Continuous input current
VS– + 10
±10
mA
mA
Current
Continuous output current(2)
Continuous current in feedback pin(2)
Junction temperature, TJ
Operating free-air, TA
45
13
105
Temperature
–40
–65
85
°C
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Long-term continuous current for electromigration limits.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±TBD
ANSI/ESDA/JEDEC JS-001, allpins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins(2)
±TBD
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
6
NOM
10
MAX
13
UNIT
V
VS
TA
Single-supply voltage
Ambient temperature
–40
25
85
°C
6.4 Thermal Information
OPA818
THERMAL METRIC(1)
DRG (SON)
8 PINS
54.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
56.0
27.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.8
ΨJB
27.2
RθJC(bot)
11.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
OPA818
www.ti.com.cn
ZHCSJO8 –MAY 2019
6.5 Electrical Characteristics: VS = ±5 V
at TA ≈ 25°C, VS+ = +5 V, VS– = –5 V, closed-loop gain (G) = 7 V/V, common-mode voltage (VCM) = midsupply, RF = 301 Ω, RL
= 100 Ω to midsupply (unless otherwise noted)
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO = 100 mVPP
790
440
50
SSBW
PM
Small-signal bandwidth
MHz
G = 10, VO = 100 mVPP
Phase margin
°
Frequency response peaking
Large-signal bandwidth
Gain-bandwidth product
Bandwdith for 0.1dB flatness
1.4
dB
LSBW
GBWP
VO = 2 VPP
400
2700
125
1400
1340
0.52
5.7
MHz
MHz
MHz
V/µs
V/µs
ns
G = 101 V/V, VO = 100 mVPP, RF = 3.01 kΩ
VO = 100 mVPP
VO = 4-V step, rising and falling
VO = 4-V step, rising and falling, G = 10
VO = 350-mV step (input tr/tf = 0.4 ns)
VO = 2-V step (input tr = 0.8 ns)
VO = 2-V step (input tr = 0.8 ns)
VO = 2-V step (input tr/tf = 0.8 ns)
VO = (VS– – 1 V) to (VS+ + 1 V)
f = 1 MHz
SR
Slew rate (20%-80%)
tr/tf
tS
Rise and fall time (10%-90%)
Settling time to 0.1%
ns
tS
Settling time to 0.01%
12
ns
Overshoot and undershoot
Overdrive recovery time
0.2%
ns
–84
–64
–52
VO = 2 VPP
f = 10 MHz
f = 50 MHz
Second-order harmonic
distortion
HD2
dBc
VO = 2 VPP
RL = 1 kΩ,
,
f = 10 MHz
–71
f = 1 MHz
f = 10 MHz
f = 50 MHz
–106
–96
VO = 2 VPP
HD3
en
Third-order harmonic distortion
Input voltage noise
dBc
–74
VO = 2 VPP
,
f = 10 MHz
–82
RL = 1 kΩ,
f ≥ 150 kHz
1/f corner
f = 10 kHz
f = 1 MHz
f = 10 MHz
2.2
15
nV/√Hz
kHz
2.5
145
0.2
fA/√Hz
fA/√Hz
Ω
in
Input current noise
ZO
Closed-loop output impedance
DC PERFORMANCE
AOL
Open-loop voltage gain
f = DC, VO = ±2 V
85
92
dB
mV
0.35
1.25
1.8
20
VOS
Input offset voltage
TA = –40°C to +85°C
TA = –40°C to +85°C
Input offset voltage drift(1)
Input bias current(2)
3
4
µV/°C
pA
–20
–500
–20
–500
73
20
IB
TA = –40°C to +85°C
500
20
1
IOS
Input offset current(2)
pA
TA = –40°C to +85°C
500
f = DC, VCM = ±0.5 V
90
dB
dB
CMRR
Common-mode rejection ratio
f = DC, VCM = ±0.5 V, TA = –40°C to +85°C
70
Internal feedback trace
resistance
Device turned OFF, OUT to FB pin
resistance
1.2
1.6
2
Ω
(1) Input offset voltage drift and input bias current drift are average values calculated by taking data at the end-points, computing the
difference, and dividing by the temperature range.
(2) Current is considered positive out of the pin. IOS = IB+ – IB–
.
Copyright © 2019, Texas Instruments Incorporated
5
OPA818
ZHCSJO8 –MAY 2019
www.ti.com.cn
Electrical Characteristics: VS = ±5 V (continued)
at TA ≈ 25°C, VS+ = +5 V, VS– = –5 V, closed-loop gain (G) = 7 V/V, common-mode voltage (VCM) = midsupply, RF = 301 Ω, RL
= 100 Ω to midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
Common-mode input impedance
Differential input impedance
Most positive input voltage(3)
Most negative input voltage(3)
500 || 1.9
500 || 0.5
VS+ – 3.2
GΩ || pF
GΩ || pF
V
VS+ – 3.6
VS– VS– + 0.25
V
VCM = VS+ – 3.6 V
–1
–1.5
–1
0.03
1
–1.5
1
mV
ΔVOS at most positive input
voltage(4)
VCM = VS+ – 3.6 V, TA = -40°C to +85°C
VCM = VS– + 0.25 V
mV
–0.23
mV
ΔVOS at most negative input
voltage(4)
VCM = VS– + 0.25 V, TA = -40°C to +85°C
–1.5
–1.5
mV
OUTPUT
VS+ – 1.2
VS+ – 1.3
VS+ – 1
VS+ – 1
V
V
V
V
V
V
V
V
TA = –40°C to +85°C
RL = 1 kΩ
VOH
Output voltage swing high
Output voltage swing low
VS+ – 0.9
RL = 1 kΩ, TA = –40°C to +85°C
VS+ – 1.2
VS– + 1.2 VS– + 1.33
VS– + 1.4
TA = –40°C to +85°C
RL = 1 kΩ
VOL
VS– + 1.1 VS– + 1.2
VS– + 1.3
RL = 1 kΩ, TA = –40°C to +85°C
VOUT = ±2.75 V, RL to midsupply =
50 Ω, [ΔVOS from no-load VOS] ≤ 1 mV
±55
±50
mA
IO_MAX
Linear output drive
VOUT = ±2.5 V, RL to midsupply =
50 Ω, [ΔVOS from no-load VOS] ≤ 1 mV,
TA = –40°C to +85°C
mA
ISC
Output short-circuit current
Capacitive load drive
±100
mA
pF
pF
30% overshoot, VOUT step = 200 mV
G = 10, 30% overshoot
2
2
CLOAD
POWER SUPPLY
VS
Single-supply operating range
6
27
23
10
13
29
V
mA
mA
µA/°C
dB
No load
27.7
IQ
Quiescent current per channel
IQ drift
No load, TA = –40°C to +85°C
No load, TA = –40°C to +85°C
ΔVS+ = ±0.25 V
31.5
42
95
75
70
80
74
Positive power supply rejection
ratio
PSRR+
PSRR–
ΔVS+ = ±0.25 V, TA = –40°C to +85°C
ΔVS– = ±0.25 V
dB
94
dB
Negative power supply rejection
ratio
ΔVS– = ±0.25 V, TA = –40°C to +85°C
dB
POWER DOWN
VTH_EN Enable voltage threshold
VTH_DIS
Power on when PD > VTH_EN, No Load
Power down when PD < VTH_DIS, No Load
No Load
VS+ – 1
V
Disable voltage threshold
Power-down VCC IQ
VS+ – 3
40
V
27
–2
µA
µA
µA
ns
ns
No load, PD = VS+
–3
PD pin bias current(2)
No load, PD = VS–
13
20
Turnon time delay
Turnoff time delay
Time to VO = 90% of final value
Time to VO = 10% of original value
270
230
(3) Defined by ΔVOS at most positive/negative input voltage specification
(4) ΔVOS = |VOS at specified VCM – VOS at 0 V VCM
|
6
Copyright © 2019, Texas Instruments Incorporated
OPA818
www.ti.com.cn
ZHCSJO8 –MAY 2019
6.6 Typical Characteristics: VS = ±5 V
at TA ≈ 25°C, VS+ = +5 V, VS– = –5 V, closed-loop gain (G) = 7 V/V, VCM = midsupply, RF = 301 Ω, RL = 100 Ω to midsupply,
small-signal VO = 100 mVPP, large-signal VO = 2 VPP (unless otherwise noted)
3
0
100
50
-3
-6
10
5
-9
G = 7 V/V, RF = 301 W
G = 10 V/V, RF = 301 W
G = 101 V/V, RF = 3.01 kW
-12
-15
1
1
10
100
1k
10
100
1k
10k
100k
1M
Frequency (MHz)
Frequency (Hz)
D001
D026
VO = 100 mVPP
图 1. Noninverting Small-Signal Frequency Response
图 2. Voltage Noise Density Vs Frequency
4000
104
15
AOL Magnitude (dB)
AOL Phase (è)
96
88
80
72
64
56
48
40
32
24
16
8
0
-15
1000
100
10
-30
-45
-60
-75
-90
-105
-120
-135
-150
-165
-180
1
0
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
D101
D027
Common-mode
noise
Simulation
Simulation
图 4. Open-Loop Gain Magnitude and Phase Vs Frequency
图 3. Current Noise Density Vs Frequency
200
100
10
2
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
D102
Simulation
图 5. Open-Loop Output Impedance Vs Frequency
版权 © 2019, Texas Instruments Incorporated
7
OPA818
ZHCSJO8 –MAY 2019
www.ti.com.cn
7 Detailed Description
7.1 Overview
The OPA818 is a 13 V supply, 2.7 GHz gain-bandwidth product (GBWP), voltage feedback operational amplifier
(op amp) featuring a 2.2nV/√Hz low noise JFET input stage. The OPA818 is decompensated to be normally
stable in gains ≥ 7 V/V. The decompensated architecture allows for a favorable tradeoff of low quiescent current
for a very high GBWP and low distortion performance in high gain applications. The high voltage capability
combined with 1400 V/µs slew rate enables applications needing wide output swings (10 VPP at VS = 12 V) for
high frequency signals such as those often found in optical front-end, test and measurement applications, and
medical systems. The low noise JFET input with pico amperes of bias current makes the device particularly
attractive for high transimpedance gain TIA applications and for test and measurement front-ends. OPA818 also
features power down mode that disables the core amplifier for power savings.
OPA818 is built using TI's proprietary high-voltage high-speed complementary bipolar SiGe process.
7.2 Functional Block Diagram
The OPA818 is a conventional voltage feedback op amp with two high-impedance inputs and a low-impedance
output. Standard amplifier configurations are supported like the two basic configurations shown in 图 6 and 图 7.
The DC operating point for each configuration is level-shifted by the reference voltage (VREF), which is typically
set to midsupply in single-supply operation. VREF is typically set to ground in split-supply applications.
VSIG
VS+
(1 + RF / RG) × VSIG
VREF
VREF
VIN
+
VOUT
œ
RG
VSœ
RF
VREF
图 6. Noninverting Amplifier
VS+
œ(RF / RG) × VSIG
VREF
+
VSIG
VOUT
VREF
VREF
VIN
œ
RG
VSœ
RF
图 7. Inverting Amplifier
7.3 Feature Description
7.3.1 Input and ESD Protection
The OPA818 is built using a very high speed complementary bipolar process. The internal junction breakdown
voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power
supplies as shown in 图 8.
These diodes provide moderate protection to input overdrive voltages beyond the supplies as well. The
protection diodes can typically support 10-mA continuous current. Where higher currents are possible (for
example, in systems with ±12-V supply parts driving into the OPA818), current limiting series resistors should be
added in series with the two inputs to limit the current. Keep these resistor values as low as possible because
high values degrade both noise performance and frequency response. There are no back-to-back ESD diodes
between VIN+ and VIN–. As a result, the differential input voltage between VIN+ and VIN– is entirely absorbed by the
VGS of the input JFET differential pair and must not exceed the voltage ratings shown in Absolute Maximum
Ratings table.
8
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OPA818
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ZHCSJO8 –MAY 2019
Feature Description (接下页)
VS+
VIN+
Power Supply
ESD Cell
Internal
Circuitry
VOUT
VINÞ
FB
VSÞ
图 8. Internal ESD Protection
7.3.2 Feedback Pin
For high speed analog design, minimizing parasitic capacitances and inductances is critical to get the best
performance from a high speed amplifier such as the OPA818. Parasitics are especially detrimental in the
feedback path and at the inverting input. They result in undesired poles and zeroes in the feedback that could
result in reduced phase margin or instability. Techniques used to correct for this phase margin reduction often
result in reduced application bandwidth. To keep system engineers from making these tradeoff choices and to
simplify the PCB layout, OPA818 features an FB pin on the same side as the inverting input pin, IN–. This allows
for a very short feedback resistor, RF, connection between the FB and the IN– pin as shown in 图 9, thus
minimizing parasitics with minimal PCB design effort. Internally the FB pin is connected to VOUT via metal
routing on the silicon. Due to the fixed metal sizing of this connection, FB pin has limited current carrying
capability and specifications in the Absolute Maximum Ratings must be adhered to for continuous operation.
PD
FB
VS+
OUT
NC
1
2
3
4
8
7
6
5
RF
INÞ
Þ
VSÞ
IN+
+
图 9. RF Connection Between FB and IN– Pins
7.3.3 Decompensated Architecture With Wide Gain-Bandwidth Product
图 10 shows the open-loop gain and phase response of the OPA818. The GBWP of an op amp is measured in
the 20 dB/decade constant slope region of the AOL magnitude plot. The open-loop gain of 60 dB for the OPA818
is along this 20 dB/decade slope and the corresponding frequency intercept is at 2.7 MHz. Converting 60 dB to
linear units (1000 V/V) and multiplying it with the 2.7 MHz frequency intercept gives the GBWP of OPA818 as 2.7
GHz. As can be inferred from the AOL Bode plot, the second pole in the AOL response occurs before AOL
magnitude drops below 0 dB (1 V/V). This results in phase change of more than 180° at 0 dB AOL indicating that
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Feature Description (接下页)
the amplifier will not be stable in a gain of 1 V/V. Amplifiers like OPA818 that are not unity-gain stable are
referred to as decompensated amplifiers. The decompensated architecture typically allows for higher GBWP,
higher slew rate, and lower noise compared to a unity-gain stable amplifier with equivalent quiescent current. The
additional advantage of the decompensated amplifier is better distortion performance at higher frequencies in
high gain applications for comparable quiescent current to a unity-gain stable amplifier.
OPA818 is stable in noise gain of 7 V/V (16.9 dB) or higher in conventional gain circuits as shown in 图 6 and 图
7. It has 790 MHz of SSBW in this gain configuration with approximately 50° phase margin.
The high GBWP and low voltage and current noise of OPA818 make it a very suitable amplifier for wideband
moderate to high transimpedance gain applications. Transimpedance gains of 50kΩ or higher benefit from the
low current noise JFET input. In a typical transimpedance (TIA) circuit as shown in 图 13, unity-gain stable
amplifier is not a requirement. At low frequencies, the noise gain of TIA is 0 dB (1 V/V) and at high frequencies
the noise gain is set by the ratio of the total input capacitance (CTOT) and the feedback capacitance (CF). To
maximize TIA closed-loop bandwidth, the feedback capacitance is generally smaller than the total input
capacitance. This results in the ratio of total input capacitance to the feedback capacitance to be greater than 1,
which is ultimately the noise gain of the TIA at higher frequencies. The blog series, What you need to know
about transimpedance amplifiers – part 1 and What you need to know about transimpedance amplifiers – part 2
describe TIA compensation techniques in greater detail.
120
110
100
90
80
70
60
50
40
30
20
10
0
104
96
88
80
72
64
56
48
40
32
24
16
8
15
TJ = -40èC
TJ = 27èC
TJ = 85èC
AOL Magnitude (dB)
AOL Phase (è)
0
-15
-30
-45
-60
-75
-90
-105
-120
-135
-150
-165
-180
0
1k
10k
100k
1M
10M
100M
1G
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
D027
D106
RL = 100 Ω
Simulation
RL = 100 Ω
Simulation
图 10. Open-Loop Gain Magnitude and Phase Vs
图 11. Open-Loop Gain Magnitude vs Temperature
Frequency
7.3.4 Low Input Capacitance
Often two primary considerations for TIA applications are maximizing TIA closed-loop bandwidth and minimizing
the total output noise to maximize Signal-to-Noise Ratio (SNR). The total input capacitance (CTOT) of TIA circuit
causes a zero in the noise gain in combination with the transimpedance gain (feedback resistor, RF) at frequency
1/(2πRFCTOT). For a fixed RF, this zero is at a lower frequency for higher CTOT thus increasing the noise gain at
lower frequency resulting in lower equivalent closed-loop bandwidth and higher total output noise compared to a
lower CTOT. By choosing an amplifier like OPA818 that features a low input capacitance (2.4 pF combined
common-mode and differential) for TIA application, the system designer can realize high closed-loop bandwidth
at low total output noise or have the flexibility to choose a photodiode with relatively higher capacitance. The
CTOT includes the input capacitance of the amplifier, the photodiode capacitance, and the PCB parasitic
capacitance at the inverting input.
10
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7.4 Device Functional Modes
7.4.1 Split-Supply Operation (+4/–2 V to ±6.5 V)
In typical split-supply operation, the mid-point between the power rails is ground. Mid-point at ground in split-
supply configuration is a valid operating condition for OPA818 when symmetric supply voltages that are greater
than or equal to ±4 V are used. This facilitates interfacing the OPA818 with common lab equipment such as
signal generators, network analyzers, oscilloscopes, and spectrum analyzers most of which have inputs and
outputs referenced to ground. However, when split-supply voltages less than ±4 V are used, care must be taken
that the input common-mode range is not violated because the typical input common-mode range of OPA818
includes VS– and extends up to 3.2 V from VS+. For example, when ±3 V supplies are used, the input common-
mode of the signal must be typically 3.2 V from VS+ and 3.6 V from VS+ under maximum specified input common-
mode range. This means ground is not included in the input common-mode range with ±3 V supplies resulting in
erroneous operation if the input signal has ground as the mid-point. To prevent this situation, +4/–2 V supplies
can be used.
7.4.2 Single-Supply Operation (6 V to 13 V)
Many newer systems use single power supply to improve efficiency and reduce the cost of the extra power
supply. The OPA818 is designed for use with split-supply configuration; however, it can be used with a single-
supply with no change in performance, as long as the input and output are biased within the linear operation of
the device. To change the circuit from split supply to single supply, level shift all the voltages to midsupply using
VREF. As described in Split-Supply Operation (+4/–2 V to ±6.5 V) , additional consideration must be given to the
input common-mode range so as not to violate it when operating with supplies less than 8 V. One of the
advantages of configuring an amplifier for single-supply operation is that the effects of –PSRR will be minimized
because the low supply rail has been grounded.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Wideband, Noninverting Operation
The OPA818 provides a unique combination of high GBWP, low-input voltage noise, and the DC precision of a
trimmed JFET-input stage to provide an exceptional high input impedance for a voltage-feedback amplifier. Its
very high GBWP of 2.7 GHz can be used to either deliver high-signal bandwidths at high gains, or to extend the
achievable bandwidth or gain in photodiode-transimpedance applications. To achieve the full performance of the
OPA818, careful attention to printed circuit board (PCB) layout and component selection is required as discussed
in the following sections of this data sheet.
图 12 shows the noninverting gain of +7 V/V circuit used as the basis for most of theTypical Characteristics: VS =
±5 V. Most of the curves were characterized using signal sources with 50-Ω driving impedance, and with
measurement equipment presenting a 50-Ω load impedance. In 图 12, the 49.9-Ω shunt resistor at the VIN
terminal matches the source impedance of the test generator, while the 49.9-Ω series resistor at the VO terminal
provides a matching resistor for the measurement equipment load. Generally, data sheet voltage swing
specifications are at the output pin (VO in 图 12) while output power specifications are at the matched 50-Ω load.
The total 100-Ω load at the output combined with the 350-Ω total feedback network load, presents the OPA818
with an effective output load of 78 Ω for the circuit of 图 12.
+5 V
0.22 …F
0.01 …F
50 ꢀ Source
50 ꢀ Load
+
VIN
VO
49.9 ꢀ
œ
49.9 ꢀ
0.22 …F
0.01 …F
œ5 V
RG
49.9 ꢀ
RF
301 ꢀ
图 12. Noninverting G = +7 V/V Configuration and Test Circuit
Voltage-feedback operational amplifiers, unlike current feedback products, can use a wide range of resistor
values to set their gain. To retain a controlled frequency response for the noninverting voltage amplifier of 图 12,
the parallel combination of RF || RG should always be less than 50Ω. In the noninverting configuration, the
parallel combination of RF || RG will form a pole with the parasitic input capacitance at the inverting node of the
OPA818 (including layout parasitics). For best performance, this pole should be at a frequency greater than the
closed loop bandwidth for the OPA818.
12
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Application Information (接下页)
8.1.2 Wideband, Transimpedance Design Using OPA818
With high GBWP, low input voltage and current noise, and low input capacitance, the OPA818 design is
optimized for wideband, low-noise transimpedance applications. The high voltage capability allows greater
flexibility of supply voltages along with wider output voltage swings. 图 13 shows an example circuit of a typical
photodiode amplifier circuit. Generally the photodiode is reverse biased in a TIA application so the photodiode
current in the circuit of图 13 flows into the op amp feedback loop resulting in an output voltage that reduces from
VREF with increasing photodiode current. In this type of configuration and depending on the application needs,
VREF can be biased closer to VS+ to achieve the desired output swing. Input common-mode range must be
considered so as not to violate it when VREF bias is used.
The key design elements that determine the closed-loop bandwidth, f–3dB, of the circuit are below:
1. The op amp GBWP
2. The transimpedance gain, RF, and,
3. The total input capacitance, CTOT, that includes photodiode capacitance, input capacitance of the amplifier
(common-mode and differential capacitance), and PCB parasitic capacitance
+5 V
VBIAS
OPA818
VREF
+
VO
œ
œ5 V
RF
CF
图 13. Wideband, Low-Noise, Transimpedance Amplifier
公式 1 shows the relationship between the above mentioned three elements for a Butterworth response.
GBWP
f-3dB
=
2pRFCTOT
(1)
The feedback resistance RF and the total input capacitance CTOT cause a zero in the noise gain that results in
instability if left uncompensated. To counteract the effect of the zero, a pole is inserted in the noise gain by
adding the feedback capacitor, CF. . The Transimpedance Considerations for High-Speed Amplifiers application
report discusses theories and equations that show how to compensate a transimpedance amplifier for a
particular gain and input capacitance. The bandwidth and compensation equations from the application report are
available in a Microsoft Excel™ calculator. What You Need To Know About Transimpedance Amplifiers – Part 1
provides a link to the calculator.
8.2 Typical Application
The high GBWP and low input voltage and current noise for the OPA818 make it an excellent wideband
transimpedance amplifier for moderate to high transimpedance gains.
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Typical Application (接下页)
Supply decoupling
not shown
+5 V
OPA818
+
VBIAS
VO
œ
œ5 V
RF
100 kꢀ
CDIFF
0.5 pF
C1
2.2 pF
C2
2.2 pF
CD
5 pF
CCM
1.9 pF
CT
47 pF
OPA818's input differential and
common-mode capacitance
图 14. Wideband, High-Sensitivity, Transimpedance Amplifier
8.2.1 Design Requirements
Design a high-bandwidth, high-transimpedance-gain amplifier with the design requirements shown in 表 1.
表 1. Design Requirements
TARGET BANDWIDTH (MHz) TRANSIMPEDANCE GAIN (kΩ) PHOTODIODE CAPACITANCE (pF)
24
100
5
8.2.2 Detailed Design Procedure
Designs that require high bandwidth from a large area detector with relatively high transimpedance gain benefit
from the low input voltage noise of the OPA818. This input voltage noise is peaked up over frequency by the
diode source capacitance, and can, in many cases, become the limiting factor to input sensitivity. 图 14 shows
the transimpedance circuit with the parameters as defined in Design Requirements. To use the Microsoft Excel™
calculator available at What You Need To Know About Transimpedance Amplifiers – Part 1 to help with the
component selection, total input capacitance, CTOT,needs to be determined. CTOT is referred as CIN in the
calculator. CTOT is the sum of CD, CDIFF, and CCM which is 7.4 pF. Using this value of CTOT, and the targeted
closed-loop bandwidth (f–3dB) of 24 MHz and transimpedance gain of 100 kΩ results in a need for an amplifier
with approximately 2.68 GHz GBWP and a feedback capacitance (CF) of 0.092 pF as shown in 图 15. These
results are for a Butterworth response with a Q = 0.707 and a phase margin of approximately 65° which
corresponds to 4.3% overshoot.
Calculator II
Closed-loop TIA Bandwidth (f-3dB
)
24.00
100.00
7.40
MHz
kOhm
pF
Feedback Resistance (RF)
Input Capacitance (CIN)
Opamp Gain Bandwidth Product (GBP)
Feedback Capacitance (CF)
2678.14
0.092
MHz
pF
图 15. Results of Inputting Design Parameters in the TIA Calculator
With OPA818's 2.7 GHz GBWP, it will be a suitable amplifier for the design requirements. A challenge with the
calculated component results is practically realizing a 0.092 pF capacitor. Such a small capacitor can be realized
by using a capacitive tee network formed by C1, C2, and CT such as that shown in 图 14. The equivalent
capacitance, CEQ, of the tee network is given by 公式 2.
14
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C1 ì C2
C1 + C2 + CT
CEQ
=
(2)
The tee network forms a capacitive attenuator from input to output with C1 and CT, and from output to input with
C2 and CT. With the value of CT being higher than C1 or C2, only a fraction of the output signal is seen by C1.
This results in a much smaller shunting current provided to the input through C1 and this reduced shunting
current effect is equivalent to how a much smaller capacitor behaves (at a fixed frequency, smaller capacitor has
higher impedance and thus reduced current). It is recommended to keep the same level of attenuation from input
to output and vice versa. To find the appropriate capacitor values for the tee network, chose an arbitrarily low but
practically realizable and equal values for capacitors C1 and C2, set CEQ = CTOT, and use 公式 3 to get the value
of the tunable capacitor, CT. The values of capacitors C1, C2, and CT in 图 14 were determined using this
process.
C1 ìC2 - (C1 + C2 )ìCEQ
CT
=
CEQ
(3)
图 16 shows the TINA simulated closed-loop bandwidth response of the circuit in 图 14. The circuit was designed
for f–3dB = 24 MHz and the simulated closed-loop 3-dB frequency is 24.6 MHz with about 0.1 dB peaking. The
OPA818 TINA model models the input common-mode and differential capacitors so they should not be added
externally when simulating in TINA. The noise simulation of the TIA circuit is shown in 图 17. The output referred
voltage noise is shown on the Y-axis to the left and the input referred current noise, which is essentially output
referred voltage noise divided by the transimpedance gain of 100k, is shown on the secondary Y-axis to the right.
The simulation results are fairly accurate because the OPA818 TINA model closely models the voltage and
current noise performance of the amplifier. The flat-band output voltage noise is 41 nV/√Hz that is equivalent to
0.41 pA/√Hz of input referred current noise. The noise in relatively low frequency region where the noise gain of
the amplifier is 1 V/V is dominated by the thermal noise of the 100 kΩ resistor (40.7 nV/√Hz at 27°C). At mid
frequencies beyond the zero formed by RF and CTOT, the noise gain of the amplifier amplifies the voltage noise of
the amplifier. The amplifier's noise starts to become the dominant noise contributor from this frequency onwards
before the output noise starts to roll off at frequencies beyond the 3-dB closed-loop bandwidth. When looked at
integrated root-mean-square (RMS) noise, the mid-frequency noise will be a significant contributor and hence
using a 2.2 nV/√Hz low-noise amplifier like OPA818 is advantageous to minimize total RMS noise in the system.
8.2.3 Application Curves
100.5
100
99.5
99
1000
700
10
7
500
5
300
200
3
2
98.5
98
100
70
1
97.5
97
0.7
0.5
50
96.5
96
30
20
0.3
0.2
95.5
95
10
0.1
1M
10M
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D103
D104
图 16. Simulated Closed-Loop Bandwidth TIA Response
图 17. Simulated TIA Noise
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9 Power Supply Recommendations
The OPA818 is intended for operation on supplies from 6 V (+4/–2 V) to 12 V (±6 V). OPA818 supports single-
supply, split and balanced bipolar supplies and unbalanced bipolar supplies. When operating at supplies below 8
V, the midsupply will be outside the input common-mode range of the amplifier. Under these supply conditions,
the common-mode must be biased appropriately for linear operation. Thus the limit to lower supply voltage
operation is the useable input voltage range for the JFET-input stage. Operating from a single supply of 12 V can
have numerous advantages. With the negative supply at ground, the DC errors due to the –PSRR term can be
minimized. Typically, AC performance improves slightly at 12-V operation with minimal increase in supply
current.
16
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10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA818 requires careful attention to
board layout parasitics and external component types. Recommendations that will optimize performance include.
1. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability. On the noninverting input, parasitic capacitance can
react with the source impedance to cause unintentional bandlimiting. Ground and power metal planes act as
one of the plates of a capacitor while the signal trace metal acts as the other separated by PCB dielectric. To
reduce this unwanted capacitance, a plane cutout around and underneath the signal I/O pins on all ground
and power planes is recommended. Otherwise, ground and power planes should be unbroken elsewhere on
the board. When configuring the amplifier as a TIA, if the required feedback capacitor is under 0.15 pF,
consider using two series resistors, each of half the value of a single resistor in the feedback loop to
minimize the parasitic capacitance from the resistor.
2. Minimize the distance (less than 0.25") from the power-supply pins to high-frequency decoupling
capacitors. Use high quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings
at least three times greater than the amplifiers maximum power supplies to ensure that there is a low-
impedance path to the amplifiers power-supply pins across the amplifiers gain bandwidth specification. At the
device pins, do not allow the ground and power plane layout to be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling
capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF
to 6.8-µF) decoupling capacitors, effective at lower frequency, must be used on the supply pins. These are
placed further from the device and are shared among several devices in the same area of the PC board.
3. Careful selection and placement of external components will preserve the high frequency
performance of the OPA818. Resistors should be of very low reactance type. Surface-mount resistors work
best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also
provide good high frequency performance. Again, keep their leads and PCB trace length as short as
possible. Never use wirewound type resistors in a high frequency application. Because the output pin and
inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series
output resistor, if any, as close as possible to the inverting input and the output pin, respectively. Other
network components, such as noninverting input termination resistors, should also be placed close to the
package. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor
values can create significant time constants that can degrade performance. When OPA818 is configured as
a conventional voltage amplifier, keep the resistor values as low as possible and consistent with the load
driving considerations. Lower resistor values minimize the effect of parasitic capacitance and reduce resistor
noise terms but because the feedback network (RF + RG for noninverting and RF for inverting configuration)
acts as a load on the amplifier, lower resistor values increase the dynamic power consumption and the
effective load on the output stage. Transimpedance applications (see 图 13) can use feedback resistors as
required by the application and as long as the feedback compensation capacitor is set considering all
parasitic capacitance terms on the inverting node.
4. Heat dissipation is important for a high voltage device like OPA818. For good thermal relief, the thermal
pad should be connected to a heat spreading plane that is preferably on the same layer as OPA818 or
connected by as many vias as possible if the plane is on a different layer. It is recommended to have at least
one heat spreading plane on the same layer as the OPA818 that makes a direct connection to the thermal
pad with wide metal for good thermal conduction when operating at high ambient temperatures. If more than
one heat spreading planes are available, connecting them by a number of vias further improves the thermal
conduction.
5. Socketing a high speed part like the OPA818 is not recommended. The additional lead length and pin-
to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which
can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the OPA818 onto the board.
10.1.1 Thermal Considerations
The OPA818 will not require heatsinking or airflow in most applications. Maximum allowed junction temperature
will set the maximum allowed internal power dissipation as described below. In no case should the maximum
junction temperature be allowed to exceed 105°C.
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Layout Guidelines (接下页)
Operating junction temperature (TJ) is given by TA + PD × RθJA. The total internal power dissipation (PD) is the
sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.
Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL
will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum
when the output is fixed at a voltage equal to 1/2 of either supply voltage (for balanced bipolar supplies). Under
this condition PDL = VS 2/(4 × RL) where RL includes feedback network loading.
Note that it is the power in the output stage and not into the load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using OPA818 in the circuit of 图 12 operating at the
maximum specified ambient temperature of +85°C and driving a grounded 100-Ω load.
PD = 10 V × 27.7 mA + 52 /(4 × (100 Ω || 350.9 Ω)) ≈ 357 mW
Maximum TJ = 85°C + (0.357 W × 54.6°C/W) = 104.5°C.
All actual applications will be operating at lower internal power and junction temperature.
10.2 Layout Example
Representative schematic
VS+
Connect PD to VS+ to enable the
1
2
8
7
CBYP
amplifier
CBYP
RS
+
To
Load
œ
Thermal
Pad
RS
RF
CBYP
Place gain and feedback resistors
close to pins to minimize stray
capacitance
VSœ
RF
3
4
6
5
No Connect
RG
RG
CBYP
Connect the thermal pad to a heat
spreading plane, generally ground
Ground and power plane exist on
inner layers.
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed.
Place bypass capacitor
close to power pins
图 18. Layout Recommendation
When configuring the OPA818 as a transimpedance amplifier additional care must be taken to minimize the
inductance between the avalanche photodiode (APD) and the amplifier. Always place the photodiode on the
same side of the PCB as the amplifier. Placing the amplifier and the APD on opposite sides of the PCB
increases the parasitic effects due to via inductance. APD packaging can be quite large which often requires the
APD to be placed further away from the amplifier than ideal. The added distance between the two device results
in increased inductance between the APD and op amp feedback network as shown in 公式 4. The added
inductance is detrimental to a decompensated amplifier's stability since it isolates the APD capacitance from the
noise gain transfer function. The noise gain is given by 公式 4. The added PCB trace inductance between the
feedback network increases the denominator in 公式 4 thereby reducing the noise gain and the phase margin. In
cases where a leaded APD in a TO can is used inductance should be further minimized by cutting the leads of
the TO can as short as possible. Also, edge mounting the photodiode on the PCB should be considered vs
through hole if the application allows.
The layout shown in 图 19 can be improved by following some of the guidelines shown in 图 20. The two key
rules to follow are:
•
Add an isolation resistor RISO as close as possible to the inverting input of the amplifier. Select the value of
RISO to be between 10 Ω and 20 Ω. The resistor dampens the potential resonance caused by the trace
inductance and the amplifiers internal capacitance.
•
Close the loop between the feedback elements (RF and CF) and RISO as close to the APD pins as possible.
This ensures a more balanced layout and reduces the inductive isolation between the APD and the feedback
18
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Layout Example (接下页)
network.
≈
’
÷
ZF
Noise Gain = 1+
∆
ZIN ◊
«
where
•
•
ZF is the total impedance of the feedback network
ZIN is the total impedance of the input network
(4)
VBIAS
VBIAS
APD
APD
Package
Package
PD
FB
1
2
8
7
6
5
VS+
PD
FB
1
2
8
7
6
5
VS+
CF
RF
OUT
RF
OUT
CF
Thermal
Pad
Close the loop close
to APD pins
Thermal
Pad
NC
INœ
NC
3
4
INœ
3
4
Trace inductance isolates
APD capacitance from the
amplifier noise gain
RISO
Place RISO close to INœ
VSœ
IN+
VSœ
IN+
图 19. Non-Ideal TIA Layout
图 20. Improved TIA Layout
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11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
20
版权 © 2019, Texas Instruments Incorporated
OPA818
www.ti.com.cn
ZHCSJO8 –MAY 2019
12.1 Package Option Addendum
12.1.1 Packaging Information
Package
Type
Package
Drawing
Package
Qty
Lead/Ball
Finish(3)
(1)
(2)
(4)
Orderable Device
Status
Pins
Eco Plan
MSL Peak Temp
Op Temp (°C)
Device Marking(5)(6)
XOPA818IDRGT
PREVIEW
WSON
DRG
8
250
TBD
Call TI
Call TI
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
版权 © 2019, Texas Instruments Incorporated
21
OPA818
ZHCSJO8 –MAY 2019
www.ti.com.cn
22
版权 © 2019, Texas Instruments Incorporated
OPA818
www.ti.com.cn
ZHCSJO8 –MAY 2019
版权 © 2019, Texas Instruments Incorporated
23
OPA818
ZHCSJO8 –MAY 2019
www.ti.com.cn
24
版权 © 2019, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2019 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA818IDRGR
OPA818IDRGT
ACTIVE
ACTIVE
SON
SON
DRG
DRG
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
OPA818
OPA818
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DRG0008B
WSON - 0.8 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.05 C
DIMENSION A
0.05
0.00
OPTION 01
OPTION 02
(0.1)
(0.2)
(DIM A) TYP
OPT 01 SHOWN
EXPOSED
THERMAL PAD
1.45 0.1
4
1
5
2X
1.5
2.4 0.1
8
6X 0.5
0.3
0.2
0.1
0.08
8X
0.6
0.4
PIN 1 ID
(OPTIONAL)
8X
C A B
C
4218886/A 01/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.45)
SYMM
8X (0.7)
1
8
8X (0.25)
(2.4)
(0.95)
5
6X (0.5)
4
(R0.05) TYP
(0.475)
(
0.2) VIA
(2.7)
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218886/A 01/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRG0008B
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.7)
1
8X (0.25)
SYMM
8
(0.635)
6X (0.5)
(1.07)
5
4
(R0.05) TYP
(1.47)
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218886/A 01/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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