OPA699ID [TI]

OPA699: 宽带、高增益限压放大器 | D | 8 | -40 to 85;


型号：	OPA699ID
厂家：	TEXAS INSTRUMENTS
描述：	OPA699: 宽带、高增益限压放大器 \| D \| 8 \| -40 to 85 放大器 PC 光电二极管
文件：	总33页 (文件大小：731K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

OPA699

www.ti.com

SBOS261D – NOVEMBER 2002 – REVISED DECEMBER 2008

Wideband, High Gain

VOLTAGE LIMITING AMPLIFIER

FEATURES

APPLICATIONS

● HIGH LINEARITY NEAR LIMITING

● FAST RECOVERY FROM OVERDRIVE: 1ns

● LIMITING VOLTAGE ACCURACY: ±10mV

● –3dB BANDWIDTH (G = +6): 260MHz

● GAIN BANDWIDTH PRODUCT: 1000MHz

● STABLE FOR G ≥ +4V/V

● TRANSIMPEDANCE WITH FAST

OVERDRIVE RECOVERY

● FAST LIMITING ADC INPUT DRIVER

● LOW PROP DELAY COMPARATOR

● NONLINEAR ANALOG SIGNAL

PROCESSING

● DIFFERENCE AMPLIFIER

● IF LIMITING AMPLIFIER

● OPA689 UPGRADE

● SLEW RATE: 1400V/µs

● ±5V AND +5V SUPPLY OPERATION

● LOW GAIN VERSION: OPA698

the signal channel. Implementing the limiting function at the

output, as opposed to the input, gives the specified limiting

accuracy for any gain, and allows the OPA699 to be used in

all standard op amp applications.

DESCRIPTION

The OPA699 is a wideband, voltage-feedback op amp that

offers bipolar output voltage limiting, and is stable for gains

≥ +4. Two buffered limiting voltages take control of the output

when it attempts to drive beyond these limits. This new

output limiting architecture holds the limiter offset error to

±10mV. The op amp operates linearly to within 20mV of the

limits.

Nonlinear analog signal processing circuits will benefit from

the OPA699 sharp transition from linear operation to output

limiting. The quick recovery time supports high-speed applica-

tions.

The OPA699 is available in an industry-standard pinout in an

SO-8 package. For lower gain applications requiring output

limiting with fast recovery, consider the OPA698.

The combination of narrow nonlinear range and low limiting

offset allows the limiting voltages to be set within 100mV of

the desired linear output range. A fast 1ns recovery from

limiting ensures that overdrive signals will be transparent to

+5V

V_H

OPA699

V_OUT

V_OUT= –2V_IN

V_L

–5V

R_F

750Ω

R_G

374Ω

V_IN

C_S

C_F

18pF

4pF

Low Gain, Improved SFDR Amplifier with Output Limiting

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

Supply Voltage ................................................................................. ±6.5V

Internal Power Dissipation........................... See Thermal Characteristics

Input Voltage Range............................................................................ ±V_S

Differential Input Voltage ..................................................................... ±V_S

Limiter Voltage Range ........................................................... ±(V_S– 0.7V)

Storage Temperature Range: D.....................................–65°C to +125°C

Lead Temperature (SO-8, soldering, 3s) ...................................... +260°C

Junction Temperature .................................................................... +150°C

ESD Resistance: HBM .................................................................... 2000V

MM ........................................................................ 200V

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may be

more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

CDM ................................................................... 1000V

NOTE: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may degrade

device reliability.

RELATED PRODUCTS

SINGLES DUALS

DESCRIPTION

Output Limiting

OPA698

Unity Gain Stable, Wideband

Voltage Feedback OPA690 OPA2690 High Slew, Unity Gain Stable

PACKAGE/ORDERING INFORMATION⁽¹⁾

SPECIFIED

PACKAGE

DESIGNATOR

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE-LEAD

OPA699

SO-8

–40°C to +85°C

OPA699ID

Rails, 100

OPA699IDR

Tape and Reel, 2500

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI website

at www.ti.com.

PIN CONFIGURATION

Top View

Inverting Input

Noninverting Input

–V_S

V_H

+V_S

Output

V_L

NC = No Connection

OPA699

SBOS261D

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= ±5V

Boldface limits are tested at +25°C.

G = +6, R_F= 750Ω, R_L= 500Ω, and V_H= –V_L= 2V, (see Figure 1 for AC performance only), unless otherwise noted.

OPA699ID

MIN/MAX OVER TEMPERATURE

TYP

C to

–40

C to

MIN/

TEST

MAX LEVEL⁽³⁾

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

70°C⁽²⁾

+85°C⁽²⁾

UNITS

AC PERFORMANCE (see Figure 1)

Small Signal Bandwidth (V_O< 0.5V_PP

)

G = +6

G = +12

G = –6

260

269

1000

7.5

220

215

210

MHz

min

typ

min

typ

min

Gain Bandwidth Product (G ≥ +20)

Gain Peaking

0.1dB Gain Flatness Bandwidth

Large-Signal Bandwidth

Step Response

V_O< 0.5V_PP, G = +6

V_O< 0.5V_PP, G = +4

V_O< 0.5V_PP

V_O= 4V_PP

820

190

800

180

750

170

290

MHz

Slew Rate

4V Step

0.5V Step

2V Step

1400

1.6

1300

1.65

1200

1.8

1100

V/µs

min

max

typ

min

typ

Rise-and-Fall Time

Settling Time: 0.05%

Spurious-Free Dynamic Range, Even

Odd

f = 5MHz, V_O= 2V_PP

NTSC, PAL, R_L= 500Ω

Differential Gain

0.012

0.008

Differential Phase

Input Noise Density

Voltage Noise

typ

f ≥ 1MHz

4.1

2.0

4.6

2.5

5.2

2.7

5.5

2.9

nV/√Hz

pA/√Hz

max

Current Noise

DC PERFORMANCE (V_CM= 0V)

Open-Loop Voltage Gain (A_OL

Input Offset Voltage

Average Drift

Input Bias Current⁽⁴⁾

Average Drift

)

V_O= ±0.5V

±1.5

—

±5.0

±6

±7

±20

±12

±20

±3

µV/°C

µA

nA/°C

µA

nA/°C

min

max

±15

±11

±15

±2.5

±10

±2

Input Offset Current

Average Drift

±0.3

—

±10

INPUT

Common-Mode Rejection Ratio

Common-Mode Input Range⁽⁵⁾

Input Impedance

Input Referred, V_CM= ±0.5V

±3.3

±3.2

±3.1

min

Differential-Mode

Common-Mode

0.32 || 1

3.5 || 1

MΩ || pF

typ

OUTPUT

V_H= –V_L= 4.3V

R_L≥ 500Ω

Output Voltage Range

Current Output, Sourcing

Sinking

±4.1

+120

–120

0.8

±3.9

+90

–90

±3.9

+85

–85

±3.8

+80

–80

min

typ

Ω

Closed-Loop Output Impedance

G = +4, f < 100kHz

POWER SUPPLY

Operating Voltage, Specified

Maximum

Quiescent Current, Maximum

Minimum

±5

—

15.5

typ

max

min

±6

15.9

15.2

±6

16.3

14.9

±6

16.6

14.6

V_S= ±5V

Power-Supply Rejection Ratio

+PSRR (Input Referred)

+V_S= 4.5V to 5.5V

min

NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambient

temperature + 23°C at high temperature limit Test Level A specifications.

(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperature

tested specifications.

(3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation. (C) Typical value for information only.

(4) Current is considered positive out-of-node.

(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.

(6) I_VH(V_Hbias current) is positive, and I_VL(V_Lbias current) is negative, under these conditions. See Note 3 and Figures 1 and 12.

(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V_H(or V_L) when V_IN= 0.

OPA699

SBOS261D

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= ±5V (Cont.)

Boldface limits are tested at +25°C.

G = +6, R_F= 750Ω, R_L= 500Ω, V_H= –V_L= 2V, (Figure 1 for AC performance only), unless otherwise noted.

OPA699ID

TYP

MIN/MAX OVER TEMPERATURE

0°C to

70°C⁽²⁾

–40°C to

+85°C⁽²⁾

MIN/

TEST

MAX LEVEL⁽³⁾

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

UNITS

OUTPUT VOLTAGE LIMITERS

Output Voltage Limited Range

Default Limit Voltage, Upper

Lower

Minimum Limiter Separation (V_H– V_L)

Maximum Limit Voltage

Limiter Input Bias Current Magnitude⁽⁶⁾

Maximum

Pins 5 and 8

±3.8

+3.5

–3.5

400

—

typ

min

max

min

max

Limiter Pins Open

V_O= 0

+3.3

–3.3

400

+3.2

–3.2

400

+3.1

–3.1

400

±4.3

—

3.4 || 1

–60

µA

nA/°C

MΩ || pF

max

min

max

typ

Minimum

Average Drift

Limiter Input Impedance

Limiter Feedthrough⁽⁷⁾

DC Performance in Limit Mode

Limiter Offset Voltage

Op Amp Input Bias Current Shift⁽⁴⁾

AC Performance in Limit Mode

Limiter Small-Signal Bandwidth

Limiter Slew Rate⁽⁸⁾

f = 5MHz

V_IN= ±0.7V

(V_O– V_H) or (V_O– V_L)

Linear ↔ Limited Operation

typ

±10

±30

±35

±40

µA

max

typ

V_IN= ±0.7V, V_O< 0.02V_PP

600

125

MHz

V/µs

typ

Limited Step Response

Overshoot

Recovery Time

Linearity Guardband⁽⁹⁾

V_IN= 0V to ±0.7V Step

V_IN= ±0.7V to 0V Step

f = 5MHz, V_O= 2V_PP

250

typ

max

typ

1.9

2.1

THERMAL CHARACTERISTICS

Temperature Range

Thermal Resistance

Specification, I

Junction-to-Ambient

–40 to +85

°C

typ

SO-8

125

°C/W

NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambient

temperature +23°C at high temperature limit Test Level A specifications.

(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperature

tested specifications.

(3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation. (C) Typical value for information only.

(4) Current is considered positive out-of-node.

(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.

(6) I_VH(V_Hbias current) is positive, and I_VL(V_Lbias current) is negative, under these conditions. See Note 3 and Figures 1 and 12.

(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V_H(or V_L) when V_IN= 0.

(8) V_Hslew rate conditions are: V_IN= +0.7V, G = +6, V_L= –2V, V_H= step between 2V and 0V. V_Lslew rate conditions are similar.

(9) Linearity Guardband is defined for an output sinusoid (f = 1MHz, V_O= 2V_PP) centered between the limiter levels (V_Hand V_L). It is the difference

between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8).

OPA699

SBOS261D

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= +5V

Boldface limits are tested at +25°C.

G = +6, R_F= 750Ω, R_L= 500Ω tied to V_CM= +2.5V, V_L= V_CM–1.2V, and V_H= V_CM+1.2V, (see Figure 2 for AC performance only), unless otherwise noted.

OPA699ID

TYP

MIN/MAX OVER TEMPERATURE

C to

–40

C to

MIN/

TEST

MAX LEVEL⁽³⁾

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

70°C⁽²⁾

+85°C⁽²⁾

UNITS

AC PERFORMANCE (see Figure 2)

Small Signal Bandwidth (V_O< 0.5V_PP

)

G = +6

G = +12

G = –6

234

242

880

200

190

180

MHz

min

typ

min

typ

min

Gain Bandwidth Product (G ≥ +20)

Gain Peaking

0.1dB Gain Flatness Bandwidth

Large-Signal Bandwidth

Step Response

V_O< 0.5V_PP

V_O< 0.5V_PP, G = +4

V_O< 0.5V_PP, G = +6

V_O= 2V_PP

700

200

650

190

600

180

250

MHz

Slew Rate

2V Step

0.5V Step

2V Step

1050

1.75

850

1.8

800

1.9

700

2.1

V/µs

min

max

typ

min

Rise-and-Fall Time

Settling Time: 0.05%

Spurious-Free Dynamic Range, Even

Odd

f = 5MHz, V_O= 2V_PP

Input Noise

Voltage Noise Density

Current Noise Density

f ≥ 1MHz

4.2

2.1

4.6

2.6

5.2

2.8

5.6

3.0

nV/√Hz

pA/√Hz

max

DC PERFORMANCE

Open-Loop Voltage Gain (A_OL

Input Offset Voltage

Average Drift

Input Bias Current⁽⁴⁾

Average Drift

)

V_O= V_CM± 0.5V

±2

—

±0.4

—

±6

±7

±8

±14

±12

±25

±3

µV/°C

µA

nA/°C

µA

nA/°C

min

max

±14

±11

±25

±2.5

±15

±10

±2

Input Offset Current

Average Drift

±15

INPUT

Common-Mode Rejection Ratio

Common-Mode Input Range⁽⁵⁾

Input Impedance

Input Referred, V_CM±0.5V

_CM±0.7

_CM±0.6

MΩ || pF

min

typ

_CM±0.8 V_CM±0.7

Differential-Mode

Common-Mode

0.32 || 1

3.5 || 1

MΩ || pF

typ

OUTPUT

V_H= V_CM+ 1.8V, V_L= V_CM– 1.8V

R_L≥ 500Ω

Output Voltage Range

Current Output, Sourcing

Sinking

_CM±1.6 V_CM±1.4

_CM±1.4

+55

–55

_CM±1.3

+50

–50

min

typ

+70

–70

0.2

+60

–60

Ω

Closed-Loop Output Impedance

G = +4, f < 100kHz

POWER SUPPLY

Operating Voltage, Specified

Maximum

Quiescent Current, Maximum

Minimum

—

14.3

typ

max

min

+12

14.9

13.6

+12

15.1

13.4

+12

15.3

13.2

V_S= +5V

Power-Supply Rejection Ratio

+PSRR (Input Referred)

V_S= 4.5V to 5.5V

typ

NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambient

temperature +23°C at high temperature limit Test Level A specifications.

(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperature

tested specifications.

(3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation. (C) Typical value for information only.

(4) Current is considered positive out of node.

(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.

(6) I_VH(V_Hbias current) is negative, and I_VL(V_Lbias current) is positive, under these conditions. See Note 3 and Figures 2 and 12.

(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V_H(or V_L) when V_IN= 0.

(8)

V_Hslew rate conditions are: V_IN= V_CM+0.4V, G = +6, V_L= V_CM–1.2V, V_H= step between V_CM+1.2V and V_CM. V_Lslew rate conditions are similar.

(9) Linearity Guardband is defined for an output sinusoid (f = 5MHz, V_O= V_CM±1V_PP) centered between the limiter levels (V_Hand V_L). It is the

difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8).

OPA699

SBOS261D

www.ti.com

ELECTRICAL CHARACTERISTICS: V_S= +5V (Cont.)

Boldface limits are tested at +25°C.

G = +6, R_F= 750Ω, R_L= 500Ω tied to V_CM= +2.5V, V_L= V_CM–1.2V, and V_H= V_CM+1.2V, (see Figure 2 for AC performance only), unless otherwise noted.

OPA699ID

TYP

MIN/MAX OVER TEMPERATURE

C to

–40

C to

MIN/

TEST

MAX LEVEL⁽³⁾

PARAMETER

CONDITIONS

+25°C

+25°C⁽¹⁾

70°C⁽²⁾

+85°C⁽²⁾

UNITS

OUTPUT VOLTAGE LIMITERS

Maximum Limited Voltage

Minimum Limited Voltage

Default Limiter Voltage

Minimum Limiter Separation (V_H– V_L)

Maximum Limit Voltage

Limiter Input Bias Current Magnitude⁽⁶⁾

Limiter Input Impedance

Limiter Isolation⁽⁷⁾

+3.9

+1.1

µA

MΩ || pF

typ

min

max

typ

Limiter Pins Open

V_O= 2.5V

_CM±1.1 V_CM±0.9

400

—

–15

3.4 || 1

–60

_CM±0.8

400

_CM±0.7

400

_CM±1.8

V_CM±1.8

typ

f = 5MHz

DC Performance in Limit Mode

Limiter Voltage Accuracy

Op Amp Bias Current Shift⁽⁴⁾

AC Performance in Limit Mode

Limiter Small-Signal Bandwidth

Limiter Slew Rate⁽⁸⁾

V_IN= V_CM±0.4V

(V_O– V_H) or (V_O– V_L)

Linear ↔ Limited Operation

±15

±30

±35

±40

µA

max

typ

V_IN= ±0.4V, V_O< 0.02V_PP

450

100

MHz

V/µs

typ

Limited Step Response

Overshoot

Recovery Time

Linearity Guardband⁽⁹⁾

V_IN= V_CMto V_CM±0.4V Step

V_IN= V_CM±0.4V to V_CMStep

f = 5MHz, V_O= 2V_PP

typ

THERMAL CHARACTERISTICS

Temperature Range

Thermal Resistance

Specification, I

Junction-to-Ambient

–40 to +85

°C

typ

SO-8

125

°C/W

NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25°C Test Level A specifications. Junction temperature = ambient

temperature +23°C at high temperature limit Test Level A specifications.

(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +1°C at high temperature limit for over-temperature

tested specifications.

(3) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and

simulation. (C) Typical value for information only.

(4) Current is considered positive out of node.

(5) CMIR tested as < 3dB degradation from minimum CMRR at specified limits.

(6) I_VH(V_Hbias current) is negative, and I_VL(V_Lbias current) is positive, under these conditions. See Note 3 and Figures 2 and 12.

(7) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V_H(or V_L) when V_IN= 0.

(8)

V_Hslew rate conditions are: V_IN= V_CM+0.4V, G = +6, V_L= V_CM–1.2V, V_H= step between V_CM+1.2V and V_CM. V_Lslew rate conditions are similar.

(9) Linearity Guardband is defined for an output sinusoid (f = 5MHz, V_O= V_CM±1V_PP) centered between the limiter levels (V_Hand V_L). It is the

difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8).

OPA699

SBOS261D

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V

T_A= +25°C, G = +6, R_F= 750Ω, and R_L= 500Ω, V_H= –V_L= 2V, unless otherwise noted.

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

G = +4

G = +6

G = −4

V_O= 0.5V_PP

G = −6

−3

G = −12

−6

−3

−6

−9

−12

−15

G = +12

−9

−12

−15

−18

G = +20

See Figure 1

See Figure 3

10M

100M

Frequency (Hz)

10M

100M

Frequency (Hz)

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

V_O= 1V_PP

V_O= 2V_PP

G = +6

G = −6

V_O= 2V_PP

V_O= 4V_PP

V_O= 7V_PP

V_O= 4V_PP

V_O= 7V_PP

See Figure 1

See Figure 3

10M

100M

Frequency (Hz)

10M

100M

Frequency (Hz)

V_L—LIMITER SMALL-SIGNAL

V_H—LIMITER SMALL-SIGNAL

FREQUENCY RESPONSE

V_O= 0.02V_PP

0.02V_PP+ 2.0V_DC

Open

125Ω

0.7V_DC

V_H

–3

–6

–9

–3

–6

–9

V_O

OPA699

V_L

0.02V_PP+ 2.0V_DC

Open

750Ω

150Ω

750Ω

150Ω

10M

100M

Frequency (Hz)

10M

100M

Frequency (Hz)

OPA699

SBOS261D

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +6, R_F= 750Ω, and R_L= 500Ω, V_H= –V_L= 2V, unless otherwise noted.

LARGE-SIGNAL PULSE RESPONSE

SMALL-SIGNAL PULSE RESPONSE

V_O= 0.5V_PP

2.5

2.0

0.4

0.3

V_O= 4V_PP

V_H= –V_L= 2.5V

1.5

0.2

1.0

0.1

0.5

–0.5

–1.0

–1.5

–2.0

–2.5

–0.1

–0.2

–0.3

–0.4

See Figure 1

Time (5ns/div)

See Figure 1

Time (5ns/div)

V_L—LIMITED PULSE RESPONSE

G = +6

V_H—LIMITED PULSE RESPONSE

2.5

2.0

2.5

2.0

V_OUT

V_H= –2V

1.5

V_IN= 0 → 0.7V

1.0

V_IN

0.5

V_IN

−0.5

−1.0

−1.5

−2.0

−2.5

–0.5

–1.0

–1.5

–2.0

–2.5

G = +6

V_OUT

V_H= +2V

_IN= 0 → 0.7V

Time (5ns/div)

LIMITED OUTPUT RESPONSE

DETAIL OF LIMITED OUTPUT RESPONSE

2.5

2.0

2.10

2.05

2.00

1.95

1.90

1.85

1.80

1.75

1.70

1.65

1.60

G = +6

_H= 2V

V_L= −2V

1.5

V_OUT

1.0

0.5

V_IN

−0.5

−1.0

−1.5

−2.0

−2.5

V_OUT

Time (200ns/div)

Time (50ns/div)

OPA699

SBOS261D

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +6, R_F= 750Ω, and R_L= 500Ω, V_H= –V_L= 2V, unless otherwise noted.

HARMONIC DISTORTION

vs LOAD RESISTANCE

5MHz HARMONIC DISTORTION

vs SUPPLY VOLTAGE

–55

–60

–65

–70

–75

–80

–85

–90

–60

–65

–70

–75

–80

–85

–90

V_O= 2V_PP

R_L= 500Ω

2nd-Harmonic

V_O= 2V_PP

f = 5MHz

3rd-Harmonic

See Figure 1

3.0

See Figure 1

100

2.5

3.5

4.0

4.5

5.0

5.5

6.0

Load Resistance (Ω)

± Supply Voltage (V)

HARMONIC DISTORTION vs FREQUENCY

V_O= 2V_PP

HARMONIC DISTORTION vs OUTPUT VOLTAGE

R_L= 500Ω

_H= –V_L= V_OPP/2 + 0.5V

f = 5MHz

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

–105

–50

–55

–60

–65

–70

–75

–80

–85

–90

R_L= 500Ω

2nd-Harmonic

3rd-Harmonic

See Figure 1

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

Output Voltage (V_PP

0.5

)

Frequency (MHz)

HARMONIC DISTORTION vs INVERTING GAIN

V_O= 2V_PP

HARMONIC DISTORTION vs NONINVERTING GAIN

−55

−60

−65

−70

−75

−80

−85

−90

–55

–60

–65

–70

–75

–80

–85

–90

–95

V_O= 2V_PP

R_L= 500Ω

2nd-Harmonic

f = 5MHz

2nd-Harmonic

3rd-Harmonic

−4

−8

−12

Gain (V/V)

−16

−20

Gain (V/V)

OPA699

SBOS261D

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +6, R_F= 750Ω, and R_L= 500Ω, V_H= –V_L= 2V, unless otherwise noted.

2-TONE, 3RD-ORDER INTERMODULATION

INTERCEPT

HARMONIC DISTORTION NEAR LIMITING VOLTAGES

−40

−50

−60

−70

−80

−90

V_O= 0V_DC± 1V_P

f = 5MHz

G = +6V/V

R_L= 500Ω

Open

V_H

P_I

P_O

2nd-Harmonic

OPA699

500Ω

V_L

Open

3rd-Harmonic

750Ω

150Ω

0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0

± Limit Voltage (V)

Frequency (MHz)

RECOMMENDED R_Svs CAPACITIVE LOAD

FREQUENCY RESPONSE vs CAPACITIVE LOAD

C_L= Open

140

120

100

C_L= 10pF

C_L= 1000pF

V_O= 0.5V_PP

G = +6

C_L= 100pF

V_IN

R_S

OPA699

(1)

1kΩ

C_L

750Ω

150Ω

(1)

Note: (1) 1kΩ is optional.

100

1000

10M

100M

Capacitive Load (pF)

Frequency (Hz)

OPEN-LOOP GAIN AND PHASE

Gain

INPUT VOLTAGE AND CURRENT NOISE DENSITY

100

–30

V_O= 0.5V_PP

–60

–90

–120

–150

–180

–210

–240

Phase

Voltage Noise (4.1nV/√Hz)

Current Noise (2pA/√Hz)

–10

100

10k

100k

10M

10k

100k

10M

100M

Frequency (Hz)

OPA699

SBOS261D

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +6, R_F= 750Ω, and R_L= 500Ω, V_H= –V_L= 2V, unless otherwise noted.

LIMITED VOLTAGE RANGE vs TEMPERATURE

VOLTAGE RANGES vs TEMPERATURE

V_H= –V_L= 4.3V

4.0

3.9

3.8

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3.0

5.0

4.5

4.0

3.5

3.0

V_Hand V_Lleft open

Internal Default Limited Voltage

V_H

Output Voltage Range

V_L

Common-Mode Input Range

−50

−25

100

−50

−25

100

Ambient Temperature (°C)

SUPPLY AND OUTPUT CURRENTS

vs TEMPERATURE

LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE

100

Output Current, Sinking

Maximum Over Temperature

Minimum Over Temperature

Output Current, Sourcing

Supply Current

–25

–50

–75

–100

Limiter Headroom = +V_S– V_H

= V_L– (–V_S)

Current = I_VHor –I_VL

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Limiter Headroom (V)

–50

–25

100

Ambient Temperature (°C)

COMMON-MODE REJECTION RATIO AND

TYPICAL DRIFT OVER TEMPERATURE

POWER-SUPPLY REJECTION vs FREQUENCY

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

–PSRR

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

CMRR

+PSRR

Input Bias Current (I_B)

Input Offset Voltage (V_OS

)

Input Offset Current (I_OS

)

–0.5

−50

−25

100

10k

100k

10M

100M

Ambient Temperature (°C)

Frequency (Hz)

OPA699

SBOS261D

www.ti.com

TYPICAL CHARACTERISTICS: V_S= ±5V (Cont.)

T_A= +25°C, G = +6, R_F= 750Ω, and R_L= 500Ω, V_H= –V_L= 2V, unless otherwise noted.

CLOSED-LOOP OUTPUT IMPEDANCE

LIMITER FEEDTHROUGH

100

−45

−50

−55

−60

−65

−70

−75

−80

−85

−90

−95

G = +4

_O= 0.5V_PP

0.02V_PP+ 2V_DC

125Ω

V_H

V_O

OPA699

V_L

Open

0.1

0.01

750Ω

150Ω

10M

100M

Frequency (Hz)

100

Frequency (MHz)

CMRR and PSRR(±) vs TEMPERATURE

OUTPUT VOLTAGE AND CURRENT LIMITATIONS

100

V_H= –V_L= 4.3V

1W Internal

Power Limit

PSRR+

R_L= 25Ω

R_L= 50Ω

–1

–2

–3

–4

–5

PSRR–

R_L= 100Ω

CMRR

1W Internal

Power Limit

–400 –300 –200 –100

100

200

300

400

−50

−25

100

Output Current (mA)

Ambient Temperature (°C)

OPA699

SBOS261D

www.ti.com

TYPICAL CHARACTERISTICS: V_S= +5V

T_A= +25°C, G = +6, R_F= 750Ω, and R_L= 500Ω to V_CM= +2.5V, V_L= V_CM– 1.2V, V_H= V_CM+ 1.2V, unless otherwise noted.

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

V_O= 0.5V_PP

G = –4

G = –6

V_O= 0.5V_PP

G = +4

G = +6

–3

–6

–9

–12

–15

–3

–6

–9

–12

–15

G = –12

G = +20

G = +12

See Figure 3

See Figure 2

10M

100M

Frequency (Hz)

10M

100M

Frequency (Hz)

LARGE-SIGNAL FREQUENCY RESPONSE

SMALL-SIGNAL PULSE RESPONSE

0.4

0.3

V_O= 1V_PP

_LIM= V_CM

± 1.2V

G = +6

V_O= 3V_PP

_LIM= V_CM± 2.0V

0.2

0.1

V_O= 2V_PP

_LIM= V_CM

± 1.5V

–0.1

–0.2

–0.3

–0.4

V_LIM= V_H= −V_L

See Figure 2

0.1

10M

100M

Frequency (Hz)

Time (5ns/div)

LARGE-SIGNAL PULSE RESPONSE

V_Hand V_L—LIMITED PULSE RESPONSE

1.5

1.0

2.5

2.0

G = +6

V_OUT

1.5

1.0

0.5

V_IN

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

See Figure 2

Time (5ns/div)

Time (20ns/div)

OPA699

SBOS261D

www.ti.com

TYPICAL CHARACTERISTICS: V_S= +5V (Cont.)

T_A= +25°C, G = +6, R_F= 750Ω, and R_L= 500Ω to V_CM= +2.5V, V_L= V_CM– 1.2V, V_H= V_CM+ 1.2V, unless otherwise noted.

HARMONIC DISTORTION vs FREQUENCY

HARMONIC DISTORTION vs LOAD RESISTANCE

V_O= 2V_PP

–50

–55

–60

–65

–70

–75

–80

–85

–90

–50

–55

–60

–65

–70

–75

–80

V_O= 2V_PP

R_L= 500Ω

f = 5MHz

2nd-Harmonic

3rd-Harmonic

See Figure 2

100

0.5

Load Resistance (Ω)

Frequency (MHz)

2-TONE, 3RD-ORDER

INTERMODULATION INTERCEPT

HARMONIC DISTORTION vs OUTPUT VOLTAGE

2nd-Harmonic

–60

–65

–70

–75

–80

–85

Open

3rd-Harmonic

P_I

V_H

P_O

OPA699

500Ω

V_L

Open

R_L= 500Ω to V_S/2

f = 5MHz

750Ω

_H= V_CM+ V_OPP/2 + 0.5V

_L= V_CM+ V_OPP/2 + 0.5V

150Ω

See Figure 2

1.0

0.5

1.5

2.0

2.5

Output Voltage Swing (V_PP

)

Frequency (MHz)

LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE

Maximum Over Temperature

HARMONIC DISTORTION NEAR LIMITING VOLTAGES

100

–40

–45

–50

–55

–60

–65

–70

–75

–80

V_O= V_CM±1V_P

f = 5MHz

R_L= 500Ω

Minimum

Over Temperature

2nd-Harmonic

3rd-Harmonic

–25

–50

–75

–100

Limiter Headroom = +V_S– V_H

= V_L– (–V_S)

Current = I_VHor –I_VL

0.5

1.0

1.5

2.0

2.5

0.9

1.0

1.1

1.2

1.3

1.4 1.5

1.6

1.7

1.8

Limiter Headroom (V)

Limit Voltages - 2.5V

OPA699

SBOS261D

www.ti.com

supply consists of two capacitors: one electrolytic 2.2µF and

one ceramic 0.1µF. The power-supply bypass capacitors are

shown explicitly in Figures 1 and 2, but will be assumed in the

other figures. An additional 0.01µF power-supply decoupling

capacitor (not shown here) can be included between the

two power-supply pins. In practical PC board layouts, this

optional, added capacitor will typically improve the 2nd

harmonic distortion performance by 3dB to 6dB.

TYPICAL APPLICATIONS

WIDEBAND VOLTAGE LIMITING OPERATION

The OPA699 is a gain voltage of +4V/V, voltage-feedback

amplifier that combines features of a wideband, high slew

rate amplifier with output voltage limiters. Its output can

swing up to 1V from each rail and can deliver up to 120mA.

These capabilities make it an ideal interface to drive an ADC

while adding overdrive protection for the ADC inputs.

SINGLE-SUPPLY, NONINVERTING AMPLIFIER

Figure 1 shows the DC-coupled, gain of +6V/V, dual power-

supply circuit configuration used as the basis of the ±5V

Electrical Characteristics and Typical Characteristics. For

test purposes, the input impedance is set to 50Ω with a

resistor to ground and the output is set to 500Ω. Voltage

swings reported in the specifications are taken directly at the

input and output pins. For the circuit of Figure 1, the total

output load will be 500Ω || 900Ω = 321Ω. The voltage limiting

pins are set to ±2V through a voltage divider network be-

tween the +V_Sand ground for V_H, and between

–V_Sand ground for V_L. These limiter voltages are adequately

bypassed with a 0.1µF ceramic capacitor to ground. The

limiter voltages (V_Hand V_L) and the respective bias currents

(I_VHand I_VL) have the polarities shown. One additional

component is included in Figure 1. An additional resistor

(100Ω) is included in series with the noninverting input.

Combined with the 25Ω DC source resistance looking back

towards the signal generator, this gives an input bias current-

canceling resistance that matches the 125Ω source resis-

tance seen at the inverting input (see the DC accuracy and

offset control section). The power-supply bypass for each

Figure 2 shows an AC-coupled, noninverting gain amplifier

for single +5V supply operation. This circuit was used for AC

characterization of the OPA699, with a 50Ω source (which it

matches) and a 500Ω load. The mid-point reference on the

noninverting input is set by two 1.5kΩ resistors. This gives an

input bias current-canceling resistance that matches the

750Ω DC source resistance seen at the inverting input (see

the DC accuracy and offset control section). The power-

supply bypass for the supply consists of two capacitors: one

electrolytic 2.2µF and one ceramic 0.1µF. The power-supply

bypass capacitors are shown explicitly in Figures 1 and 2, but

will be assumed in the other figures. The limiter voltages (V_H

and V_L) and the respective bias currents (I_VHand I_VL) have

the polarities shown. These limiter voltages are adequately

bypassed with a 0.1µF ceramic capacitor to ground. Notice

that the single-supply circuit can use three resistors to set V_H

and V_L, where the dual-supply circuit usually uses four to

reference the limit voltages to ground. While this circuit

shows +5V operation, the same circuit may be used for

single supplies up to +12V.

3.01kΩ 1.91kΩ

+V_S= +5V

V_S= +5V

0.1µF

2.2µF

0.1µF

2.2µF

523Ω

V_H= +2V

0.1µF

100Ω

V_H= 3.7V

1.5kΩ

I_VH

V_IN

0.1µF

I_VH

976Ω

0.1µF

49.9Ω

V_IN

V_O

OPA699

53.6Ω

1.5kΩ

V_O

500Ω

I_VL

500Ω

OPA699

R_G

R_F

750Ω

150Ω

I_VL

R_F

750Ω

0.1µF

V_L= –2V

R_G

V_L= 1.3V

150Ω

523Ω

0.1µF

2.2µF

3.01kΩ 1.91kΩ

–V_S= –5V

FIGURE 1. DC-Coupled, Dual-Supply Amplifier.

FIGURE 2. AC-Coupled, Single-Supply Amplifier.

OPA699

SBOS261D

www.ti.com

WIDEBAND INVERTING OPERATION

Operating the OPA699 as an inverting amplifier has several

benefits and is particularly useful when a matched 50Ω

source and input impedance are required. Figure 3 shows

the inverting gain of –4V/V circuit used as the basis of the

inverting mode typical characteristics.

G = –15

G = +15

+5V

+2V

R_T

169Ω

V_H

0.1µF

OPA699

V_O

10M

100M

V_L

Frequency (Hz)

500Ω

–5V

–2V

FIGURE 4. G = +15 and –15 Frequency Response.

R_G

187Ω

R_F

50Ω Source

V_I

750Ω

LOW-GAIN COMPENSATION FOR IMPROVED SFDR

R_M

68.1Ω

Where a low gain is desired, and inverting operation is

acceptable, a new external compensation technique can be

used to retain the full slew rate and noise benefits of the

OPA699, while giving increased loop gain and the associ-

ated distortion improvements offered by a non-unity-gain

stable op amp. This technique shapes the loop gain for good

stability, while giving an easily controlled 2nd-order low-pass

frequency response. To set the compensation capacitors (C_S

and C_F), consider the half-circuit of Figure 5, where the 50Ω

source is used.

FIGURE 3. Inverting G = –4 Specifications and Test Circuit.

In the inverting case, only the feedback resistor appears as

part of the total output load in parallel with the actual load. For

a 500Ω load used in the typical characteristics, this gives a

total load of 329Ω in this inverting configuration. The gain

resistor is set to get the desired gain (in this case, 187Ω for

a gain of –4) while an additional input resistor (R_M) can be

used to set the total input impedance equal to the source, if

desired. In this case, R_M= 68.1Ω in parallel with the 187Ω

gain setting resistor gives a matched input impedance of

50Ω. This matching is only needed when the input needs to

be matched to a source impedance, as in the characteriza-

tion testing done using the circuit of Figure 3.

Considering only the noise gain for the circuit of Figure 5, the

low-frequency noise gain (N_G1) is set by the resistor ratio,

while the high-frequency noise gain (N_G2) is set by the

capacitor ratio. The capacitor values set both the transition

frequencies and the high-frequency noise gain. If the high-

frequency noise gain, determined by N_G2= 1 + C_S/C_F, is set

to a value greater than the recommended minimum stable

gain for the op amp, and the noise gain pole (set by 1/R_FC_F)

is placed correctly, a very well controlled 2nd-order low-pass

frequency response results.

For bias current-cancellation matching, the noninverting input

requires a 169Ω resistor to ground. The calculation for this

resistor includes a DC-coupled 50Ω source impedance along

with R_Gand R_M. Although this resistor will provide cancella-

tion for the bias current, it must be well-decoupled (0.1µF in

Figure 3) to filter the noise contribution of the resistor and the

input current noise.

+5V

V_H

As the required R_Gresistor approaches 50Ω at higher gains,

the bandwidth for the circuit in Figure 3 will far exceed the

bandwidth at that same gain magnitude for the noninverting

circuit of Figure 1. This occurs due to the lower noise gain for

the circuit of Figure 3 when the 50Ω source impedance is

included in the analysis. For instance, at a signal gain of –15

(R_G= 50Ω, R_M= open, R_F= 750Ω) the noise gain for the

circuit of Figure 3 will be 1 + 750Ω/(50Ω + 50Ω) = 8.5 due to

the addition of the 50Ω source in the noise gain equation.

This approach gives considerably higher bandwidth than the

noninverting gain of +15. Using the 1GHz gain bandwidth

product for the OPA699, an inverting gain of –15 from a 50Ω

source to a 50Ω R_Gwill give 140MHz bandwidth, whereas

the noninverting gain of +8 will give 55MHz, as shown in the

measured results of Figure 4.

200Ω

V_O

OPA699

V_L

R_F

R_G

402Ω

V_I

C_S

13pF

C_F

2.8pF

–5V

FIGURE 5. Broadband, Low-Inverting Gain External

Compensation.

OPA699

SBOS261D

www.ti.com

To choose the values for both C_Sand C_F, two parameters and

only three equations need to be solved. The first parameter is

the target high-frequency noise gain (NG₂), which should be

greater than the minimum stable gain for the OPA699. Here,

a target of NG₂= 26 is used. The second parameter is the

desired low-frequency signal gain, which also sets the low-

frequency noise gain (NG₁). To simplify this discussion, we will

target a maximally flat 2nd-order low-pass Butterworth fre-

quency response (Q = 0.707). The signal gain shown in Figure

5 sets the low-frequency noise gain to NG₁= 1 + R_F/R_G(= 2

in this example). Then, using only these two gains and the

gain bandwidth product for the OPA699 (1000MHz), the key

frequency in the compensation is set by Equation1.

Finally, since C_Sand C_Fset the high-frequency noise gain,

determine C_Susing Equation 3 (solving for C_Sby using

NG₂= 6):

C_S= NG − 1C

(3)

(

)

which gives C_S= 15pF.

Both of these calculated values have been reduced slightly

in Figure 5 to account for parasitics. The resulting closed-

loop bandwidth is approximately equal to Equation 4.

(4)

f_–3dB

Z_O• GBP

For the values shown in Figure 5, f_–3dBis approximately

149MHz. This is less than that predicted by simply dividing

the Gain Bandwidth Product (GBP) product by NG₁. The

compensation network controls the bandwidth to a lower

value, while providing the full slew rate at the output and an

improved distortion performance due to increased loop gain

at frequencies below NG₁• Z_O.

GBP

NG²₁

NG₁

NG₂

NG₁

NG₂

Z_O

1−

− 1− 2

(1)

Physically, this Z_O(22.3MHz for the values shown above) is

set by 1/(2πR_F(C_F+ C_S)) and is the frequency at which the

rising portion of the noise gain would intersect the unity gain

if projected back to a 0dB gain. The actual zero in the noise

gain occurs at NG₁• Z_Oand the pole in the noise gain occurs

at NG₂• Z_O. That pole is physically set by 1/(R_FC_F). Since

GBP is expressed in Hz, multiply Z_Oby 2π and use to get C_F

by solving Equation 2.

LOW DISTORTION, LIMITED OUTPUT,

ADC INPUT DRIVER

Figure 6 shows a simple ADC driver that operates on a single

supply, and gives excellent distortion performance. The limit

voltages track the input range of the converter, completely

protecting against input overdrive. Note that the limiting

voltages have been set 100mV above/below the correspond-

ing reference voltage from the converter. This circuit also

implements an improved distortion for an inverting gain of

–2 using external compensation.

C_F

= 3pF

(

)

(2)

2πR_FZ_ONG₂

V_S= +5V

562Ω

V_H= +3.6V

V_S= +5V

0.1µF

102Ω

1.4kΩ

+3.5V

V_S= +5V

REFT

RSEL

+V_S

0.1µF

OPA699

24.9Ω

ADS822

10-Bit

40MSPS

10-Bit

Data

100pF

REFB

+1.5V

INT/EXT GND

1000pF

750Ω

374Ω

V_IN

102Ω

18pF

4pF

V_L= +1.4V

0.1µF

562Ω

FIGURE 6. Single Supply, Limiting ADC Input Driver.

OPA699

SBOS261D

www.ti.com

LIMITED OUTPUT, DIFFERENTIAL ADC INPUT DRIVER

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Figure 7 shows a differential ADC driver that takes advan-

tage of the OPA699 limiters to protect the input of the ADC.

Two OPA699s are used. The first one is an inverting configu-

ration at a gain of –2. The second one is in a noninverting

configuration at a gain of +2. Refer to the section, Low Gain

Compensation for Improved SFDR, for a discussion of stabil-

ity issues of the OPA699 operating at a gain less than 4.

Each amplifier is swinging 2V_PPproviding a 4V_PPdifferential

signal to drive the input of the ADC. Limiters have been set

100mV away from the magnitude of each amplifier maximum

signal to provide input protection for the ADC while maintain-

ing an acceptable distortion level.

Output

–0.5

–1.0

Input

Time (5ns/div)

PRECISION HALF WAVE RECTIFIER

FIGURE 9. 100MHz Sinewave Rectified.

Figure 8 shows a half wave rectifier with outstanding preci-

sion and speed. V_H(pin 8) will default to a 3.5 typically if left

open, while the negative limit is set to ground.

VERY HIGH-SPEED SCHMITT TRIGGER

Figure 10 shows a very high-speed Schmitt Trigger. The

output levels are precisely defined, and the switching time is

exceptional. The output voltage swings between V_Hand V_L.

The gain for the circuit in Figure 8 is set at +6. Figure 9 shows

input and output for ±0.5V 100MHz input.

+V_S= +5V

50Ω

R₂

Source

402Ω

75Ω

V_O= Open

V_IN

R₁

200Ω

+2V

V_O

OPA699

V_REF

R₃

V_H

V_L

200Ω

OPA699

V_OUT

150Ω

750Ω

V_IN

–2V

–V_S= –5V

FIGURE 10. Very High-Speed Schmitt Trigger.

FIGURE 8. Precision Half-Wave Rectifier.

+5V

+1.1V

OPA699

–1.1V

–5V

10pF

100Ω

1kΩ

24.9Ω 0.01µF

1kΩ

ADC

V_CM

+5V

4V_PP

+1.1V

V_IN= 200mV_PP

0.01µF

24.9Ω

OPA699

–5V

100Ω

10pF

–1.1V

900Ω

100Ω

FIGURE 7. Single to Differential AC-Coupled, High Gain Output Limited ADC Driver.

OPA699

SBOS261D

www.ti.com

The circuit operates as follows. When the input voltage is

less than V_HLthen the output is limiting at V_H. When the input

is greater than V_HH, then the output is limiting at V_L, with V_HL

and V_HHdefined as the following:

OPERATING SUGGESTIONS

THEORY OF OPERATION

The OPA699 is a voltage-feedback, gain of +4V/V stable op

amp. The output voltage is limited to a range set by the

voltage on the limiter pins (5 and 8). When the input tries to

overdrive the output, the limiters take control of the output

buffer. This action from the limiters avoids saturating any part

of the signal path, giving quick overdrive recovery and

excellent limiter accuracy at any signal gain. The limiters

have a very sharp transition from the linear region of opera-

tion to output limiting. This transition allows the limiter volt-

ages to be set very near (< 100mV) the desired signal range.

The distortion performance is also very good near the limiter

voltages.

R₁||R₂||R₃

R₁

R₁||R₂||R₃

R₂

V_{HL, HH}

× V_REF

× V_OUT

Due to the inverting function realized by the Schmitt Trigger,

V_HLcorresponds to V_OUT= V_H, and V_HHcorresponds to

V_OUT= V_L.

Figure 11 shows the Schmitt Trigger operating with V_REF

+5V. This gives us V_HH= 2.4V and V_HL= 1.6V. The propa-

gation delay for the OPA699 in a Schmitt Trigger configura-

tion is 4ns from high-to-low, and 4ns from low-to-high.

OUTPUT LIMITERS

The output voltage is linearly dependent on the input(s) when

it is between the limiter voltages V_H(pin 8) and V_L(pin 5).

When the output tries to exceed V_Hor V_L, the corresponding

limiter buffer takes control of the output voltage and holds it

at V_Hor V_L. Because the limiters act on the output, their

accuracy does not change with the gain. The transition from

the linear region of operation to output limiting is very

sharp—the desired output signal can safely come to within

30mV of V_Hor V_Lwith no onset of non-linearity. The limiter

voltages can be set to within 0.7V of the supplies (V_L≥ –V_S

+ 0.7V, V_H≤ +V_S– 0.7V). They must also be at least 400mV

apart (V_H– V_L≥ 0.4V). When pins 5 and 8 are left open, V_H

and V_Lgo to the default voltage limit; the minimum values are

given in the electrical specifications. Looking at Figure 12 for

the zero bias current case shows the expected range of

(V_S– default limit voltages) = headroom.

V_OUT

–1

V_IN

–2

–3

–4

Time (10ns/div)

FIGURE 11. Schmitt Trigger Time Domain Response for a

10MHz Sinewave.

DESIGN-IN TOOLS

DEMONSTRATION FIXTURE

100

A printed circuit board (PCB) is available to assist in the initial

evaluation of circuit performance using the OPA699. The

fixture is offered free of charge as an unpopulated PCB,

delivered with user's guide. The summary information for this

fixture is shown in Table I.

Maximum Over Temperature

Minimum Over Temperature

–25

ORDERING

NUMBER

LITERATURE

NUMBER

–50

PRODUCT

PACKAGE

Limiter Headroom = +V_S– V_H

= V_L– (–V_S)

Current = I_VHor –I_VL

OPA699ID

SO-8

DEM-OPA-SO-1A

SBOU009

–75

–100

TABLE I. Demonstration Fixture.

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Limiter Headroom (V)

The demonstration fixture can be requested at the Texas

Instruments web site (www.ti.com) through the OPA699

product folder.

FIGURE 12. Limiter Bias Current vs Bias Voltage.

OPA699

SBOS261D

www.ti.com

When the limiter voltages are more than 2.1V from the

supplies (V_L≥ –V_S+ 2.1V or V_H≤ +V_S– 2.1V), you can use

simple resistor dividers to set V_Hand V_L(see Figure 1). Make

sure to include the limiter input bias currents (Figure 8) in the

calculations (that is, I_VL= 50µA into pin 5, and I_VH= +50µA

out of pin 8). For good limiter voltage accuracy, run a

minimum 1mA quiescent bias current through these resis-

tors. When the limiter voltages need to be within 2.1V of the

supplies (V_L≤ –V_S+ 2.1V or V_H≥ +V_S– 2.1V), consider using

low impedance buffers to set V_Hand V_Lto minimize errors

due to bias current uncertainty. This condition will typically be

the case for single-supply operation (V_S= +5V). Figure 2

runs 2.5mA through the resistive divider that sets V_Hand V_L.

This limits errors due to I_VHand I_VL< ±1% of the target limit

voltages. The limiters’ DC accuracy depends on attention to

detail. The two dominant error sources can be improved as

follows:

OUTPUT DRIVE

The OPA699 has been optimized to drive 500Ω loads, such

as ADCs. It still performs very well driving 100Ω loads; the

specifications are shown for the 500Ω load. This makes the

OPA699 an ideal choice for a wide range of high-frequency

applications.

Many high-speed applications, such as driving ADCs, require

op amps with low output impedance. As shown in the typical

performance curve Output Impedance vs Frequency, the

OPA699 maintains very low closed-loop output impedance

over frequency. Closed-loop output impedance increases

with frequency, since loop gain decreases with frequency.

THERMAL CONSIDERATIONS

The OPA699 will not require heat sinking under most oper-

ating conditions. Maximum desired junction temperature will

set a maximum allowed internal power dissipation as de-

scribed below. In no case should the maximum junction

temperature be allowed to exceed 150°C.

• Power supplies, when used to drive resistive dividers that

set V_Hand V_L, can contribute large errors (for example,

±5%). Using a more accurate source, and bypassing pins

5 and 8 with good capacitors, will improve limiter PSRR.

The total internal power dissipation (P_D) is the sum of

quiescent power (P_DQ) and the additional power dissipated in

the output stage (P_DL) while delivering load power. P_DQis

simply the specified no-load supply current times the total

supply voltage across the part. P_DLdepends on the required

output signals and loads. For a grounded resistive load, and

equal bipolar supplies, it is at maximum when the output is

• The resistor tolerances in the resistive divider can also

dominate. Use 1% resistors.

Other error sources also contribute, but should have little

impact on the limiters’ DC accuracy:

• Reduce offsets caused by the Limiter Input Bias Currents.

Select the resistors in the resistive divider(s) as described

above.

at 1/2 either supply voltage. In this condition, P_DL= V_S/(4R_L)

where R_Lincludes the feedback network loading. Note that it

is the power in the output stage, and not in the load, that

determines internal power dissipation.

• Consider the signal path DC errors as contributing to

uncertainty in the useable output swing.

• The limiter offset voltage only slightly degrades limiter

accuracy. Figure 13 shows how the limiters affect distor-

tion performance. Virtually no degradation in linearity is

observed for output voltage swinging right up to the limiter

voltages. In this plot a fixed ±1V output swing is driven

while the limiter voltages are reduced symmetrically. Until

the limiters are reduced to ±1.1V, little distortion degrada-

tion is observed.

The operating junction temperature is: T_J= T_A+ P_Dx θ_JA,

where T_Ais the ambient temperature. For example, the

maximum T_Jfor a OPA699ID with G = +6, R_F= 750Ω,

R_L= 500Ω, and ±V_S= ±5V at the maximum T_A= +85°C is

calculated as:

P_DQ= 10V × 15.5mA = 155mW

(

)

(

)

P_DL

= 19.4mW

4 × 500Ω || 900Ω

(

)

P_D= 155mW + 19.4mW = 174.4mW

−40

V_O= 0V_DC± 1V_P

f = 5MHz

T_J= 85°C + 174.4mW ×125°C / W = 107°C

−50

−60

−70

−80

−90

_L= 500Ω

This would be the maximum T_Jfrom V_O= ±2.5V_DC. Most

applications will be at a lower output stage power and have

a lower T_J.

2nd-Harmonic

CAPACITIVE LOADS

3rd-Harmonic

Capacitive loads, such as the input to ADCs, will decrease

the amplifier phase margin, which may cause high-frequency

peaking or oscillations. Capacitive loads ≥ 2pF should be

isolated by connecting a small resistor in series with the

output, as shown in Figure 14. Increasing the gain from +2

will improve the capacitive drive capabilities due to increased

phase margin.

0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0

± Limit Voltage (V)

FIGURE 13. Harmonic Distortion Near Limit Voltages.

OPA699

SBOS261D

www.ti.com

The pulse settling characteristics, when recovering from

overdrive, are extremely good as shown in the typical char-

acteristics.

R_G

R_F

DISTORTION

R_S

The OPA699 distortion performance is specified for a 500Ω

load, such as an ADC. Driving loads with smaller resistance

will increase the distortion, as illustrated in Figure 15. Re-

member to include the feedback network in the load resis-

tance calculations.

V_O

OPA699

R_L

C_L

R_T

R_Lis optional

–55

2nd-Harmonic

V_O= 2V_PP

–60

–65

–70

–75

–80

–85

–90

f = 5MHz

FIGURE 14. Driving Capacitive Loads.

In general, capacitive loads should be minimized for optimum

high-frequency performance. The capacitance of coax cable

(29pF/ft for RG-58) will not load the amplifier when the

coaxial cable, or transmission line, is terminated in its char-

acteristic impedance.

3rd-Harmonic

See Figure 1

FREQUENCY RESPONSE COMPENSATION

100

The OPA699 is internally compensated to be unity-gain

stable, and has a nominal phase margin of 60° at a gain of

+6. Phase margin and peaking improve at higher gains.

Recall that an inverting gain of –5 is equivalent to a gain of

+6 for bandwidth purposes (that is, noise gain = 6). Standard

external compensation techniques work with this device.

For example, in the inverting configuration, the bandwidth

may be limited without modifying the inverting gain by placing

a series RC network to ground on the inverting node. This

has the effect of increasing the noise gain at high frequen-

cies, which limits the bandwidth.

Load Resistance (Ω)

FIGURE 15. 5MHz Harmonic Distortion vs Load Resistance.

NOISE PERFORMANCE

High slew rate, voltage-feedback op amps usually achieve

their slew rate at the expense of a higher input noise voltage.

The 4.1nV/√Hz input voltage noise for the OPA699, how-

ever, is much lower than comparable amplifiers. The input-

referred voltage noise, and the two input-referred current

noise terms, combine to give low output noise under a wide

variety of operating conditions. Figure 16 shows the op amp

noise analysis model with all the noise terms included. In this

model, all noise terms are taken to be noise voltage or

If a unity-gain stable amplifier is needed, the OPA698 is

recommended.

In applications where a large feedback resistor is required,

such as a photodiode transimpedance amplifier, the parasitic

capacitance from the inverting input to ground causes peak-

ing or oscillations. To compensate for this effect, connect a

small capacitor in parallel with the feedback resistor. The

bandwidth will be limited by the pole that the feedback

resistor and this capacitor create. In other high-gain applica-

tions, use a three-resistor Tee network to reduce the RC time

constants set by the parasitic capacitances.

current density terms in either nV/√Hz or pA/√Hz

E_NI

E_O

OPA699

R_S

I_BN

PULSE SETTLING TIME

E_RS

The OPA699 is capable of an extremely fast settling time in

response to a pulse input. Frequency response flatness and

phase linearity are needed to obtain the best settling times.

For capacitive loads, such as an ADC, use the recom-

mended R_Sin the typical performance curve Recommended

R_Svs Capacitive Load. Extremely fine-scale settling (0.01%)

requires close attention to ground return current in the supply

decoupling capacitors.

R_F

√4kTR_S

√4kTR_F

I_BI

R_G

4kT

R_G

4kT = 1.6E –20J

at 290°K

FIGURE 16. Op Amp Noise Analysis Model.

OPA699

SBOS261D

www.ti.com

The total output spot noise voltage can be computed as the

square root of the sum of all squared output noise voltage

contributors. Equation 5 shows the general form for the

output noise voltage using the terms shown in Figure 16.

through the feedback resistor. In selecting an offset trim

method, one key consideration is the impact on the desired

signal path frequency response. If the signal path is intended

to be noninverting, the offset control is best applied as an

inverting summing signal to avoid interaction with the signal

source. If the signal path is intended to be inverting, applying

the offset control to the noninverting input may be consid-

ered. However, the DC offset voltage on the summing

junction will set up a DC current back into the source which

must be considered. Applying an offset adjustment to the

inverting op amp input can change the noise gain and

frequency response flatness. For a DC-coupled inverting

amplifier, Figure 17 shows one example of an offset adjust-

ment technique that has minimal impact on the signal fre-

quency response. In this case, the DC offsetting current is

brought into the inverting input node through resistor values

that are much larger than the signal path resistors. This will

insure that the adjustment circuit has minimal effect on the

loop gain as well as the frequency response.

(5)

E_O

E_NI+ I_BNR_S+ 4kTR_SNG²+ I R

+ 4kTR_FNG

(

)

(

)

Dividing this expression by the noise gain (NG = (1+R_F/R_G))

will give the equivalent input-referred spot noise voltage at

the noninverting input, as shown in Equation 6.

(6)

I_BIR_F

4kTR_F

E_N

E_NI+ I_BNR_S+ 4kTR_S

(

)

Evaluating these two equations for the OPA699 circuit and

component values (see Figure 1) will give a total output spot

noise voltage of 27.4nV/√Hz and a total equivalent input spot

noise voltage of 4.6nV/√Hz. This total input-referred spot

noise voltage is only slightly higher than the 4.1nV/√Hz

specification for the op amp voltage noise alone. This will be

the case as long as the impedances appearing at each

op amp input are limited to a maximum value of 300Ω.

Keeping both (R_F|| R_G) and the noninverting input source

impedance less than 300Ω will satisfy both noise and

frequency response flatness considerations. Since the resis-

tor-induced noise is negligible, additional capacitive decoupling

across the bias current cancellation resistor (R_T) for the

inverting op amp configuration of Figure 3 is not required, but

is still desirable.

+5V

Supply Decoupling

Not Shown

V_O

OPA699

0.1µF

328Ω

–5V

R_G

R_F

+5V

150Ω

750Ω

V_I

5kΩ

±200mV Output Adjustment

20kΩ

10kΩ

DC ACCURACY AND OFFSET CONTROL

0.1µF

R_F

^O= –

V_I

= –5

The balanced input stage of a wideband voltage feedback op

amp allows good output DC accuracy in a large variety of

applications. The power-supply current trim for the OPA699

gives even tighter control than comparable products. Al-

though the high-speed input stage does require relatively

high input bias current (typically 3µA at each input terminal),

the close matching between them may be used to reduce the

output DC error caused by this current. The total output offset

voltage may be considerably reduced by matching the DC

source resistances appearing at the two inputs. This reduces

the output DC error due to the input bias currents to the offset

current times the feedback resistor. Evaluating the configura-

tion of Figure 1, using worst-case +25°C input offset voltage

and current specifications, gives a worst-case output offset

voltage, with NG = noninverting signal gain, equal to:

R_G

–5V

FIGURE 17. DC-Coupled, Inverting Gain of –5, with Offset

Adjustment.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with the high-frequency

OPA699 requires careful attention to layout design and

component selection. Recommended PCB layout techniques

and component selection criteria are:

a) Minimize parasitic capacitance to any AC ground for all

of the signal I/O pins. Open a window in the ground and

power planes around the signal I/O pins, and leave the

ground and power planes unbroken elsewhere.

±(NG • V_OS(MAX)) ± (R_F• I_OS(MAX)

= ±(2 • 5mV) ± (750Ω • 2.0µA)

= ±11.5mV

)

b) Provide a high quality power supply. Use linear regu-

lators, ground plane and power planes to provide power.

Place high frequency 0.1µF decoupling capacitors < 0.2"

away from each power-supply pin. Use wide, short traces to

connect to these capacitors to the ground and power planes.

Also use larger (2.2µF to 6.8µF) high-frequency decoupling

A fine-scale output offset null, or DC operating point adjust-

ment, is often required. Numerous techniques are available

for introducing DC offset control into an op amp circuit. Most

of these techniques eventually reduce to adding a DC current

OPA699

SBOS261D

www.ti.com

capacitors to bypass lower frequencies. They may be some-

what further from the device, and be shared among several

adjacent devices.

h) Do not use sockets for high-speed parts like the OPA699.

The additional lead length and pin-to-pin capacitance intro-

duced by the socket creates an extremely troublesome

parasitic network. Best results are obtained by soldering the

part onto the board.

c) Place external components close to the OPA699. This

minimizes inductance, ground loops, transmission line ef-

fects and propagation delay problems. Be extra careful with

the feedback (R_F), input and output resistors.

POWER SUPPLIES

d) Use high-frequency components to minimize parasitic

elements. Resistors should be a very low reactance type.

Surface-mount resistors work best and allow a tighter layout.

Metal film or carbon composition axially-leaded resistors can

also provide good performance when their leads are as short

as possible. Never use wirewound resistors for high-fre-

quency applications. Remember that most potentiometers

have large parasitic capacitances and inductances. Multi-

layer ceramic chip capacitors work best and take up little

space. Monolithic ceramic capacitors also work very well.

Use R_Ftype capacitors with low ESR and ESL. The large

power pin bypass capacitors (2.2µF to 6.8µF) should be

tantalum for better high frequency and pulse performance.

The OPA699 is nominally specified for operation using either

±5V supplies or a single +5V supply. The maximum specified

total supply voltage of 13V allows reasonable tolerances on

the supplies. Higher supply voltages can break down internal

junctions, possibly leading to catastrophic failure. Single-

supply operation is possible as long as common mode

voltage constraints are observed. The common-mode input

and output voltage specifications can be interpreted as a

required headroom to the supply voltage. Observing this

input and output headroom requirement will allow design of

non-standard or single-supply operation circuits. Figure 2

shows one approach to single-supply operation.

e) Choose low resistor values to minimize the time con-

stant set by the resistor and its parasitic parallel capacitance.

Good metal film or surface mount resistors have approxi-

mately 0.2pF parasitic parallel capacitance. For resistors

> 1.5kΩ, this adds a pole and/or zero below 500MHz. Make

sure that the output loading is not too heavy. The recom-

mended 750Ω feedback resistor is a good starting point in

most designs.

INPUT AND ESD PROTECTION

The OPA699 is built using a very high-speed complementary

bipolar process. The internal junction breakdown voltages

are relatively low for these very small geometry devices.

These breakdowns are reflected in the Absolute Maximum

Ratings table. All device pins are protected with internal ESD

protection diodes to the power supplies, as shown in Figure

18.

f) Use short direct traces to other wideband devices on

the board. Short traces act as a lumped capacitive load.

Wide traces (50 to 100 mils) should be used. Estimate the

total capacitive load at the output, and use the series isola-

tion resistor recommended in the typical performance curve,

Recommended R_Svs Capacitive Load. Parasitic loads < 2pF

may not need the isolation resistor.

These diodes provide moderate protection to input overdrive

voltages above the supplies as well. The protection diodes

can typically support 30mA continuous current. Where higher

currents are possible (e.g., in systems with ±15V supply parts

driving into the OPA699), current limiting series resistors

should be added into the two inputs. Keep these resistor

values as low as possible, since high values degrade both

noise performance and frequency response.

g) When long traces are necessary, use transmission line

design techniques (consult an ECL design handbook for

microstrip and stripline layout techniques). A 50Ω transmis-

sion line is not required on board—a higher characteristic

impedance will help reduce output loading. Use a matching

series resistor at the output of the op amp to drive a

transmission line, and a matched load resistor at the other

end to make the line appear as a resistor. If the 6dB of

attenuation that the matched load produces is not accept-

able, and the line is not too long, use the series resistor at the

source only. This will isolate the source from the reactive load

presented by the line, but the frequency response will be

degraded. Multiple destination devices are best handled as

separate transmission lines, each with its own series source

and shunt load terminations. Any parasitic impedances act-

ing on the terminating resistors will alter the transmission line

match, and can cause unwanted signal reflections and reac-

tive loading.

+V_CC

External

Internal

Circuitry

–V_CC

FIGURE 18. I/O Pin ESD Protection.

OPA699

SBOS261D

www.ti.com

Revision History

DATE

REVISION PAGE

SECTION

Absolute Maximum Ratings Changed minimum Storage Temperature Range from −40°C to −65°C.

Design-In Tools Board part number changed.

DESCRIPTION

12/08

3/06

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

OPA699

SBOS261D

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

14-Oct-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

OPA699ID

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

OPA

699

Samples

OPA699IDR

ACTIVE

2500 RoHS & Green

NIPDAU

OPA

699

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

14-Oct-2022

OTHER QUALIFIED VERSIONS OF OPA699 :

Military : OPA699M

•

NOTE: Qualified Version Definitions:

Military - QML certified for Military and Defense Applications

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

OPA699IDR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC

SPQ

Length (mm) Width (mm) Height (mm)

356.0 356.0 35.0

OPA699IDR

2500

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

SOIC

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

OPA699ID

506.6

3940

4.32

Pack Materials-Page 3

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

OPA699ID [TI]

相关型号：

OPA699IDR

OPA699IDR

OPA699IDRG4

OPA699M

OPA699MJD

OPA703

OPA703

OPA703NA

OPA703NA

OPA703NA/250

OPA703NA/250G4

OPA703NA/3K