OPA690IDG4 [TI]
具有禁用功能的宽带电压反馈运算放大器 | D | 8 | -40 to 85;
| 型号： | OPA690IDG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有禁用功能的宽带电压反馈运算放大器 | D | 8 | -40 to 85 放大器 光电二极管 运算放大器 放大器电路 |
| 文件： | 总24页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA690
O
P
A
6
9
0
O
P
A
6
9
0
SBOS223A—DECEMBER 2001 – REVISED JULY 2002
Wideband, Voltage Feedback
OPERATIONAL AMPLIFIER With Disable
FEATURES
APPLICATIONS
● FLEXIBLE SUPPLY RANGE:
● VIDEO LINE DRIVER
+5V to +12V Single Supply
● xDSL LINE DRIVER/RECEIVER
● HIGH SPEED IMAGING CHANNELS
● ADC BUFFERS
● PORTABLE INSTRUMENTS
● TRANSIMPEDANCE AMPLIFIERS
● ACTIVE FILTERS
±2.5V to ±5V Dual Supply
● UNITY-GAIN STABLE: 500MHz (G = 1)
● HIGH OUTPUT CURRENT: 190mA
● OUTPUT VOLTAGE SWING: ±4.0V
● HIGH SLEW RATE: 1800V/µs
● LOW SUPPLY CURRENT: 5.5mA
● LOW DISABLED CURRENT: 100µA
● OPA680 UPGRADE
● WIDEBAND +5V OPERATION: 220MHz (G = 2)
The OPA690’s low 5.5mA supply current is precisely trimmed
at 25°C. This trim, along with low temperature drift, gives
lower maximum supply current than competing products.
System power may be reduced further using the optional
disable control pin. Leaving this disable pin open, or holding
it HIGH, will operate the OPA690 normally. If pulled LOW,
the OPA690 supply current drops to less than 100µA while
the output goes to a high impedance state. This feature may
be used for power savings.
DESCRIPTION
The OPA690 represents a major step forward in unity-gain
stable, voltage feedback op amps. A new internal architec-
ture provides slew rate and full-power bandwidth previously
found only in wideband current feedback op amps. A new
output stage architecture delivers high currents with a
minimal headroom requirement. These combine to give
exceptional single-supply operation. Using a single +5V
supply, the OPA690 can deliver a 1V to 4V output swing
with over 150mA drive current and 150MHz bandwidth.
This combination of features makes the OPA690 an ideal
RGB line driver or single-supply Analog-to-Digital Con-
OPA690 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
Voltage Feedback
Current Feedback
Fixed Gain
OPA680
OPA691
OPA692
OPA2690
OPA2691
OPA2682
OPA3690
OPA3691
OPA3692
verter (ADC) input driver.
+5V
R1
3.3V
R1
2.5V
R4
20Ω
3
2
8
OPA690
4
THS1040
AIN+
C2
0.1µF
C1
R2
C3
20pF
VI
10-Bit
40MSPS
AIN–
R5
20Ω
C6
20pF
R3
C4
10µF
VREF = 1V
C5
0.1µF
Single-Supply ADC Driver
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation .................................... See Thermal Analysis
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ........................................................................... ±VS
Storage Temperature Range: D, DBV ........................... –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
ESD Resistance: HBM .................................................................... 2000V
MM ........................................................................ 200V
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
CDM .................................................................... 1500V
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
DESIGNATOR(1)
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
OPA690ID
SO-8
D
–40°C to +85°C
OPA690
OPA690ID
Rails, 100
"
"
"
"
"
OPA690IDR
Tape and Reel, 2500
OPA690IDBV
SOT23-6
DBV
–40°C to +85°C
OAEI
OPA690IDBVT
OPA690IDBVR
Tape and Reel, 250
Tape and Reel, 3000
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN CONFIGURATIONS
Top View
SOT23
Top View
SO
Output
1
2
3
6
5
4
+VS
–VS
DIS
NC
1
2
3
4
8
7
6
5
DIS
Noninverting Input
Inverting Input
Inverting Input
+VS
Noninverting Input
Output
NC
–VS
OAEI
Pin Orientation/Package Marking
OPA690
2
SBOS223A
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
RF = 402Ω, RL = 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted.
OPA690ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
0
°
C to
–40
°
C to
MIN/
TEST
MAX LEVEL(3)
PARAMETER
CONDITIONS
+25°C
+25°C(1)
70°C(2)
+85°C(2)
UNITS
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth
G = +1, VO = 0.5Vp-p, RF = 25Ω
G = +2, VO = 0.5Vp-p
G = +10, VO = 0.5Vp-p
G ≥ 10
500
220
30
300
30
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
typ
typ
typ
typ
typ
typ
typ
typ
typ
typ
typ
typ
C
C
C
C
C
C
C
C
C
C
C
C
165
20
200
160
19
190
150
18
180
Gain-Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
G = +2, VO < 0.5Vp-p
VO < 0.5Vp-p
G = +2, VO = 5Vp-p
G = +2, 4V Step
G = +2, VO = 0.5V Step
G = +2, VO = 5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
4
200
1800
1.4
2.8
12
1400
1200
900
Rise-and-Fall Time
ns
ns
ns
Settling Time to 0.02%
0.1%
8
Harmonic Distortion
2nd-Harmonic
G = +2, f = 5MHz, VO = 2Vp-p
RL = 100Ω
–68
–77
–70
–81
5.5
3.1
0.06
0.03
–64
–70
–68
–78
–62
–68
–66
–76
–60
–66
–64
–75
dBc
dBc
dBc
typ
typ
typ
typ
typ
typ
typ
typ
C
C
C
C
C
C
C
C
RL ≥ 500Ω
RL = 100Ω
RL ≥ 500Ω
3rd-Harmonic
dBc
Input Voltage Noise
Input Current Noise
Differential Gain
f > 1MHz
f > 1MHz
nV/√Hz
pA/√Hz
%
G = +2, NTSC, VO = 1.4Vp, RL = 150
G = +2, NTSC, VO = 1.4Vp, RL = 150
Differential Phase
deg
DC PERFORMANCE(4)
Open-Loop Voltage Gain (AOL
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Average Bias Current Drift (magnitude)
Input Offset Current
Average Offset Current Drift
)
VO = 0V, RL = 100Ω
VCM = 0V
69
±1.0
58
±4
56
±4.5
±10
±9
±20
±1.4
±7
54
±4.7
±10
±11
±40
±1.6
±9
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
VCM = 0V
V
CM = 0V
+3
±8
VCM = 0V
VCM = 0V
±0.1
±1.0
V
CM = 0V
INPUT
Common-Mode Input Range (CMIR)(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
±3.5
65
±3.4
60
±3.3
57
±3.2
56
V
dB
min
min
A
A
VCM = ±1V
CM = 0
V
190 || 0.6
3.2 || 0.9
kΩ || pF
MΩ || pF
typ
typ
C
C
VCM = 0
OUTPUT
Voltage Output Swing
No Load
100Ω Load
±4.0
±3.9
+190
–190
±250
0.04
±3.8
±3.7
+160
–160
±3.7
±3.6
+140
–140
±3.6
±3.3
+100
–100
V
V
mA
mA
mA
Ω
min
min
min
min
typ
A
A
A
A
C
C
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current Limit
Closed-Loop Output Impedance
V
O = 0
VO = 0
VO = 0
G = +2, f = 100kHz
typ
DISABLE (Disabled LOW)
Power-Down Supply Current (+VS)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
VDIS = 0
VIN = 1VDC
VIN = 1VDC
G = +2, 5MHz
–100
200
25
70
4
±50
±20
3.3
1.8
75
–200
–240
–260
µA
ns
ns
dB
pF
mV
mV
V
max
typ
typ
typ
typ
typ
typ
min
max
max
A
C
C
C
C
C
C
A
A
A
G = +2, RL = 150Ω, VIN = 0
G = +2, RL = 150Ω, VIN = 0
3.5
1.7
130
3.6
1.6
150
3.7
1.5
160
V
µA
Control Pin Input Bias Current (VDIS
)
VDIS = 0
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
Max Quiescent Current
Min Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
±5
V
V
mA
mA
dB
typ
max
max
min
min
C
A
A
A
A
±6.0
5.8
5.3
68
±6
6.0
5.1
66
±6
6.2
4.7
64
VS = ±5V
VS = ±5V
Input Referred
5.5
5.5
75
THERMAL CHARACTERISTICS
Specified Operating Range D, DBV Package
Thermal Resistance, θJA
–40 to +85
°C
typ
C
Junction-to-Ambient
D
SO-8
125
150
°C/W
°C/W
typ
typ
C
C
DBV SOT23-6
NOTES: (1) Junction Temperature = Ambient for 25°C specifications. (2) Junction Temperature = Ambient at low temperature limit: Junction Temperature = Ambient
+10°C at high temperature limit for over temperature specifications. (3)Test Levels: (A)100%tested at 25°C. Overtemperature limits by characterizationand simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. VCM is the input common-mode
voltage. (5) Tested < 3dB below minimum CMRR specification at ±CMIR limits.
OPA690
SBOS223A
3
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
RF = 402Ω, RL = 100Ω, and G = +2, (see Figure 2 for AC performance only), unless otherwise noted.
OPA690ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
0
°
C to
–40
°
C to
MIN/
TEST
MAX LEVEL(3)
PARAMETER
CONDITIONS
+25°C
+25°C(1)
70°C(2)
+85°C(2)
UNITS
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth
G = +1, VO < 0.5Vp-p, RF = ±25Ω
G = +2, VO < 0.5Vp-p
G = +10, VO < 0.5Vp-p
G ≥ 10
400
190
25
250
20
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
typ
typ
typ
typ
typ
typ
typ
typ
typ
typ
typ
typ
C
C
C
C
C
C
C
C
C
C
C
C
150
18
180
145
17
170
140
16
160
Gain-Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
G = +2, VO < 0.5Vp-p
V
O < 0.5Vp-p
5
G = +2, VO = 2Vp-p
G = +2, 2V Step
G = +2, VO = 0.5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
220
1000
1.6
2.0
12
700
670
550
Rise-and-Fall Time
ns
ns
ns
Settling Time to 0.02%
0.1%
8
Harmonic Distortion
2nd-Harmonic
G = +2, f = 5MHz, VO = 2Vp-p
R
R
L = 100Ω to VS/2
L ≥ 500Ω to VS/2
–65
–75
–68
–77
5.6
3.2
0.06
0.02
–60
–70
–64
–73
–59
–68
–62
–71
–56
–66
–60
–70
dBc
dBc
dBc
typ
typ
typ
typ
typ
typ
typ
typ
C
C
C
C
C
C
C
C
3rd-Harmonic
RL = 100Ω to VS/2
RL ≥ 500Ω to VS/2
dBc
Input Voltage Noise
Input Current Noise
Differential Gain
f > 1MHz
f > 1MHz
nV/√Hz
pA/√Hz
%
G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS /2
G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS /2
Differential Phase
deg
DC PERFORMANCE(4)
Open-Loop Voltage Gain (AOL
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Average Bias Current Drift (magnitude)
Input Offset Current
Average Offset Current Drift
)
VO = 2.5V, RL = 100Ω to 2.5V
VCM = 2.5V
63
±1.0
56
±4
54
±4.3
±10
±9
±20
±1.4
±7
52
±4.7
±10
±11
±40
±1.6
±9
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
VCM = 2.5V
VCM = 2.5V
+3
±8
±1
VCM = 2.5V
VCM = 2.5V
±0.3
VCM = 2.5V
INPUT
Least Positive Input Voltage(5)
Most Positive Input Voltage(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
1.5
3.5
63
1.6
3.4
58
1.7
3.3
56
1.8
3.2
54
V
V
dB
max
min
min
A
A
A
V
CM = 2.5V ±0.5V
Differential-Mode
Common-Mode
VCM = 2.5V
92 || 1.4
2.2 || 1.5
kΩ || pF
MΩ || pF
typ
typ
C
C
VCM = 2.5V
OUTPUT
Most Positive Output Voltage
No Load
L = 100Ω to 2.5V
No Load
RL = 100Ω to 2.5V
4
3.9
1
1.1
+160
–160
±250
0.04
3.8
3.7
1.2
1.3
+120
–120
3.6
3.5
1.4
1.5
+100
–100
3.5
3.4
1.5
1.7
+80
–80
V
V
V
min
min
min
max
max
min
typ
A
A
A
A
A
A
C
C
R
Least Positive Output Voltage
V
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current
mA
mA
mA
Ω
Closed-Loop Output Impedance
G = +2, f = 100kHz
typ
DISABLE (Disable LOW)
Power-Down Supply Current (+VS)
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (VDIS
VDIS = 0
G = +2, 5MHz
–100
65
4
±50
±20
3.3
1.8
75
–200
–240
–260
µA
dB
pF
mV
mV
V
max
typ
typ
typ
typ
min
max
typ
A
C
C
C
C
A
A
C
G = +2, RL = 150Ω, VIN = VS /2
G = +2, RL = 150Ω, VIN = VS /2
3.5
1.7
130
3.6
1.6
150
3.7
1.5
160
V
µA
)
VDIS = 0
POWER SUPPLY
Specified Single-Supply Operating Voltage
Maximum Single-Supply Operating Voltage
Max Quiescent Current
Min Quiescent Current
Power-Supply Rejection Ratio (+PSRR)
5
V
V
mA
mA
dB
typ
max
max
min
typ
C
B
A
A
C
12
5.2
4.7
12
5.4
4.4
12
5.6
4.0
VS = +5V
VS = +5V
Input Referred
4.9
4.9
72
TEMPERATURE RANGE
Specification: D, DBV
–40 to +85
°C
typ
C
Thermal Resistance, θJA
Junction-to-Ambient
D
SO-8
125
150
°C/W
°C/W
typ
typ
C
C
DBV SOT23-6
NOTES: (1) Junction Temperature = Ambient for 25°C tested specifications. (2) Junction Temperature = Ambient at low temperature limit: Junction Temperature =
Ambient +10°C at high temperature limit for over temperature tested specifications. (3) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization
and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. VCM is the input
common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ±CMIR limits.
OPA690
4
SBOS223A
www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
LARGE-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
VO = 0.5Vp-p
6
3
9
6
G = +1
F = 25Ω
R
0
VO = 2Vp-p
VO = 1Vp-p
G = 2
G = 5
3
–3
–6
–9
–12
–15
0
G = 10
VO = 4Vp-p
VO = 7Vp-p
–3
–6
0.5
1
10
Frequency (MHz)
100
500
0.7
10
Frequency (MHz)
100
700
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
400
300
+4
G = +2
O = 0.5Vp-p
G = +2
O = 5Vp-p
+3
+2
+1
0
V
V
200
100
0
–100
–200
–300
–400
–1
–2
–3
–4
Time (5ns/div)
Time (5ns/div)
COMPOSITE VIDEO dG/dP
DISABLE FEEDTHROUGH vs FREQUENCY
VDIS = 0
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
0.2
0.175
0.15
0.125
0.1
+5V
No Pull-Down
With 1.3kΩ Pull-Down
Video In
75Ω
OPA690
Optional
1.3kΩ
Pull-Down
402Ω
dG
402Ω
dG
–5V
dP
0.075
0.05
0.025
0
dP
Reverse
Forward
1M
1
2
3
4
100k
10M
100M
Number of 150Ω Loads
Frequency (Hz)
OPA690
SBOS223A
5
www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
5MHz HARMONIC DISTORTION
vs SUPPLY VOLTAGE
HARMONIC DISTORTION vs LOAD RESISTANCE
O = 2Vp-p
–60
–65
–70
–75
–80
–85
–90
–60
–65
–70
–75
–80
VO = 2Vp-p
RL = 100Ω
f = 5MHz
V
f = 5MHz
2nd-Harmonic
3rd-Harmonic
2nd-Harmonic
3rd-Harmonic
100
1000
2
2.5
3
3.5
4
4.5
5
5.5
6
Load Resistance (Ω)
Supply Voltage (±VS)
HARMONIC DISTORTION vs FREQUENCY
VO = 2Vp-p
HARMONIC DISTORTION vs OUTPUT VOLTAGE
–40
–50
–60
–70
–80
–90
–100
–60
–65
–70
–75
–80
RL = 100Ω
f = 5MHz
RL = 100Ω
2nd-Harmonic
3rd-Harmonic
2nd-Harmonic
3rd-Harmonic
0.1
1
10
20
0.1
1
5
Frequency (MHz)
Output Voltage Swing (Vp-p)
HARMONIC DISTORTION vs NONINVERTING GAIN
HARMONIC DISTORTION vs INVERTING GAIN
–40
–40
–50
–60
–70
–80
VO = 2Vp-p
RL = 100Ω
VO = 2Vp-p
RL = 100Ω
f = 5MHz
RF = 1kΩ
–50 f = 5MHz
Figure1
–60
2nd-Harmonic
2nd-Harmonic
3rd-Harmonic
3rd-Harmonic
–70
–80
–90
1
10
20
1
10
20
Gain (V/V)
Inverting Gain (V/V)
OPA690
6
SBOS223A
www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
INPUT VOLTAGE AND CURRENT NOISE DENSITY
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
100
10
1
50MHz
20MHz
Voltage Noise 5.5nV/√Hz
Current Noise 3.1pA/√Hz
10MHz
Load Power at Matched 50Ω Load,
see Figure 1
–8
–6
–4
–2
0
2
4
6
8
10
100
1k
10k
100k
1M
10M
Single-Tone Load Power (dBm)
Frequency (Hz)
FREQUENCY RESPONSE vs CAPACITIVE LOAD
G = +2
RECOMMENDED RS vs CAPACITIVE LOAD
9
6
80
70
60
50
40
30
20
10
0
CL = 10pF
CL = 100pF
3
CL = 22pF
CL = 47pF
0
VIN
–3
–6
–9
RS
VOUT
OPA690
1kΩ
CL
402Ω
402Ω
1kΩ is optional.
0
20
40
60
80 100 120 140 160 180 200
10
100
1000
Frequency (20MHz/div)
Capacitive Load (pF)
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
VDIS
DISABLE/ENABLE GLITCH
VDIS
6
6
4
2
0
4
2
0
2.0
1.6
1.2
0.8
0.4
0
30
20
Output Voltage
Each Channel
10
Output Voltage
Vi = 0V
SO-14
Package
Only
0
G = +2
–10
–20
–30
V
IN = +1V
Time (50ns/div)
Time (20ns/div)
OPA690
SBOS223A
7
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TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
TYPICAL DC DRIFT OVER TEMPERATURE
5
4
2
1.5
1
20
10
0
Output Current Limited
1W Internal
Power Limit
)
Input Bias Current (IB
3
2
0.5
0
1
Input Offset Current (IOS
)
0
25Ω
Load Line
50Ω Load Line
–1
–2
–3
–4
–5
–0.5
–1
–10
–20
100Ω Load Line
)
Input Offset Voltage (VOS
–1.5
–2
1W Internal
Power Limit
Output Current Limit
–300
–200
–100
0
100
200
300
–50
–25
0
25
50
75
100
125
IO (mA)
Ambient Temperature (°C)
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Sourcing Output Current
100
90
80
70
60
50
40
30
20
10
0
8
7
6
5
4
3
250
200
150
100
50
–PSRR
CMRR
Sinking Output Current
+PSRR
Quiescent Supply Current
0
10k
100k
1M
10M
100M
125
–50
–25
0
25
50
75
100
Frequency (MHz)
Ambient Temperature (°C)
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
OPEN-LOOP GAIN AND PHASE
Open-Loop Gain
10
1
70
60
50
40
30
20
10
0
0
+5V
–30
–60
–90
–120
–150
–180
OPA690
200Ω
Open-Loop Phase
ZO
–5V
402Ω
402Ω
0.1
0.01
–210
–240
–270
–10
–20
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
OPA690
8
SBOS223A
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TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, (see Figure 2 for AC performance only), unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
VO = 0.5Vp-p
LARGE-SIGNAL FREQUENCY RESPONSE
VO = 2Vp-p
6
3
9
6
G = +1
RF = 25Ω
G = +2
VO = 3Vp-p
VO = 1Vp-p
0
3
G = +5
–3
–6
–9
0
G = +10
–3
–6
0.7 1
10
Frequency (Hz)
100
700
0.5
1
10
Frequency (MHz)
100
500
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
G = +2
O = 0.5Vp-p
G = +2
VO = 2Vp-p
V
Time (5ns/div)
Time (5ns/div)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
CL = 10pF
50
45
40
35
30
25
20
15
10
5
9
6
CL = 100pF
3
0
CL = 22pF
+5V
–3
–6
–9
714Ω
714Ω
0.1µF
VIN
RS
714Ω
VOUT
OPA690
58Ω
CL
CL = 47pF
402Ω +5V
402Ω
0
1
10
100
1000
0
20
40
60
80 100 120 140 160 180 200
Capacitive Load (pF)
Frequency (20MHz/div)
OPA690
SBOS223A
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TYPICAL CHARACTERISTICS: VS = +5V (Cont.)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, (see Figure 2 for AC performance only), unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
VO = 2Vp-p
HARMONIC DISTORTION vs FREQUENCY
VO = 2Vp-p
–60
–65
–70
–75
–80
–40
–50
–60
–70
–80
–90
–100
RL = 100Ω to 2.5V
f = 5MHz
2nd-Harmonic
3rd-Harmonic
2nd-Harmonic
3rd-Harmonic
100
1000
0.1
1
10
20
Resistance (Ω)
Frequency (MHz)
2-TONE, 3RD-ORDER
HARMONIC DISTORTION vs OUTPUT VOLTAGE
INTERMODULATION SPURIOUS
–60
–65
–70
–75
–80
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
RL = 100Ω to 2.5V
f = 5MHz
50MHz
3rd-Harmonic
20MHz
2nd-Harmonic
10MHz
Load Power at Matched 50Ω Load, see Figure 2
–10 –8 –6 –4 –2
Single-Tone Load Power (dBm)
0.1
1
3
–14
–12
0
2
Output Voltage Swing (Vp-p)
OPA690
10
SBOS223A
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matches the 200Ω source resistance seen at the inverting
input (see the DC Accuracy and Offset Control section). In
addition to the usual power-supply decoupling capacitors to
ground, a 0.1µF capacitor is included between the two power-
supply pins. In practical PC board layouts, this optional-added
capacitor will typically improve the 2nd-harmonic distortion
performance by 3dB to 6dB.
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE FEEDBACK OPERATION
The OPA690 provides an exceptional combination of high
output power capability with a wideband, unity-gain stable
voltage feedback op amp using a new high slew rate input
stage. Typical differential input stages used for voltage feed-
back op amps are designed to steer a fixed-bias current to
the compensation capacitor, setting a limit to the achievable
slew rate. The OPA690 uses a new input stage which places
the transconductance element between two input buffers,
using their output currents as the forward signal. As the error
voltage increases across the two inputs, an increasing cur-
rent is delivered to the compensation capacitor. This pro-
vides very high slew rate (1800V/µs) while consuming
relatively low quiescent current (5.5mA). This exceptional
full-power performance comes at the price of a slightly higher
input noise voltage than alternative architectures. The
5.5nV/√Hzinput voltage noise for the OPA690 is exception-
ally low for this type of input stage.
Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration which is the basis of the +5V Specifica-
tions and Typical Characteristics. Though not a “rail-to-rail”
design, the OPA690 requires minimal input and output volt-
age headroom compared to other very wideband voltage
feedback op amps. It will deliver a 3Vp-p output swing on
a single +5V supply with > 150MHz bandwidth. The key
requirement of broadband single-supply operation is to main-
tain input and output signal swings within the useable voltage
ranges at both the input and the output. The circuit of Figure 2
establishes an input midpoint bias using a simple resistive
divider from the +5V supply (two 698Ω resistors). The input
signal is then AC-coupled into the midpoint voltage bias. The
input voltage can swing to within 1.5V of either supply pin,
giving a 2Vp-p input signal range centered between the
supply pins. The input impedance matching resistor (59Ω)
used for testing is adjusted to give a 50Ω input load when the
parallel combination of the biasing divider network is in-
cluded. Again, an additional resistor (50Ω in this case) is
included directly in series with the noninverting input. This
minimum recommended value provides part of the DC source
resistance matching for the noninverting input bias current. It
is also used to form a simple parasitic pole to roll off the
frequency response at very high frequencies (> 500MHz)
using the input parasitic capacitance to form a bandlimiting
pole. The gain resistor (RG) is AC-coupled, giving the circuit
a DC gain of +1, which puts the input DC bias voltage (2.5V)
at the output as well. The output voltage can swing to within
Figure 1 shows the DC-coupled, gain of +2, dual power-
supply circuit configuration used as the basis of the ±5V
Electrical Characteristics and Typical Characteristics. For test
purposes, the input impedance is set to 50Ω with a resistor to
ground and the output impedance is set to 50Ω with a series
output resistor. Voltage swings reported in the specifications
are taken directly at the input and output pins, while output
powers (dBm) are at the matched 50Ω load. For the circuit of
Figure 1, the total effective load will be 100Ω || 804Ω. The
disable control line is typically left open to ensure normal
amplifier operation. Two optional components are included in
Figure 1. An additional resistor (175Ω) is included in series
with the noninverting input. Combined with the 25Ω DC
source resistance looking back towards the signal generator,
this gives an input bias current cancelling resistance that
+5V
+5V
+VS
0.1µF
6.8µF
+
+
0.1µF
6.8µF
50Ω Source
0.1µF
50Ω Source
698Ω
50Ω
175Ω
DIS
VO
50Ω Load
DIS
VO 100Ω
VI
50Ω
50Ω
VI
OPA690
59Ω
698Ω
VS/2
OPA690
0.1µF
RF
402Ω
RF
402Ω
RG
RG
402Ω
402Ω
6.8µF
0.1µF
0.1µF
+
–5V
FIGURE 2. AC-Coupled, G = +2, Single-Supply, Specifica-
tion and Test Circuit.
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifica-
tion and Test Circuit.
OPA690
SBOS223A
11
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1V of either supply pin while delivering > 100mA output current.
A demanding 100Ω load to a midpoint bias is used in this
characterization circuit. The new output stage circuit used in the
OPA690 can deliver large bipolar output currents into this
midpoint load with minimal crossover distortion, as shown in the
+5V supply, 3rd-harmonic distortion plots.
70
68
66
64
62
60
58
56
54
52
50
VO = 2Vp-p, 10MHz
SINGLE-SUPPLY ADC INTERFACE
Most modern, high performance ADC (such as the TI ADS8xx
and ADS9xx series) operate on a single +5V (or lower) power
supply. It has been a considerable challenge for single-supply
op amps to deliver a low distortion input signal at the ADC input
for signal frequencies exceeding 5MHz. The high slew rate,
exceptional output swing, and high linearity of the OPA690
make it an ideal single-supply ADC driver. The circuit on the
front page shows one possible (inverting) interface. Figure 3
shows the test circuit of Figure 2 modified for a capacitive (ADC)
load and with an optional output pull-down resistor (RB).
0
1
2
3
4
5
6
7
8
9
10
Output Pull-Down Current (mA)
FIGURE 4. SFDR versus IB.
HIGH-PERFORMANCE DAC TRANSIMPEDANCE
AMPLIFIER
The OPA690 in the circuit of Figure 3 provides > 200MHz
bandwidth for a 2Vp-p output swing. Minimal 3rd-harmonic
distortion or 2-tone, 3rd-order intermodulation distortion will be
observed due to the very low crossover distortion in the OPA690
output stage. The limit of output Spurious-Free Dynamic Range
(SFDR) will be set by the 2nd-harmonic distortion. Without RB,
the circuit of Figure 3 measured at 10MHz shows an SFDR of
57dBc. This may be improved by pulling additional DC bias
current (IB) out of the output stage through the optional RB
resistor to ground (the output midpoint is at 2.5V for Figure 3).
Adjusting IB gives the improvement in SFDR shown in Figure 4.
SFDR improvement is achieved for IB values up to 5mA, with
worse performance for higher values.
High-frequency DDS Digital-to-Analog Converters (DACs)
require a low distortion output amplifier to retain their
SFDR performance into real-world loads. See Figure 5
for a single-ended output drive implementation. In this
circuit, only one side of the complementary output drive
signal is used. The diagram shows the signal output
current connected into the virtual ground summing junc-
tion of the OPA690, which is set up as a transimpedance
stage or “I-V converter”. The unused current output of the
DAC is connected to ground. If the DAC requires its
outputs terminated to a compliance voltage other than
ground for operation, the appropriate voltage level may
be applied to the noninverting input of the OPA690. The
+5V
Power-Supply Decoupling Not Shown
698Ω
698Ω
DIS
RS
0.1µF
50Ω
VI
30Ω
2.5V DC
±1V AC
1Vp-p
OPA690
59Ω
50pF
ADC Input
402Ω
402Ω
0.1µF
RB
IB
FIGURE 3. Single-Supply ADC Input Driver.
OPA690
12
SBOS223A
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50Ω
VO = IO RF
OPA690
+12V
High-Speed
DAC
RF
CF
2kΩ
2kΩ
50Ω
8Vp-p
4Vp-p
OPA690
CD
IO
0.1µF
50Ω
GBP → Gain Bandwidth
Load
Product (Hz) for the OPA690
50Ω
400Ω
1Vp-p
IO
5pF
50Ω
Source
FIGURE 6. High Power Coax Line Driver.
FIGURE 5. DAC Transimpedance Amplifier.
DC gain for this circuit is equal to RF. At high frequencies,
the DAC output capacitance will produce a zero in the noise
gain for the OPA690 that may cause peaking in the closed-
loop frequency response. CF is added across RF to compen-
sate for this noise gain peaking. To achieve a flat
transimpedance frequency response, the pole in the feed-
back network should be set to:
of the amplifier using a single 12V supply. Figure 6 shows
such a circuit set for a gain of 8 to the output or 4 to the load.
The 5pF capacitor in the feedback loop provides added
bandwidth control for the signal path.
SINGLE-SUPPLY ACTIVE FILTERS
The high bandwidth provided by the OPA690, while operat-
ing on a single +5V supply, lends itself well to high-frequency
active filter designs. Again, the key additional requirement is
to establish the DC operating point of the signal near the
supply midpoint for highest dynamic range. Figure 7 shows
an example design of a 5MHz low-pass Butterworth filter
using the Sallen-Key topology.
1/ 2πRFCF
= GBP / 4πRFCD
which will give a closed-loop transimpedance bandwidth
f
–3dB, of approximately:
f–3dB
=
GBP / 2πRFCD
Both the input signal and the gain setting resistor are AC-
coupled using 0.1µF blocking capacitors (actually giving
bandpass response with the low-frequency pole set to 32kHz
for the component values shown). As discussed for Figure 2,
this allows the midpoint bias formed by the two 1.87kΩ
resistors to appear at both the input and output pins. The
HIGH POWER LINE DRIVER
The large output swing capability of the OPA690 and its high
current capability allows it to drive a 50Ω line with a peak-to-
peak signal up to 4Vp-p at the load, or 8Vp-p at the output
+5V
5MHz, 2nd-Order Butterworth Filter Response
15
1.87kΩ
137Ω
100pF
10
5
DIS
0.1µF
432Ω
VI
4
VI
OPA690
1.87kΩ
150pF
5MHz, 2nd-Order
Butterworth Filter
0
1.5kΩ
–5
100k
500Ω
0.1µF
1M
10M
Frequency (Hz)
FIGURE 7. Single-Supply, High-Frequency Active Filter.
OPA690
SBOS223A
13
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midband signal gain is set to +4 (12dB) in this case. The
capacitor to ground on the noninverting input is intentionally
set larger to dominate input parasitic terms. At a gain of +4,
the OPA690 on a single supply will show ~80MHz small- and
large-signal bandwidth. The resistor values have been slightly
adjusted to account for this limited bandwidth in the amplifier
stage. Tests of this circuit show a precise 5MHz, –3dB point
with a maximally flat passband (above the 32kHz AC-cou-
pling corner), and a maximum stopband attenuation of 36dB
at the amplifier’s –3dB bandwidth of 80MHz.
frequency response flatness. Usually, for G > 1 application, the
feedback resistor value should be between 200Ω and 1.5kΩ.
Below 200Ω, the feedback network will present additional
output loading which can degrade the harmonic distortion
performance of the OPA690. Above 1.5kΩ, the typical parasitic
capacitance (approximately 0.2pF) across the feedback resistor
may cause unintentional band-limiting in the amplifier response.
A good rule of thumb is to target the parallel combination of RF
and RG (see Figure 1) to be less than approximately 300Ω. The
combined impedance RF || RG interacts with the inverting input
capacitance, placing an additional pole in the feedback network
and thus, a zero in the forward response. Assuming a 2pF total
parasitic on the inverting node, holding RF || RG < 300Ω will keep
this pole above 250MHz. By itself, this constraint implies that the
feedback resistor RF can increase to several kΩ at high gains.
This is acceptable as long as the pole formed by RF and any
parasitic capacitance appearing in parallel is kept out of the
frequency range of interest.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial evalu-
ation of circuit performance using the OPA690 in its three
package styles. All of these are available free as an
unpopulated PC board delivered with descriptive documenta-
tion. The summary information for these boards is shown
below:
BANDWIDTH VERSUS GAIN: NONINVERTING
OPERATION
Voltage feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP by
the noninverting signal gain (also called the Noise Gain, or
NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90°, as
it does in high gain configurations. At low gains (increased
feedback factors), most amplifiers will exhibit a more com-
plex response with lower phase margin. The OPA690 is
compensated to give a slightly peaked response in a
noninverting gain of 2 (see Figure 1). This results in a typical
gain of +2 bandwidth of 220MHz, far exceeding that pre-
dicted by dividing the 300MHz GBP by 2. Increasing the gain
will cause the phase margin to approach 90° and the band-
width to more closely approach the predicted value of (GBP/
NG). At a gain of +10, the 30MHz bandwidth shown in the
Electrical Characteristics agrees with that predicted using the
simple formula and the typical GBP of 300MHz.
BOARD
PART
NUMBER
LITERATURE
REQUEST
NUMBER
PRODUCT
PACKAGE
OPA690ID
OPA690IDBV
SO-8
SOT23-6
DEM-OPA68xU
DEM-OPA6xxN
SBOU009
SBOU010
The board can be requested on Texas Instruments’ web site
(www.ti.com.).
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. A
SPICE model for the OPA690 is available through the Texas
Instruments internet web page (http://www.ti.com). These
models do a good job of predicting small-signal AC and
transient performance under a wide variety of operating
conditions. They do not do as well in predicting the harmonic
distortion or dG/dP characteristics. These models do not
attempt to distinguish between the package types in their
small-signal AC performance.
Frequency response in a gain of +2 may be modified to
achieve exceptional flatness simply by increasing the noise
gain to 2.5. One way to do this, without affecting the +2 signal
gain, is to add an 804Ω resistor across the two inputs in the
circuit of Figure 1. A similar technique may be used to reduce
peaking in unity-gain (voltage follower) applications. For
example, by using a 402Ω feedback resistor along with a
402Ω resistor across the two op amp inputs, the voltage
follower response will be similar to the gain of +2 response
of Figure 2. Further reducing the value of the resistor across
the op amp inputs will further dampen the frequency re-
sponse due to increased noise gain.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Since the OPA690 is a unity-gain stable voltage feedback op
amp, a wide range of resistor values may be used for the
feedback and gain setting resistors. The primary limits on these
values are set by dynamic range (noise and distortion) and
parasitic capacitance considerations. For a noninverting unity-
gain follower application, the feedback connection should be
made with a 25Ω resistor, not a direct short. This will isolate the
inverting input capacitance from the output pin and improve the
The OPA690 exhibits minimal bandwidth reduction going to
single-supply (+5V) operation as compared with ±5V. This is
because the internal bias control circuitry retains nearly
constant quiescent current as the total supply voltage be-
tween the supply pins is changed.
OPA690
14
SBOS223A
www.ti.com
INVERTING AMPLIFIER OPERATION
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence influences the
bandwidth. For the example in Figure 8, the RM value
combines in parallel with the external 50Ω source imped-
ance, yielding an effective driving impedance of 50Ω || 67Ω
= 28.6Ω. This impedance is added in series with RG for
calculating the noise gain (NG). The resultant NG is 2.8 for
Figure 8, as opposed to only 2 if RM could be eliminated as
discussed above. The bandwidth will therefore be slightly
lower for the gain of –2 circuit of Figure 8 than for the gain
of +2 circuit of Figure 1.
Since the OPA690 is a general-purpose, wideband voltage
feedback op amp, all of the familiar op amp application
circuits are available to the designer. Inverting operation is
one of the more common requirements and offers several
performance benefits. Figure 8 shows a typical inverting
configuration where the I/O impedances and signal gain from
Figure 1 are retained in an inverting circuit configuration.
+5V
The third important consideration in inverting amplifier design
is setting the bias current cancellation resistor on the
noninverting input (RB). If this resistor is set equal to the total
DC resistance looking out of the inverting node, the output
DC error, due to the input bias currents, will be reduced to
(Input Offset Current) • RF. If the 50Ω source impedance is
DC-coupled in Figure 8, the total resistance to ground on the
inverting input will be 228Ω. Combining this in parallel with
the feedback resistor gives the RB = 146Ω used in this
example. To reduce the additional high frequency noise
introduced by this resistor, it is sometimes bypassed with a
capacitor. As long as RB < 350Ω, the capacitor is not required
since the total noise contribution of all other terms will be less
than that of the op amp’s input noise voltage. As a minimum,
the OPA690 requires an RB value of 50Ω to damp out
parasitic-induced peaking—a direct short to ground on the
noninverting input runs the risk of a very high frequency
instability in the input stage.
+
0.1µF
6.8µF
0.1µF
DIS
RO
50Ω
OPA690
RB
146Ω
50Ω Load
50Ω
RG
200Ω
RF
402Ω
Source
RM
67Ω
0.1µF
6.8µF
+
–5V
FIGURE 8. Gain of –2 Example Circuit.
OUTPUT CURRENT AND VOLTAGE
In the inverting configuration, three key design consider-
ations must be noted. The first is that the gain resistor (RG)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted-pair, long
PC board trace, or other transmission line conductor), RG
may be set equal to the required termination value and RF
adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise per-
formance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting RG to 50Ω
for input matching eliminates the need for RM but requires a
100Ω feedback resistor. This has the interesting advantage
that the noise gain becomes equal to 2 for a 50Ω source
impedance—the same as the noninverting circuits consid-
ered above. However, the amplifier output will now see the
100Ω feedback resistor in parallel with the external load. In
general, the feedback resistor should be limited to the 200Ω
to 1.5kΩ range. In this case, it is preferable to increase both
the RF and RG values, as shown in Figure 8, and then
achieve the input matching impedance with a third resistor
(RM) to ground. The total input impedance becomes the
parallel combination of RG and RM.
The OPA690 provides output voltage and current capabilities
that are unsurpassed in a low-cost monolithic op amp. Under
no-load conditions at +25°C, the output voltage typically
swings closer than 1V to either supply rail; the tested swing
limit is within 1.2V of either rail. Into a 15Ω load (the minimum
tested load), it is tested to deliver more than ±160mA.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
“Output Voltage and Current Limitations” plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA690’s output drive capabilities,
noting that the graph is bounded by a “Safe Operating Area”
of 1W maximum internal power dissipation. Superimposing
resistor load lines onto the plot shows that the OPA690 can
drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the
output capabilities or the 1W dissipation limit. A 100Ω load
line (the standard test circuit load) shows the full ±3.9V
output swing capability, as shown in the typical specifica-
tions.
OPA690
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The minimum specified output voltage and current specifica-
tions over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold startup will the
output current and voltage decrease to the numbers shown
in the tested tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
Figure 9 demonstrates this technique, allowing lower values
of RS to be used for a given capacitive load.
+5V
50Ω
175Ω
Power-supply decoupling not shown.
R
VBE’s (increasing the available output voltage swing) and
increasing their current gains (increasing the available out-
put current). In steady-state operation, the available output
voltage and current will always be greater than that shown in
the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum speci-
fied operating ambient.
50Ω
RNG
VO
OPA690
CL
402Ω
402Ω
–5V
To protect the output stage from accidental shorts to ground
and the power supplies, output short-circuit protection is
included in the OPA690. The circuit acts to limit the maxi-
mum source or sink current to approximately 250mA.
FIGURE 9. Capacitive Load Driving with Noise Gain Tuning.
This gain of +2 circuit includes a noise gain tuning resistor
across the two inputs to increase the noise gain, increasing the
unloaded phase margin for the op amp. Although this tech-
nique will reduce the required RS resistor for a given capacitive
load, it does increase the noise at the output. It also will
decrease the loop gain, slightly decreasing the distortion per-
formance. If, however, the dominant distortion mechanism
arises from a high RS value, significant dynamic range im-
provement can be achieved using this technique. Figure 10
shows the required RS versus CLOAD parametric on noise gain
using this technique. This is the circuit of Figure 9 with RNG
adjusted to increase the noise gain (increasing the phase
margin) then sweeping CLOAD and finding the required RS to
get a flat frequency response. This plot also gives the required
RS versus CLOAD for the OPA690 operated at higher signal
gains.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including additional
external capacitance which may be recommended to im-
prove ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA690 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier’s open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness,
pulse response fidelity, and/or distortion, the simplest and
most effective solution is to isolate the capacitive load from
the feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load. This
does not eliminate the pole from the loop response, but
rather shifts it and adds a zero at a higher frequency. The
additional zero acts to cancel the phase lag from the capaci-
tive load pole, thus increasing the phase margin and improv-
ing stability.
100
90
80
70
NG = 2
60
50
40
30
The Typical Characteristics show the recommended RS
versus capacitive load and the resulting frequency response
at the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA690. Long PC
board traces, unmatched cables, and connections to multiple
devices can easily exceed this value. Always consider this
effect carefully, and add the recommended series resistor as
close as possible to the OPA690 output pin (see Board
Layout Guidelines).
20
NG = 3
10
NG = 4
0
1
10
100
1000
Capacitive Load (pF)
FIGURE 10. Required RS vs Noise Gain.
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For the
OPA690 operating in a gain of +2, the frequency response
at the output pin is already slightly peaked without the
capacitive load requiring relatively high values of RS to flatten
the response at the load. Increasing the noise gain will
reduce the peaking as described previously. The circuit of
DISTORTION PERFORMANCE
The OPA690 provides good distortion performance into
a 100Ω load on ±5V supplies. Relative to alternative solu-
tions, it provides exceptional performance into lighter loads
and/or operating on a single +5V supply. Generally, until the
fundamental signal reaches very high frequency or power
OPA690
16
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levels, the 2nd-harmonic will dominate the distortion with a
negligible 3rd-harmonic component. Focusing then on the
2nd-harmonic, increasing the load impedance improves
distortion directly. Remember that the total load includes
the feedback network; in the noninverting configuration (see
Figure 1) this is sum of RF + RG, while in the inverting
configuration, it is just RF. Also, providing an additional
supply decoupling capacitor (0.1µF) between the supply pins
(for bipolar operation) improves the 2nd-order distortion
slightly (3dB to 6dB).
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the
output noise voltage using the terms shown in Figure 11.
(1)
2
2
2
EO
=
ENI + IBNRS + 4kTRS NG2 + I R
+ 4kTRFNG
(
)
(
)
BI
F
Dividing this expression by the noise gain (NG = (1+RF/RG))
will give the equivalent input-referred spot noise voltage at the
noninverting input, as shown in Equation 2.
In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. The new output stage
used in the OPA690 actually holds the difference between
fundamental power and the 2nd- and 3rd-harmonic powers
relatively constant with increasing output power until very
large output swings are required (> 4Vp-p). This also shows
up in the 2-tone, 3rd-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are moder-
ately low at low output power levels. The output stage
continues to hold them low even as the fundamental power
reaches very high levels. As the Typical Characteristics
show, the spurious intermodulation powers do not increase
as predicted by a traditional intercept model. As the funda-
mental power level increases, the dynamic range does not
decrease significantly. For 2 tones centered at 20MHz, with
10dBm/tone into a matched 50Ω load (i.e., 2Vp-p for each
tone at the load, which requires 8Vp-p for the overall 2-tone
envelope at the output pin), the Typical Characteristics show
47dBc difference between the test tone powers and the 3rd-
order intermodulation spurious powers. This performance
improves further when operating at lower frequencies.
(2)
2
IBIRF
NG
4kTRF
NG
2
2
EN
=
ENI + IBNRS + 4kTRS
+
+
(
)
Evaluating these two equations for the OPA690 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 12.3nV/√Hz and a total equivalent input spot
noise voltage of 6.1nV/√Hz. This is including the noise added
by the bias current cancellation resistor (175Ω) on the
noninverting input. This total input-referred spot noise volt-
age is only slightly higher than the 5.5nV/√Hz specification
for the op amp voltage noise alone. This will be the case as
long as the impedances appearing at each op amp input are
limited to the previously recommend maximum value of
300Ω. Keeping both (RF || RG) and the noninverting input
source impedance less than 300Ω will satisfy both noise and
frequency response flatness considerations. Since the resis-
tor-induced noise is relatively negligible, additional capacitive
decoupling across the bias current cancellation resistor (RB)
for the inverting op amp configuration of Figure 8 is not
required.
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 5.5nV/√Hz input voltage noise for
the OPA690 is, however, much lower than comparable
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms, combine to give low
output noise under a wide variety of operating conditions.
Figure 11 shows the op amp noise analysis model with all the noise
terms included. In this model, all noise terms are taken to be noise
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power-supply current trim for the OPA690
gives even tighter control than comparable products. Al-
though the high-speed input stage does require relatively
high input bias current (typically ±8µA at each input terminal),
the close matching between them may be used to reduce the
output DC error caused by this current. The total output offset
voltage may be considerably reduced by matching the DC
source resistances appearing at the two inputs. This reduces
the output DC error due to the input bias currents to the offset
current times the feedback resistor. Evaluating the configura-
tion of Figure 1, using worst-case +25°C input offset voltage
and current specifications, gives a worst-case output offset
voltage equal to: – (NG = noninverting signal gain)
voltage or current density terms in either nV/√Hz or pA/√Hz
.
ENI
EO
OPA690
RS
IBN
ERS
RF
√4kTRS
±(NG • VOS(MAX)) ± (RF • IOS(MAX)
= ±(2 • 4mV) ± (402Ω • 1µA)
= ±8.4mV
)
√4kTRF
IBI
RG
4kT
RG
4kT = 1.6E –20J
at 290°K
FIGURE 11. Op Amp Noise Analysis Model.
OPA690
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A fine-scale output offset null, or DC operating point adjust-
ment, is often required. Numerous techniques are available
for introducing DC offset control into an op amp circuit. Most
of these techniques eventually reduce to adding a DC current
through the feedback resistor. In selecting an offset trim
method, one key consideration is the impact on the desired
signal path frequency response. If the signal path is intended
to be noninverting, the offset control is best applied as an
inverting summing signal to avoid interaction with the signal
source. If the signal path is intended to be inverting, applying
the offset control to the noninverting input may be consid-
ered. However, the DC offset voltage on the summing
junction will set up a DC current back into the source which
must be considered. Applying an offset adjustment to the
inverting op amp input can change the noise gain and
frequency response flatness. For a DC-coupled inverting
amplifier, Figure 12 shows one example of an offset adjust-
ment technique that has minimal impact on the signal fre-
quency response. In this case, the DC offsetting current is
brought into the inverting input node through resistor values
that are much larger than the signal path resistors. This will
insure that the adjustment circuit has minimal effect on the
loop gain and hence the frequency response.
+VS
15kΩ
Q1
25kΩ
110kΩ
IS
VDIS
Control
–VS
FIGURE 13. Simplified Disable Control Circuit.
LOW, additional current is pulled through the 15kΩ resistor,
eventually turning on those two diodes (≈75µA). At this point,
any further current pulled out of VDIS goes through those
diodes holding the emitter-base voltage of Q1 at approxi-
mately 0V. This shuts off the collector current out of Q1,
turning the amplifier off. The supply current in the disable
mode are only those required to operate the circuit of Figure
13. Additional circuitry ensures that turn-on time occurs
faster than turn-off time (make-before-break).
+5V
Supply Decoupling
Not Shown
When disabled, the output and input nodes go to a high
impedance state. If the OPA690 is operating in a gain of +1,
this will show a very high impedance at the output and
exceptional signal isolation. If operating at a gain greater
than +1, the total feedback network resistance (RF + RG) will
appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the input and
output will be connected through the feedback network
resistance (RF + RG) and the isolation will be very poor as a result.
VO
OPA690
0.1µF
328Ω
–5V
RG
500Ω
RF
1kΩ
+5V
VI
5kΩ
5kΩ
±200mV Output Adjustment
20kΩ
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 14
shows these glitches for the circuit of Figure 1 with the input
signal at 0V. The glitch waveform at the output pin is plotted
along with the DIS pin voltage.
10kΩ
0.1µF
V
RF
O = –
VI
= –2
RG
–5V
FIGURE 12. DC-Coupled, Inverting Gain of –2, with Offset
Adjustment.
DISABLE/ENABLE GLITCH
6
4
DISABLE OPERATION
VDIS
2
The OPA690 provides an optional disable feature that may
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control pin
is left unconnected, the OPA690 will operate normally. To
disable, the control pin must be asserted LOW. Figure 13
shows a simplified internal circuit for the disable control
feature.
0
30
20
10
Output Voltage
0
Vi = 0V
–10
–20
In normal operation, base current to Q1 is provided through
the 110kΩ resistor, while the emitter current through the
15kΩ resistor sets up a voltage drop that is inadequate to
turn on the two diodes in Q1’s emitter. As VDIS is pulled
–30
Time (20ns/div)
FIGURE 14. Disable/Enable Glitch.
OPA690
18
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The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 14, the edge rate
was reduced until no further reduction in glitch amplitude was
observed. This approximately 1V/ns maximum slew rate may
be achieved by adding a simple RC filter into the DIS pin
from a higher speed logic line. If extremely fast transition
logic is used, a 1kΩ series resistor between the logic gate
and the DIS input pin will provide adequate bandlimiting
using just the parasitic input capacitance on the DIS pin
while still ensuring adequate logic level swing.
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Other-
wise, ground and power planes should be unbroken else-
where on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these capaci-
tors. An optional supply decoupling capacitor (0.1µF) across
the two power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF)
decoupling capacitors, effective at lower frequency, should
also be used on the main supply pins. These may be placed
somewhat farther from the device and may be shared among
several devices in the same area of the PC board.
THERMAL ANALYSIS
Due to the high output power capability of the OPA690,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
Operating junction temperature (TJ) is given by TA + PD • θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA690. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded resis-
tors can also provide good high-frequency performance.
Again, keep their leads and PC board traces as short as
possible. Never use wirewound type resistors in a high-
frequency application. Since the output pin and inverting
input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as noninverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resis-
tors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values > 1.5kΩ,
this parasitic capacitance can add a pole and/or zero below
500MHz that can effect circuit operation. Keep resistor val-
ues as low as possible consistent with load driving consider-
ations. The 402Ω feedback used in the Electrical Character-
istics is a good starting point for design. Note that a 25Ω
feedback resistor, rather than a direct short, is suggested for
the unity-gain follower application. This effectively isolates
the inverting input capacitance from the output pin that would
otherwise cause an additional peaking in the gain of +1
frequency response.
2
bipolar supplies). Under this condition, PDL = VS /(4 • RL)
where RL includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an
OPA690IDBV (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 20Ω load.
PD = 10V • 6.2mA + 52/(4 • (20Ω || 804Ω)) = 382mW
Maximum TJ = +85°C + (0.38W • 150°C/W) = 142°C.
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower tested junction temperatures. The highest pos-
sible internal dissipation will occur if the load requires current
to be forced into the output for positive output voltages or
sourced from the output for negative output voltages. This
puts a high current through a large internal voltage drop in
the output transistors. The output V-I plot shown in the
Typical Characteristics include a boundary for 1W maximum
internal power dissipation under these conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency am-
plifier like the OPA690 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
OPA690
SBOS223A
19
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d) Connections to other wideband devices on the board
may be made with short, direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RS from the
plot of Recommended RS vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an RS since the
OPA690 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an RS
are allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly terminated transmission
line is acceptable, implement a matched impedance trans-
mission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline layout
techniques). A 50Ω environment is normally not necessary
on board, and in fact, a higher impedance environment will
improve distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance defined
(based on board material and trace dimensions), a matching
series resistor into the trace from the output of the OPA690
is used as well as a terminating shunt resistor at the input of
the destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device;
this total effective impedance should be set to match the
trace impedance. The high output voltage and current capa-
bility of the OPA690 allows multiple destination devices to be
handled as separate transmission lines, each with their own
series and shunt terminations. If the 6dB attenuation of a
doubly-terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only. Treat
the trace as a capacitive load in this case and set the series
resistor value as shown in the plot of “Recommended RS vs
Capacitive Load”. This will not preserve signal integrity as
well as a doubly-terminated line. If the input impedance of the
destination device is low, there will be some signal attenua-
tion due to the voltage divider formed by the series output
into the terminating impedance.
e) Socketing a high-speed part like the OPA690 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA690
onto the board.
INPUT AND ESD PROTECTION
The OPA690 is built using a very high-speed complementary
bipolar process. The internal junction breakdown voltages
are relatively low for these very small geometry devices.
These breakdowns are reflected in the Absolute Maximum
Ratings table. All device pins are protected with internal
ESD protection diodes to the power supplies as shown in
Figure 15.
+VCC
External
Pin
Internal
Circuitry
–VCC
FIGURE 15. Internal ESD Protection.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply
parts driving into the OPA690), current-limiting series resis-
tors should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
OPA690
20
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PACKAGE DRAWINGS
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.069 (1,75) MAX
0.004 (0,10)
0.004 (0,10)
PINS **
8
14
16
DIM
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/E 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
OPA690
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21
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PACKAGE DRAWINGS (Cont.)
DBV (R-PDSO-G6)
MPDS026C – FEBRUARY 1997 – REVISED JANUARY 2001
PLASTIC SMALL-OUTLINE
0,50
0,25
M
0,20
0,95
6X
6
4
0,15 NOM
1,70
1,50
3,00
2,60
1
3
Gage Plane
3,00
2,80
0,25
0°–8°
0,55
0,35
Seating Plane
0,10
1,45
0,95
0,05 MIN
4073253-5/F 10/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Leads 1, 2, 3 are wider than leads 4, 5, 6 for package orientation.
OPA690
22
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
OPA690ID
OPA690IDBVR
OPA690IDBVT
OPA690IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOP
SOP
SOIC
D
8
6
6
8
100
3000
250
DBV
DBV
D
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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logic.ti.com
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microcontroller.ti.com
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