OPA4205APWT [TI]
Quad, rail-to-rail bipolar precision e-trim™ op amp with low input bias current and low noise | PW | 14 | -40 to 125;型号: | OPA4205APWT |
厂家: | TEXAS INSTRUMENTS |
描述: | Quad, rail-to-rail bipolar precision e-trim™ op amp with low input bias current and low noise | PW | 14 | -40 to 125 |
文件: | 总42页 (文件大小:2889K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
OPA205, OPA2205, OPA4205
ZHCSLB1F –APRIL 2020 –REVISED MARCH 2023
OPAx205 4µV、0.08µV/°C 低功耗超β 双极e-trim™ 运算放大器
1 特性
3 说明
• e-trim™ 运算放大器性能
OPA205、OPA2205 和 OPA4205 (OPAx205) 是业界
通用 OPAx277 系列的新一代版本。OPA206 和
OPA2206 是使用相同运算放大器内核的相关器件,但
具有高于电源电压±40V 的输入过压保护的额外特性。
这些器件是具有超 β 输入的精密双极 e-trim™ 运算放
大器。TI 的专有微调技术用于实现 ±4μV(±2µV,高
等级)的典型输入失调电压和 ±0.08μV(±0.04µV,
高等级)的典型输入失调电压漂移。
– 低失调电压:25µV(最大值),
15µV(最大值,高等级)
– 低失调电压漂移:±0.5µV/°C(典型值),
±0.2µV/°C(最大值,高等级)
• 超β输入
– 输入偏置电流:500 pA(最大值)
– 输入电流噪声:110fA/√Hz
• 低噪声
OPAx205 采用双极工艺设计,可针对仅220µA 的静态
电流提供 3.6MHz 增益带宽。这些器件还可在 1kHz 下
实现仅 7.2nV/√Hz 的低电压噪声密度。得益于超 β
输入,OPAx205 具有 100pA(典型值)的超低输入偏
置电流和110fA/√Hz 的电流噪声密度。
– 0.1 至10Hz:0.2µVPP
– 电压噪声:7.2nV/√Hz
• AOL、CMRR 和PSRR:> 126dB(全温度范围)
• 增益带宽积:3.6MHz
• 低静态电流:240µA(最大值)
• 压摆率:4V/µs
• 过载功率限制器
OPAx205 的高性能使这些器件成为了高精度和低功耗
系统的理想选择,例如流量和压力变送器、便携式数据
采集(DAQ) 系统和高密度源测量单元(SMU)。
• 轨到轨输出
• EMI 和RFI 已滤除的输入
• 宽电源电压范围:4.5V 至36V
• 温度范围:–40°C 至+125°C
• 提供标准等级(OPAx205A) 和
高等级(OPA2205,预发布)
• OPA206 和OPA2206 提供±40V 过压保护
器件信息
封装(1)
器件型号
OPA205
通道
D(SOIC,8)
单通道
双通道
双通道
四通道
四通道
D(SOIC,8)
OPA2205(2)
DGK(VSSOP,8)
D(SOIC,14)
PW(TSSOP,14)
OPA4205
2 应用
• 流量变送器
• 串式逆变器
(1) 如需了解所有可用封装,请参阅数据表末尾的封装选项附录。
(2) 高等级版本为预发布信息(而非量产数据)。
• 数据采集(DAQ)
• 源测量单元(SMU)
• 实验室和现场仪表
• 电池测试
• 模拟输入模块
• 压力变送器
750 ꢀ
15
12
9
470 pF
+7 V
3 kꢀ
œ
2.4 kꢀ
IN+
+
OPA2205
Þ7 V
100 ꢀ
100 ꢀ
+7 V
œ
1.1 nF
1 nF
VOUT
6
+
THP210
Þ7 V
+7 V
2.4 kꢀ
3 kꢀ
œ
3
INÞ
+
470 pF
OPA2205
Þ7 V
0
750 ꢀ
-0.1 -0.08 -0.06 -0.04 -0.02
0
0.02 0.04 0.06 0.08 0.1
Offset Voltage Drift (µV/°C)
OPA2205 典型应用
OPAx205 失调电压漂移
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBOS962
OPA205, OPA2205, OPA4205
ZHCSLB1F –APRIL 2020 –REVISED MARCH 2023
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram.........................................22
8.3 Feature Description...................................................23
8.4 Device Functional Modes..........................................24
9 Application and Implementation..................................25
9.1 Application Information............................................. 25
9.2 Typical Applications.................................................. 25
9.3 Power Supply Recommendations.............................28
9.4 Layout....................................................................... 28
10 Device and Documentation Support..........................30
10.1 Device Support....................................................... 30
10.2 文档支持..................................................................30
10.3 接收文档更新通知................................................... 30
10.4 支持资源..................................................................30
10.5 Trademarks.............................................................30
10.6 静电放电警告.......................................................... 30
10.7 术语表..................................................................... 30
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information: OPA205.................................... 7
6.5 Thermal Information: OPA2205.................................. 7
6.6 Thermal Information: OPA4205.................................. 7
6.7 Electrical Characteristics: VS = ±5 V...........................8
6.8 Electrical Characteristics: VS = ±15 V.......................10
6.9 Typical Characteristics..............................................12
7 Parameter Measurement Information..........................21
7.1 Typical Specifications and Distributions....................21
8 Detailed Description......................................................22
8.1 Overview...................................................................22
Information.................................................................... 30
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision E (December 2022) to Revision F (March 2023)
Page
• 更改了标题以与标准级器件规格保持一致...........................................................................................................1
• 添加了OPA2205 D(SOIC,8)封装和相关内容作为量产数据........................................................................ 1
• 添加了OPA4205 D(SOIC,14)封装和相关内容作为量产数据...................................................................... 1
• Changed maximum input bias from ±0.4 nA to ±0.5 nA................................................................................... 21
• Changed offset and offset drift values to match standard-grade device specifications in Detailed Design
Description .......................................................................................................................................................26
• Changed Figure 9-6 to show correct VS+ connection ..................................................................................... 29
Changes from Revision D (September 2022) to Revision E (December 2022)
Page
• 添加了 OPA4205 TSSOP 封装和相关内容作为量产数据................................................................................... 1
• Changed typical input offset voltage from 8 µV to 4 µV in Electrical Characteristics .........................................8
• Changed maximum input offset voltage from 50 µV to 25 µV in Electrical Characteristics ............................... 8
• Changed maximum input offset voltage over temperature from 80 µV to 55 µV in Electrical Characteristics .....
............................................................................................................................................................................8
• Changed typical input offset voltage from 8 µV to 4 µV in Electrical Characteristics .......................................10
• Changed maximum input offset voltage from 50 µV to 25 µV in Electrical Characteristics ............................. 10
• Changed maximum input offset voltage over temperature from 80 µV to 55 µV in Electrical Characteristics .....
..........................................................................................................................................................................10
Changes from Revision C (July 2022) to Revision D (September 2022)
Page
• 将OPA205 (SOIC) 从“预发布”更改为“量产数据”(正在供货).................................................................1
Changes from Revision B (August 2021) to Revision C (July 2022)
Page
• 添加了 OPA205 D (SOIC) 封装作为预告信息(预发布)...................................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBOS962
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Changes from Revision A (May 2021) to Revision B (August 2021)
Page
• Changed Figure 6-22, Voltage Noise Density vs Frequency, to show voltage noise density instead of current
noise density.....................................................................................................................................................12
Changes from Revision * (April 2020) to Revision A (May 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 将OPA2205 从“预告信息(预发布)”更改为“量产数据(正在供货)”..................................................... 1
• Changed both Electrical Characteristics tables to show differentiated performance between OPA2205 (high
grade) and OPA2205A (standard grade)............................................................................................................8
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English Data Sheet: SBOS962
OPA205, OPA2205, OPA4205
ZHCSLB1F –APRIL 2020 –REVISED MARCH 2023
www.ti.com.cn
5 Pin Configuration and Functions
NC
œIN
+IN
Vœ
1
2
3
4
8
7
6
5
NC
V+
œ
OUT
NC
+
Not to scale
图5-1. OPA205 D Package, 8-Pin SOIC (Top View)
表5-1. Pin Functions: OPA205
PIN
TYPE
DESCRIPTION
NAME
NO.
+IN
–IN
NC
3
Input
Input
Noninverting input
2
Inverting input
1, 5, 8
No internal connection (can be left floating)
Output
—
OUT
V+
6
7
4
Output
Positive (highest) power supply
Negative (lowest) power supply
—
—
V–
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
图5-2. OPA2205 DGK Package, 8-Pin VSSOP and D Package, 8-pin SOIC (Top View)
表5-2. Pin Functions: OPA2205
PIN
TYPE
DESCRIPTION
NAME
NO.
3
+IN A
Input
Input
Input
Input
Output
Output
—
Noninverting input, channel A
Inverting input, channel A
Noninverting input, channel B
Inverting input, channel B
Output, channel A
2
–IN A
+IN B
–IN B
OUT A
OUT B
V+
5
6
1
7
Output, channel B
8
Positive (highest) power supply
Negative (lowest) power supply
4
V–
—
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBOS962
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OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
8
Not to scale
图5-3. OPA4205 PW Package, 14-Pin TSSOP and D Package, 14-Pin SOIC (Top View)
Pin Functions: OPA4205
PIN
TYPE
DESCRIPTION
NAME
NO.
3
+IN A
+IN B
+IN C
+IN D
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
—
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Inverting input, channel A
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Output, channel A
5
10
12
2
–IN A
–IN B
–IN C
–IN D
OUT A
OUT B
OUT C
OUT D
V+
6
9
13
1
7
Output, channel B
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
11
V–
—
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English Data Sheet: SBOS962
OPA205, OPA2205, OPA4205
ZHCSLB1F –APRIL 2020 –REVISED MARCH 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
Single supply
VS
V
Supply voltage, VS = (V+) –(V–)
Dual supply
Common-mode
Differential
±20
(V+) + 0.5
±0.5
(V–) –0.5
Signal input pin voltage
V
Signal input pin current
Output short-circuit(2)
Operating temperature
Junction temperature
Storage temperature
±10
mA
Continuous
TA
150
150
150
°C
°C
°C
–40
TJ
TSTG
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002((2))
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single supply
Dual supply
VS
TA
Supply voltage, VS = (V+) –(V–)
±2.25
–40
±18
125
Operating temperature
°C
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English Data Sheet: SBOS962
6
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6.4 Thermal Information: OPA205
OPA205
THERMAL METRIC(1)
D (SOIC)
8 PINS
121.5
64.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
℃/W
℃/W
℃/W
℃/W
℃/W
℃/W
RθJC(top)
RθJB
65.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
18.2
ψJT
64.3
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2205
OPA2205
THERMAL METRIC(1)
D (SOIC)
8 PINS
126.9
67.1
DGK (VSSOP)
8 PINS
175.6
63.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
70.3
97.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
18.8
7.8
ψJT
69.5
95.5
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4205
OPA4205
THERMAL METRIC(1)
D (SOIC)
14 PINS
86.5
PW (TSSOP)
14 PINS
117.1
36.0
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
38.5
43.5
59.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.4
2.6
ψJT
42.9
58.3
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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English Data Sheet: SBOS962
OPA205, OPA2205, OPA4205
ZHCSLB1F –APRIL 2020 –REVISED MARCH 2023
www.ti.com.cn
6.7 Electrical Characteristics: VS = ±5 V
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±2
MAX
UNIT
OFFSET VOLTAGE
±15
±25
OPA2205
TA = –40°C to +125°C
VOS
Input offset voltage
μV
±4
±25
OPAx205A
±55
TA = –40°C to +125°C
TA = –40°C to +125°C
TA = –40°C to +125°C
OPA2205
±0.04
±0.08
±0.05
±0.2
±0.5
±0.25
±0.5
±0.5
±1
dVOS/dT Input offset voltage drift
μV/°C
OPAx205A
OPA2205,
VS = ±2.25 V to ±18 V
TA = –40°C to +125°C
TA = –40°C to +125°C
Power supply rejection
PSRR
ratio
μV/V
±0.05
OPAx205A,
VS = ±2.25 V to ±18 V
f = dc
130
110
Channel separation,
(dual, quad)
dB
f = 100 kHz
INPUT BIAS CURRENT
±0.1
±0.1
±0.1
±0.4
±0.6
±0.9
±0.5
±0.75
±1
TA = 0°C to 85°C
OPA2205
TA = –40°C to +125°C
IB
Input bias current
nA
nA
TA = 0°C to 85°C
OPAx205A
TA = –40°C to +125°C
±0.4
±0.5
±0.6
TA = 0°C to 85°C
IOS
Input offset current
Input voltage noise
TA = –40°C to +125°C
NOISE
f = 0.1 Hz to 10 Hz
f = 10 Hz
0.2
7.4
7.2
7.2
μVPP
Input voltage noise
density
en
f = 100 Hz
nV/√Hz
f = 1 kHz
Input current noise
density
in
f = 1 kHz
110
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
V
(V–) + 1
(V+) –1.4
OPA2205, (V–) + 1 V < VCM < (V+) –1.4 V,
TA = –40°C to +125°C
124
140
140
Common-mode rejection
ratio
CMRR
dB
OPAx205A, (V–) + 1 V < VCM < (V+) –1.4 V,
TA = –40°C to +125°C
124
INPUT IMPEDANCE
ZID
Differential
9 || 4.4
MΩ|| pF
GΩ|| pF
ZICM
Common-mode
300 || 4.4
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English Data Sheet: SBOS962
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6.7 Electrical Characteristics: VS = ±5 V (continued)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
OPA2205,
TA = –40°C to +125°C,
(V–) + 200 mV < VO < (V+) –200 mV
126
126
126
126
132
130
132
130
RL = 10 kΩ
RL = 2 kΩ
RL = 10 kΩ
RL = 2 kΩ
AOL
Open-loop voltage gain
dB
OPAx205A,
TA = –40°C to +125°C,
(V–) + 200 mV < VO < (V+) –200 mV
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
3.6
3.2
67
MHz
V/μs
Slew rate
4-V step, gain = –1
Phase margin
degrees
RL = 10 kΩ, CL = 25 pF
To 0.024% (12-bit),
4-V step, gain = 1,
CL = 30 pF
Falling
Rising
2.2
tS
Settling time
μs
2.8
0.3
Overload recovery time
Gain = –10
μs
Total harmonic distortion
+ noise
THD+N
0.0004
%
VO = 5 VPP, gain = +1, f = 1 kHz, RL = 2 kΩ
OUTPUT
RL = 10 kΩ
(V–) + 0.2
(V–) + 0.2
(V–) + 0.2
(V+) –0.2
(V+) –0.2
(V+) –0.2
AOL > 126 dB
Voltage output swing
from rail
V
RL = 2 kΩ
TA = –40°C to +125°C, RL = 10 kΩ
ISC
Short-circuit current
Capacitive load drive
±25
mA
CLOAD
See Typical Characteristics
See Typical Characteristics
Open-loop output
impedance
RO
POWER SUPPLY
220
240
310
Quiescent current per
amplifier
IQ
IO = 0 mA
μA
TA = –40°C to +125°C
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English Data Sheet: SBOS962
OPA205, OPA2205, OPA4205
ZHCSLB1F –APRIL 2020 –REVISED MARCH 2023
www.ti.com.cn
6.8 Electrical Characteristics: VS = ±15 V
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
±2
MAX
UNIT
OFFSET VOLTAGE
±15
±25
OPA2205
TA = –40°C to +125°C
VOS
Input offset voltage
μV
±4
±25
OPAx205A
±55
TA = –40°C to +125°C
TA = –40°C to +125°C
TA = –40°C to +125°C
OPA2205
±0.04
±0.08
±0.05
±0.2
±0.5
±0.25
±0.5
±0.5
±1
dVOS/dT Input offset voltage drift
μV/°C
OPAx205A
OPA2205,
VS = ±2.25 V to ±18 V
TA = –40°C to +125°C
TA = –40°C to +125°C
Power supply rejection
PSRR
ratio
μV/V
±0.05
OPAx205A,
VS = ±2.25 V to ±18 V
f = dc
130
110
Channel separation,
(dual, quad)
dB
f = 100 kHz
INPUT BIAS CURRENT
±0.1
±0.1
±0.1
±0.4
±0.6
±0.9
±0.5
±1
TA = 0°C to 85°C
OPA2205
TA = –40°C to +125°C
IB
Input bias current
nA
nA
TA = 0°C to 85°C
OPAx205A
±1.2
±0.4
±0.8
±0.9
TA = –40°C to +125°C
TA = 0°C to 85°C
IOS
Input offset current
Input voltage noise
TA = –40°C to +125°C
NOISE
f = 0.1 Hz to 10 Hz
f = 10 Hz
0.2
7.4
7.2
7.2
μVPP
Input voltage noise
density
en
f = 100 Hz
nV/√Hz
f = 1 kHz
Input current noise
density
in
f = 1 kHz
110
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
V
(V–) + 1
126
(V+) –1.4
140
140
140
140
OPA2205,
(V–) + 1 V < VCM < (V+) –1.4 V
124
TA = –40°C to +125°C
TA = –40°C to +125°C
Common-mode rejection
ratio
CMRR
dB
126
OPAx205A,
(V–) + 1 V < VCM < (V+) –1.4 V
124
INPUT IMPEDANCE
ZID
Differential
9 || 4.4
MΩ|| pF
GΩ|| pF
ZICM
Common-mode
300 || 4.3
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6.8 Electrical Characteristics: VS = ±15 V (continued)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
RL = 10 kΩ,
(V–) + 200 mV < VO
(V+) –200 mV
132
132
126
126
135
135
132
130
<
<
<
<
OPA2205,
TA = –40°C to +125°C
RL = 2 kΩ,
(V–) + 350 mV < VO
(V+) –350 mV
AOL
Open-loop voltage gain
dB
RL = 10 kΩ,
(V–) + 200 mV < VO
(V+) –200 mV
OPAx205A,
TA = –40°C to +125°C
RL = 2 kΩ,
(V–) + 350 mV < VO
(V+) –350 mV
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product CL = 30 pF
3.6
4
MHz
V/μs
Slew rate
10-V step, gain = –1
RL = 10 kΩ, CL = 25 pF
Phase margin
58
2.8
degrees
To 0.024% (12-bit),
10-V step, gain = 1,
CL = 30 pF
Falling
Rising
tS
Settling time
μs
4.5
0.2
Overload recovery time
Gain = –10
μs
Total harmonic distortion
+ noise
THD+N
0.0004
%
VO = 5 VPP, gain = +1, f = 1 kHz, RL = 2 kΩ
OUTPUT
RL = 10 kΩ
RL = 2 kΩ
(V–) + 0.2
(V–) + 0.35
(V–) + 0.2
(V+) –0.2
(V+) –0.35
(V+) –0.2
AOL > 126 dB
Voltage output swing
from rail
V
TA = –40°C to +125°C, RL = 10 kΩ
ISC
Short-circuit current
Capacitive load drive
±25
mA
CLOAD
See Typical Characteristics
See Typical Characteristics
Open-loop output
impedance
RO
POWER SUPPLY
220
240
310
Quiescent current per
amplifier
IQ
IO = 0 mA
μA
TA = –40°C to +125°C
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6.9 Typical Characteristics
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ(unless otherwise noted)
表6-1. Table of Graphs
DESCRIPTION
FIGURE
图6-1
Offset Voltage Production Distribution at 25°C
Offset Voltage at 125°C
图6-2
Offset Voltage at –40°C
图6-3
Offset Voltage vs Temperature
图6-4
Offset Voltage Drift Distribution
图6-5
Offset Voltage vs Output Voltage
图6-6
Offset Voltage vs Power Supply Voltage
Power-Supply Rejection Ratio vs Temperature
Power-Supply and Common-Mode Rejection Ratio vs Frequency
Common-Mode Rejection Ratio vs Temperature
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs VCM at Low Supply
Offset Voltage vs VCM at High Supply
Open-Loop Gain and Phase vs Frequency
Open-Loop Gain vs Swing From the Rail
Open-Loop Gain vs Temperature
图6-7
图6-8
图6-9
图6-10
图6-11
图6-12
图6-13
图6-14
图6-15
图6-16
图6-17
图6-18
图6-19
图6-20
图6-21
图6-22
图6-23
图6-24
图6-25
图6-26
图6-27
图6-28
图6-29
图6-30
图6-31
图6-32
图6-33
图6-34
图6-35
图6-36
图6-37
图6-38
图6-39
图6-40
图6-41
图6-42
图6-43
图6-44
Closed-Loop Gain vs Frequency
Input Bias Production Distribution
Input Bias vs Common-Mode Voltage
Input Bias and Input Offset Current vs Temperature
Input Offset Current Production Distribution
Voltage Noise Density vs Frequency
0.1-Hz to 10-Hz Noise
Total Harmonic Distortion + Noise Ratio vs Frequency
Total Harmonic Distortion + Noise Ratio vs Output Amplitude
Current Noise vs Frequency
Maximum Output Voltage vs Frequency
Output Voltage Swing vs Output Sourcing Current
Output Voltage Swing vs Output Sinking Current
Open-Loop Output Impedance vs Frequency
No Phase Reversal
Small-Signal Overshoot vs Capacitive Load, Gain = +1
Small-Signal Overshoot vs Capacitive Load, Gain = –1
Phase Margin vs Capacitive Load
Positive Overload Recovery, Gain = –1
Negative Overload Recovery, Gain = –1
Settling Time
Small-Signal Step Response, Gain = +1
Small-Signal Step Response, Gain = –1
Large-Signal Step Response, Gain = +1
Large-Signal Step Response, Gain = –1
Short-Circuit Current vs Temperature
Electromagnetic Interference Rejection (EMIRR)
Quiescent Current vs Supply Voltage
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6.9 Typical Characteristics
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ(unless otherwise noted)
表6-1. Table of Graphs (continued)
DESCRIPTION
FIGURE
Quiescent Current vs Temperature
图6-45
25
20
15
10
5
25
20
15
10
5
0
0
-15 -12
-9
-6
-3
0
3
6
9
12
15
-20
-15
-10
-5
0
5
10
15
20
Input Offset Voltage (µV)
Offset Voltage (µV)
TA = 25°C
TA = 125°C
图6-1. Offset Voltage Production Distribution at 25°C
图6-2. Offset Voltage Distribution at 125°C
20
20
10
0
15
10
5
+3 Sigma
–3 Sigma
-10
0
-20
-20
-15
-10
-5
0
5
10
15
20
-50
-25
0
25
50
75
100
125
Offset Voltage (µV)
Temperature (°C)
TA = –40°C
图6-3. Offset Voltage Distribution at -40°C
图6-4. Offset Voltage vs Temperature
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6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ(unless otherwise noted)
15
12
9
10
8
6
4
2
0
6
-2
-4
-6
-8
-10
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
3
0
-0.1 -0.08 -0.06 -0.04 -0.02
0
0.02 0.04 0.06 0.08 0.1
-18
-14
-10
-6
-2
2
6
10
14
18
Offset Voltage Drift (µV/°C)
Output Voltage (V)
图6-5. Offset Voltage Drift Distribution
图6-6. Offset Voltage vs Output Voltage
200
0.0001
10
5
190
180
170
160
150
140
0.001
0.01
0.1
0
-5
-10
-50
-25
0
25
50
75
100
125
0
10
20
30
40
Temperature (°C)
Supply Voltage (V)
图6-7. Offset Voltage vs Power Supply Voltage
图6-8. Power-Supply Rejection Ratio vs Temperature
160
150
140
130
120
0.01
0.1
1
160
140
120
100
80
CMRR
–PSRR
+PSRR
60
40
20
0
1
10
100
1k
10k
100k
1M
10M
-50
-25
0
25
50
75
100
125
Frequency (Hz)
Temperature (°C)
图6-9. Power-Supply and Common-Mode Rejection Ratio vs
图6-10. Common-Mode Rejection Ratio vs Temperature
Frequency
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6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ(unless otherwise noted)
10
15
10
5
5
0
0
-5
-5
-10
-10
-14.5
-14
-13.5
-13
-15
-10
-5
0
5
10
14
Common-mode Voltage (V)
Common-mode Voltage (V)
图6-11. Offset Voltage vs Common-Mode Voltage
图6-12. Offset Voltage vs VCM at Low Supply
15
160
240
Gain
140
120
100
80
Phase 200
160
120
80
10
5
60
40
40
0
0
20
-40
-80
0
-5
12.5
-20
100m
-120
10M
13
13.5
14
1
10
100
1k
10k
100k
1M
Common-mode Voltage (V)
Frequency (Hz)
图6-13. Offset Voltage vs VCM at High Supply
图6-14. Open-Loop Gain and Phase vs Frequency
180
160
140
120
100
80
0.001
0.01
0.1
180
0.001
RL = 2 kohm
RL = 10 kohm
170
160
150
140
130
120
0.01
0.1
1
1
10
100
1000
60
0.09
-50
-25
0
25
50
75
100
125
0.1
0.11
0.12
0.13
0.14
0.15
Temperature (°C)
Swing from the Rail (V)
图6-16. Open-Loop Gain vs Temperature
图6-15. Open-Loop Gain vs Swing From the Rail
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6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ(unless otherwise noted)
50
40
30
20
10
0
24
20
16
12
8
Gain = +1
Gain = –1
Gain = +10
Gain = +100
-10
-20
-30
4
0
100
1k
10k
100k
1M
10M
-500
-250
0
250
500
Frequency (Hz)
Input Bias Current (pA)
图6-17. Closed-Loop Gain vs Frequency
图6-18. Input Bias Production Distribution
2
1.5
1
0.75
0.6
0.45
0.3
0.15
0
TA= –40°C
TA = 25°C
TA = 85°C
TA = 125°C
IB–
IB+
IOS
0.5
0
-0.5
-1
-1.5
-2
-15
-10
-5
0
5
10
15
-50
-25
0
25
50
75
100
125
Common-Mode Voltage (V)
Temperature (°C)
图6-19. Input Bias vs Common-Mode Voltage
图6-20. Input Bias and Input Offset Current vs Temperature
24
20
16
12
8
100
10
4
1
100m
0
1
10
100
1k
10k
100k
-400 -300 -200 -100
0
100
200
300
400
Frequency (Hz)
Input Offset Current (pA)
图6-22. Voltage Noise Density vs Frequency
图6-21. Input Offset Current Production Distribution
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6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ(unless otherwise noted)
-70
G = –1, 10 kohm Load
G = –1, 2 kohm Load
G = +1, 10 kohm Load
G = +1, 2 kohm Load
-80
-90
-100
-110
-120
Time (1 s/div)
100
1k
Frequency (Hz)
10k
图6-24. Total Harmonic Distortion + Noise Ratio
图6-23. 0.1-Hz to 10-Hz Noise
vs Frequency
1000
-60
-66
G = +1, 2 kohm Load
G = –1, 2 kohm Load
G = +1, 10 kohm Load
G = –1, 10 kohm Load
-72
-78
-84
100
-90
-96
-102
-108
-114
-120
10
100m
1
10
100
1k
10k
100k
10m
100m
1
10
Frequency (Hz)
Amplitude (VRMS
)
图6-26. Current Noise vs Frequency
图6-25. Total Harmonic Distortion + Noise Ratio
vs Output Amplitude
40
35
30
25
20
15
10
5
15
12.5
10
Vs = ±18 V
Vs = ±2.25 V
7.5
5
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
2.5
0
0
1
10
100
1k
10k
100k
1M
10M
0
5
10
15
20
25
30
Frequency (Hz)
Output Current (mA)
图6-27. Maximum Output Voltage vs Frequency
图6-28. Output Voltage Swing vs Output Sourcing Current
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6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ(unless otherwise noted)
0
-2.5
-5
1000
100
10
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
-7.5
-10
-12.5
-15
1
10
100
1k
10k
100k
1M
10M
0
5
10
15
20
25
30
Frequency (Hz)
Output Current (mA)
图6-30. Open-Loop Output Impedance vs Frequency
图6-29. Output Voltage Swing vs Output Sinking Current
60
Input (V)
RISO = 0 ohm
RISO = 25 ohm
RISO = 50 ohm
Output (V)
50
40
30
20
10
0
Time (100 µs/div)
30
100
Capactiance (pF)
1000
Gain = 1
图6-32. Small-Signal Overshoot vs Capacitive Load,
图6-31. No Phase Reversal
Gain = +1
80
70
60
50
40
30
20
10
100
RISO = 0 ohm
RISO = 25 ohm
90
RISO = 50 ohm
80
70
60
50
40
30
20
10
0
20
100
1000
30
100
Capactiance (pF)
1000
Capacitance (pF)
Gain = –1
图6-34. Phase Margin vs Capacitive Load
图6-33. Small-Signal Overshoot vs Capacitive Load,
Gain = –1
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6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ(unless otherwise noted)
VOUT
VIN
VOUT
VIN
Time (500 ns/div)
Time (500 ns/div)
Gain = –1
Gain = –1
图6-35. Positive Overload Recovery, Gain = –1
图6-36. Negative Overload Recovery, Gain = –1
3
VOUT (V)
VIN (V)
Falling (mV)
Rising (mV)
2
1
0
-1
-2
-3
2
3
4
5
6
Time (uS)
Time (1 µS/div)
Gain = 1
图6-37. Settling Time
图6-38. Small-Signal Step Response, Gain = +1
VOUT (V)
VIN (V)
VIN (V)
VOUT (V)
Time (1 µS/div)
Time (2 µS/div)
Gain = 1
Gain = –1
图6-40. Large-Signal Step Response, Gain = +1
图6-39. Small-Signal Step Response, Gain = –1
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6.9 Typical Characteristics (continued)
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ(unless otherwise noted)
28
VOUT (V)
VIN (V)
25
22
19
16
13
Positive Output Voltage
Negative Output Voltage
10
-50
-25
0
25
50
75
100
125
Temperature (°C)
Time (2 µS/div)
Gain = –1
图6-41. Large-Signal Step Response, Gain = –1
图6-42. Short-Circuit Current vs Temperature
140
250
200
150
100
50
130
120
110
100
90
80
Vs = 4.5V
70
60
50
40
0
10
100
Frequency (MHz)
1000
6000
0
8
16
24
32
40
Supply Voltage (V)
图6-43. Electromagnetic Interference Rejection
图6-44. Quiescent Current vs Supply Voltage
360
320
280
240
200
160
120
-50
-25
0
25
50
75
100
125
Temperature (°C)
图6-45. Quiescent Current vs Temperature
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7 Parameter Measurement Information
7.1 Typical Specifications and Distributions
To design a more robust circuit, designers often have questions about a typical specification of an amplifier. As a
result of natural variations in process technology and manufacturing procedures, every specification of an
amplifier exhibits some amount of deviation from the ideal value, such as the input bias current of an amplifier.
These deviations often follow Gaussian (bell curve), or normal distributions. Circuit designers can leverage this
information to guard-band their system, even when there is no minimum or maximum specification in the
Electrical Characteristics.
0.00312% 0.13185%
0.13185% 0.00312%
0.00002%
0.00002%
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1 1 1 1 1 1 1 1
1
1
1
ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1
ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61
ꢀ
图7-1. Ideal Gaussian Distribution
图 7-1 shows an example distribution, where µ, is the mean of the distribution, and where σ, or sigma, is the
standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-thirds
(68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the mean
(from µ –σto µ + σ).
Depending on the specification, values listed in the typical column of Electrical Characteristics are represented in
different ways. As a general guideline, if a specification naturally has a nonzero mean (for example, gain
bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near
zero (for example, input bias current), then the typical value is equal to the mean plus one standard deviation
(µ + σ) to most accurately represent the typical value.
Use this chart to calculate the approximate probability of a specification in a unit. For example, the OPAx205
typical input bias current is ±0.1 nA; therefore, 68.2% of all devices are expected to have an input bias from
±0.1 nA. At 4σ, 99.9937% of the distribution has an input bias less than ±0.28 nA, which means that 0.0063% of
the population is outside of these limits, and corresponds to approximately 1 in 15,873 units.
Units that are found to exceed any tested minimum or maximum specifications are removed from production
material. For example, the OPAx205 have a maximum input bias of ±0.5 nA at 25°C. Although this value
corresponds to approximately 6σ (approximately 1 in 500 million units), TI removes any unit with a larger input
bias from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guard band for your application, and design worst-case conditions using this value. Use this
information to only estimate the performance of a device.
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8 Detailed Description
8.1 Overview
The OPAx205 are the first 36-V bipolar, e-trim operational amplifiers that uses a package-level offset trim to
minimize the offset voltage and offset voltage drift introduced during the manufacturing process. This trim is
performed after the device has been assembled to remove any offset errors introduced throughout the
manufacturing process, and trim communication is disabled afterward. These devices also feature super-beta
inputs that decrease the input bias current and input current noise.
The following section shows the simplified diagram of the OPAx205.
8.2 Functional Block Diagram
V+
e-trimTM
Pre-Driver
OUT
Super Beta
+IN
IN
Input Devices
Overload
Power
Limiter
V
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8.3 Feature Description
8.3.1 Input Offset Trimming
The OPAx205 are the industry's first e-trim operational amplifiers built on a bipolar process. The input offset
voltage of an amplifier is determined by the inherent mismatch between the input transistors. The offset can be
minimized using laser-trimming performed during the manufacturing process while the devices are still in the
bare silicon form. However, when the silicon is packaged, the packaging process introduces additional offset due
to mechanic stresses. TI's new trimming processes are used to trim the offset after the packaging process is
complete to minimize both inherent and package-induced offsets. After trimming, communication is disabled to
make sure the amplifiers operate properly in the final system.
A comparison between production offset values for the industry-popular, laser-trimmed OPA2277 and the
OPAx205 proprietary trim can be seen in 图8-1 and 图8-2.
25
20
15
10
5
16
14
12
10
8
Typical distribution
of packaged units.
Single, dual, and
quad included.
6
4
2
0
0
–50–45–40–35–30–25–20–15–10–5
0 5 10 15 20 25 30 35 40 45 50
-50 -40 -30 -20 -10
0
10
20
30
40
50
Offset Voltage (µV)
Input Offset Voltage (µV)
图8-1. OPA2277 Laser-Trimmed Operational
图8-2. OPAx205 e-trim™ Operational Amplifier
Amplifier Offset
Offset
The OPAx205 are also trimmed at two temperatures to minimize the input offset voltage drift over temperature.
The final performance of the offset drift can be seen in 图8-3.
15
12
9
6
3
0
-0.1 -0.08 -0.06 -0.04 -0.02
0
0.02 0.04 0.06 0.08 0.1
Offset Voltage Drift (µV/°C)
图8-3. OPAx205 e-trim™ Operational Amplifier Drift
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8.3.2 Lower Input Bias With Super-Beta Inputs
The OPAx205 have a super-beta input transistor architecture. In a transistor, the beta value is the ratio between
the current flowing into the base and the current flowing from the collector to the emitter. A super-beta transistor
is one where the beta value has been increased from several hundred to thousands. In a bipolar amplifier, the
input bias current is the current flowing into the base of the input transistor pair, as well as a small leakage
current that flows through the ESD diodes. A super-beta input reduces the input bias current of the amplifier. In
addition, the super-beta inputs lower the input current noise that is directly related to the input bias current of the
device. A comparison between the input bias current of the OPA2277 and the OPAx205 super-beta input bias
currents can be seen in 图8-4 and 图8-5.
5
4
6
5
IBN
IBP
4
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
-1
-2
-3
-4
-5
Curves represent typical
production units.
–75
–50
–25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
图8-4. OPA2277 Input Bias Current
图8-5. OPAx205 Super-Beta Input Bias Current
8.3.3 Overload Power Limiter
In many bipolar-based amplifiers, the output stage of the amplifier can draw significant (several milliamperes) of
quiescent current if the output voltage becomes clipped (that is, the output voltage becomes limited by the
negative or positive supply voltage). This condition can cause the system to enter a high-power consumption
state, and potentially cause oscillations between the power supply and signal chain. The OPAx205 have an
advanced output stage design that eliminates this problem. When the output voltage reaches either supply (V+
or V–), there is virtually no additional current consumption from the nominal quiescent current. This feature
helps eliminate any potential system problems when the signal chain is disrupted by large external transient
voltage.
8.3.4 EMI Rejection
The OPAx205 use integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources, such as wireless communications and densely populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved through circuit design techniques that improve the system
performance. Additional information can be found in the EMI Rejection Ratio of Operation Amplifiers application
report.
8.4 Device Functional Modes
The OPAx205 have a single functional mode and are operational with any supply between 4.5 V (±2.25 V) and
36 V (±18 V).
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
9.1 Application Information
The OPAx205 are unity-gain stable operational amplifiers with very low offset voltage, offset voltage drift, voltage
noise, current noise and power consumption. These features make this device family a great choice for a variety
of space-constrained and power-constrained systems.
9.2 Typical Applications
9.2.1 High-Precision Signal-Chain Input Buffer
A common application for the OPAx205 is an input buffer for the signal chain of a data acquisition (DAQ) or field
instrumentation system. This amplifier family is selected because of the low offset and drift that maintain system
accuracy across a variety of operating conditions. The low power consumption of the OPAx205 enables the
device to be used in battery-operated or high-density applications, where thermal dissipation is difficult. The low
1/f (flicker) noise and broadband noise allow for higher-accuracy signal chains, such as those using a 24-bit
delta-sigma analog-to-digital converter (ADC). If a higher sampling rate is needed, the OPAx205 can be paired
with a fully differential amplifier, such as the THP210, to drive the ADC inputs. 图 9-1 shows the OPA2205
configured as an input buffer to a differential ADC driver.
750 ꢀ
470 pF
+7 V
3 kꢀ
œ
2.4 kꢀ
IN+
+
OPA2205
Þ7 V
100 ꢀ
100 ꢀ
+7 V
œ
1.1 nF
1 nF
VOUT
+
THP210
Þ7 V
+7 V
2.4 kꢀ
3 kꢀ
œ
INÞ
+
470 pF
OPA2205
Þ7 V
750 ꢀ
图9-1. OPA2205 Configured as a DAQ Input Buffer
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9.2.1.1 Design Requirements
The design requirements for this application are:
• Input range: ±10 V
• Input frequency: 10 kHz
• Output voltage: ±3.3 V
• Quiescent current: < 1.5 mA
9.2.1.2 Detailed Design Procedure
In this application, the input signal ranges from –10 V to +10 V with a frequency of up to 10 kHz. Because of
possible portable-use cases for this data acquisition system (DAQ), low power consumption is required to
minimize battery drain and thermal dissipation requirements.
To maintain high system accuracy the OPA2205 is selected as input buffers. This device is selected because of
the high dc precision (4 µV offset and 0.08 µV/°C offset drift), low flicker noise (0.2 µVpp), and low quiescent
current (220 µA). The buffers are followed by a high-precision, fully differential amplifier such as the THP210,
which is capable of accurately driving a 24-bit, fully differential ADC such as the ADS127L01.
9.2.1.3 Application Curves
The gain plot for this system can be seen in 图9-2. This plot shows proper attenuation of the ±10-V signal to the
target ±3.3-V output, and adequate bandwidth to support the input frequency range.
0
-25
-50
-75
-100
-125
-150
10
100
1K
10K 100K
Frequency (Hz)
1M
10M
100M
图9-2. Gain Plot of DAQ Front End
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9.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier
图 9-3 shows the OPA2205 configured as a two-op-amp, discrete instrumentation amplifier. This configuration
allows for a differential signal measurement, such as the signal from a load cell, with higher input impedance to
the signal chain than most monolithic instrumentation amplifiers. The strong ac and dc performance of the
OPA2205 enables high accuracy measurements.
V+
V1
+
–
V
OUT = (V1 – V2)(1 + R2/R1)
OPA2205
R2
V
V+
R1
V2
+
–
OPA2205
V
R2
R1
GND
图9-3. OPA2205 Configured as a Two-Op-Amp, Discrete Instrumentation Amplifier
9.2.3 Second-Order Low-Pass Filter
The OPAx205 has a very-low broadband voltage noise of only 7.2 nV/√Hz and flicker noise of 0.2 µVPP given
the low power consumption of only 220 µA, making this device an excellent choice for low-power filter
applications. 图 9-4 is an example of one channel of the OPAx205 configured as a second-order low-pass filter
with a cutoff frequency of 50 kHz.
2.25 k
1 nF
2.25 k
1.13 k
Input
–
+
Output
4 nF
GND
GND
图9-4. Second-Order Low-Pass Filter
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9.3 Power Supply Recommendations
The OPAx205 operate with a power supply between 4.5 V to 36 V (±2.25 V to ±18 V). Parameters that can
exhibit significant variance with regard to operating voltage are presented in 节6.9.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see 节9.4.1.
9.4 Layout
9.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications. Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as
well as through the individual op amp. Bypass capacitors are used to reduce the coupled noise by providing
low-impedance power sources local to the analog circuitry.
• Make sure to physically separate digital and analog grounds paying attention to the flow of the ground
current. Separate grounding for analog and digital portions of circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in 图9-5, keep RF and RG
close to the inverting input to minimize parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Clean the PCB following board assembly for best performance.
• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic
package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced
into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.
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9.4.2 Layout Example
VIN
+
VOUT
RG
RF
图9-5. Schematic Representation
Place components
close to device and to
each other to reduce
parasitic errors
Run the input traces
as far away from
the supply lines
as possible
RF
VS+
NC
NC
RG
Use a low-ESR,
V+
GND
VIN
–IN
+IN
V–
ceramic bypass
capacitor
OUTPUT
NC
GND
GND
VS–
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
图9-6. Operational Amplifier Board Layout for Noninverting Configuration
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Development Support
The following evaluation modules are available:
• DIP-ADAPTER-EVM
• DIYAMP-EVM
10.1.1.1 PSpice® for TI
PSpice® for TI 是可帮助评估模拟电路性能的设计和仿真环境。在进行布局和制造之前创建子系统设计和原型解决
方案,可降低开发成本并缩短上市时间。
10.2 文档支持
10.2.1 相关文档
请参阅以下相关文档:
• 德州仪器(TI),DIP-ADAPTER-EVM 用户指南
• 德州仪器(TI),DIYAMP-SOIC-EVM 用户指南
10.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
10.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
10.5 Trademarks
e-trim™ and TI E2E™ are trademarks of Texas Instruments.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
所有商标均为其各自所有者的财产。
10.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA205ADR
OPA205ADT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OP205A
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Call TI
OP205A
22A5
OPA2205ADGKR
OPA2205ADGKT
OPA2205ADR
OPA2205ADT
OPA4205ADR
OPA4205ADT
OPA4205APWR
OPA4205APWT
XOPA205ADR
XOPA2205DGKR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
22A5
8
2205A
SOIC
D
8
2205A
SOIC
D
14
14
14
14
8
OPA4205A
OPA4205A
OP4205A
OP4205A
SOIC
D
TSSOP
TSSOP
SOIC
PW
PW
D
250
3000
2500
RoHS & Green
TBD
VSSOP
DGK
8
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2023
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA205ADR
OPA205ADT
SOIC
SOIC
D
D
8
8
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
16.4
16.4
12.4
12.4
6.4
6.4
5.3
5.3
6.4
6.4
6.5
6.5
6.9
6.9
5.2
5.2
3.4
3.4
5.2
5.2
9.0
9.0
5.6
5.6
2.1
2.1
1.4
1.4
2.1
2.1
2.1
2.1
1.6
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
OPA2205ADGKR
OPA2205ADGKT
OPA2205ADR
OPA2205ADT
OPA4205ADR
OPA4205ADT
OPA4205APWR
OPA4205APWT
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
2500
250
8
8
3000
250
SOIC
D
8
SOIC
D
14
14
14
14
3000
250
SOIC
D
TSSOP
TSSOP
PW
PW
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA205ADR
OPA205ADT
SOIC
SOIC
D
D
8
8
3000
250
356.0
210.0
356.0
210.0
356.0
210.0
356.0
210.0
356.0
210.0
356.0
185.0
356.0
185.0
356.0
185.0
356.0
185.0
356.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
OPA2205ADGKR
OPA2205ADGKT
OPA2205ADR
OPA2205ADT
OPA4205ADR
OPA4205ADT
OPA4205APWR
OPA4205APWT
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
2500
250
8
8
3000
250
SOIC
D
8
SOIC
D
14
14
14
14
3000
250
SOIC
D
TSSOP
TSSOP
PW
PW
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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