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OPA3693IDBQRG4 [TI]

具有禁用功能的三路、超宽带、固定增益、视频缓冲器 | DBQ | 16;
OPA3693IDBQRG4
型号： OPA3693IDBQRG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

具有禁用功能的三路、超宽带、固定增益、视频缓冲器 | DBQ | 16
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OPA3693  
www.ti.com ............................................................................................................................................ SBOS353A–DECEMBER 2006–REVISED AUGUST 2008  
Triple, Ultra-Wideband, Fixed-Gain,  
VIDEO BUFFER with Disable  
1
FEATURES  
DESCRIPTION  
2
•
650MHz BANDWIDTH (G = +2)  
The OPA3693 provides an easy to use, broadband,  
triple, fixed-gain buffer amplifier. Depending on the  
external connections, the internal resistor network  
may be used to provide either a fixed gain of +2  
video buffer or a gain of +1 or –1 voltage buffer. The  
•
•
•
•
FIXED GAIN OF ±1 or +2  
OUTPUT VOLTAGE SWING: ±4.1V  
ULTRA-HIGH SLEW RATE: 2500V/µs  
3RD-ORDER INTERCEPT: > 40dBm  
(f < 50MHz)  
OPA3693 offers  
a
slew rate (2500V/µs) and  
bandwidth (> 800MHz) normally associated with a  
much higher supply current. A new output stage  
architecture delivers high output current with a  
minimal headroom and crossover distortion. This  
combination of features makes the OPA3693 an ideal  
RGB line driver or single-supply undersampling  
analog-to-digital converter (ADC) input driver.  
•
•
LOW POWER: 130mW/channel  
LOW DISABLED POWER: 0.4mW/channel  
APPLICATIONS  
•
MULTIPLE LINE VIDEO DISTRIBUTION  
AMPLIFIER (DA)  
The OPA3693 13mA/channel supply current is  
precisely trimmed at +25°C. This trim, along with a  
low temperature drift, gives lower system power over  
temperature. System power can be further reduced  
using the optional disable control pin. Leaving this pin  
open, or holding it HIGH, gives normal operation. If  
pulled LOW, the OPA3693 supply current drops to  
less than 130µA/channel. This power-saving feature,  
along with exceptional single +5V operation, make  
the OPA3693 ideal for portable applications. The  
OPA3693 is available in an SSOP-16 package.  
•
•
•
•
PORTABLE INSTRUMENTS  
BROADBAND VIDEO LINE DRIVERS  
ADC BUFFERS  
HIGH-FREQUENCY ACTIVE FILTERS  
VR  
VG  
VB  
75W  
75W  
75W  
75W Cable  
1/3  
OPA3693  
75W  
75W  
75W  
RG-59  
300W  
300W  
300W  
300W  
OPA3693 RELATED PRODUCTS  
FEATURE  
SINGLES  
DUALS  
TRIPLES  
75W Cable  
1/3  
OPA3693  
Voltage  
Feedback  
OPA690  
OPA2690  
OPA3690  
RG-59  
Current  
Feedback  
OPA691  
OPA2691  
OPA3691  
300W  
Fixed Gain  
Fixed Gain  
>900MHz  
OPA692  
OPA693  
OPA695  
—
—
OPA3692  
—
75W Cable  
OPA2695  
OPA3695  
1/3  
OPA3693  
RG-59  
300W  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006–2008, Texas Instruments Incorporated  
OPA3693  
SBOS353A–DECEMBER 2006–REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ORDERING INFORMATION(1)  
SPECIFIED  
PACKAGE  
DESIGNATOR  
TEMPERATURE  
RANGE  
PACKAGE  
MARKING  
ORDERING  
NUMBER  
TRANSPORT MEDIA,  
QUANTITY  
PRODUCT  
PACKAGE  
OPA3693IDBQ  
Rail, 75  
OPA3693  
SSOP-16  
DBQ  
–40°C to +85°C  
OP3693  
OPA3693IDBQR  
Tape and Reel, 2500  
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS(1)  
Power Supply  
±6.5VDC  
Internal Power Dissipation  
Differential Input Voltage  
See Thermal Analysis  
±1.2V  
Input Common-Mode Voltage Range  
Storage Temperature Range  
Lead Temperature (soldering, 10s)  
±VS  
–65°C to +125°C  
+300°C  
Peak  
+150°C  
Maximum Junction  
Temperature, TJ  
Continuous Operation, Long-Term Reliability  
Human Body Model (HBM)  
Charge Device Model (CDM)  
+140°C  
1500V  
ESD Rating  
1000V  
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these and any other conditions beyond  
those specified is not supported.  
Top View  
SSOP  
OPA3693  
300W  
300W  
300W  
300W  
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
-IN A  
+IN A  
DIS B  
-IN B  
+IN B  
DIS A  
+VS  
CH A  
OUT A  
300W  
-VS  
OUT B  
+VS  
CH B  
DIS C  
-IN C  
+IN C  
300W  
OUT C  
-VS  
CH C  
2
Submit Documentation Feedback  
Copyright © 2006–2008, Texas Instruments Incorporated  
Product Folder Link(s): OPA3693  
 
OPA3693  
www.ti.com ............................................................................................................................................ SBOS353A–DECEMBER 2006–REVISED AUGUST 2008  
ELECTRICAL CHARACTERISTICS: VS = ±5V  
Boldface limits are tested at +25°C.  
At G = +2 (–IN grounded) and RL = 100Ω, unless otherwise noted.  
OPA3693IDBQ  
TYP  
MIN/MAX OVER TEMPERATURE  
0°C to –40°C to  
TEST  
MIN/  
MAX  
LEVEL  
(1)  
PARAMETER  
CONDITIONS  
+25°C  
+25°C(2) +70°C(3) +85°C(3)  
UNITS  
AC PERFORMANCE  
Small-Signal Bandwidth (VO = 1.0VPP  
)
G = +1  
G = +2  
800  
650  
650  
320  
3
MHz  
MHz  
MHz  
MHz  
dB  
typ  
min  
min  
min  
max  
typ  
C
B
B
B
B
C
B
B
B
C
C
500  
500  
120  
4.3  
480  
480  
110  
5.3  
470  
470  
105  
5.7  
G = –1  
Bandwidth for 0.2dB Gain Flatness  
Peaking at a Gain of +1  
Large-Signal Bandwidth  
Slew Rate  
VO = 1.0VPP  
VO = 1.0VPP  
VO = 4VPP  
380  
2500  
0.6  
1.2  
16  
MHz  
V/µs  
ns  
VO = 4V Step  
VO = 0.5V Step  
VO = 5V Step  
VO = 2V Step  
VO = 2V Step  
f = 10MHz, VO = 2VPP  
RL = 100Ω  
2200  
0.8  
2100  
0.8  
2000  
0.9  
min  
max  
max  
typ  
Rise-and-Fall Time  
1.3  
1.3  
1.4  
ns  
Settling Time to 0.02%  
Settling Time to 0.1%  
Harmonic Distortion  
2nd-Harmonic  
ns  
12  
ns  
typ  
–75  
–80  
–78  
–84  
1.8  
–66  
–78  
–75  
–80  
2
–65  
–77  
–65  
–79  
2.7  
21  
–64  
–76  
–64  
–76  
2.9  
22  
dBc  
dBc  
max  
max  
max  
max  
max  
max  
max  
typ  
B
B
B
B
B
B
B
C
C
C
C
C
R
L ≥ 500Ω  
RL = 100Ω  
L ≥ 500Ω  
3rd-Harmonic  
dBc  
R
dBc  
Input Voltage Noise  
f > 1MHz  
f > 1MHz  
nV/√Hz  
pA/√Hz  
pA/√Hz  
%
Noninverting Input Current Noise  
18  
19  
Inverting Input Current Noise (internal)  
Differential Gain  
f > 1MHz  
22  
24  
26  
27  
NTSC, RL = 150Ω  
NTSC, RL = 37.5Ω  
NTSC, RL = 150Ω  
NTSC, RL = 37.5Ω  
f = 10MHz  
0.03  
0.03  
0.01  
0.1  
%
typ  
Differential Phase  
deg  
typ  
deg  
typ  
Crosstalk (2 channels driven)  
DC PERFORMANCE(4)  
Gain Error  
–65  
dBc  
typ  
G = +1  
G = +2  
±0.7  
±0.6  
±0.5  
%
%
%
typ  
C
A
B
±1.0  
1.1  
1.0  
1.2  
1.1  
max  
max  
G = –1, Rs = 0Ω  
±0.9  
Internal RF and RG  
Maximum  
300  
300  
±0.6  
341  
264  
±3.5  
345  
260  
±3.7  
±8  
347  
258  
±4.0  
±8  
Ω
Ω
max  
min  
A
A
A
B
A
B
A
B
Minimum  
Input Offset Voltage  
VCM = 0V  
VCM = 0V  
VCM = 0V  
VCM = 0V  
VCM = 0V  
VCM = 0V  
mV  
max  
max  
max  
max  
max  
max  
Average Offset Voltage Drift  
Noninverting Input Bias Current  
Average Noninverting Input Bias Current Drift  
Inverting Input Bias Current (internal)  
Average Inverting Input Bias Current Drift  
µV/°C  
µA  
+15  
±20  
±35  
±50  
±43  
170  
±52  
50  
±45  
170  
±54  
60  
nA/°C  
µA  
nA/°C  
(1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization  
and simulation. (C) Typical value only for information.  
(2) Junction temperature = ambient for +25°C specifications.  
(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +27°C at high temperature limit for over  
temperature specifications.  
(4) Current is considered positive out of pin.  
Copyright © 2006–2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): OPA3693  
OPA3693  
SBOS353A–DECEMBER 2006–REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com  
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)  
Boldface limits are tested at +25°C.  
At G = +2 (–IN grounded) and RL = 100Ω, unless otherwise noted.  
OPA3693IDBQ  
TYP  
MIN/MAX OVER TEMPERATURE  
0°C to –40°C to  
TEST  
MIN/  
MAX  
LEVEL  
(1)  
PARAMETER  
CONDITIONS  
+25°C  
+25°C(2) +70°C(3) +85°C(3)  
UNITS  
INPUT  
Common-Mode Input Voltage Range (CMIR)  
Noninverting Input Impedance  
OUTPUT  
±3.4  
±3.3  
±3.2  
±3.2  
V
min  
typ  
B
C
300 || 1.2  
kΩ || pF  
Voltage Output Swing  
No Load  
100Ω Load  
±4.1  
±3.8  
±100  
0.18  
±3.9  
±3.7  
±85  
±3.9  
±3.7  
±80  
±3.8  
±3.7  
±70  
V
V
min  
min  
min  
typ  
A
A
A
C
Current Output: Sinking, Sourcing  
Closed-Loop Output Impedance  
DISABLE (Disabled LOW)  
Power-Down Supply Current (+VS)  
Disable Time  
VO = 0  
mA  
Ω
G = +2, f = 100kHz  
VDIS = 0, All Channels  
VIN = ±0.25VDC  
–390  
1
–600  
–650  
–665  
µA  
µs  
ns  
dB  
pF  
mV  
mV  
V
typ  
typ  
A
C
C
C
C
C
C
A
A
A
Enable Time  
VIN = ±0.25VDC  
25  
typ  
Off Isolation  
G = +2, 10MHz  
70  
typ  
Output Capacitance in Disable  
Turn-On Glitch  
4
typ  
G = +2, VIN = 0  
G = +2, VIN = 0  
±100  
±20  
3.3  
1.8  
75  
typ  
Turn-Off Glitch  
typ  
Enable Voltage  
3.5  
1.7  
3.6  
1.6  
3.7  
1.5  
min  
max  
max  
Disable Voltage  
V
Control Pin Input Bias Current (DIS)  
POWER SUPPLY  
VDIS = 0, Each Channel  
130  
143  
149  
µA  
Specified Operating Voltage  
Minimum Operating Voltage  
Maximum Operating Voltage  
Maximum Quiescent Current  
Minimum Quiescent Current  
Power-Supply Rejection Ratio (–PSRR)  
TEMPERATURE RANGE  
Specification: IDBQ  
±5  
V
V
typ  
min  
max  
max  
min  
typ  
C
B
A
A
A
A
±1.75  
±6  
±1.8  
±6  
±1.9  
±6  
V
VS = ±5V  
VS = ±5V  
39  
39  
62  
41  
42.2  
34.8  
50  
43.5  
33  
mA  
mA  
dB  
37.5  
52  
Input-Referred, f < 100kHz  
49  
–40 to +85  
80  
°C  
typ  
typ  
C
C
Thermal Resistance, θJA  
DBQ SSOP-16  
Junction-to-Ambient  
°C/W  
4
Submit Documentation Feedback  
Copyright © 2006–2008, Texas Instruments Incorporated  
Product Folder Link(s): OPA3693  
OPA3693  
www.ti.com ............................................................................................................................................ SBOS353A–DECEMBER 2006–REVISED AUGUST 2008  
ELECTRICAL CHARACTERISTICS: VS = +5V  
Boldface limits are tested at +25°C.  
At G = +2 (–IN grounded) and RL = 100Ω to VS/2, unless otherwise noted.  
OPA3693IDBQ  
TYP  
MIN/MAX OVER TEMPERATURE  
0°C to –40°C to  
TEST  
MIN/  
MAX  
LEVEL  
(1)  
PARAMETER  
CONDITIONS  
+25°C  
+25°C(2) +70°C(3) +85°C(3)  
UNITS  
AC PERFORMANCE (see Figure 29)  
Small-Signal Bandwidth (VO = 0.5VPP  
)
G = +1  
G = +2  
600  
500  
450  
280  
2.2  
MHz  
MHz  
typ  
C
B
C
B
B
C
B
C
C
C
C
400  
390  
380  
min  
G = –1  
Bandwidth for 0.2dB Gain Flatness  
Peaking at a Gain of +1  
Large-Signal Bandwidth  
Slew Rate  
VO < 0.5VPP  
VO < 0.5VPP  
VO = 2VPP  
110  
2.9  
100  
3.9  
96  
MHz  
dB  
min  
max  
typ  
4.2  
425  
1500  
0.8  
MHz  
V/µs  
ns  
2V Step  
1200  
1100  
1000  
min  
typ  
Rise-and-Fall Time  
VO = 0.5V Step  
VO = 2V Step  
VO = 2V Step  
VO = 2V Step  
f = 10MHz, VO = 2VPP  
RL = 100Ω to VS/2  
1.0  
ns  
typ  
Settling Time to 0.02%  
Settling Time to 0.1%  
Harmonic Distortion  
2nd-Harmonic  
16  
ns  
typ  
12  
ns  
typ  
–72  
–73  
–67  
–67  
1.8  
18  
–62  
–67  
–62  
–62  
2
–62  
–66  
–61  
–61  
2.7  
21  
–61  
–66  
–60  
–60  
2.9  
22  
dBc  
dBc  
max  
max  
max  
max  
max  
max  
max  
B
B
B
B
B
B
B
R
L ≥ 500Ω to VS/2  
3rd-Harmonic  
RL = 100Ω to VS/2  
dBc  
R
L ≥ 500Ω to VS/2  
dBc  
Input Voltage Noise  
f > 1MHz  
nV/√Hz  
pA/√Hz  
pA/√Hz  
Noninverting Input Current Noise  
f > 1MHz  
19  
Inverting Input Current Noise (internal)  
DC PERFORMANCE(4)  
Gain Error  
f > 1MHz  
22  
24  
26  
27  
G = +1  
G = +2  
±0.8  
±0.6  
±0.5  
%
%
%
typ  
C
A
B
± 1.2  
±1.3  
±1.2  
±1.4  
±1.3  
max  
max  
G = –1, Rs = 0Ω  
±1.1  
Internal RF and RG  
Maximum  
300  
300  
±0.6  
341  
264  
±3.5  
345  
260  
±4.0  
±12  
±33  
±170  
±52  
±50  
347  
258  
±4.2  
±12  
±35  
±170  
±54  
±60  
Ω
Ω
max  
min  
A
A
A
B
A
B
A
B
Minimum  
Input Offset Voltage  
VCM = VS/2  
VCM = VS/2  
VCM = VS/2  
VCM = VS/2  
VCM = VS/2  
VCM = VS/2  
mV  
max  
max  
max  
max  
max  
max  
Average Offset Voltage Drift  
Noninverting Input Bias Current  
Average Noninverting Input Bias Current Drift  
Inverting Input Bias Current (internal)  
Average Inverting Input Bias Current Drift  
µV/°C  
µA  
±5  
±25  
±50  
nA/°C  
µA  
±20  
nA/°C  
(1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization  
and simulation. (C) Typical value only for information.  
(2) Junction temperature = ambient for +25°C specifications.  
(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +14°C at high temperature limit for over  
temperature specifications.  
(4) Current is considered positive out of pin.  
Copyright © 2006–2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): OPA3693  
OPA3693  
SBOS353A–DECEMBER 2006–REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com  
ELECTRICAL CHARACTERISTICS: VS = +5V (continued)  
Boldface limits are tested at +25°C.  
At G = +2 (–IN grounded) and RL = 100Ω to VS/2, unless otherwise noted.  
OPA3693IDBQ  
TYP  
MIN/MAX OVER TEMPERATURE  
0°C to –40°C to  
TEST  
MIN/  
MAX  
LEVEL  
(1)  
PARAMETER  
CONDITIONS  
+25°C  
+25°C(2) +70°C(3) +85°C(3)  
UNITS  
INPUT  
Least Positive Input Voltage  
Most Positive Input Voltage  
Noninverting Input Impedance  
OUTPUT  
1.6  
3.4  
1.7  
3.3  
1.8  
3.2  
1.8  
3.2  
V
V
max  
min  
typ  
B
B
C
300 || 1.2  
kΩ || pF  
Most Positive Output Voltage  
No Load  
RL = 100Ω Load to VS/2  
No Load  
4.2  
4.0  
4.0  
3.9  
1.0  
1.1  
±85  
V
V
min  
min  
max  
max  
min  
typ  
A
A
A
A
A
C
Least Positive Output Voltage  
0.8  
V
RL = 100Ω Load to VS/2  
VO = VS/2  
1.0  
V
Current Output Sourcing, Sinking  
Closed-Loop Output Impedance  
DISABLE (Disabled LOW)  
Power-Down Supply Current (+VS)  
Disable Time  
±100  
0.18  
±80  
±70  
mA  
Ω
G = +2, f = 100kHz  
VDIS = 0, All Channels  
G = +2, 10MHz  
–400  
1
–550  
-600  
-625  
µA  
µs  
ns  
dB  
pF  
mV  
mV  
V
typ  
typ  
typ  
typ  
typ  
typ  
typ  
min  
max  
typ  
C
C
C
C
C
C
C
B
B
C
Enable Time  
25  
Off Isolation  
70  
Output Capacitance in Disable  
Turn-On Glitch  
4
G = +2, VIN = VS/2  
G = +2, VIN = VS/2  
±100  
±20  
3.3  
1.8  
75  
Turn-Off Glitch  
Enable Voltage  
3.5  
1.7  
3.6  
1.6  
3.7  
1.5  
Disable Voltage  
V
Control Pin Input Bias Current (DIS)  
POWER SUPPLY  
VDIS = 0, Each Channel  
130  
143  
149  
µA  
Specified Single-Supply Operating Voltage  
Minimum Operating Voltage  
Maximum Single-Supply Operating Voltage  
Maximum Quiescent Current  
Minimum Quiescent Current  
Power-Supply Rejection Ratio (+PSRR)  
TEMPERATURE RANGE  
Specification: IDBQ  
5
V
V
typ  
min  
max  
max  
min  
typ  
C
B
A
A
A
C
+3.5  
+12  
36.5  
32  
+3.6  
+12  
38  
+3.8  
+12  
V
VS = +5V  
VS = +5V  
34.5  
34.5  
53  
39.2  
27.2  
mA  
mA  
dB  
28.1  
Input-Referred  
–40 to +85  
80  
°C  
typ  
typ  
C
C
Thermal Resistance, θJA  
DBQ SSOP-16  
Junction-to-Ambient  
°C/W  
6
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TYPICAL CHARACTERISTICS: ±5V  
At G = +2 (–IN grounded) and RL = 100Ω, unless otherwise noted.  
NONINVERTING SMALL-SIGNAL  
FREQUENCY RESPONSE  
NONINVERTING LARGE-SIGNAL  
FREQUENCY RESPONSE  
3
2
8
7
G = +1V/V  
1
6
G = +2V/V  
VO = 2VPP  
0
5
-1  
-2  
-3  
-4  
-5  
-6  
4
VO = 1VPP  
3
VO = 7VPP  
G = -1V/V  
2
VO = 4VPP  
1
0
-1  
10M  
100M  
1G  
0
100  
200  
300  
400  
500  
600  
700  
800  
Frequency (Hz)  
Figure 1.  
Frequency (MHz)  
Figure 2.  
FREQUENCY RESPONSE FLATNESS vs LOAD  
DEVIATION FROM LINEAR PHASE  
0.2  
0.1  
1.00  
0.75  
0.50  
0.25  
0
RL = 100W  
RL = 150W  
G = +1  
RL = 75W  
G = -1  
0
RL = 100W  
-0.1  
-0.2  
-0.3  
-0.4  
RL = 200W  
-0.25  
-0.50  
-0.75  
-1.00  
G = +2  
0
100  
200  
300  
400  
500  
0
50  
100  
150  
200  
Frequency (MHz)  
Frequency (MHz)  
Figure 3.  
Figure 4.  
GAIN OF +2 PULSE RESPONSE  
GAIN OF +1 PULSE RESPONSE  
3
2
3
2
Large Signal  
Large Signal  
1
1
Small Signal  
Small Signal  
0
0
-1  
-2  
-3  
-1  
-2  
-3  
Time (20ns/div)  
Time (20ns/div)  
Figure 5.  
Figure 6.  
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TYPICAL CHARACTERISTICS: ±5V (continued)  
At G = +2 (–IN grounded) and RL = 100Ω, unless otherwise noted.  
10MHz HARMONIC DISTORTION vs  
LOAD RESISTANCE  
10MHz HARMONIC DISTORTION vs  
SUPPLY VOLTAGE  
-60  
-65  
-70  
-75  
-80  
-85  
-60  
-65  
-70  
-75  
-80  
-85  
-90  
G = +2V/V  
VO = 2VPP  
G = +2V/V  
VO = 2VPP  
2nd-Harmonic  
2nd-Harmonic  
3rd-Harmonic  
3rd-Harmonic  
50  
100  
500  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
Load Resistance (W)  
Supply Voltage (±V)  
Figure 7.  
Figure 8.  
10MHz HARMONIC DISTORTION vs  
OUTPUT VOLTAGE  
G = +2 HARMONIC DISTORTION vs FREQUENCY  
-40  
-60  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
-100  
G = +2V/V  
RL = 100W  
G = +2V/V  
RL = 100W  
-50  
-60  
VO = 2VPP  
2nd-Harmonic  
-70  
2nd-Harmonic  
3rd-Harmonic  
3rd-Harmonic  
-80  
-90  
-100  
0.5  
1
5
0.5  
1
10  
Frequency (MHz)  
50  
Output Voltage (VPP  
)
Figure 9.  
Figure 10.  
G = –1 HARMONIC DISTORTION vs FREQUENCY  
G = +1 HARMONIC DISTORTION vs FREQUENCY  
-50  
-55  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
-100  
G = +1V/V  
G = -1V/V  
RL = 100W  
VO = 2VPP  
2nd-Harmonic  
RL = 100W  
-60 VO = 2VPP  
2nd-Harmonic  
-65  
-70  
-75  
-80  
-85  
-90  
-95  
3rd-Harmonic  
3rd-Harmonic  
-100  
0.1  
1
10  
50  
0.1  
1
10  
50  
Frequency (MHz)  
Frequency (MHz)  
Figure 11.  
Figure 12.  
8
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TYPICAL CHARACTERISTICS: ±5V (continued)  
At G = +2 (–IN grounded) and RL = 100Ω, unless otherwise noted.  
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT  
60  
INPUT VOLTAGE vs CURRENT NOISE DENSITY  
100  
10  
1
PI  
55  
50  
45  
40  
35  
30  
25  
20  
15  
10  
1/3  
PO  
OPA3693  
50W  
Inverting Current Noise (internal)  
500W  
300W  
22pA/ÖHz  
300W  
Noninverting Current Noise  
17.8pA/ÖHz  
RL = 500W  
PI  
50W  
1/3  
PO  
OPA3693  
50W  
50W  
300W  
Voltage Noise  
1.8nV/ÖHz  
RL = 100W  
300W  
0
50  
100  
150  
200  
250  
100  
1k  
10k  
100k  
1M  
10M  
Frequency (MHz)  
Frequency (MHz)  
Figure 13.  
Figure 14.  
SMALL-SIGNAL FREQUENCY RESPONSE vs  
CAPACITIVE LOAD  
RECOMMENDED RS vs CAPACITIVE LOAD  
9
6
3
0
60  
50  
40  
30  
20  
10  
0
G = +2  
G = +2  
Optimized RS  
< 0.5dB Peaking  
CL = 100pF  
CL = 10pF  
CL = 20pF  
VIN  
CL = 50pF  
RS  
1/3  
VO  
OPA3693  
-3  
50W  
300W  
CL  
1kW  
-6  
-9  
300W  
1kW is optional  
10  
100  
1000  
1
10  
100  
Frequency (MHz)  
Capacitive Load (pF)  
Figure 15.  
Figure 16.  
SETTLING TIME  
DISABLED FEEDTHROUGH vs FREQUENCY  
20  
15  
-20  
-30  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
G = +2  
G = +2  
RL = 100W  
VDIS = 0V  
RL = 100W  
2V ® 0V  
10  
Output Step  
Forward and Reverse  
5
Input  
0
-5  
Output  
-10  
-15  
-20  
See Figure 36  
See Figure 42  
10  
0
2
4
6
8
10 12 14 16 18 20  
100  
1000  
Time (2ns/div)  
Frequency (MHz)  
Figure 17.  
Figure 18.  
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TYPICAL CHARACTERISTICS: ±5V (continued)  
At G = +2 (–IN grounded) and RL = 100Ω, unless otherwise noted.  
PSRR vs FREQUENCY  
CLOSED-LOOP OUTPUT IMPEDANCE  
65  
60  
55  
50  
45  
40  
35  
30  
25  
20  
10  
-PSRR  
+5V  
+PSRR  
1/3  
OPA3693  
50W  
ZO  
-5V  
300W  
1
300W  
0.1  
1k  
10k  
100k  
1M  
10M  
100M  
10k  
100k  
1M  
10M  
100M  
Frequency (Hz)  
Frequency (Hz)  
Figure 20.  
Figure 19.  
OUTPUT VOLTAGE AND CURRENT LIMITATIONS  
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE  
140  
44  
42  
40  
38  
36  
34  
32  
30  
5
4
1W Internal Power Boundary  
Single-Channel  
Supply Current  
Left Scale  
135  
130  
125  
120  
115  
110  
105  
3
100W Load Line  
50W Load Line  
20W Load Line  
Sourcing Output Current  
Right Scale  
2
1
0
-1  
-2  
-3  
-4  
-5  
Sinking Output Current  
Right Scale  
1W Internal  
Power Boundary  
Single-Channel  
-50  
-25  
0
25  
50  
75  
100  
125  
-250 -200 -150 -100 -50  
0
50 100 150 200 250  
Temperature (°C)  
IO (mA)  
Figure 21.  
Figure 22.  
NONINVERTING OVERDRIVE RECOVERY  
INVERTING OVERDRIVE RECOVERY  
6
6
G = +2  
G = -1  
RL = 100W  
RL = 100W  
4
2
4
2
Output  
Input  
Output  
Input  
0
0
-2  
-4  
-6  
-2  
-4  
-6  
See Figure 42  
See Figure 44  
Time (50ns/div)  
Time (50ns/div)  
Figure 23.  
Figure 24.  
10  
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TYPICAL CHARACTERISTICS: ±5V (continued)  
At G = +2 (–IN grounded) and RL = 100Ω, unless otherwise noted.  
COMMON-MODE INPUT AND OUTPUT SWING vs  
TYPICAL DC DRIFT OVER TEMPERATURE  
SUPPLY VOLTAGE  
1.0  
0.5  
16  
8
6
5
4
3
2
1
0
IB+  
Output  
0
0
VIO  
Input  
-0.5  
-1.0  
-8  
-16  
IB- (internal)  
-50  
-25  
0
25  
50  
75  
100  
125  
2.0  
2.5  
3.0 3.5  
4.0 4.5  
5.0  
5.5  
6.0  
6.5  
Ambient Temperature (°C)  
Supply Voltages (±V)  
Figure 25.  
Figure 26.  
COMPOSITE VIDEO dG/dP  
LARGE-SIGNAL DISABLE/ENABLE RESPONSE  
7
6
5
4
3
2
1
0
0.12  
0.10  
0.08  
0.06  
0.04  
0.02  
0
+5V  
No Pull-Down  
With 1.0k Pull-Down  
DIS  
Video In  
Video Loads  
1/3  
OPA3693  
VDIS  
dP  
dP  
75W  
Optional  
1.0kW  
Pull-Down  
-5V  
VOUT  
dG  
dG  
G = +2  
-1  
VIN = 1VDC  
-2  
-3  
RL = 100W  
See Figure 36  
Time (500ns/div)  
1
2
3
4
Number of 150W Loads  
Figure 27.  
Figure 28.  
INPUT RETURN LOSS vs FREQUENCY (S11)  
OUTPUT RETURN LOSS vs FREQUENCY (S22)  
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
0
-10  
-20  
-30  
-40  
-50  
-60  
-70  
G = +2  
See Figure 42  
G = -1  
See Figure 44  
without Trim Capacitor  
G = +2  
See Figure 42  
with Trim Capacitor  
10M  
100M  
1G  
10M  
100M  
1G  
Frequency (Hz)  
Frequency (Hz)  
Figure 29.  
Figure 30.  
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TYPICAL CHARACTERISTICS: ±5V (continued)  
At G = +2 (–IN grounded) and RL = 100Ω, unless otherwise noted.  
ALL HOSTILE CROSSTALK  
-40  
Input-Referred  
-50  
-60  
-70  
-80  
-90  
0
1
10  
100  
Frequency (MHz)  
Figure 31.  
12  
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TYPICAL CHARACTERISTICS: +5V  
At G = +2V/V (–IN grounded) and RL = 100Ω to VS/2, unless otherwise noted.  
NONINVERTING SMALL-SIGNAL  
FREQUENCY RESPONSE  
LARGE-SIGNAL FREQUENCY RESPONSE  
3
2
8
7
VO = 1VPP  
G = +1V/V  
6
G = +2V/V  
5
1
4
0
3
VO = 3VPP  
VO = 1VPP  
2
-1  
-2  
-3  
-4  
-5  
-6  
1
G = -1V/V  
0
VO = 2VPP  
-1  
-2  
-3  
-4  
-5  
-6  
G = +2V/V  
RL = 100W  
1M  
10M  
100M  
Frequency (Hz)  
1G  
0
100 200 300 400 500 600 700 800 900 1000  
Frequency (MHz)  
Figure 32.  
Figure 33.  
SMALL-SIGNAL BANDWIDTH vs  
SINGLE-SUPPLY VOLTAGE  
FREQUENCY RESPONSE FLATNESS vs LOAD  
0.2  
0.1  
700  
650  
600  
550  
500  
450  
400  
G = +2V/V  
RL = 75W  
RL = 100W  
VO = 0.5VPP  
RL = 100W  
RL = 200W  
0
-0.1  
-0.2  
-0.3  
-0.4  
RL = 150W  
G = +2V/V  
0
100  
200  
300  
4
5
6
7
8
9
10  
11  
12  
Frequency (MHz)  
Single-Supply Voltage (V)  
Figure 34.  
GAIN OF +2 PULSE RESPONSE  
Large Signal  
Figure 35.  
GAIN OF +1 PULSE RESPONSE  
Large Signal  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
Small Signal  
Small Signal  
Time (2ns/div)  
Time (2ns/div)  
Figure 36.  
Figure 37.  
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TYPICAL CHARACTERISTICS: +5V (continued)  
At G = +2V/V (–IN grounded) and RL = 100Ω to VS/2, unless otherwise noted.  
HARMONIC DISTORTION vs FREQUENCY (G = +2)  
HARMONIC DISTORTION vs OUTPUT VOLTAGE  
0
-20  
-55  
-60  
-65  
-70  
-75  
-80  
-85  
G = +2V/V  
G = +2V/V  
RL = 100W  
RL = 100W  
VO = 2VPP  
f = 10MHz  
3rd-Harmonic  
-40  
-60  
2nd-Harmonic  
2nd-Harmonic  
3rd-Harmonic  
-80  
-100  
-120  
0.1  
1
10  
0.5  
1
10  
Frequency (MHz)  
50  
Output Voltage (VPP  
Figure 39.  
)
Figure 38.  
HARMONIC DISTORTION vs LOAD RESISTANCE  
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT  
50  
-55  
-60  
-65  
-70  
-75  
-80  
G = +2V/V  
f = 10MHz  
PI  
1/3  
45  
40  
35  
30  
25  
20  
15  
PO  
OPA3693  
50W  
RL = 500W  
500W  
300W  
300W  
3rd-Harmonic  
2nd-Harmonic  
PI  
50W  
1/3  
PO  
OPA3693  
50W  
50W  
300W  
300W  
RL = 100W  
200  
50  
100  
Load Resistance (W)  
500  
0
50  
100  
150  
250  
300  
Frequency (MHz)  
Figure 40.  
Figure 41.  
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APPLICATION INFORMATION  
WIDEBAND BUFFER OPERATION  
must provide the noninverting input bias current  
required by the input stage to operate. An alternative  
approach to a gain of +1 buffer is described in the  
Wideband Unity-Gain Buffer section of this data  
sheet.  
The OPA3693 gives the exceptional ac performance  
of a wideband current-feedback op amp with a highly  
linear output stage. It features internal RF and RG  
resistors, making it a simple matter to select a gain of  
+2V/V, +1V/V, or –1V/V with no external resistors.  
Requiring only 13mA/ch supply current, the OPA3693  
output swings to within 1V of either supply with >  
+5V  
+
6.8mF  
650MHz small-signal bandwidth and  
> 250MHz  
0.1mF  
delivering 7VPP into a 100Ω load. This low output  
headroom in a very high-speed amplifier gives  
remarkable single +5V operation. The OPA3693  
delivers 2VPP swing with > 400MHz bandwidth  
operating on a single +5V supply. The primary  
advantage of a current-feedback fixed-gain video  
buffer (as opposed to a slew-enhanced, low-gain,  
stable voltage-feedback implementation) is a higher  
slew rate with lower quiescent power and output  
noise.  
50W Source  
DIS  
VI  
50W  
1/3  
OPA3693  
50W  
VO  
50W Load  
RF  
300W  
RG  
300W  
Figure 42 shows the dc-coupled, gain of +2V/V, dual  
power-supply circuit configuration used as the basis  
for the ±5V Electrical Characteristics table and  
Typical Characteristics curves. For test purposes, the  
input impedance is set to 50Ω with a resistor to  
ground and the output impedance is set to 50Ω with a  
series output resistor. Voltage swings reported in the  
specifications are taken directly at the input and  
output pins while load powers (dBm) are defined at a  
matched 50Ω load. For the circuit of Figure 42, the  
total effective load is 100Ω || 600Ω = 85.7Ω. The  
disable control line (DIS) is typically left open to  
ensure normal amplifier operation. In addition to the  
usual power-supply decoupling capacitors to ground,  
a 0.01µF capacitor can be included between the two  
power-supply pins. This optional added capacitor  
typically improves the 2nd-harmonic distortion  
performance by 3dB to 6dB.  
0.1mF  
6.8mF  
+
-5V  
Figure 42. DC-Coupled, G = +2, Bipolar-Supply,  
Specification and Test Circuit  
+5V  
+
6.8mF  
0.1mF  
50W Source  
DIS  
50W  
VI  
1/3  
OPA3693  
50W  
VO  
50W Load  
RF  
300W  
Figure 43 shows the DC-coupled, gain of +1V/V  
buffer configuration used as a starting point for the  
gain of +5V Typical Characteristic curves. In this  
case, the inverting input resistor, RG, is left open  
giving a very broadband gain of +1V/V performance.  
While the test circuit shows a 50Ω input resistor, a  
buffer application is typically transforming from a  
source that cannot drive a heavy load to a 100Ω load,  
such as shown in Figure 43. The noninverting input  
impedance of the OPA3693 is typically 100kΩ || 2pF.  
Driving directly into the noninverting input provides  
this very light load to the source. However, the source  
RG  
300W  
0.1mF  
6.8mF  
+
Open  
-5V  
Figure 43. DC-Coupled, G = +1V/V,  
Bipolar-Supply, Specification and Test Circuit  
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Figure 44 shows the DC-coupled, gain of –1V/V  
buffer configuration used as a starting point for the  
gain of –1V/V Typical Characteristic curves. The input  
impedance is set to 50Ω using the parallel  
combination of an external 60.4Ω resistor and the  
internal 300Ω RG resistor. The noninverting input is  
tied directly to ground. Since the internal design for  
the OPA3693 is current-feedback, trying to get  
improved dc accuracy by including a resistor on the  
noninverting input to ground is ineffective. Using a  
direct short to ground on the noninverting input  
reduces both the contribution of the dc bias current  
and noise current to the output error. While the  
external 60.4Ω is used here to match to the 50Ω  
source from the test equipment, the maximum input  
impedance in this configuration is limited to the 300Ω  
RG resistor even with the RM resistor removed. Unlike  
the noninverting unity gain buffer application,  
removing RM does not strongly impact the dc  
operating point because the short on the noninverting  
input of Figure 44 provides the dc operating voltage.  
This application of the OPA3693 provides a very  
broadband, high-output, signal inverter.  
in the single +5V Typical Characteristic curves, the  
OPA3693 provides > 300MHz bandwidth driving a  
3VPP swing into a 100Ω load. The key requirement of  
broadband single-supply operation is to maintain  
input and output signal swings within the useable  
voltage ranges at both the input and the output.  
The circuit of Figure 45 shows the AC-coupled, gain  
of +2V/V, video buffer circuit used as the basis for the  
Electrical  
Characteristics  
table  
and  
Typical  
Characteristics curves. The circuit of Figure 45  
establishes an input midpoint bias using a simple  
resistive divider from the +5V supply (two 604Ω  
resistors). The input signal is then AC-coupled into  
this midpoint voltage bias. The input voltage can  
swing to within 1.6V of either supply pin, giving a  
1.8VPP input signal range centered between the  
supply pins. The input impedance matching resistor  
(60.4Ω) used for testing is adjusted to give a 50Ω  
input match when the parallel combination of the  
biasing divider network is included. The gain resistor  
(RG) is AC-coupled, giving the circuit a dc gain of  
+1V/V, which puts the input dc bias voltage (2.5V) on  
the output as well. Again, on a single +5V supply, the  
output voltage can swing to within 1V of either supply  
pin while delivering more than 85mA output current. A  
demanding 100Ω load to a midpoint bias is used in  
this characterization circuit. The new output stage  
used in the OPA3693 can deliver large bipolar output  
current into this midpoint load with minimal crossover  
distortion, as illustrated by the +5V supply,  
3rd-harmonic distortion plots.  
+5V  
+
6.8mF  
0.1mF  
DIS  
50W  
VO  
1/3  
OPA3693  
+VS  
+5V  
50W Load  
50W Source  
RG  
RF  
+
0.1mF  
6.8mF  
300W  
300W  
50W Source  
1000pF  
604W  
604W  
VI  
DIS  
VO 100W  
RM  
VI  
60.4W  
0.1mF  
6.8mF  
+
1/3  
OPA3693  
60.4W  
VS/2  
-5V  
RF  
300W  
Figure 44. DC-Coupled, G = –1V/V, Bipolar-Supply  
Specification and Test Circuit  
RG  
300W  
SINGLE-SUPPLY OPERATION  
1000pF  
The OPA3693 may be used over a single-supply  
range of +3.5V to +12V. Though not a rail-to-rail  
output design, the OPA3693 requires minimal input  
and output voltage headroom compared to other  
very-wideband video buffer amplifiers. As illustrated  
Figure 45. AC-Coupled, G = +2V/V, Single-Supply  
Specification and Test Circuit  
16  
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While the circuit of Figure 45 shows +5V  
single-supply operation, this same circuit may be  
used for single supplies ranging as high as +12V  
nominal. The noninverting input bias resistors are  
relatively low in Figure 45 to minimize output dc offset  
as a result of noninverting input bias current. At  
higher signal-supply voltage, these resistors should  
be increased to limit the added supply current drawn  
through this path.  
The input impedance is still set by RM as the  
apparent impedance looking into RG is very high. RM  
may be increased to show a higher input impedance,  
but larger values begin to impact dc output offset  
voltage.  
+5V  
DIS  
Figure 46 shows the AC-coupled, G = +1V/V,  
single-supply specification and test circuit. In this  
case, the gain setting resistor, RG, is simply left open  
to get a gain of +1V for ac signals. Once again, the  
noninverting input is dc biased at midsupply, putting  
that same VS/2 at the output pin. The signal is  
AC-coupled into this midpoint with an added  
termination resistor on the source side of the blocking  
capacitor.  
RO  
50W  
VO  
1/3  
OPA3693  
RG  
RF  
300W  
300W  
VI  
RM  
50W  
-5V  
VS  
+5V  
Figure 47. Improved Unity-Gain Buffer  
+
0.1mF  
6.8mF  
This circuit creates an additional input offset voltage  
as the difference in the two input bias currents times  
the impedance to ground at VI. Figure 48 shows a  
comparison of small-signal frequency response for  
the unity-gain buffer of Figure 43 compared to the  
improved approach shown in Figure 47.  
604W  
604W  
50W Source  
1000pF  
DIS  
100W  
VI  
VO  
1/3  
OPA3693  
60.4W  
VS/2  
RF  
300W  
2
G = +1, Figure 43  
RG  
300W  
1
0
Open  
-1  
G = +1, Figure 47  
-2  
Figure 46. AC-Coupled, G = +1V/V, Single-Supply  
Specification and Test Circuit  
-3  
-4  
-5  
-6  
WIDEBAND UNITY-GAIN BUFFER WITH  
IMPROVED FLATNESS  
10  
100  
1000  
As shown in the Typical Characteristic curves, the  
unity-gain buffer configuration of Figure 43 illustrates  
a peaking in the frequency response exceeding 2dB.  
This configuration gives the slight amount of  
overshoot and ringing apparent in the gain of +1V/V  
pulse response curves. A similar circuit that holds a  
flatter frequency response, giving improved pulse  
fidelity, is shown in Figure 47. This circuit removes  
the peaking by bootstrapping out any parasitic effects  
on RG.  
Frequency (MHz)  
Figure 48. Buffer Frequency Response  
Comparison  
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HIGH-FREQUENCY ACTIVE FILTERS  
This type of filter depends on a low output impedance  
from the amplifier through very high frequencies to  
continue to provide an increasing attenuation with  
frequency. As the amplifier output impedance rises  
with frequency, any input signal or noise starts to  
feed directly through to the output via the feedback  
capacitor. Because the OPA3693 used in Figure 49  
has a 650MHz bandwidth, the active filter continues  
to rolloff through frequencies exceeding 200MHz.  
Figure 50 shows the frequency response for the filter  
of Figure 49, where the desired 40MHz cutoff is  
achieved and a 40dB/dec roll-off is held through very  
high frequencies.  
The extremely wide bandwidth of the OPA3693  
allows a wide range of active filter topologies to be  
implemented with minimal amplifier bandwidth  
interaction in the filter shape. Sallen-Key filters, for  
example, using either a gain of +1V/V or gain of  
+2V/V amplifier, may be easily implemented with no  
external gain setting elements. In general, given a  
desired filter ωO, the amplifier should have at least  
20X that ωO to minimize filter interaction with the  
amplifier frequency response. Figure 49 illustrates an  
example gain of +2 line driver using the OPA3693  
that incorporates a 40MHz low-pass Butterworth  
response with just a few external components. The  
filter resistor values have been adjusted slightly here  
from an ideal filter analysis to account for parasitic  
effects.  
9
6
3
0
-3  
+5V  
-6  
22pF  
-9  
-12  
-15  
-18  
-21  
-24  
100W  
226W  
VI  
50W  
22pF  
1/3  
OPA3693  
VO  
50W  
0W  
Source  
RF  
300W  
1
10  
Frequency (MHz)  
100  
1000  
RG  
Figure 50. 40MHz Low-Pass Active Filter  
Response  
300W  
-5V  
Figure 49. Line Driver with 40MHz Low-Pass  
Active Filter  
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HIGH-SPEED INSTRUMENTATION  
AMPLIFIER  
9
6
Figure 51 shows an instrumentation amplifier based  
on the OPA3693. The offset matching between inputs  
3
makes this configuration an attractive input stage for  
0
this application. The differential-to-single-ended gain  
-3  
for this circuit is 2V/V. The inputs are  
high-impedance, with only 1.2pF to ground at each  
-6  
input. The loads on the OPA3693 outputs are equal  
for the best harmonic distortion possible.  
-9  
VOUT  
20log  
-12  
-15  
|V1 - V2|  
1
10M  
100M  
Frequency (Hz)  
1G  
V1  
150W  
150W  
1/3  
OPA3693  
300W  
300W  
300W  
300W  
Figure 52. High-Speed Instrumentation Amplifier  
Response  
1/3  
OPA3693  
VOUT  
MULTIPLEXED CONVERTER DRIVER  
300W  
300W  
The converter driver in Figure 53 multiplexes among  
the three input signals. The OPA3693 enable and  
disable times support multiplexing among video  
signals. The make-before-break disable characteristic  
of the OPA3693 ensures that the output is always  
under control. To avoid large switching glitches,  
switch during the sync or retrace portions of the video  
signal—the two inputs should be almost equal at  
these times. The output is always under control, so  
the switching glitches for two 0V inputs are < 20mV.  
With standard video signals levels at the inputs, the  
maximum differential voltage across the disabled  
inputs does not exceed the ±1.2V maximum allowed.  
1/3  
OPA3693  
V2  
Figure 51. High-Speed Instrumentation Amplifier  
As shown in Figure 52, the OPA3693 used as an  
instrumentation amplifier has  
bandwidth. This plot has been made for a 1VPP  
output signal using a low-impedance differential input  
source.  
a 420MHz, –3dB  
The output resistors isolate the outputs from each  
other when switching between channels. The  
feedback network of the disabled channels forms part  
of the load seen by the enabled amplifier, attenuating  
the signal slightly.  
LOW-PASS FILTER  
The circuit in Figure 54 realizes  
a 7th-order  
Butterworth low-pass filter with a –3dB bandwidth of  
20MHz. This filter is based on the KRC active filter  
topology that uses an amplifier with the fixed gain ≥  
1. The OPA3693 makes a good amplifier for this type  
of filter. The component values have been adjusted to  
compensate for the parasitic effects of the op amp.  
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0.1mF  
V1  
V2  
V3  
100W  
100W  
100W  
4.99kW  
1/3  
OPA3693  
0.1mF  
4.99kW  
300W  
300W  
300W  
300W  
+5V  
REFT  
+3.5V  
REFB  
+1.5V  
0.1mF  
1/3  
OPA3693  
+In  
ADS828 10-Bit  
75MSPS  
300W  
100pF  
-In  
CM  
0.1mF  
1/3  
OPA3693  
300W  
Selection  
Logic  
Figure 53. Multiplexed Converter Driver  
120pF  
56pF  
49.9W  
47.5W  
110W  
VIN  
220pF  
255W  
124W  
82pF  
1/3  
1/3  
22pF  
OPA3693  
OPA3693  
300W  
300W  
300W  
300W  
180pF  
48.7W  
7TH-ORDER BUTTERWORTH  
FILTER RESPONSE  
95.3W  
20  
-0  
1/3  
OPA3693  
68pF  
VOUT  
-20  
-40  
300W  
-60  
300W  
-80  
-100  
1
3
10  
30  
100  
300  
1000  
Frequency (MHz)  
Figure 54. 7th-Order Butterworth Filter  
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DESIGN-IN TOOLS  
show the zero-voltage output current limit and the  
zero-current output voltage limit, respectively. The  
four quadrants give a more detailed view of the  
OPA3693 output drive capabilities, noting that the  
graph is bounded by a Safe Operating Area of 1W  
maximum internal power dissipation. Superimposing  
resistor load lines onto the plot shows that the  
OPA3693 can drive ±3.4V into 20Ω or ±3.7V into 50Ω  
without exceeding either the output capabilities or the  
1W dissipation limit. A 100Ω load line (the standard  
test-circuit load) shows full ±3.8V output swing  
capability, as shown in the Typical Characteristics.  
DEMONSTRATION BOARDS  
A printed circuit board (PCB) is available to assist in  
the initial evaluation of circuit performance using the  
OPA3693. The fixture is offered free of charge as an  
unpopulated PCB, delivered with a user's guide. The  
summary information for this fixture is shown in  
Table 2.  
Table 2. Demonstration Fixture  
ORDERING  
NUMBER  
LITERATURE  
NUMBER  
The minimum specified output voltage and current  
specifications over temperature are set by worst-case  
simulations at the cold temperature extreme. Only at  
cold startup will the output current and voltage  
decrease to the numbers shown in the  
over-temperature min/max specifications. As the  
output transistors deliver power, their junction  
PRODUCT  
PACKAGE  
OPA3693IDBQ,  
Noninverting  
SSOP-16  
DEM-OPA-SSOP-3C  
DEM-OPA-SSOP-3D  
SBOU047  
SBOU046  
OPA3693IDBQ,  
Inverting  
SSOP-16  
The demonstration fixture can be requested at the  
Texas Instruments web site (www.ti.com) through the  
OPA3693 product folder.  
temperatures increase, which decreases their VBE  
s
(increasing the available output voltage swing) and  
increases their current gains (increasing the available  
output current). In steady-state operation, the  
available output voltage and current is always greater  
OPERATING SUGGESTIONS  
than  
that  
shown  
in  
the  
over-temperature  
GAIN SETTING  
characteristics since the output stage junction  
temperatures are higher than the minimum specified  
operating ambient.  
Setting the gain for the OPA3693 is very easy. For a  
gain of +2, ground the –IN pin and drive the +IN pin  
with the signal. For a gain of +1, either leave the –IN  
pin open and drive the +IN pin or drive both the +IN  
and –IN pins (see Figure 47). For a gain of –1,  
ground the +IN pin and drive the –IN pin with the  
input signal. An external resistor may be used in  
series with the –IN pin to reduce the gain. However,  
because the internal resistors (RF and RG) have a  
tolerance and temperature drift different than the  
external resistor, the absolute gain accuracy and gain  
drift over temperature are relatively poor compared to  
the previously described standard gain connections  
using no external resistor.  
To maintain maximum output stage linearity, no  
output short-circuit protection is provided. This  
configuration is not normally a problem, since most  
applications include a series matching resistor at the  
output that limits the internal power dissipation if the  
output side of this resistor is shorted to ground.  
However, shorting the output pin directly to an  
adjacent positive power-supply pin, in most cases,  
destroys the amplifier. If additional protection to a  
power-supply short is required, consider a small  
series resistor in the power-supply leads. Under  
heavy output loads, this reduces the available output  
voltage swing. A 5Ω series resistor in each supply  
lead limits the internal power dissipation to < 1W for  
an output short while decreasing the available output  
voltage swing only 0.5V, for up to 100mA desired  
load currents. Always place the 0.1µF power-supply  
decoupling capacitors after these supply-current  
limiting resistors directly on the device supply pins.  
OUTPUT CURRENT AND VOLTAGE  
The OPA3693 provides output voltage and current  
capabilities that can easily support multiple video  
loads and/or 100Ω loads with very low distortion.  
Under no-load conditions at +25°C, the output voltage  
typically swings to 1V of either supply rail; the tested  
swing limit is within 1.2V of either rail. Into a 15Ω load  
(the minimum tested load), it is tested to deliver more  
than ±90mA.  
DRIVING CAPACITIVE LOADS  
One of the most demanding, and yet very common,  
load conditions for an op amp is capacitive loading.  
Often, the capacitive load is the input of an  
analog-to-digital converter (ADC), including additional  
external capacitance, which may be recommended to  
improve ADC linearity. A high-speed, high open-loop  
gain amplifier like the OPA3693 can be very  
susceptible to decreased stability and may give  
The specifications described above, though familiar in  
the industry, consider voltage and current limits  
separately. In many applications, it is the voltage ×  
current, or V-I product, which is more relevant to  
circuit operation. Refer to the Output Voltage and  
Current Limitations plot (Figure 21) in the Typical  
Characteristics. The X- and Y-axes of this graph  
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closed-loop response peaking when a capacitive load  
is placed directly on the output pin. When the  
amplifier open-loop output resistance is considered,  
this capacitive load introduces an additional pole in  
the signal path that can decrease the phase margin.  
Several external solutions to this problem have been  
suggested. When the primary considerations are  
frequency response flatness, pulse response fidelity,  
and/or distortion, the simplest and most effective  
solution is to isolate the capacitive load from the  
feedback loop by inserting a series isolation resistor  
between the amplifier output and the capacitive load.  
This resistor does not eliminate the pole from the loop  
response, but rather shifts it and adds a zero at a  
higher frequency. The additional zero acts to cancel  
the phase lag from the capacitive load pole, thus  
increasing the phase margin and improving stability.  
The OPA3693 has an extremely low 3rd-order  
harmonic distortion. This feature also produces a high  
two-tone, 3rd-order intermodulation intercept. Two  
graphs for this intercept are given in the in the Typical  
Characteristics; one for ±5V and one for +5V. The  
lower curve shown in each graph is defined at the  
50Ω load when driven through a 50Ω matching  
resistor, to allow direct comparisons to RF MMIC  
devices. The higher curve in each graph shows the  
intercept if the output is taken directly at the output  
pin with a 500Ω load, to allow prediction of the  
3rd-order spurious level when driving a lighter load,  
such as an ADC input. The output matching resistor  
attenuates the voltage swing from the output pin to  
the load by 6dB. If the OPA3693 drives directly into  
the input of a high-impedance device, such as an  
ADC, this 6dB attenuation is not taken and the  
intercept increases, as shown in the 500Ω load  
typical characteristic.  
The Typical Characteristics show a Recommended  
RS vs Capacitive Load curve (Figure 15) to help the  
designer pick a value to give < 0.5dB peaking to the  
load. The resulting frequency response curves show  
The intercept is used to predict the intermodulation  
spurious levels for two closely-spaced frequencies. If  
the two test frequencies (f1 and f2) are specified in  
terms of average and delta frequency, fO = (f1 + f2)/2  
and Δf = |f2 – f1|/2, then the two, 3rd-order, close-in  
spurious tones appear at fO ±3 × Δf. The difference  
between two equal test tone power levels and these  
intermodulation spurious power levels is given by  
ΔdBc = 2 × (IM3 – PO), where IM3 is the intercept  
taken from the Typical Characteristics and PO is the  
power level in dBm at the 50Ω load for one of the two  
closely-spaced test frequencies. For instance, at  
50MHz, the OPA3693 at a gain of +2 has an intercept  
of 47dBm at a matched 50Ω load. If the full envelope  
of the two frequencies needs to be 2VPP at this load,  
this requires each tone to be 4dBm (1VPP). The  
3rd-order intermodulation spurious tones will then be  
2 × (47 – 4) = 83dBc below the test tone power level  
(–79dBm). If this same 2VPP two-tone envelope were  
delivered directly into a lighter 500Ω load, the  
intercept would increase to the 48dBm shown in the  
Typical Characteristics. With the same output signal  
and gain conditions, but now driving directly into a  
light load with no matching loss, the 3rd-order  
spurious tones will then be at least 2 × (48 – 4) =  
92dBc below the 4dBm test tone power levels  
centered on 50MHz (–88dBm). We are still using a  
4dBm for the 1VPP output swing into this 500Ω load.  
While not strictly correct from a power standpoint, this  
does give the correct prediction for spurious level.  
The class AB output stage for the OPA3693 is much  
more voltage-swing-dependent on output distortion  
than strictly power-dependent. To use the 500Ω  
intercept curve, use the single-tone voltage swing as  
if it were driving a 50Ω load to compute the PO used  
in the intercept equation.  
a
0.5dB peaked response for several selected  
capacitive loads and recommended RS combinations.  
Parasitic capacitive loads greater than 2pF can begin  
to degrade the performance of the OPA3693. Long  
PCB traces, unmatched cables, and connections to  
other amplifier inputs can easily exceed this value.  
Always consider this effect carefully, and add the  
recommended series resistor as close as possible to  
the OPA3693 output pin (see the Board Layout  
Guidelines section).  
The criterion for setting this RS resistor is a maximum  
bandwidth, flat frequency response at the load  
(< 0.5dB peaking). For the OPA3693 operating at a  
gain of +2V/V, the frequency response at the output  
pin is very flat to begin with, allowing relatively small  
values of RS to be used for low capacitive loads.  
DISTORTION PERFORMANCE  
The OPA3693 provides good distortion performance  
into a 100Ω load on ±5V supplies. Relative to  
alternative solutions, the OPA3693 holds much lower  
distortion at higher frequencies (> 20MHz) than  
alternative solutions. Generally, until the fundamental  
signal reaches very high-frequency or power levels,  
the 2nd-harmonic dominates the distortion with a  
negligible 3rd-harmonic component. Focusing then on  
the 2nd-harmonic, increasing the load impedance  
improves distortion directly. Remember that the total  
load includes the feedback network—in the  
noninverting configuration (see Figure 42), this value  
is the sum of RF + RG, while in the inverting  
configuration it is just RF (see Figure 44). Also,  
providing an additional supply decoupling capacitor  
(0.01µF) between the supply pins (for bipolar  
operation) improves the 2nd-order distortion slightly  
(3dB to 6dB).  
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GAIN ACCURACY AND LINEARITY  
0.0200  
Figure 42 Test Circuit  
The OPA3693 provides improved absolute gain  
0.0175  
accuracy and dc linearity over earlier fixed gain of two  
0.0150  
line drivers. Operating at a gain of +2V/V by tying the  
–IN pin to ground, the OPA3693 shows a maximum  
gain error of ±1% at +25°C. The dc gain therefore lies  
between 1.98V/V and 2.02V/V at room temperature.  
Over the specified temperature ranges, this gain  
tolerance expands only slightly due to the matched  
temperature drift for RF and RG. Achieving this gain  
accuracy requires a very low impedance ground at  
–IN. Typical production lots show a much tighter  
distribution in gain than this ±1% specification.  
Figure 55 shows a typical distribution in measured  
gain at the gain of +2V/V configuration, in this case  
showing a slight drop in the mean (0.25%) from the  
nominal but with a very tight distribution.  
0.0125  
0.0100  
0.0075  
0.0050  
0.0025  
0
RL = 100W  
RL = 500W  
2
3
4
5
6
7
8
VO (peak-to-peak)  
Figure 56. DC Linearity vs Output Swing and  
Loads  
700  
Mean = 1.9883  
NOISE PERFORMANCE  
s = 0.0967  
600  
The OPA3693 offers an excellent balance between  
voltage and current noise terms to achieve a low  
output noise under a variety of operating conditions.  
The inverting node noise current (internal) appears at  
the output multiplied by the relatively low 300Ω  
feedback resistor. The input noise voltage  
(1.8nV/√Hz) is extremely low for a unity-gain stable  
amplifier. This low input voltage noise was achieved  
at the price of higher noninverting input current noise  
(17.8pA/√Hz). As long as the ac source impedance  
looking out of the noninverting input is less than  
100Ω, this current noise does not contribute  
significantly to the total output noise. The op amp  
input voltage noise and the two input current noise  
terms combine to give low output noise for the each  
of the three gain settings available using the  
OPA3693. Figure 57 shows the op amp noise  
analysis model with all of the noise terms included. In  
this model, all noise terms are taken to be noise  
voltage or current density terms in either nV/√Hz or  
pA/√Hz.  
500  
400  
300  
200  
100  
0
Gain (V/V)  
Figure 55. Typical +2V/V Gain Distribution  
The exceptionally linear output stage (as illustrated by  
the high 3rd-order intermodulation intercept) and low  
thermal gradient induced errors for the OPA3693 give  
an extremely linear output over large voltage swings  
and heavy loads. Figure 56 shows the tested  
deviation (in % of peak-to-peak) from linearity for a  
range of symmetrical output swings and loads. Below  
4VPP, for either a 100Ω or a 500Ω load, the OPA3693  
delivers greater than 14-bit linear output response.  
ENI  
1/3  
EO  
OPA3693  
RS  
IBN  
ERS  
RF  
4kTRS  
4kTRF  
IBI  
RG  
4kT  
RG  
4kT = 1.6E -20J  
at 290K  
Figure 57. Op Amp Noise Model  
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±(NG ´ VOS) + (IBN ´ RS/2 ´ NG) ± (IBI ´ RF)  
The total output spot noise voltage can be computed  
as the square root of the sum of all squared output  
= ±(2 ´ 3.5mV) + (35mA ´ 25W ´ 2) ± (50mA ´ 300W)  
noise voltage contributors. Equation 1 shows the  
= ±7mV ± 1.75mV ± 15mV  
general form for the output noise voltage using the  
terms shown in Figure 57.  
= ±23.75mV  
where NG = noninverting signal gain.  
EO  
=
ENI2 + (IBNRS)2 + 4kTRS NG2 + (IBIRF)2 + 4kTRFNG  
Minimizing the resistance seen by the noninverting  
input also minimizes the output dc error. For  
(1)  
improved dc precision in  
a wideband low-gain  
Dividing this expression through by noise gain (NG =  
1 + RF/RG) gives the equivalent input-referred spot  
noise voltage at the noninverting input, as shown in  
amplifier, consider the OPA842 where a bipolar input  
is acceptable (low source resistance) or the OPA656  
where a JFET input is required.  
Equation 2.  
2
IBIRF  
NG  
4kTRF  
NG  
DISABLE OPERATION  
EN =  
ENI2 + (IBNRS)2 + 4kTRS +  
+
The OPA3693 provides an optional disable feature  
that can be used to reduce system power. If the VDIS  
control pin is left unconnected, the OPA3693  
operates normally. This shutdown is intended only as  
a power-savings feature. Forward path isolation when  
disabled is very good for small signals for gains of +1  
or +2. Large-signal isolation is not ensured. Using this  
feature to multiplex two or more outputs together is  
not recommended. Large signals applied to the  
disabled output stages can turn on parasitic devices  
degrading signal linearity for the desired channel.  
(2)  
Evaluating the output noise and input noise  
expressions for the two noninverting gain  
configurations, and with two different values for the  
noninverting source impedance, gives output and  
input-referred spot noise voltages of Table 3.  
Table 3. Total Output and Input-Referred Noise  
OUTPUT SPOT  
NOISE  
EO (nV/√Hz)  
TOTAL INPUT  
SPOT NOISE  
EN (nV/√Hz)  
RS  
(Ω)  
CONFIGURATION  
G = +2 (Figure 42)  
G = +2 (Figure 42)  
G = +1 (Figure 43)  
G = +1 (Figure 43)  
Turn-on time is very quick from the shutdown  
condition (typically < 60ns). Turn-off time strongly  
depends on the selected gain configuration and load,  
but is typically 3µs for the circuit of Figure 42.  
25  
300  
25  
8.3  
14  
4.15  
7
7.3  
9.2  
7.3  
9.2  
300  
To shutdown, the control pin must be asserted low.  
This logic control is referenced to the positive supply,  
as the simplified circuit of Figure 58 shows.  
The output noise is being dominated by the inverting  
current noise times the internal feedback resistor.  
This gives a total input-referred noise voltage that  
exceeds the 1.8nV voltage term for the amplifier  
itself.  
+VS  
DC ACCURACY AND OFFSET CONTROL  
15kW  
A current-feedback op amp such as the OPA3693  
provides exceptional bandwidth and slew rate giving  
fast pulse settling but only moderate dc accuracy.  
The Electrical Characteristics show an input offset  
voltage comparable to high-speed voltage-feedback  
amplifiers. However, the two input bias currents are  
somewhat higher and are unmatched. Whereas bias  
current cancellation techniques are very effective with  
most voltage-feedback op amps, they do not  
generally reduce the output dc offset for wideband  
current-feedback op amps. Since the two input bias  
currents are unrelated in both magnitude and polarity,  
matching the source impedance looking out of each  
input to reduce their error contribution to the output is  
ineffective. Evaluating the configuration of Figure 42,  
using worst-case +25°C input offset voltage and the  
two input bias currents, gives a worst-case output  
offset range equal to:  
Q1  
110kW  
25kW  
-VS  
IS  
VDIS  
Control  
Figure 58. Simplified Disable Control Circuit  
In normal operation, base current to Q1 is provided  
through the 110kΩ resistor while the emitter current  
through the 15kΩ resistor sets up a voltage drop that  
is inadequate to turn on the two diodes in the Q1  
emitter. As VDIS is pulled LOW, additional current is  
24  
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OPA3693  
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PD = 10V ´ 43.5mA + 3 ´ 52/(4 ´ (100W || 600W)) = 654mW  
pulled through the 15kΩ resistor, eventually turning  
on these two diodes (≈ 80µA). At this point, any  
further current pulled out of VDIS goes through those  
Maximum TJ = +85°C + (0.654W ´ 80°C/W) = 137°C  
diodes holding the emitter-base voltage of Q1 at  
approximately 0V. This shuts off the collector current  
All actual applications operate at a lower junction  
out of Q1, turning the amplifier off. The supply current  
temperature than the +137°C computed above.  
in the shutdown mode is only that required to operate  
Compute your actual output stage power to get an  
the circuit of Figure 58.  
accurate estimate of maximum junction temperature,  
or use the results shown here as an absolute  
maximum.  
The shutdown feature for the OPA3693 is a positive  
supply referenced, current-controlled interface.  
Open-collector (or drain) interfaces are most  
effective, as long as the controlling logic can sustain  
the resulting voltage (in the open mode) that appears  
at the VDIS pin. That voltage is one diode below the  
positive supply voltage applied to the OPA3693. For  
voltage output logic interfaces, the on/off voltage  
levels described in the Electrical Characteristics apply  
only for a +5V positive supply on the OPA3693. An  
open-drain interface is recommended for shutdown  
operation using a higher positive supply for the  
OPA3693 and/or logic families with inadequate  
high-level voltage swings.  
BOARD LAYOUT GUIDELINES  
Achieving  
optimum  
performance  
with  
a
high-frequency amplifier such as the OPA3693  
requires careful attention to PCB layout parasitics and  
external component types. Recommendations that  
will optimize performance include:  
a) Minimize parasitic capacitance to any ac ground  
for all of the signal I/O pins. Parasitic capacitance on  
the output can cause instability; on the noninverting  
input, it can react with the source impedance to  
cause unintentional bandlimiting. To reduce  
unwanted capacitance, create a window around the  
signal I/O pins in all of the ground and power planes  
around those pins. Otherwise, ground and power  
planes should be unbroken elsewhere on the board.  
THERMAL ANALYSIS  
The OPA3693 does not require heatsinking or airflow  
in most applications. Maximum desired junction  
temperature sets the maximum allowed internal  
power dissipation as described here. In no case  
should the maximum junction temperature be allowed  
to exceed +150°C.  
b) Minimize the distance (< 0.25”) from the  
power-supply  
pins  
to  
high-frequency  
0.1µF  
decoupling capacitors. At the device pins, the ground  
and power plane layout should not be in close  
proximity to the signal I/O pins. Avoid narrow power  
and ground traces to minimize inductance between  
the pins and the decoupling capacitors. The  
power-supply connections should always be  
decoupled with these capacitors. Larger (2.2µF to  
6.8µF) decoupling capacitors, effective at lower  
frequency, should also be used on the supply pins.  
These may be placed somewhat farther from the  
device and may be shared among several devices in  
the same area of the PCB.  
Operating junction temperature (TJ) is given by TA  
+
PD × θJA. The total internal power dissipation (PD) is  
the sum of quiescent power (PDQ) and additional  
power dissipated in the output stage (PDL) to deliver  
load power. Quiescent power is simply the specified  
no-load supply current times the total supply voltage  
across the part. PDL depends on the required output  
signal and load but would, for a grounded resistive  
load, be at a maximum when the output is fixed at a  
voltage equal to 1/2 either supply voltage (for equal  
bipolar supplies). Under this worst-case condition,  
2
c) Careful selection and placement of external  
PDL = VS /(4 × RL) where RL includes feedback  
components  
performance of the OPA3693. Use resistors that  
have low reactance at high frequencies.  
preserve  
the  
high-frequency  
network loading. This value is the absolute highest  
power that can be dissipated for a given RL. All actual  
applications dissipate less power in the output stage.  
Surface-mount resistors work best and allow a tighter  
overall layout. Metal film and carbon composition  
axially-leaded resistors can also provide good  
high-frequency performance. Again, keep their leads  
and PCB trace length as short as possible. Never use  
Note that it is the power in the output stage and not  
into the load that determines internal power  
dissipation.  
As a worst-case example, compute the maximum TJ  
using an OPA3693IDBQ (SSOP-16 package) in the  
circuit of Figure 42 operating at the maximum  
specified ambient temperature of +85°C and driving a  
grounded 100Ω load at VS/2. Maximum internal  
power is:  
wirewound type resistors in  
a
high-frequency  
application. Since the output pin and inverting input  
pin are the most sensitive to parasitic capacitance,  
always position the series output resistor, if any, as  
close as possible to the output pin. Because the  
inverting input node is internal for the OPA3693, it is  
more robust to layout issues than amplifiers with  
similar speed but external feedback and gain  
Copyright © 2006–2008, Texas Instruments Incorporated  
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25  
Product Folder Link(s): OPA3693  
OPA3693  
SBOS353A–DECEMBER 2006–REVISED AUGUST 2008 ............................................................................................................................................ www.ti.com  
resistors. Other network components, such as  
noninverting input termination resistors, should also  
be placed close to the package. Good axial metal film  
or surface-mount resistors have approximately 0.2pF  
in shunt with the resistor. For resistor values > 2.0kΩ,  
this parasitic capacitance can add a pole and/or zero  
below 400MHz that can effect circuit operation. Keep  
resistor values as low as possible consistent with  
load driving considerations.  
integrity as well as a doubly-terminated line. If the  
input impedance of the destination device is low,  
there will be some signal attenuation due to the  
voltage divider formed by the series output into the  
terminating impedance.  
e) Socketing a high-speed part such as the  
OPA3693 is not recommended. The additional lead  
length and pin-to-pin capacitance introduced by the  
socket can create an extremely troublesome parasitic  
network, which can make it almost impossible to  
achieve a smooth, stable frequency response. Best  
results are obtained by soldering the OPA3693  
directly onto the board.  
d) Connections to other wideband devices on the  
PCB may be made with short direct traces or through  
onboard transmission lines. For short connections,  
consider the trace and the input to the next device as  
a lumped capacitive load. Relatively wide traces  
(50mils to 100mils) should be used, preferably with  
ground and power planes opened up around them.  
Estimate the total capacitive load and set RS from the  
plot of Recommended RS vs Capacitive Load  
(Figure 15). Low parasitic capacitive loads (< 4pF)  
may not need an RS since the OPA3693 is nominally  
compensated to operate with a 2pF parasitic load. If a  
long trace is required, and the 6dB signal loss  
intrinsic to a doubly-terminated transmission line is  
INPUT AND ESD PROTECTION  
The OPA3693 is built using a very high-speed  
complementary bipolar process. The internal junction  
breakdown voltages are relatively low for these very  
small geometry devices. These breakdowns are  
reflected in the Absolute Maximum Ratings table. All  
device pins are protected with internal ESD protection  
diodes to the power supplies, as shown in Figure 59.  
acceptable, implement  
a
matched impedance  
+VCC  
transmission line using microstrip or stripline  
techniques (consult an ECL design handbook for  
microstrip and stripline layout techniques). A 50Ω  
environment is normally not necessary on board, and  
in fact, a higher impedance environment improves  
distortion, as shown in the distortion versus load  
plots. With a characteristic board trace impedance  
defined based on board material and trace  
dimensions, a matching series resistor into the trace  
from the output of the OPA3693 is used, as well as a  
terminating shunt resistor at the input of the  
destination device. Remember also that the  
terminating impedance is the parallel combination of  
the shunt resistor and the input impedance of the  
destination device; this total effective impedance  
should be set to match the trace impedance. If the  
6dB attenuation of a doubly-terminated transmission  
External  
Pin  
Internal  
Circuitry  
-VCC  
Figure 59. Internal ESD Protection  
These diodes provide moderate protection to input  
overdrive voltages above the supplies as well. The  
protection diodes can typically support 30mA  
continuous current. Where higher currents are  
possible (for example, in systems with ±15V supply  
parts driving into the OPA3693), current limiting  
series resistors may be added on the noninverting  
input. Keep this resistor value as low as possible  
since high values degrade both noise performance  
and frequency response. The inverting input already  
has a 300Ω resistor from the external pin to the  
internal summing junction for the op amp. This  
resistor provides considerable protection for that  
node.  
line is unacceptable,  
a
long trace can be  
series-terminated at the source end only. Treat the  
trace as a capacitive load in this case and set the  
series resistor value as illustrated in the plot of  
Figure 15. This configuration does not preserve signal  
26  
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Product Folder Link(s): OPA3693  
 
OPA3693  
www.ti.com ............................................................................................................................................ SBOS353A–DECEMBER 2006–REVISED AUGUST 2008  
Revision History  
Changes from Original (December 2006) to Revision A ................................................................................................ Page  
•
Changed storage temperature range rating in Absolute Maximum Ratings table from –40°C to +125°C to –65°C to  
+125°C................................................................................................................................................................................... 2  
Copyright © 2006–2008, Texas Instruments Incorporated  
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27  
Product Folder Link(s): OPA3693  
PACKAGE OPTION ADDENDUM  
www.ti.com  
29-Jun-2023  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
OPA3693IDBQ  
OPA3693IDBQR  
OPA3693IDBQRG4  
ACTIVE  
ACTIVE  
LIFEBUY  
SSOP  
SSOP  
SSOP  
DBQ  
DBQ  
DBQ  
16  
16  
16  
75  
RoHS & Green  
NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
-40 to 85  
OP3693  
Samples  
Samples  
2500 RoHS & Green  
2500 RoHS & Green  
NIPDAU  
NIPDAU  
OP3693  
OP3693  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
29-Jun-2023  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
OPA3693IDBQR  
SSOP  
DBQ  
16  
2500  
330.0  
12.4  
6.4  
5.2  
2.1  
8.0  
12.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SSOP DBQ 16  
SPQ  
Length (mm) Width (mm) Height (mm)  
356.0 356.0 35.0  
OPA3693IDBQR  
2500  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
3-Jun-2022  
TUBE  
T - Tube  
height  
L - Tube length  
W - Tube  
width  
B - Alignment groove width  
*All dimensions are nominal  
Device  
Package Name Package Type  
DBQ SSOP  
Pins  
SPQ  
L (mm)  
W (mm)  
T (µm)  
B (mm)  
OPA3693IDBQ  
16  
75  
506.6  
8
3940  
4.32  
Pack Materials-Page 3  
PACKAGE OUTLINE  
DBQ0016A  
SSOP - 1.75 mm max height  
SCALE 2.800  
SHRINK SMALL-OUTLINE PACKAGE  
C
SEATING PLANE  
.228-.244 TYP  
[5.80-6.19]  
.004 [0.1] C  
A
PIN 1 ID AREA  
14X .0250  
[0.635]  
16  
1
2X  
.189-.197  
[4.81-5.00]  
NOTE 3  
.175  
[4.45]  
8
9
16X .008-.012  
[0.21-0.30]  
B
.150-.157  
[3.81-3.98]  
NOTE 4  
.069 MAX  
[1.75]  
.007 [0.17]  
C A  
B
.005-.010 TYP  
[0.13-0.25]  
SEE DETAIL A  
.010  
[0.25]  
GAGE PLANE  
.004-.010  
[0.11-0.25]  
0 - 8  
.016-.035  
[0.41-0.88]  
DETAIL A  
TYPICAL  
(.041 )  
[1.04]  
4214846/A 03/2014  
NOTES:  
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.  
Dimensioning and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed .006 inch, per side.  
4. This dimension does not include interlead flash.  
5. Reference JEDEC registration MO-137, variation AB.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DBQ0016A  
SSOP - 1.75 mm max height  
SHRINK SMALL-OUTLINE PACKAGE  
16X (.063)  
[1.6]  
SEE  
DETAILS  
SYMM  
1
16  
16X (.016 )  
[0.41]  
14X (.0250 )  
[0.635]  
8
9
(.213)  
[5.4]  
LAND PATTERN EXAMPLE  
SCALE:8X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL  
METAL  
.002 MAX  
[0.05]  
ALL AROUND  
.002 MIN  
[0.05]  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4214846/A 03/2014  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DBQ0016A  
SSOP - 1.75 mm max height  
SHRINK SMALL-OUTLINE PACKAGE  
16X (.063)  
[1.6]  
SYMM  
1
16  
16X (.016 )  
[0.41]  
SYMM  
14X (.0250 )  
[0.635]  
9
8
(.213)  
[5.4]  
SOLDER PASTE EXAMPLE  
BASED ON .005 INCH [0.127 MM] THICK STENCIL  
SCALE:8X  
4214846/A 03/2014  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
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