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OPA2205ADGKT [TI]

Dual, rail-to-rail bipolar precision e-trim™ op amp with low input bias current and low noise | DGK | 8 | -40 to 125;
OPA2205ADGKT
型号： OPA2205ADGKT
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Dual, rail-to-rail bipolar precision e-trim™ op amp with low input bias current and low noise | DGK | 8 | -40 to 125
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OPA205, OPA2205, OPA4205  
SBOS962F – APRIL 2020 – REVISED MARCH 2023  
OPAx205 4-µV, 0.08-µV/°C, Low-Power, Super Beta, Bipolar, e-trim™ Op Amps  
1 Features  
3 Description  
•
e-trim™ operational amplifier performance  
– Low offset voltage: 25 µV (max),  
15 µV (max, high grade)  
– Low offset voltage drift: ±0.5 µV/°C (max),  
±0.2 µV/°C (max, high grade)  
Super beta inputs  
– Input bias current: 500 pA (max)  
– Input current noise: 110 fA/√Hz  
Low noise  
The OPA205, OPA2205, and OPA4205 (OPAx205)  
are the next generation of the industry-standard  
OPAx277 family. The OPA206 and OPA2206 are  
related devices with the same op-amp core, but with  
the added feature of input overvoltage protection  
±40 V above the supplies. These devices are  
precision, bipolar e-trim™ op amps with super-beta  
inputs. TI's proprietary trimming technology is used to  
achieve a typical input offset voltage of ±4 µV (±2 µV,  
high grade), and a typical input offset voltage drift of  
±0.08 µV (±0.04 µV, high grade).  
•
•
•
– 0.1 to 10-Hz: 0.2 µVPP  
– Voltage noise: 7.2 nV/√Hz  
AOL, CMRR, and PSRR: > 126 dB (full  
temperature range)  
Gain bandwidth product: 3.6 MHz  
Low quiescent current: 240 µA (max)  
Slew rate: 4 V/µs  
Overload power limiter  
Rail-to-rail output  
EMI and RFI filtered inputs  
Wide supply: 4.5 V to 36 V  
Temperature range: –40°C to +125°C  
Available in standard grade (OPAx205A) and  
high grade (OPA2205, preview)  
Available with ±40-V overvoltage protection in the  
OPA206 and OPA2206  
Designed on a bipolar process, the OPAx205 provide  
3.6‑MHz gain bandwidth for a mere 220 µA of  
quiescent current. The devices also achieve a low  
voltage noise density of only 7.2 nV/√Hz at 1 kHz.  
The super-beta inputs of the OPAx205 have a very  
low input bias current of 100 pA (typical) and a current  
noise density of 110 fA/√Hz.  
•
•
•
•
•
•
•
•
•
The high performance of the OPAx205 makes these  
devices an excellent choice for systems requiring  
high precision and low power consumption, such  
as flow and pressure transmitters, portable data  
acquisition (DAQ) systems, and high-density source  
measurement units (SMU).  
•
Device Information  
2 Applications  
PART NUMBER  
OPA205  
CHANNELS  
PACKAGE(1)  
•
•
•
•
•
•
•
•
Flow transmitter  
String inverter  
Single  
D (SOIC, 8)  
Dual  
Dual  
Quad  
Quad  
D (SOIC, 8)  
OPA2205(2)  
Data acquisition (DAQ)  
Source measurement unit (SMU)  
Lab and field instrumentation  
Battery test  
Analog input module  
Pressure transmitter  
DGK (VSSOP, 8)  
D (SOIC, 14)  
OPA4205  
PW (TSSOP, 14)  
(1) For all available packages, see the package option  
addendum at the end of the data sheet.  
(2) High-grade version is preview (not Production Data).  
750 ꢀ  
15  
12  
9
470 pF  
+7 V  
3 kꢀ  
œ
2.4 kꢀ  
IN+  
+
OPA2205  
Þ7 V  
100 ꢀ  
100 ꢀ  
+7 V  
œ
1.1 nF  
1 nF  
VOUT  
+
6
THP210  
Þ7 V  
+7 V  
2.4 kꢀ  
3 kꢀ  
œ
INÞ  
+
470 pF  
3
OPA2205  
Þ7 V  
750 ꢀ  
0
-0.1 -0.08 -0.06 -0.04 -0.02  
0
0.02 0.04 0.06 0.08 0.1  
Offset Voltage Drift (µV/°C)  
OPA2205 Typical Application  
OPAx205 Offset Voltage Drift  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION  
DATA.  
 
 
 
 
 
OPA205, OPA2205, OPA4205  
SBOS962F – APRIL 2020 – REVISED MARCH 2023  
www.ti.com  
Table of Contents  
1 Features............................................................................1  
2 Applications.....................................................................1  
3 Description.......................................................................1  
4 Revision History.............................................................. 2  
5 Pin Configuration and Functions...................................4  
6 Specifications.................................................................. 6  
6.1 Absolute Maximum Ratings........................................ 6  
6.2 ESD Ratings .............................................................. 6  
6.3 Recommended Operating Conditions.........................6  
6.4 Thermal Information: OPA205.................................... 7  
6.5 Thermal Information: OPA2205.................................. 7  
6.6 Thermal Information: OPA4205.................................. 7  
6.7 Electrical Characteristics: VS = ±5 V...........................8  
6.8 Electrical Characteristics: VS = ±15 V.......................10  
6.9 Typical Characteristics..............................................12  
7 Parameter Measurement Information..........................21  
7.1 Typical Specifications and Distributions....................21  
8 Detailed Description......................................................22  
8.1 Overview...................................................................22  
8.2 Functional Block Diagram.........................................22  
8.3 Feature Description...................................................23  
8.4 Device Functional Modes..........................................24  
9 Application and Implementation..................................25  
9.1 Application Information............................................. 25  
9.2 Typical Applications.................................................. 25  
9.3 Power Supply Recommendations.............................28  
9.4 Layout....................................................................... 28  
10 Device and Documentation Support..........................30  
10.1 Device Support....................................................... 30  
10.2 Documentation Support.......................................... 30  
10.3 Receiving Notification of Documentation Updates..30  
10.4 Support Resources................................................. 30  
10.5 Trademarks.............................................................30  
10.6 Electrostatic Discharge Caution..............................30  
10.7 Glossary..................................................................30  
11 Mechanical, Packaging, and Orderable  
Information.................................................................... 30  
4 Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision E (December 2022) to Revision F (March 2023)  
Page  
•
•
•
•
•
Changed title to align with standard-grade device specifications.......................................................................1  
Added OPA2205 D (SOIC, 8) package and associated content as production data..........................................1  
Added OPA4205 D (SOIC, 14) package and associated content as production data........................................1  
Changed maximum input bias from ±0.4 nA to ±0.5 nA................................................................................... 21  
Changed offset and offset drift values to match standard-grade device specifications in Detailed Design  
Description .......................................................................................................................................................26  
Changed Figure 9-6 to show correct VS+ connection ..................................................................................... 29  
•
Changes from Revision D (September 2022) to Revision E (December 2022)  
Page  
•
•
•
•
Added OPA4205 TSSOP package and associated content as production data................................................ 1  
Changed typical input offset voltage from 8 µV to 4 µV in Electrical Characteristics .........................................8  
Changed maximum input offset voltage from 50 µV to 25 µV in Electrical Characteristics ............................... 8  
Changed maximum input offset voltage over temperature from 80 µV to 55 µV in Electrical Characteristics .....  
............................................................................................................................................................................8  
Changed typical input offset voltage from 8 µV to 4 µV in Electrical Characteristics .......................................10  
Changed maximum input offset voltage from 50 µV to 25 µV in Electrical Characteristics ............................. 10  
Changed maximum input offset voltage over temperature from 80 µV to 55 µV in Electrical Characteristics .....  
..........................................................................................................................................................................10  
•
•
•
Changes from Revision C (July 2022) to Revision D (September 2022)  
Page  
•
Changed OPA205 (SOIC) from preview to production data (active).................................................................. 1  
Changes from Revision B (August 2021) to Revision C (July 2022)  
Page  
•
Added OPA205 D (SOIC) package as advanced information (preview)............................................................ 1  
Changes from Revision A (May 2021) to Revision B (August 2021)  
Page  
•
Changed Figure 6-22, Voltage Noise Density vs Frequency, to show voltage noise density instead of current  
noise density.....................................................................................................................................................12  
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OPA205, OPA2205, OPA4205  
SBOS962F – APRIL 2020 – REVISED MARCH 2023  
www.ti.com  
Changes from Revision * (April 2020) to Revision A (May 2021)  
Page  
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document................. 1  
Changed OPA2205 from advanced information (preview) to production data (active).......................................1  
Changed both Electrical Characteristics tables to show differentiated performance between OPA2205 (high  
grade) and OPA2205A (standard grade)............................................................................................................8  
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Product Folder Links: OPA205 OPA2205 OPA4205  
OPA205, OPA2205, OPA4205  
SBOS962F – APRIL 2020 – REVISED MARCH 2023  
www.ti.com  
5 Pin Configuration and Functions  
NC  
œIN  
+IN  
Vœ  
1
2
3
4
8
7
6
5
NC  
V+  
œ
OUT  
NC  
+
Not to scale  
Figure 5-1. OPA205 D Package, 8-Pin SOIC (Top View)  
Table 5-1. Pin Functions: OPA205  
PIN  
TYPE  
DESCRIPTION  
NAME  
NO.  
+IN  
–IN  
NC  
OUT  
V+  
3
Input  
Input  
—
Noninverting input  
Inverting input  
2
1, 5, 8  
No internal connection (can be left floating)  
Output  
6
7
4
Output  
—
Positive (highest) power supply  
Negative (lowest) power supply  
V–  
—
OUT A  
œIN A  
+IN A  
Vœ  
1
2
3
4
8
7
6
5
V+  
OUT B  
œIN B  
+IN B  
Not to scale  
Figure 5-2. OPA2205 DGK Package, 8-Pin VSSOP and D Package, 8-pin SOIC (Top View)  
Table 5-2. Pin Functions: OPA2205  
PIN  
TYPE  
DESCRIPTION  
NAME  
NO.  
3
+IN A  
–IN A  
+IN B  
–IN B  
Input  
Input  
Input  
Input  
Output  
Output  
—
Noninverting input, channel A  
Inverting input, channel A  
Noninverting input, channel B  
Inverting input, channel B  
Output, channel A  
2
5
6
OUT A  
OUT B  
V+  
1
7
Output, channel B  
8
Positive (highest) power supply  
Negative (lowest) power supply  
V–  
4
—
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www.ti.com  
OUT A  
œIN A  
+IN A  
V+  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
OUT D  
œIN D  
+IN D  
Vœ  
+IN B  
œIN B  
OUT B  
+IN C  
œIN C  
OUT C  
8
Not to scale  
Figure 5-3. OPA4205 PW Package, 14-Pin TSSOP and D Package, 14-Pin SOIC (Top View)  
Pin Functions: OPA4205  
PIN  
TYPE  
DESCRIPTION  
NAME  
NO.  
3
+IN A  
+IN B  
+IN C  
+IN D  
–IN A  
–IN B  
–IN C  
–IN D  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Output  
Output  
Output  
—
Noninverting input, channel A  
Noninverting input, channel B  
Noninverting input, channel C  
Noninverting input, channel D  
Inverting input, channel A  
Inverting input, channel B  
Inverting input, channel C  
Inverting input, channel D  
Output, channel A  
5
10  
12  
2
6
9
13  
1
OUT A  
OUT B  
OUT C  
OUT D  
V+  
7
Output, channel B  
8
Output, channel C  
14  
4
Output, channel D  
Positive (highest) power supply  
Negative (lowest) power supply  
V–  
11  
—
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OPA205, OPA2205, OPA4205  
SBOS962F – APRIL 2020 – REVISED MARCH 2023  
www.ti.com  
6 Specifications  
6.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
MAX  
40  
UNIT  
Single supply  
VS  
Supply voltage, VS = (V+) – (V–)  
Signal input pin voltage  
V
Dual supply  
Common-mode  
Differential  
±20  
(V–) – 0.5  
(V+) + 0.5  
±0.5  
V
Signal input pin current  
Output short-circuit(2)  
Operating temperature  
Junction temperature  
Storage temperature  
±10  
mA  
Continuous  
TA  
–40  
150  
150  
150  
°C  
°C  
°C  
TJ  
TSTG  
–65  
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply  
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.  
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully  
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.  
(2) Short-circuit to ground, one amplifier per package.  
6.2 ESD Ratings  
VALUE  
±2000  
±1000  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002((2))  
V(ESD)  
Electrostatic discharge  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
6.3 Recommended Operating Conditions  
over operating free-air temperature range (unless otherwise noted)  
MIN  
4.5  
NOM  
MAX  
36  
UNIT  
V
Single supply  
Dual supply  
VS  
TA  
Supply voltage, VS = (V+) – (V–)  
Operating temperature  
±2.25  
–40  
±18  
125  
°C  
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OPA205, OPA2205, OPA4205  
SBOS962F – APRIL 2020 – REVISED MARCH 2023  
www.ti.com  
6.4 Thermal Information: OPA205  
OPA205  
THERMAL METRIC(1)  
D (SOIC)  
8 PINS  
121.5  
64.3  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
℃/W  
℃/W  
℃/W  
℃/W  
℃/W  
℃/W  
RθJC(top)  
RθJB  
65.0  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
18.2  
ψJB  
64.3  
RθJC(bot)  
N/A  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
6.5 Thermal Information: OPA2205  
OPA2205  
THERMAL METRIC(1)  
D (SOIC)  
8 PINS  
126.9  
67.1  
DGK (VSSOP)  
8 PINS  
175.6  
63.1  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
70.3  
97.2  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
18.8  
7.8  
ψJB  
69.5  
95.5  
RθJC(bot)  
N/A  
N/A  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
6.6 Thermal Information: OPA4205  
OPA4205  
THERMAL METRIC(1)  
D (SOIC)  
14 PINS  
86.5  
PW (TSSOP)  
14 PINS  
117.1  
36.0  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
38.5  
43.5  
59.3  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
7.4  
2.6  
ψJB  
42.9  
58.3  
RθJC(bot)  
N/A  
N/A  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
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SBOS962F – APRIL 2020 – REVISED MARCH 2023  
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6.7 Electrical Characteristics: VS = ±5 V  
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
±2  
MAX  
UNIT  
OFFSET VOLTAGE  
±15  
±25  
OPA2205  
TA = –40°C to +125°C  
VOS  
Input offset voltage  
μV  
μV/°C  
μV/V  
dB  
±4  
±25  
OPAx205A  
TA = –40°C to +125°C  
TA = –40°C to +125°C  
TA = –40°C to +125°C  
±55  
OPA2205  
±0.04  
±0.08  
±0.05  
±0.2  
±0.5  
±0.25  
±0.5  
±0.5  
±1  
dVOS/dT Input offset voltage drift  
OPAx205A  
OPA2205,  
VS = ±2.25 V to ±18 V  
TA = –40°C to +125°C  
TA = –40°C to +125°C  
Power supply rejection  
PSRR  
ratio  
±0.05  
OPAx205A,  
VS = ±2.25 V to ±18 V  
f = dc  
130  
110  
Channel separation,  
(dual, quad)  
f = 100 kHz  
INPUT BIAS CURRENT  
±0.1  
±0.1  
±0.1  
±0.4  
±0.6  
±0.9  
±0.5  
±0.75  
±1  
OPA2205  
TA = 0°C to 85°C  
TA = –40°C to +125°C  
IB  
Input bias current  
nA  
nA  
OPAx205A  
TA = 0°C to 85°C  
TA = –40°C to +125°C  
±0.4  
±0.5  
±0.6  
IOS  
Input offset current  
Input voltage noise  
TA = 0°C to 85°C  
TA = –40°C to +125°C  
NOISE  
f = 0.1 Hz to 10 Hz  
f = 10 Hz  
0.2  
7.4  
7.2  
7.2  
μVPP  
Input voltage noise  
density  
en  
f = 100 Hz  
nV/√Hz  
f = 1 kHz  
Input current noise  
density  
in  
f = 1 kHz  
110  
fA/√Hz  
INPUT VOLTAGE  
VCM  
Common-mode voltage  
(V–) + 1  
124  
(V+) – 1.4  
V
OPA2205, (V–) + 1 V < VCM < (V+) – 1.4 V,  
TA = –40°C to +125°C  
140  
140  
Common-mode rejection  
ratio  
CMRR  
dB  
OPAx205A, (V–) + 1 V < VCM < (V+) – 1.4 V,  
TA = –40°C to +125°C  
124  
INPUT IMPEDANCE  
ZID  
Differential  
9 || 4.4  
MΩ || pF  
GΩ || pF  
ZICM  
Common-mode  
300 || 4.4  
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6.7 Electrical Characteristics: VS = ±5 V (continued)  
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OPEN-LOOP GAIN  
OPA2205,  
TA = –40°C to +125°C,  
(V–) + 200 mV < VO < (V+) – 200 mV  
RL = 10 kΩ  
126  
126  
126  
126  
132  
130  
132  
130  
RL = 2 kΩ  
RL = 10 kΩ  
RL = 2 kΩ  
AOL  
Open-loop voltage gain  
dB  
OPAx205A,  
TA = –40°C to +125°C,  
(V–) + 200 mV < VO < (V+) – 200 mV  
FREQUENCY RESPONSE  
GBW  
SR  
Gain-bandwidth product  
3.6  
3.2  
67  
MHz  
V/μs  
Slew rate  
4-V step, gain = –1  
Phase margin  
RL = 10 kΩ, CL = 25 pF  
degrees  
To 0.024% (12-bit),  
4-V step, gain = 1,  
CL = 30 pF  
Falling  
Rising  
2.2  
tS  
Settling time  
μs  
2.8  
0.3  
Overload recovery time Gain = –10  
Total harmonic distortion  
μs  
%
THD+N  
VO = 5 VPP, gain = +1, f = 1 kHz, RL = 2 kΩ  
0.0004  
+ noise  
OUTPUT  
RL = 10 kΩ  
RL = 2 kΩ  
(V–) + 0.2  
(V–) + 0.2  
(V–) + 0.2  
(V+) – 0.2  
(V+) – 0.2  
(V+) – 0.2  
AOL > 126 dB  
Voltage output swing  
from rail  
V
TA = –40°C to +125°C, RL = 10 kΩ  
ISC  
Short-circuit current  
Capacitive load drive  
±25  
mA  
CLOAD  
See Typical Characteristics  
See Typical Characteristics  
Open-loop output  
impedance  
RO  
POWER SUPPLY  
220  
240  
310  
Quiescent current per  
amplifier  
IQ  
IO = 0 mA  
μA  
TA = –40°C to +125°C  
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6.8 Electrical Characteristics: VS = ±15 V  
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
±2  
MAX  
UNIT  
OFFSET VOLTAGE  
±15  
±25  
OPA2205  
TA = –40°C to +125°C  
VOS  
Input offset voltage  
μV  
μV/°C  
μV/V  
dB  
±4  
±25  
OPAx205A  
TA = –40°C to +125°C  
TA = –40°C to +125°C  
TA = –40°C to +125°C  
±55  
OPA2205  
±0.04  
±0.08  
±0.05  
±0.2  
±0.5  
±0.25  
±0.5  
±0.5  
±1  
dVOS/dT Input offset voltage drift  
OPAx205A  
OPA2205,  
VS = ±2.25 V to ±18 V  
TA = –40°C to +125°C  
TA = –40°C to +125°C  
Power supply rejection  
PSRR  
ratio  
±0.05  
OPAx205A,  
VS = ±2.25 V to ±18 V  
f = dc  
130  
110  
Channel separation,  
(dual, quad)  
f = 100 kHz  
INPUT BIAS CURRENT  
±0.1  
±0.1  
±0.1  
±0.4  
±0.6  
±0.9  
±0.5  
±1  
OPA2205  
TA = 0°C to 85°C  
TA = –40°C to +125°C  
IB  
Input bias current  
nA  
nA  
OPAx205A  
TA = 0°C to 85°C  
TA = –40°C to +125°C  
±1.2  
±0.4  
±0.8  
±0.9  
IOS  
Input offset current  
Input voltage noise  
TA = 0°C to 85°C  
TA = –40°C to +125°C  
NOISE  
f = 0.1 Hz to 10 Hz  
f = 10 Hz  
0.2  
7.4  
7.2  
7.2  
μVPP  
Input voltage noise  
density  
en  
f = 100 Hz  
nV/√Hz  
f = 1 kHz  
Input current noise  
density  
in  
f = 1 kHz  
110  
fA/√Hz  
V
INPUT VOLTAGE  
VCM  
Common-mode voltage  
(V–) + 1  
126  
(V+) – 1.4  
140  
140  
140  
140  
OPA2205,  
(V–) + 1 V < VCM < (V+) – 1.4 V  
TA = –40°C to +125°C  
TA = –40°C to +125°C  
124  
Common-mode rejection  
ratio  
CMRR  
dB  
126  
OPAx205A,  
(V–) + 1 V < VCM < (V+) – 1.4 V  
124  
INPUT IMPEDANCE  
ZID  
Differential  
9 || 4.4  
MΩ || pF  
GΩ || pF  
ZICM  
Common-mode  
300 || 4.3  
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6.8 Electrical Characteristics: VS = ±15 V (continued)  
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OPEN-LOOP GAIN  
RL = 10 kΩ,  
(V–) + 200 mV < VO  
(V+) – 200 mV  
<
<
<
<
132  
132  
126  
126  
135  
135  
132  
130  
OPA2205,  
TA = –40°C to +125°C  
RL = 2 kΩ,  
(V–) + 350 mV < VO  
(V+) – 350 mV  
AOL  
Open-loop voltage gain  
dB  
RL = 10 kΩ,  
(V–) + 200 mV < VO  
(V+) – 200 mV  
OPAx205A,  
TA = –40°C to +125°C  
RL = 2 kΩ,  
(V–) + 350 mV < VO  
(V+) – 350 mV  
FREQUENCY RESPONSE  
GBW  
SR  
Gain-bandwidth product CL = 30 pF  
3.6  
4
MHz  
V/μs  
Slew rate  
10-V step, gain = –1  
Phase margin  
RL = 10 kΩ, CL = 25 pF  
58  
2.8  
degrees  
To 0.024% (12-bit),  
10-V step, gain = 1,  
CL = 30 pF  
Falling  
Rising  
tS  
Settling time  
μs  
4.5  
0.2  
Overload recovery time Gain = –10  
Total harmonic distortion  
μs  
%
THD+N  
VO = 5 VPP, gain = +1, f = 1 kHz, RL = 2 kΩ  
0.0004  
+ noise  
OUTPUT  
RL = 10 kΩ  
RL = 2 kΩ  
(V–) + 0.2  
(V–) + 0.35  
(V–) + 0.2  
(V+) – 0.2  
(V+) – 0.35  
(V+) – 0.2  
AOL > 126 dB  
Voltage output swing  
from rail  
V
TA = –40°C to +125°C, RL = 10 kΩ  
ISC  
Short-circuit current  
Capacitive load drive  
±25  
mA  
CLOAD  
See Typical Characteristics  
See Typical Characteristics  
Open-loop output  
impedance  
RO  
POWER SUPPLY  
220  
240  
310  
Quiescent current per  
amplifier  
IQ  
IO = 0 mA  
μA  
TA = –40°C to +125°C  
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6.9 Typical Characteristics  
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)  
Table 6-1. Table of Graphs  
DESCRIPTION  
FIGURE  
Offset Voltage Production Distribution at 25°C  
Offset Voltage at 125°C  
Figure 6-1  
Figure 6-2  
Figure 6-3  
Figure 6-4  
Figure 6-5  
Figure 6-6  
Figure 6-7  
Figure 6-8  
Figure 6-9  
Figure 6-10  
Figure 6-11  
Figure 6-12  
Figure 6-13  
Figure 6-14  
Figure 6-15  
Figure 6-16  
Figure 6-17  
Figure 6-18  
Figure 6-19  
Figure 6-20  
Figure 6-21  
Figure 6-22  
Figure 6-23  
Figure 6-24  
Figure 6-25  
Figure 6-26  
Figure 6-27  
Figure 6-28  
Figure 6-29  
Figure 6-30  
Figure 6-31  
Figure 6-32  
Figure 6-33  
Figure 6-34  
Figure 6-35  
Figure 6-36  
Figure 6-37  
Figure 6-38  
Figure 6-39  
Figure 6-40  
Figure 6-41  
Figure 6-42  
Figure 6-43  
Figure 6-44  
Figure 6-45  
Offset Voltage at –40°C  
Offset Voltage vs Temperature  
Offset Voltage Drift Distribution  
Offset Voltage vs Output Voltage  
Offset Voltage vs Power Supply Voltage  
Power-Supply Rejection Ratio vs Temperature  
Power-Supply and Common-Mode Rejection Ratio vs Frequency  
Common-Mode Rejection Ratio vs Temperature  
Offset Voltage vs Common-Mode Voltage  
Offset Voltage vs VCM at Low Supply  
Offset Voltage vs VCM at High Supply  
Open-Loop Gain and Phase vs Frequency  
Open-Loop Gain vs Swing From the Rail  
Open-Loop Gain vs Temperature  
Closed-Loop Gain vs Frequency  
Input Bias Production Distribution  
Input Bias vs Common-Mode Voltage  
Input Bias and Input Offset Current vs Temperature  
Input Offset Current Production Distribution  
Voltage Noise Density vs Frequency  
0.1-Hz to 10-Hz Noise  
Total Harmonic Distortion + Noise Ratio vs Frequency  
Total Harmonic Distortion + Noise Ratio vs Output Amplitude  
Current Noise vs Frequency  
Maximum Output Voltage vs Frequency  
Output Voltage Swing vs Output Sourcing Current  
Output Voltage Swing vs Output Sinking Current  
Open-Loop Output Impedance vs Frequency  
No Phase Reversal  
Small-Signal Overshoot vs Capacitive Load, Gain = +1  
Small-Signal Overshoot vs Capacitive Load, Gain = –1  
Phase Margin vs Capacitive Load  
Positive Overload Recovery, Gain = –1  
Negative Overload Recovery, Gain = –1  
Settling Time  
Small-Signal Step Response, Gain = +1  
Small-Signal Step Response, Gain = –1  
Large-Signal Step Response, Gain = +1  
Large-Signal Step Response, Gain = –1  
Short-Circuit Current vs Temperature  
Electromagnetic Interference Rejection (EMIRR)  
Quiescent Current vs Supply Voltage  
Quiescent Current vs Temperature  
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6.9 Typical Characteristics (continued)  
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)  
25  
20  
15  
10  
5
25  
20  
15  
10  
5
0
0
-15 -12  
-9  
-6  
-3  
0
3
6
9
12  
15  
-20  
-15  
-10  
-5  
0
5
10  
15  
20  
125  
18  
Input Offset Voltage (µV)  
Offset Voltage (µV)  
TA = 25°C  
TA = 125°C  
Figure 6-1. Offset Voltage Production Distribution at 25°C  
Figure 6-2. Offset Voltage Distribution at 125°C  
20  
20  
10  
0
15  
10  
5
+3 Sigma  
–3 Sigma  
-10  
0
-20  
-50  
-20  
-15  
-10  
-5  
0
5
10  
15  
20  
-25  
0
25  
50  
75  
100  
Offset Voltage (µV)  
Temperature (°C)  
TA = –40°C  
Figure 6-3. Offset Voltage Distribution at -40°C  
Figure 6-4. Offset Voltage vs Temperature  
15  
12  
9
10  
8
6
4
2
0
6
-2  
-4  
-6  
-8  
-10  
TA = –40°C  
TA = 25°C  
TA = 85°C  
TA = 125°C  
3
0
-0.1 -0.08 -0.06 -0.04 -0.02  
0
0.02 0.04 0.06 0.08 0.1  
-18  
-14  
-10  
-6  
-2  
2
6
10  
14  
Offset Voltage Drift (µV/°C)  
Output Voltage (V)  
Figure 6-5. Offset Voltage Drift Distribution  
Figure 6-6. Offset Voltage vs Output Voltage  
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6.9 Typical Characteristics (continued)  
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)  
200  
190  
180  
170  
160  
150  
140  
0.0001  
0.001  
0.01  
10  
5
0
-5  
0.1  
-10  
-50  
-25  
0
25  
50  
75  
100  
125  
0
10  
20  
30  
40  
Temperature (°C)  
Supply Voltage (V)  
Figure 6-7. Offset Voltage vs Power Supply Voltage  
Figure 6-8. Power-Supply Rejection Ratio vs Temperature  
160  
150  
140  
130  
120  
0.01  
0.1  
1
160  
CMRR  
–PSRR  
+PSRR  
140  
120  
100  
80  
60  
40  
20  
0
1
10  
100  
1k  
10k  
100k  
1M  
10M  
-50  
-25  
0
25  
50  
75  
100  
125  
Frequency (Hz)  
Temperature (°C)  
Figure 6-9. Power-Supply and Common-Mode Rejection Ratio  
vs Frequency  
Figure 6-10. Common-Mode Rejection Ratio vs Temperature  
10  
15  
10  
5
5
0
0
-5  
-5  
-10  
-10  
-14.5  
-14  
-13.5  
-13  
-15  
-10  
-5  
0
5
10  
14  
Common-mode Voltage (V)  
Common-mode Voltage (V)  
Figure 6-11. Offset Voltage vs Common-Mode Voltage  
Figure 6-12. Offset Voltage vs VCM at Low Supply  
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6.9 Typical Characteristics (continued)  
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)  
15  
10  
5
160  
140  
120  
100  
80  
240  
Gain  
Phase 200  
160  
120  
80  
60  
40  
40  
0
0
20  
-40  
-80  
-120  
0
-5  
12.5  
-20  
100m  
13  
13.5  
14  
1
10  
100  
1k  
10k  
100k  
1M  
10M  
Common-mode Voltage (V)  
Frequency (Hz)  
Figure 6-13. Offset Voltage vs VCM at High Supply  
Figure 6-14. Open-Loop Gain and Phase vs Frequency  
180  
0.001  
0.01  
0.1  
180  
170  
160  
150  
140  
130  
120  
0.001  
0.01  
0.1  
RL = 2 kohm  
RL = 10 kohm  
160  
140  
120  
100  
80  
1
10  
100  
1
125  
60  
0.09  
1000  
0.15  
-50  
-25  
0
25  
50  
75  
100  
0.1  
0.11  
0.12  
0.13  
0.14  
Temperature (°C)  
Swing from the Rail (V)  
Figure 6-16. Open-Loop Gain vs Temperature  
Figure 6-15. Open-Loop Gain vs Swing From the Rail  
50  
24  
Gain = +1  
Gain = –1  
Gain = +10  
Gain = +100  
40  
30  
20  
10  
0
20  
16  
12  
8
-10  
-20  
-30  
4
0
100  
1k  
10k  
100k  
1M  
10M  
-500  
-250  
0
250  
500  
Frequency (Hz)  
Input Bias Current (pA)  
Figure 6-17. Closed-Loop Gain vs Frequency  
Figure 6-18. Input Bias Production Distribution  
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6.9 Typical Characteristics (continued)  
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)  
2
1.5  
1
0.75  
0.6  
0.45  
0.3  
0.15  
0
TA= –40°C  
TA = 25°C  
TA = 85°C  
TA = 125°C  
IB–  
IB+  
IOS  
0.5  
0
-0.5  
-1  
-1.5  
-2  
-15  
-10  
-5  
0
5
10  
15  
-50  
-25  
0
25  
50  
75  
100  
125  
Common-Mode Voltage (V)  
Temperature (°C)  
Figure 6-19. Input Bias vs Common-Mode Voltage  
24  
Figure 6-20. Input Bias and Input Offset Current vs Temperature  
100  
20  
16  
12  
8
10  
4
1
100m  
0
1
10  
100  
1k  
10k  
100k  
-400 -300 -200 -100  
0
100  
200  
300  
400  
Frequency (Hz)  
Input Offset Current (pA)  
Figure 6-22. Voltage Noise Density vs Frequency  
Figure 6-21. Input Offset Current Production Distribution  
-70  
G = –1, 10 kohm Load  
G = –1, 2 kohm Load  
G = +1, 10 kohm Load  
G = +1, 2 kohm Load  
-80  
-90  
-100  
-110  
-120  
Time (1 s/div)  
100  
1k  
10k  
Frequency (Hz)  
Figure 6-24. Total Harmonic Distortion + Noise Ratio  
vs Frequency  
Figure 6-23. 0.1-Hz to 10-Hz Noise  
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6.9 Typical Characteristics (continued)  
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)  
1000  
100  
10  
-60  
-66  
G = +1, 2 kohm Load  
G = –1, 2 kohm Load  
G = +1, 10 kohm Load  
G = –1, 10 kohm Load  
-72  
-78  
-84  
-90  
-96  
-102  
-108  
-114  
-120  
100m  
1
10  
100  
1k  
10k  
100k  
10m  
100m  
1
10  
Frequency (Hz)  
Amplitude (VRMS  
)
Figure 6-26. Current Noise vs Frequency  
Figure 6-25. Total Harmonic Distortion + Noise Ratio  
vs Output Amplitude  
40  
15  
12.5  
10  
Vs = ±18 V  
Vs = ±2.25 V  
35  
30  
25  
20  
15  
10  
5
7.5  
5
TA = –40°C  
TA = 25°C  
TA = 85°C  
TA = 125°C  
2.5  
0
0
1
10  
100  
1k  
10k  
100k  
1M  
10M  
0
5
10  
15  
20  
25  
30  
Frequency (Hz)  
Output Current (mA)  
Figure 6-27. Maximum Output Voltage vs Frequency  
Figure 6-28. Output Voltage Swing vs Output Sourcing Current  
0
1000  
TA = –40°C  
TA = 25°C  
TA = 85°C  
-2.5  
-5  
TA = 125°C  
100  
-7.5  
-10  
-12.5  
-15  
10  
1
10  
100  
1k  
10k  
100k  
1M  
10M  
0
5
10  
15  
20  
25  
30  
Frequency (Hz)  
Output Current (mA)  
Figure 6-30. Open-Loop Output Impedance vs Frequency  
Figure 6-29. Output Voltage Swing vs Output Sinking Current  
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6.9 Typical Characteristics (continued)  
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)  
60  
Input (V)  
RISO = 0 ohm  
RISO = 25 ohm  
Output (V)  
50  
40  
30  
20  
10  
0
RISO = 50 ohm  
Time (100 µs/div)  
30  
100  
Capactiance (pF)  
1000  
Gain = 1  
Figure 6-32. Small-Signal Overshoot vs Capacitive Load,  
Gain = +1  
Figure 6-31. No Phase Reversal  
80  
70  
60  
50  
40  
30  
20  
10  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
RISO = 0 ohm  
RISO = 25 ohm  
RISO = 50 ohm  
20  
100  
1000  
30  
100  
1000  
Capacitance (pF)  
Capactiance (pF)  
Gain = –1  
Figure 6-34. Phase Margin vs Capacitive Load  
Figure 6-33. Small-Signal Overshoot vs Capacitive Load,  
Gain = –1  
VOUT  
VIN  
VOUT  
VIN  
Time (500 ns/div)  
Gain = –1  
Time (500 ns/div)  
Gain = –1  
Figure 6-35. Positive Overload Recovery, Gain = –1  
Figure 6-36. Negative Overload Recovery, Gain = –1  
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6.9 Typical Characteristics (continued)  
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)  
3
VOUT (V)  
VIN (V)  
Falling (mV)  
Rising (mV)  
2
1
0
-1  
-2  
-3  
2
3
4
5
6
Time (uS)  
Time (1 µS/div)  
Gain = 1  
Figure 6-37. Settling Time  
Figure 6-38. Small-Signal Step Response, Gain = +1  
VOUT (V)  
VIN (V)  
VIN (V)  
VOUT (V)  
Time (1 µS/div)  
Time (2 µS/div)  
Gain = –1  
Gain = 1  
Figure 6-39. Small-Signal Step Response, Gain = –1  
Figure 6-40. Large-Signal Step Response, Gain = +1  
28  
VOUT (V)  
VIN (V)  
25  
22  
19  
16  
13  
Positive Output Voltage  
Negative Output Voltage  
10  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (°C)  
Time (2 µS/div)  
Gain = –1  
Figure 6-42. Short-Circuit Current vs Temperature  
Figure 6-41. Large-Signal Step Response, Gain = –1  
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6.9 Typical Characteristics (continued)  
at TA = 25°C, VS = ±15V, VCM = VOUT = midsupply, and RL = 10 kΩ (unless otherwise noted)  
140  
130  
120  
110  
100  
90  
250  
200  
150  
100  
50  
80  
Vs = 4.5V  
70  
60  
50  
40  
0
10  
100  
Frequency (MHz)  
1000  
6000  
0
8
16  
24  
32  
40  
Supply Voltage (V)  
Figure 6-43. Electromagnetic Interference Rejection  
Figure 6-44. Quiescent Current vs Supply Voltage  
360  
320  
280  
240  
200  
160  
120  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (°C)  
Figure 6-45. Quiescent Current vs Temperature  
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7 Parameter Measurement Information  
7.1 Typical Specifications and Distributions  
To design a more robust circuit, designers often have questions about a typical specification of an amplifier.  
As a result of natural variations in process technology and manufacturing procedures, every specification of an  
amplifier exhibits some amount of deviation from the ideal value, such as the input bias current of an amplifier.  
These deviations often follow Gaussian (bell curve), or normal distributions. Circuit designers can leverage  
this information to guard-band their system, even when there is no minimum or maximum specification in the  
Electrical Characteristics.  
0.00312% 0.13185%  
0.13185% 0.00312%  
0.00002%  
0.00002%  
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%  
1
1 1 1 1 1 1 1 1  
1
1
1
ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1  
ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61  
ꢀ
Figure 7-1. Ideal Gaussian Distribution  
Figure 7-1 shows an example distribution, where µ, is the mean of the distribution, and where σ, or sigma, is the  
standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-thirds  
(68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the mean  
(from µ – σ to µ + σ).  
Depending on the specification, values listed in the typical column of Electrical Characteristics are represented  
in different ways. As a general guideline, if a specification naturally has a nonzero mean (for example, gain  
bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near  
zero (for example, input bias current), then the typical value is equal to the mean plus one standard deviation  
(µ + σ) to most accurately represent the typical value.  
Use this chart to calculate the approximate probability of a specification in a unit. For example, the OPAx205  
typical input bias current is ±0.1 nA; therefore, 68.2% of all devices are expected to have an input bias from  
±0.1 nA. At 4σ, 99.9937% of the distribution has an input bias less than ±0.28 nA, which means that 0.0063% of  
the population is outside of these limits, and corresponds to approximately 1 in 15,873 units.  
Units that are found to exceed any tested minimum or maximum specifications are removed from production  
material. For example, the OPAx205 have a maximum input bias of ±0.5 nA at 25°C. Although this value  
corresponds to approximately 6σ (approximately 1 in 500 million units), TI removes any unit with a larger input  
bias from production material.  
For specifications with no value in the minimum or maximum column, consider selecting a sigma value  
of sufficient guard band for your application, and design worst-case conditions using this value. Use this  
information to only estimate the performance of a device.  
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8 Detailed Description  
8.1 Overview  
The OPAx205 are the first 36-V bipolar, e-trim operational amplifiers that uses a package-level offset trim  
to minimize the offset voltage and offset voltage drift introduced during the manufacturing process. This trim  
is performed after the device has been assembled to remove any offset errors introduced throughout the  
manufacturing process, and trim communication is disabled afterward. These devices also feature super-beta  
inputs that decrease the input bias current and input current noise.  
The following section shows the simplified diagram of the OPAx205.  
8.2 Functional Block Diagram  
V+  
e-trimTM  
Pre-Driver  
OUT  
Super Beta  
+IN  
IN  
Input Devices  
Overload  
Power  
Limiter  
V
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8.3 Feature Description  
8.3.1 Input Offset Trimming  
The OPAx205 are the industry's first e-trim operational amplifiers built on a bipolar process. The input offset  
voltage of an amplifier is determined by the inherent mismatch between the input transistors. The offset can be  
minimized using laser-trimming performed during the manufacturing process while the devices are still in the  
bare silicon form. However, when the silicon is packaged, the packaging process introduces additional offset due  
to mechanic stresses. TI's new trimming processes are used to trim the offset after the packaging process is  
complete to minimize both inherent and package-induced offsets. After trimming, communication is disabled to  
make sure the amplifiers operate properly in the final system.  
A comparison between production offset values for the industry-popular, laser-trimmed OPA2277 and the  
OPAx205 proprietary trim can be seen in Figure 8-1 and Figure 8-2.  
25  
20  
15  
10  
5
16  
14  
12  
10  
8
Typical distribution  
of packaged units.  
Single, dual, and  
quad included.  
6
4
2
0
0
–50–45–40–35–30–25–20–15–10–5  
0 5 10 15 20 25 30 35 40 45 50  
-50 -40 -30 -20 -10  
0
10  
20  
30  
40  
50  
Offset Voltage (µV)  
Input Offset Voltage (µV)  
Figure 8-1. OPA2277 Laser-Trimmed Operational  
Amplifier Offset  
Figure 8-2. OPAx205 e-trim™ Operational Amplifier  
Offset  
The OPAx205 are also trimmed at two temperatures to minimize the input offset voltage drift over temperature.  
The final performance of the offset drift can be seen in Figure 8-3.  
15  
12  
9
6
3
0
-0.1 -0.08 -0.06 -0.04 -0.02  
0
0.02 0.04 0.06 0.08 0.1  
Offset Voltage Drift (µV/°C)  
Figure 8-3. OPAx205 e-trim™ Operational Amplifier Drift  
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8.3.2 Lower Input Bias With Super-Beta Inputs  
The OPAx205 have a super-beta input transistor architecture. In a transistor, the beta value is the ratio between  
the current flowing into the base and the current flowing from the collector to the emitter. A super-beta transistor  
is one where the beta value has been increased from several hundred to thousands. In a bipolar amplifier, the  
input bias current is the current flowing into the base of the input transistor pair, as well as a small leakage  
current that flows through the ESD diodes. A super-beta input reduces the input bias current of the amplifier. In  
addition, the super-beta inputs lower the input current noise that is directly related to the input bias current of the  
device. A comparison between the input bias current of the OPA2277 and the OPAx205 super-beta input bias  
currents can be seen in Figure 8-4 and Figure 8-5.  
5
4
6
5
IBN  
IBP  
4
3
3
2
2
1
1
0
0
–1  
–2  
–3  
–4  
–5  
-1  
-2  
-3  
-4  
-5  
Curves represent typical  
production units.  
–75  
–50  
–25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (°C)  
Temperature (°C)  
Figure 8-4. OPA2277 Input Bias Current  
8.3.3 Overload Power Limiter  
Figure 8-5. OPAx205 Super-Beta Input Bias Current  
In many bipolar-based amplifiers, the output stage of the amplifier can draw significant (several milliamperes)  
of quiescent current if the output voltage becomes clipped (that is, the output voltage becomes limited by the  
negative or positive supply voltage). This condition can cause the system to enter a high-power consumption  
state, and potentially cause oscillations between the power supply and signal chain. The OPAx205 have an  
advanced output stage design that eliminates this problem. When the output voltage reaches either supply (V+  
or V–), there is virtually no additional current consumption from the nominal quiescent current. This feature helps  
eliminate any potential system problems when the signal chain is disrupted by large external transient voltage.  
8.3.4 EMI Rejection  
The OPAx205 use integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from  
sources, such as wireless communications and densely populated boards with a mix of analog signal chain and  
digital components. EMI immunity can be improved through circuit design techniques that improve the system  
performance. Additional information can be found in the EMI Rejection Ratio of Operation Amplifiers application  
report.  
8.4 Device Functional Modes  
The OPAx205 have a single functional mode and are operational with any supply between 4.5 V (±2.25 V) and  
36 V (±18 V).  
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9 Application and Implementation  
Note  
Information in the following applications sections is not part of the TI component specification,  
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for  
determining suitability of components for their purposes, as well as validating and testing their design  
implementation to confirm system functionality.  
9.1 Application Information  
The OPAx205 are unity-gain stable operational amplifiers with very low offset voltage, offset voltage drift, voltage  
noise, current noise and power consumption. These features make this device family a great choice for a variety  
of space-constrained and power-constrained systems.  
9.2 Typical Applications  
9.2.1 High-Precision Signal-Chain Input Buffer  
A common application for the OPAx205 is an input buffer for the signal chain of a data acquisition (DAQ) or  
field instrumentation system. This amplifier family is selected because of the low offset and drift that maintain  
system accuracy across a variety of operating conditions. The low power consumption of the OPAx205 enables  
the device to be used in battery-operated or high-density applications, where thermal dissipation is difficult. The  
low 1/f (flicker) noise and broadband noise allow for higher-accuracy signal chains, such as those using a 24-bit  
delta-sigma analog-to-digital converter (ADC). If a higher sampling rate is needed, the OPAx205 can be paired  
with a fully differential amplifier, such as the THP210, to drive the ADC inputs. Figure 9-1 shows the OPA2205  
configured as an input buffer to a differential ADC driver.  
750 ꢀ  
470 pF  
+7 V  
3 kꢀ  
œ
2.4 kꢀ  
IN+  
+
OPA2205  
Þ7 V  
100 ꢀ  
100 ꢀ  
+7 V  
œ
1.1 nF  
1 nF  
VOUT  
+
THP210  
Þ7 V  
+7 V  
2.4 kꢀ  
3 kꢀ  
œ
INÞ  
+
470 pF  
OPA2205  
Þ7 V  
750 ꢀ  
Figure 9-1. OPA2205 Configured as a DAQ Input Buffer  
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9.2.1.1 Design Requirements  
The design requirements for this application are:  
•
•
•
•
Input range: ±10 V  
Input frequency: 10 kHz  
Output voltage: ±3.3 V  
Quiescent current: < 1.5 mA  
9.2.1.2 Detailed Design Procedure  
In this application, the input signal ranges from –10 V to +10 V with a frequency of up to 10 kHz. Because  
of possible portable-use cases for this data acquisition system (DAQ), low power consumption is required to  
minimize battery drain and thermal dissipation requirements.  
To maintain high system accuracy the OPA2205 is selected as input buffers. This device is selected because of  
the high dc precision (4 µV offset and 0.08 µV/°C offset drift), low flicker noise (0.2 µVpp), and low quiescent  
current (220 µA). The buffers are followed by a high-precision, fully differential amplifier such as the THP210,  
which is capable of accurately driving a 24-bit, fully differential ADC such as the ADS127L01.  
9.2.1.3 Application Curves  
The gain plot for this system can be seen in Figure 9-2. This plot shows proper attenuation of the ±10-V signal to  
the target ±3.3-V output, and adequate bandwidth to support the input frequency range.  
0
-25  
-50  
-75  
-100  
-125  
-150  
10  
100  
1K  
10K 100K  
Frequency (Hz)  
1M  
10M  
100M  
Figure 9-2. Gain Plot of DAQ Front End  
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9.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier  
Figure 9-3 shows the OPA2205 configured as a two-op-amp, discrete instrumentation amplifier. This  
configuration allows for a differential signal measurement, such as the signal from a load cell, with higher  
input impedance to the signal chain than most monolithic instrumentation amplifiers. The strong ac and dc  
performance of the OPA2205 enables high accuracy measurements.  
V+  
V1  
+
–
V
OUT = (V1 – V2)(1 + R2/R1)  
OPA2205  
R2  
V
V+  
R1  
V2  
+
–
OPA2205  
V
R2  
R1  
GND  
Figure 9-3. OPA2205 Configured as a Two-Op-Amp, Discrete Instrumentation Amplifier  
9.2.3 Second-Order Low-Pass Filter  
The OPAx205 has a very-low broadband voltage noise of only 7.2 nV/√Hz and flicker noise of 0.2 µVPP given the  
low power consumption of only 220 µA, making this device an excellent choice for low-power filter applications.  
Figure 9-4 is an example of one channel of the OPAx205 configured as a second-order low-pass filter with a  
cutoff frequency of 50 kHz.  
2.25 k  
1 nF  
2.25 k  
1.13 k  
Input  
–
+
Output  
4 nF  
GND  
GND  
Figure 9-4. Second-Order Low-Pass Filter  
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9.3 Power Supply Recommendations  
The OPAx205 operate with a power supply between 4.5 V to 36 V (±2.25 V to ±18 V). Parameters that can  
exhibit significant variance with regard to operating voltage are presented in Section 6.9.  
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or  
high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section  
9.4.1.  
9.4 Layout  
9.4.1 Layout Guidelines  
For best operational performance of the device, use good PCB layout practices, including:  
•
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close  
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply  
applications. Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as  
well as through the individual op amp. Bypass capacitors are used to reduce the coupled noise by providing  
low-impedance power sources local to the analog circuitry.  
•
•
Make sure to physically separate digital and analog grounds paying attention to the flow of the ground  
current. Separate grounding for analog and digital portions of circuitry is one of the simplest and most  
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to  
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup.  
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If  
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed  
to in parallel with the noisy trace.  
•
•
•
Place the external components as close to the device as possible. As shown in Figure 9-5, keep RF and RG  
close to the inverting input to minimize parasitic capacitance.  
Keep the length of input traces as short as possible. Always remember that the input traces are the most  
sensitive part of the circuit.  
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce  
leakage currents from nearby traces that are at different potentials.  
•
•
Clean the PCB following board assembly for best performance.  
Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic  
package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced  
into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30  
minutes is sufficient for most circumstances.  
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9.4.2 Layout Example  
VIN  
+
VOUT  
RG  
RF  
Figure 9-5. Schematic Representation  
Place components  
close to device and to  
each other to reduce  
parasitic errors  
Run the input traces  
as far away from  
the supply lines  
as possible  
RF  
VS+  
NC  
NC  
RG  
Use a low-ESR,  
V+  
GND  
VIN  
–IN  
+IN  
V–  
ceramic bypass  
capacitor  
OUTPUT  
NC  
GND  
GND  
VS–  
VOUT  
Ground (GND) plane on another layer  
Use low-ESR,  
ceramic bypass  
capacitor  
Figure 9-6. Operational Amplifier Board Layout for Noninverting Configuration  
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10 Device and Documentation Support  
10.1 Device Support  
10.1.1 Development Support  
The following evaluation modules are available:  
•
•
DIP-ADAPTER-EVM  
DIYAMP-EVM  
10.1.1.1 PSpice® for TI  
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create  
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development  
cost and time to market.  
10.2 Documentation Support  
10.2.1 Related Documentation  
For related documentation see the following:  
•
•
Texas Instruments, DIP-ADAPTER-EVM user's guide  
Texas Instruments, DIYAMP-SOIC-EVM user's guide  
10.3 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on  
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For  
change details, review the revision history included in any revised document.  
10.4 Support Resources  
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight  
from the experts. Search existing answers or ask your own question to get the quick design help you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do  
not necessarily reflect TI's views; see TI's Terms of Use.  
10.5 Trademarks  
e-trim™ and TI E2E™ are trademarks of Texas Instruments.  
PSpice® is a registered trademark of Cadence Design Systems, Inc.  
All trademarks are the property of their respective owners.  
10.6 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
10.7 Glossary  
TI Glossary  
This glossary lists and explains terms, acronyms, and definitions.  
11 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGE OPTION ADDENDUM  
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16-Apr-2023  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
OPA205ADR  
OPA205ADT  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
D
D
8
8
3000 RoHS & Green  
250 RoHS & Green  
2500 RoHS & Green  
250 RoHS & Green  
3000 RoHS & Green  
250 RoHS & Green  
3000 RoHS & Green  
250 RoHS & Green  
3000 RoHS & Green  
NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Call TI  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
OP205A  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
Samples  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
Call TI  
OP205A  
22A5  
OPA2205ADGKR  
OPA2205ADGKT  
OPA2205ADR  
OPA2205ADT  
OPA4205ADR  
OPA4205ADT  
OPA4205APWR  
OPA4205APWT  
XOPA205ADR  
XOPA2205DGKR  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
D
8
8
22A5  
8
2205A  
SOIC  
D
8
2205A  
SOIC  
D
14  
14  
14  
14  
8
OPA4205A  
OPA4205A  
OP4205A  
OP4205A  
SOIC  
D
TSSOP  
TSSOP  
SOIC  
PW  
PW  
D
250  
3000  
2500  
RoHS & Green  
TBD  
VSSOP  
DGK  
8
TBD  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-Apr-2023  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
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17-Apr-2023  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
OPA205ADR  
OPA205ADT  
SOIC  
SOIC  
D
D
8
8
3000  
250  
330.0  
180.0  
330.0  
180.0  
330.0  
180.0  
330.0  
180.0  
330.0  
180.0  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
16.4  
16.4  
12.4  
12.4  
6.4  
6.4  
5.3  
5.3  
6.4  
6.4  
6.5  
6.5  
6.9  
6.9  
5.2  
5.2  
3.4  
3.4  
5.2  
5.2  
9.0  
9.0  
5.6  
5.6  
2.1  
2.1  
1.4  
1.4  
2.1  
2.1  
2.1  
2.1  
1.6  
1.6  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
16.0  
16.0  
12.0  
12.0  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
OPA2205ADGKR  
OPA2205ADGKT  
OPA2205ADR  
OPA2205ADT  
OPA4205ADR  
OPA4205ADT  
OPA4205APWR  
OPA4205APWT  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
D
8
2500  
250  
8
8
3000  
250  
SOIC  
D
8
SOIC  
D
14  
14  
14  
14  
3000  
250  
SOIC  
D
TSSOP  
TSSOP  
PW  
PW  
3000  
250  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
17-Apr-2023  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
OPA205ADR  
OPA205ADT  
SOIC  
SOIC  
D
D
8
8
3000  
250  
356.0  
210.0  
356.0  
210.0  
356.0  
210.0  
356.0  
210.0  
356.0  
210.0  
356.0  
185.0  
356.0  
185.0  
356.0  
185.0  
356.0  
185.0  
356.0  
185.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
35.0  
OPA2205ADGKR  
OPA2205ADGKT  
OPA2205ADR  
OPA2205ADT  
OPA4205ADR  
OPA4205ADT  
OPA4205APWR  
OPA4205APWT  
VSSOP  
VSSOP  
SOIC  
DGK  
DGK  
D
8
2500  
250  
8
8
3000  
250  
SOIC  
D
8
SOIC  
D
14  
14  
14  
14  
3000  
250  
SOIC  
D
TSSOP  
TSSOP  
PW  
PW  
3000  
250  
Pack Materials-Page 2  
PACKAGE OUTLINE  
D0008A  
SOIC - 1.75 mm max height  
SCALE 2.800  
SMALL OUTLINE INTEGRATED CIRCUIT  
C
SEATING PLANE  
.228-.244 TYP  
[5.80-6.19]  
.004 [0.1] C  
A
PIN 1 ID AREA  
6X .050  
[1.27]  
8
1
2X  
.189-.197  
[4.81-5.00]  
NOTE 3  
.150  
[3.81]  
4X (0 -15 )  
4
5
8X .012-.020  
[0.31-0.51]  
B
.150-.157  
[3.81-3.98]  
NOTE 4  
.069 MAX  
[1.75]  
.010 [0.25]  
C A B  
.005-.010 TYP  
[0.13-0.25]  
4X (0 -15 )  
SEE DETAIL A  
.010  
[0.25]  
.004-.010  
[0.11-0.25]  
0 - 8  
.016-.050  
[0.41-1.27]  
DETAIL A  
TYPICAL  
(.041)  
[1.04]  
4214825/C 02/2019  
NOTES:  
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.  
Dimensioning and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed .006 [0.15] per side.  
4. This dimension does not include interlead flash.  
5. Reference JEDEC registration MS-012, variation AA.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
D0008A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
8X (.061 )  
[1.55]  
SYMM  
SEE  
DETAILS  
1
8
8X (.024)  
[0.6]  
SYMM  
(R.002 ) TYP  
[0.05]  
5
4
6X (.050 )  
[1.27]  
(.213)  
[5.4]  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:8X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
EXPOSED  
METAL  
EXPOSED  
METAL  
.0028 MAX  
[0.07]  
.0028 MIN  
[0.07]  
ALL AROUND  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4214825/C 02/2019  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
D0008A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
8X (.061 )  
[1.55]  
SYMM  
1
8
8X (.024)  
[0.6]  
SYMM  
(R.002 ) TYP  
[0.05]  
5
4
6X (.050 )  
[1.27]  
(.213)  
[5.4]  
SOLDER PASTE EXAMPLE  
BASED ON .005 INCH [0.125 MM] THICK STENCIL  
SCALE:8X  
4214825/C 02/2019  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you  
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these  
resources.  
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for  
TI products.  
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023, Texas Instruments Incorporated  

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