OPA2197 [TI]
双路 36V 精密轨到轨输入/输出、低失调电压运算放大器;
| 型号： | OPA2197 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路 36V 精密轨到轨输入/输出、低失调电压运算放大器 放大器 运算放大器 |
| 文件： | 总50页 (文件大小：2161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA197, OPA2197, OPA4197
ZHCSEI8C –JANUARY 2016–REVISED MARCH 2018
OPAx197 36V 轨到轨输入/输出
、低失调电压精密运算放大器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
低失调电压：±100µV（最大值）
低失调电压温漂：±2.5µV/°C（最大值）
低噪声：1kHz 时为 5.5nV/√Hz
高共模抑制：120dB（最小值）
低偏置电流：±5pA（典型值）
轨到轨输入和输出
OPAx197 系列（OPA197、OPA2197 和 OPA4197）
是新一代 36V 运算放大器。
这些器件具有出色的直流精度和交流性能，包括轨至轨
输入/输出、低偏移（典型值为 ±25µV）、低温漂（典
型值为 ±0.25µV/°C）和 10MHz 带宽。
OPAx196 拥有 拥有诸多独一无二的特性，例如电源轨
的差分输入电压范围、高输出电流 (±65mA)、高达
1nF 的高容性负载驱动以及高转换率 (20V/µs)，是稳
健耐用的高性能运算放大器，适用于各种高压工业 应
用。
高带宽：10MHz GBW
高压摆率：20V/µs
低静态电流：每个放大器 1mA（典型值）
宽电源电压范围：±2.25V 至 ±18V，+4.5V 至
+36V
•
•
•
•
已过滤电磁干扰 (EMI) 和射频干扰 (RFI) 的输入
电源轨的差分输入电压范围
高容性负载驱动能力：1nF
OPA197 系列运算放大器采用标准封装，在 -40°C 至
+125°C 的额定温度范围内工作。
器件信息(1)
行业标准封装：
器件型号
封装
SOIC (8)
封装尺寸（标称值）
–
–
–
SOIC-8、SOT-5 和 VSSOP-8 单体封装
SOIC-8 和 VSSOP-8 双列封装
4.90mm × 3.90mm
小外形尺寸晶体管
(SOT) (5)
OPA197
2.90mm × 1.60mm
四通道电源版本采用 SOIC-14 和 TSSOP-14 封
装
VSSOP (8)
SOIC (8)
3.00mm × 3.00mm
4.90mm × 3.90mm
3.00mm × 3.00mm
8.65mm x 3.90mm
5.00mm x 4.40mm
OPA2197
OPA4197
2 应用
VSSOP (8)
SOIC (14)
TSSOP (14)
•
•
•
•
•
•
•
多路复用数据采集系统
测试和测量设备
高分辨率模数转换器 (ADC) 驱动器放大器
SAR ADC 基准缓冲器
可编程逻辑控制器
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
高侧和低侧电流检测
高精度比较器
OPA197 应用于高压多路复用数据采集系统
Analog Inputs
REF3140
RC Filter
RC Filter
OPA625
Reference Driver
Bridge Sensor
Gain
Gain
Gain
OPA197
+
4:2
HV MUX
Thermocouple
REF
VIN
+
OPA197
P
OPA197
+
Antialiasing
Filter
ADS8864
VIN
Current Sensing
M
High-Voltage Multiplexed Input
High-Voltage Level Translation
VCM
Optical Sensor
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS737
OPA197, OPA2197, OPA4197
ZHCSEI8C –JANUARY 2016–REVISED MARCH 2018
www.ti.com.cn
目录
7.3 Feature Description................................................. 20
7.4 Device Functional Modes........................................ 26
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Applications ................................................ 27
Power Supply Recommendations...................... 30
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information: OPA197 .................................. 6
6.5 Thermal Information: OPA2197 ................................ 6
6.6 Thermal Information: OPA4197 ................................ 6
8
9
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 31
11 器件和文档支持 ..................................................... 32
11.1 器件支持................................................................ 32
11.2 文档支持................................................................ 32
11.3 相关链接................................................................ 32
11.4 接收文档更新通知 ................................................. 33
11.5 社区资源................................................................ 33
11.6 商标....................................................................... 33
11.7 静电放电警告......................................................... 33
11.8 Glossary................................................................ 33
12 机械、封装和可订购信息....................................... 33
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8
V to 36 V)................................................................... 7
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS
=
4.5 V to 8 V)............................................................... 9
6.9 Typical Characteristics............................................ 11
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
7
4 修订历史记录
Changes from Revision B (October 2016) to Revision C
Page
•
•
已更改 将“低失调电压：±250µV（最大值）”更改成了“低失调电压：±100µV（最大值）” ..................................................... 1
Changed Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) Input offset voltage VS = ±18 V under
OFFSET VOLTAGE from "±250" to "±100"; remove "TA = 0°C to 85°C" and "TA = –40°C to +125°C" rows from same ...... 7
•
•
•
Changed Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) Input offset voltage VCM = (V+) – 1.5 V
under OFFSET VOLTAGE from "±250" to "±100"; remove "TA = 0°C to 85°C" and "TA = –40°C to +125°C" rows
from same............................................................................................................................................................................... 7
Changed Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) Input offset voltage VS = ±2.25 V, VCM
= (V+) – 3 V under OFFSET VOLTAGE from "±250" to "±100"; remove "TA = 0°C to 85°C" and "TA = –40°C to
+125°C" rows from same........................................................................................................................................................ 9
Changed Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) Input offset voltage VS = ±3 V, VCM
=
(V+) – 1.5 V under OFFSET VOLTAGE from "±250" to "±100"; remove "TA = 0°C to 85°C" and "TA = –40°C to
+125°C" rows from same........................................................................................................................................................ 9
•
•
Changed "0" on Frequency (Hz) axis to "0.1" ..................................................................................................................... 11
Changed "....to achieve a very low offset voltage of 250 µV (max)..." to "...to achieve a very low offset voltage of 100
µV (maximum)..." ................................................................................................................................................................. 19
Changes from Revision A (July 2016) to Revision B
Page
•
•
•
•
Added new row for PW package to Input bias current parameter ......................................................................................... 7
Added new row for PW package to Input offset current parameter ...................................................................................... 7
Added new footnote (1) to Open-loop gain parameter........................................................................................................... 7
Changed Slew rate parameter from 20 V/µs : to 14 V/µs .................................................................................................... 10
Changes from Original (January 2016) to Revision A
Page
•
Added OPA2197 and OPA4197 CDM values to ESD Ratings table...................................................................................... 5
2
Copyright © 2016–2018, Texas Instruments Incorporated
OPA197, OPA2197, OPA4197
www.ti.com.cn
ZHCSEI8C –JANUARY 2016–REVISED MARCH 2018
5 Pin Configuration and Functions
D and DGK Packages: OPA197
8-Pin SOIC and VSSOP
Top View
D and DGK Packages: OPA2197
8-Pin SOIC and VSSOP
Top View
NC
-IN
+IN
V-
1
2
3
4
8
7
6
5
NC
V+
OUT A
-IN A
+IN A
V-
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
OUT
NC
DBV Package: OPA197
5-Pin SOT
D and PW Packages: OPA4197
14-Pin SOIC and TSSOP
Top View
Top View
V+
OUT
V-
1
2
3
5
4
OUT A
1
2
3
4
5
6
7
14 OUT D
-IN A
+IN A
V+
13 -IN D
12 +IN D
11 V-
-IN
+IN
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
OUT C
Copyright © 2016–2018, Texas Instruments Incorporated
3
OPA197, OPA2197, OPA4197
ZHCSEI8C –JANUARY 2016–REVISED MARCH 2018
www.ti.com.cn
Pin Functions: OPA197
PIN
OPA197
I/O
DESCRIPTION
NAME
D (SOIC),
DGK (VSSOP)
DBV (SOT)
+IN
–IN
NC
OUT
V+
3
3
4
I
Noninverting input
Inverting input
2
I
1, 5, 8
—
1
—
O
—
—
No internal connection (can be left floating)
Output
6
7
4
5
Positive (highest) power supply
Negative (lowest) power supply
V–
2
Pin Functions: OPA2197 and OPA4197
PIN
OPA2197
OPA4197
I/O
DESCRIPTION
NAME
D (SOIC),
D (SOIC),
DGK (VSSOP)
PW (TSSOP)
+IN A
+IN B
+IN C
+IN D
–IN A
–IN B
–IN C
–IN D
OUT A
OUT B
OUT C
OUT D
V+
3
5
3
5
I
I
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Inverting input, channel A
Inverting input, channel B
Inverting input,,channel C
Inverting input, channel D
Output, channel A
—
—
2
10
12
2
I
I
I
6
6
I
—
—
1
9
I
13
1
I
O
O
O
O
—
—
7
7
Output, channel B
—
—
8
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
V–
4
11
4
Copyright © 2016–2018, Texas Instruments Incorporated
OPA197, OPA2197, OPA4197
www.ti.com.cn
ZHCSEI8C –JANUARY 2016–REVISED MARCH 2018
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Dual supply
Supply voltage, VS = (V+) – (V–)
±20
40
V
Single supply
Common-mode
Voltage
(V–) – 0.5
(V+) + 0.5
(V+) – (V–) + 0.2
±10
V
Signal input pins
Output short circuit(2)
Temperature
Differential
Current
mA
Continuous
150
Operating, TA
Junction, TJ
Storage, Tstg
–55
–65
150
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±4000
±1000
±750
UNIT
ALL DEVICES
V(ESD)
Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V
V
V
V
OPA197
V(ESD)
Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
OPA2197
V(ESD)
OPA4197
V(ESD)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2.25
4.5
NOM
MAX
±18
36
UNIT
Dual supply
Supply voltage, VS = (V+) – (V–)
Operating temperature, TA
V
Single supply
–40
125
°C
Copyright © 2016–2018, Texas Instruments Incorporated
5
OPA197, OPA2197, OPA4197
ZHCSEI8C –JANUARY 2016–REVISED MARCH 2018
www.ti.com.cn
6.4 Thermal Information: OPA197
OPA197
DBV (SOT)
5 PINS
158.8
60.7
THERMAL METRIC(1)
D (SOIC)
8 PINS
115.8
60.1
DGK (VSSOP)
8 PINS
180.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
67.9
56.4
44.8
102.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
12.8
1.6
10.4
ψJB
55.9
4.2
100.3
RθJC(bot)
N/A
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2197
OPA2197
THERMAL METRIC(1)
D (SOIC)
8 PINS
107.9
53.9
DGK (VSSOP)
8 PINS
158
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
48.6
48.9
78.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
6.6
3.9
ψJB
48.3
77.3
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4197
OPA4197
THERMAL METRIC(1)
D (SOIC)
14 PINS
86.4
PW (TSSOP)
14 PINS
92.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
46.3
27.5
41.0
33.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
11.3
1.9
ψJB
40.7
33.1
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2016–2018, Texas Instruments Incorporated
OPA197, OPA2197, OPA4197
www.ti.com.cn
ZHCSEI8C –JANUARY 2016–REVISED MARCH 2018
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = ±18 V
±25
±10
±100
±100
±2.5
±4.5
VOS
Input offset voltage
µV
VCM = (V+) – 1.5 V
VS = ±18 V, VCM = (V+) – 3 V
VS = ±18 V, VCM = (V+) – 1.5 V
±0.5
±0.8
dVOS/dT
PSRR
Input offset voltage drift
TA = –40°C to +125°C
µV/°C
µV/V
Power-supply rejection
ratio
TA = –40°C to +125°C
TA = –40°C to +125°C
±1
±3
INPUT BIAS CURRENT
±5
±20
±5
pA
nA
pA
nA
IB
Input bias current
PW package only
±15
±20
±2
±2
IOS
Input offset current
Input voltage noise
TA = –40°C to +125°C
PW package only
f = 0.1 Hz to 10 Hz
±10
NOISE
(V–) – 0.1 V < VCM < (V+) – 3 V
1.30
4
En
µVPP
(V+) – 1.5 V < VCM < (V+) + 0.1 V f = 0.1 Hz to 10 Hz
f = 100 Hz
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 1 kHz
10.5
5.5
32
Input voltage noise
density
en
nV/√Hz
f = 100 Hz
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 1 kHz
12.5
Input current noise
density
in
f = 1 kHz
1.5
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
range
VCM
(V–) – 0.1
(V+) + 0.1
V
120
110
100
80
140
126
120
100
VS = ±18 V,
(V–) – 0.1 V < VCM < (V+) – 3 V
TA = –40°C to +125°C
dB
Common-mode
rejection ratio
VS = ±18 V,
(V+) – 1.5 V < VCM < (V+)
CMRR
TA = –40°C to +125°C
VS = ±18 V,
(V+) – 3 V < VCM < (V+) – 1.5 V
See Typical Characteristics
INPUT IMPEDANCE
ZID
ZIC
Differential
Common-mode
100 || 1.6
1 || 6.4
MΩ || pF
1013Ω || pF
OPEN-LOOP GAIN
VS = ±18 V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RLOAD = 2 kΩ
120
110
120
110
134
126
143
134
TA = –40°C to +125°C
TA = –40°C to +125°C
Open-loop voltage
gain(1)
AOL
dB
VS = ±18 V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RLOAD = 10 kΩ
(1) For OPA2197, OPA4197: When driving high current loads on multiple channels, make sure the junction temperature does not exceed
125°C.
Copyright © 2016–2018, Texas Instruments Incorporated
7
OPA197, OPA2197, OPA4197
ZHCSEI8C –JANUARY 2016–REVISED MARCH 2018
www.ti.com.cn
Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
SR
Unity gain bandwidth
10
20
MHz
V/µs
Slew rate
VS = ± 18 V, G = 1, 10-V step
V S = ±18 V, G = 1, 10-V step
V S = ±18 V, G = 1, 5-V step
V S = ±18 V, G = 1, 10-V step
V S = ±18 V, G = 1, 5-V step
1.4
0.9
2.1
1.8
200
To 0.01%
ts
Settling time
µs
ns
To 0.001%
tOR
Overload recovery time VIN × G = VS
Total harmonic
THD+N
OUTPUT
G = 1, f = 1 kHz, VO = 3.5 VRMS
0.00008%
distortion + noise
No load
5
95
25
125
500
25
Positive rail
RLOAD = 10 kΩ
RLOAD = 2 kΩ
No load
430
5
Voltage output swing
from rail
VO
mV
Negative rail
VS = ±18 V
RLOAD = 10 kΩ
RLOAD = 2 kΩ
95
125
500
430
±65
ISC
Short-circuit current
Capacitive load drive
mA
CLOAD
See Typical Characteristics
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A, See Figure 26
375
Ω
POWER SUPPLY
IO = 0 A
1
1.3
1.5
Quiescent current per
IQ
mA
°C
amplifier
TEMPERATURE
Thermal protection(2)
TA = –40°C to +125°C, IO = 0 A
140
(2) For a detailed description of thermal protection, see the Thermal Protection section.
8
Copyright © 2016–2018, Texas Instruments Incorporated
OPA197, OPA2197, OPA4197
www.ti.com.cn
ZHCSEI8C –JANUARY 2016–REVISED MARCH 2018
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = ±2.25 V, VCM = (V+) – 3 V
±5
±100
µV
VOS
Input offset voltage
(V+) – 3.5 V < VCM < (V+) – 1.5 V
VS = ±3 V, VCM = (V+) – 1.5 V
VS = ±2.25 V, VCM = (V+) – 3 V
VS = ±2.25 V, VCM = (V+) – 1.5 V
See Common-Mode Voltage Range section
±10
±0.5
±0.8
±100
±2.5
±4.5
µV
dVOS/dT
PSRR
Input offset voltage drift
TA = –40°C to +125°C
µV/°C
Power-supply rejection
ratio
TA = –40°C to +125°C, VCM = VS / 2 – 0.75 V
±2
µV/V
INPUT BIAS CURRENT
±5
±2
±20
±5
pA
nA
pA
nA
IB
Input bias current
TA = –40°C to +125°C
TA = –40°C to +125°C
±20
±2
IOS
Input offset current
Input voltage noise
NOISE
En
(V–) – 0.1 V < VCM < (V+) – 3 V, f = 0.1 Hz to 10 Hz
(V+) – 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz
1.30
4
µVPP
f = 100 Hz
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 1 kHz
10.5
5.5
32
Input voltage noise
density
en
nV/√Hz
f = 100 Hz
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 1 kHz
12.5
Input current noise
density
in
f = 1 kHz
1.5
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
range
VCM
(V–) – 0.1
(V+) + 0.1
V
90
88
94
77
110
104
120
100
VS = ±2.25 V,
(V–) – 0.1 V < VCM < (V+) – 3 V
TA = –40°C to +125°C
dB
Common-mode
rejection ratio
VS = ±2.25 V,
(V+) – 1.5 V < VCM < (V+)
CMRR
TA = –40°C to +125°C
VS = ±2.25 V,
(V+) – 3 V < VCM < (V+) – 1.5 V
See Typical Characteristics
INPUT IMPEDANCE
ZID
ZIC
Differential
Common-mode
100 || 1.6
1 || 6.4
MΩ || pF
1013Ω || pF
OPEN-LOOP GAIN
VS = ±2.25 V,
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RLOAD = 2 kΩ
104
100
104
100
126
114
134
120
TA = –40°C to +125°C
TA = –40°C to +125°C
AOL
Open-loop voltage gain
dB
VS = ±2.25 V,
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RLOAD = 10 kΩ
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Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
SR
Unity gain bandwidth
10
14
MHz
V/µs
µs
Slew rate
G = 1, 1-V step
To 0.01%
ts
Settling time
VS = ±3 V, G = 1, 5-V step
1
tOR
Overload recovery time VIN× G = VS
200
ns
OUTPUT
No load
5
95
25
125
500
25
Positive rail
RLOAD = 10 kΩ
RLOAD = 2 kΩ
No load
430
5
Voltage output swing
from rail
VO
mV
Negative rail
RLOAD = 10 kΩ
RLOAD = 2 kΩ
95
125
500
430
±65
ISC
Short-circuit current
Capacitive load drive
VS = ±2.25 V
mA
CLOAD
See Typical Characteristics
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A, see Figure 26
375
Ω
POWER SUPPLY
1
1.3
1.5
Quiescent current per
IQ
IO = 0 A
mA
°C
amplifier
TEMPERATURE
Thermal protection(1)
TA = –40°C to +125°C
140
(1) For a detailed description of thermal protection, see the Thermal Protection section.
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6.9 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Figure 1, Figure 2, Figure 3
Figure 4
Offset Voltage Production Distribution
Offset Voltage Drift Distribution
Offset Voltage vs Temperature
Figure 5
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Power Supply
Figure 6, Figure 7, Figure 8
Figure 9
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain and Phase vs Frequency
Input Bias Current vs Common-Mode Voltage
Input Bias Current vs Temperature
Output Voltage Swing vs Output Current (maximum supply)
CMRR and PSRR vs Frequency
CMRR vs Temperature
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14, Figure 15
Figure 16
Figure 17
PSRR vs Temperature
Figure 18
0.1-Hz to 10-Hz Noise
Figure 19
Input Voltage Noise Spectral Density vs Frequency
THD+N Ratio vs Frequency
Figure 20
Figure 21
THD+N vs Output Amplitude
Figure 22
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
Open Loop Gain vs Temperature
Open Loop Output Impedance vs Frequency
Small Signal Overshoot vs Capacitive Load (100-mV output step)
No Phase Reversal
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27, Figure 28
Figure 29
Positive Overload Recovery
Figure 30
Negative Overload Recovery
Figure 31
Small-Signal Step Response (100 mV)
Large-Signal Step Response
Figure 32, Figure 33
Figure 34
Settling Time
Figure 35, Figure 36, ,
Figure 37
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
Propagation Delay Rising Edge
Figure 38
Figure 39
Propagation Delay Falling Edge
Figure 40
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
500
400
300
200
100
0
35
30
25
20
15
10
5
0
-100 -80 -60 -40 -20
0
20 40 60 80 100
-60 -50 -40 -30 -20 -10
0
10 20 30 40 50 60
Input Offset Voltage (mV)
Input Offset Voltage (mV)
4770 production units
Figure 1. Offset Voltage Production Distribution at 25°C
Figure 2. Offset Voltage Production Distribution at 125°C
35
15
30
25
20
15
10
5
12
9
6
3
0
0
-200 -150 -100
-50
0
50
100
150
200
-1.2 -1.0 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8 1.0 1.2
Input Offset Voltage (mV)
Input Offset Voltage Drift (mV/èC)
Figure 3. Offset Voltage Production Distribution at –40°C
Figure 4. Offset Voltage Drift Distribution
from –40°C to +125°C
150
100
50
75
50
25
0
0
œ50
œ100
œ150
-25
-50
-75
0
25
50
75
100 125 150
œ75 œ50 œ25
-20
-15
-10
-5
0
5
10
15
20
Temperature (°C)
Common-Mode Voltage (V)
C001
6 typical units
9 typical units
Figure 5. Offset Voltage vs Temperature
Figure 6. Offset Voltage vs Common-Mode Voltage
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
200
150
100
50
75
50
25
0
0
-25
-50
-75
-100
-50
-100
-150
-200
13
14
15
16
17
18
19
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
Common-Mode Voltage (V)
Common-Mode Voltage (V)
6 typical units
6 typical units
Figure 7. Offset Voltage vs Common-Mode Voltage
Figure 8. Offset Voltage vs Common-Mode Voltage
100
140
120
100
80
280
Open Loop Gain
Phase
75
50
240
200
160
120
80
25
0
60
-25
-50
-75
-100
40
20
40
0
0
-20
-40
10M 100M
0
2
4
6
8
10
12
14
16
18
20
1
10
100
1k
10k
100k
1M
Power-Supply Voltage (V)
Frequency (Hz)
6 typical units
CLOAD = 15 pF
Figure 9. Offset Voltage vs Power Supply
Figure 10. Open-Loop Gain and Phase vs Frequency
60
40
20
0
1000
800
G = 100 V/V
G = +1 V/V
G = 10 V/V
G = -1 V/V
600
400
200
0
œ200
œ400
œ600
œ800
œ1000
-20
0.0
5.0
10.0 15.0 20.0
œ20.0 œ15.0 œ10.0 œ5.0
1k
10k
100k
Frequency (Hz)
1M
10M
50M
VCM (V)
C001
Figure 11. Closed-Loop Gain and Phase vs Frequency
Figure 12. Input Bias Current vs Common-Mode Voltage
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
3000
2000
1000
0
(V-) + 5
(V-) + 4
(V-) + 3
(V-) + 2
(V-) + 1
(V-)
IB-
IB+
IOS
+125°C
+85°C
-40°C
25°C
(V-) - 1
-1000
0
10
20
30
40
50
60
70
80
-75
-50
-25
0
25
50
75
100
125
Temperature (èC)
Output Current (mA)
C001
Figure 13. Input Bias Current vs Temperature
Figure 14. Output Voltage Swing from Negative Power
Supply vs Output Current (Maximum Supply)
(V+) + 1
(V+)
160.0
140.0
120.0
100.0
80.0
(V+) - 1
(V+) - 2
(V+) - 3
(V+) - 4
(V+) - 5
25°C
-40°C
+125°C
60.0
+PSRR
40.0
CMRR
20.0
-PSRR
0.0
+85°C
0
10
20
30
40
50
60
70
80
1
10
100
1k
10k
100k
1M
C012
Output Current (mA)
Frequency (Hz)
C001
Figure 16. CMRR and PSRR vs Frequency
Figure 15. Output Voltage Swing from Positive Power
Supply vs Output Current (Maximum Supply)
10
8
1
0.8
0.6
0.4
0.2
0
6
4
VS = ±2.25 V
2
0
œ2
-0.2
-0.4
-0.6
-0.8
-1
VS = ±18 V
œ4
œ6
œ8
œ10
0
25
50
75
100 125 150
0
25
50
75
100 125 150
œ75 œ50 œ25
œ75 œ50 œ25
Temperature (°C)
Temperature (°C)
C001
C001
Figure 17. CMRR vs Temperature
Figure 18. PSRR vs Temperature
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1000
VCM = 0 V (P-Channel)
VCM = V+ - 100 mV (N-Channel)
500
300
200
100
50
30
20
10
5
3
2
1
100m
1
10
100
1k
10k
100k
Frequency (Hz)
Time (1 s/div)
Peak-to-peak noise = VRMS × 6.6 = 1.30 VPP
Figure 19. 0.1-Hz to 10-Hz Noise
Figure 20. Input Voltage Noise Spectral Density
vs Frequency
0.1
0.01
1
0.1
G = 1 V/V, RL = 10 kW
G = 1 V/V, RL = 2 kW
G = -1 V/V, RL = 2 kW
G = -1 V/V, RL = 10 kW
G = 1 V/V, RL = 10 kW
G = 1 V/V, RL = 2 kW
G = -1 V/V, RL = 2 kW
G = -1 V/V, RL = 10 kW
0.01
0.001
0.0001
1E-5
0.001
0.0001
1E-5
10
100
1k
10k
100k
0.01
0.1
1
10 20
Frequency (Hz)
Output Amplitude (VRMS)
VOUT = 3.5 VRMS, BW = 80 kHz
f = 1 kHz, BW = 80 kHz
Figure 21. THD+N Ratio vs Frequency
Figure 22. THD+N vs Output Amplitude
1.2
1.1
1
1.2
1.1
1
VS = ê2.25 V
VS = ê18 V
0.9
0.8
0.9
0.8
0
4
8
12
16
20
24
28
32
36
-50
-25
0
25
50
75
100
125
Supply Voltage (V)
Temperature (èC)
Figure 23. Quiescent Current vs Supply Voltage
Figure 24. Quiescent Current vs Temperature
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
3
10k
VS = ê2.25 V
VS = ê18 V
2
1k
1
0
100
10
-1
-2
-3
0.1
1
10
100
1k
10k 100k 1M
10M
-50
-25
0
25
50
75
100
125
Frequency (Hz)
C016
Temperature (èC)
Figure 26. Open-Loop Output Impedance vs Frequency
Figure 25. Open-Loop Gain vs Temperature
45
40
35
30
25
20
15
10
5
50
RISO = 0 W
RISO = 25 W
RISO = 50 W
RISO = 0 W
RISO = 25 W
RISO = 50 W
45
40
35
30
25
20
15
10
5
0
20 30 40 50 70 100
200 300 500 7001000
2000
20 30 40 50 70 100
200 300 500 7001000
2000
Capacitive Load (pF)
Capacitive Load (pF)
G = –1 V/V
G = 1 V/V
Figure 27. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 28. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Output
Input
Output
Input
Time (200 ms/div)
Time (200 ns/div)
VS = ±18 V, input = ±18.5 VPP
G = –10 V/V
Figure 29. No Phase Reversal
Figure 30. Positive Overload Recovery
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Output
Input
Time (200 ns/div)
Time (200 ns/Div)
G = –10 V/V
G = 1 V/V
Figure 31. Negative Overload Recovery
Figure 32. Small-Signal Step Response
Time (150 ns/Div)
Time (300 ns/Div)
G = –1 V/V
G = 1 V/V
Figure 33. Small-Signal Step Response
Figure 34. Large-Signal Step Response
4
3
4
3
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Time (ms)
Time (ms)
G = 1, 0.01% settling = ±1 mV, step applied at t = 0
G = 1, 0.01% settling = ±500 µV, step applied at t = 0
Figure 35. Settling Time (10-V Positive Step)
Figure 36. Settling Time (5-V Positive Step)
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at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
30
Sinking current
Maximum output voltage without
slew-rate induced distortion.
VS = ±15 V
Sourcing current
25
20
15
10
5
80
60
40
20
0
VS = ±5 V
VS = ±2.25 V
0
10k
100k
1M
10M
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
Frequency (Hz)
C033
Figure 37. Short-Circuit Current vs Temperature
Figure 38. Maximum Output Voltage vs Frequency
Overdrive = 100 mV
VOUT Voltage
tpLH = 1.1 ꢀs
tpLH = 0.97 ꢀs
VOUT Voltage
Overdrive = 100 mV
Time (200 ns/div)
Time (200 ns/div)
C025
C026
Figure 39. Propagation Delay Rising Edge
Figure 40. Propagation Delay Falling Edge
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7 Detailed Description
7.1 Overview
The OPAx197 uses a patented two-temperature trim architecture to achieve a very low offset voltage of 250 µV
(max) and low voltage offset drift of 0.75 µV/°C (maximum) over the full specified temperature range. This level
of precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial
sensors, filters, and high-voltage data acquisition.
7.2 Functional Block Diagram
OPAx197
-
NCH Input
Stage
+
+IN
-
OUT
High
Capacitive Load
Compensation
36-V
Differential
Front End
Output
Stage
Slew
Boost
+
-IN
+
PCH Input
Stage
t
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7.3 Feature Description
7.3.1 Input Protection Circuitry
The OPAx197 uses a unique input architecture to eliminate the need for input protection diodes, but still provides
robust input protection under transient conditions. Conventional input diode protection schemes shown in
Figure 41 can be activated by fast transient step responses and can introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 42. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended settling
time, as shown in Figure 43.
V+
V+
+IN
-IN
+IN
-IN
OUT
OUT
OPAx197
~0.7 V
36 V
V-
V-
OPAx197 Provides Full 36-V
Differential Input Range
Conventional Input Protection
Limits Differential Input Range
Figure 41. OPA197 Input Protection Does Not Limit Differential Input Capability
1
Ron_mux
Vn = +10 V
RFILT
+10 V
Sn
D
1
2
~œ9.3 V
+10 V
CFILT
CS
CD
Vinœ
2
Ron_mux
Sn+1
Vn+1 = œ10 V RFILT
œ10 V
~0.7 V
Vout
CFILT
CS
Idiode_transient
Vin+
œ10 V
Input Low Pass Filter
Simplified Mux Model
Buffer Amplifier
Figure 42. Back-to-Back Diodes Create Settling Issues
100
Op amp with standard input diodes
OPA197
50
0
0.1% settling = ê10 mV
-50
-100
0
6
12
18
24
30
36
42
48
54
60
Time (ms)
Figure 43. OPA197 Protection Circuit Maintains Fast-Settling Transient Response
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Feature Description (continued)
The OPAx197 family of operational amplifiers provides a true high-impedance differential input capability for high-
voltage applications. This patented input protection architecture does not introduce additional signal distortion or
delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications.
The OPA197 can tolerate a maximum differential swing (voltage between inverting and noninverting pins of the
op amp) of up to 36 V, making the device suitable for use as a comparator or in applications with fast-ramping
input signals such as multiplexed data-acquisition systems, as shown in Figure 53.
7.3.2 EMI Rejection
The OPAx197 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx197 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 44 shows the results of this testing on the OPA197. Table 2 shows the EMIRR IN+ values for the OPA197
at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be
centered on or operated near the particular frequency shown. Detailed information can also be found in the
application report EMI Rejection Ratio of Operational Amplifiers, SBOA128, available for download from
www.ti.com.
160.0
PRF = -10 dBm
VSUPPLY = ±18 V
VCM = 0 V
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
10M
100M
Frequency (Hz)
1G
10G
C017
Figure 44. EMIRR Testing
Table 2. OPA197 EMIRR IN+ For Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
44.1 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5.0 GHz
52.8 dB
61.0 dB
69.5 dB
88.7 dB
105.5 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
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7.3.3 Phase Reversal Protection
The OPAx197 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPAx197 is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 45.
Output
Input
Time (200 ms/div)
Figure 45. No Phase Reversal
7.3.4 Thermal Protection
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the OPAx197 is 150°C.
Exceeding this temperature causes damage to the device. The OPAx197 has a thermal protection feature that
prevents damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 140°C. Figure 46 shows an application example for
the OPA197 that has significant self heating (159°C) because of its power dissipation (0.81 W). Thermal
calculations indicate that for an ambient temperature of 65°C the device junction temperature must reach 187°C.
The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 46 depicts
how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the
output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.
Normal
Operation
VOUT
3 V
TA = 65°C
+30 V
PD = 0.81W
ꢀJA = 116°C/W
TJ = 116°C/W × 0.81W + 65°C
TJ = 159°C (expected)
Output
High-Z
0 V
-
150°C
140ºC
OPAx197
+
IOUT = 30 mA
+
3 V
œ
RL
100 Ω
+
VIN
3 V
œ
Figure 46. Thermal Protection
7.3.5 Capacitive Load and Stability
The OPAx197 features a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads; see Figure 47 and Figure 48. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an
amplifier will be stable in operation.
22
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45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
RISO = 0 W
RISO = 25 W
RISO = 50 W
RISO = 0 W
RISO = 25 W
RISO = 50 W
0
20 30 40 50 70 100
200 300 500 7001000
2000
20 30 40 50 70 100
200 300 500 7001000
2000
Capacitive Load (pF)
Capacitive Load (pF)
Figure 47. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step, G = –1 V/V)
Figure 48. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step, G = 1 V/V)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
(10-Ω to 20-Ω) resistor, RISO, in series with the output, as shown in Figure 49. This resistor significantly reduces
ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in
parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at
low output levels. A high capacitive load drive makes the OPA197 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 49 uses an isolation resistor,
RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase
margin, and results using the OPA197 are summarized in Table 3. For additional information on techniques to
optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation,
and test results.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
Figure 49. Extending Capacitive Load Drive with the OPA197
Table 3. OPA197 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and
Measured Results
PARAMETER
Capacitive Load
Phase Margin
RISO (Ω)
VALUE
100 pF
1000 pF
0.01 µF
0.1 µF
1 µF
45°
60°
45°
60°
45°
60°
45°
6.2
60°
45°
2.0
60°
4.7
47.0
360.0
24.0
100.0
20.0
51.0
15.8
Measured
Overshoot (%)
23.2 8.6
45.1°
10.4
22.5
9.0
22.1
8.7
23.1
8.6
21.0
8.6
Calculated PM
58.1°
45.8°
59.7°
46.1°
60.1°
45.2°
60.2°
47.2°
60.2°
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using
an Isolation Resistor .
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7.3.6 Common-Mode Voltage Range
The OPAx197 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 50. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition
region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can vary
modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD
performance may be degraded compared to operation outside this region.
V+
IS1
œIN
PCH1
NCH4
NCH3
PCH2
+IN
FUSE BANK
TRIM
TRIM
Vœ
Figure 50. Rail-to-Rail Input Stage
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPAx197 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode voltage range, as
shown in Figure 51.
P-Channel
Region
Transition
Region
N-Channel
Region
P-Channel
Region
Transition
Region
N-Channel
Region
200
100
200
100
0
0
œ100
œ100
œ200
œ300
OPAx197
Input Offset Voltage vs Vcm
œ200
œ300
Input Offset Voltage vs Vcm
without a precision trimmed Input
œ15.0 œ14.0
…
11.0
12.0
13.0
14.0
15.0
œ15.0 œ14.0
…
11.0
12.0
13.0
14.0
15.0
Common-Mode Voltage (V)
Common-Mode Voltage (V)
Figure 51. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers
24
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7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. See Figure 52 for an illustration of the ESD circuits contained in the OPAx197 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
RF
+VS
VDD
OPAx197
100 Ω
100 Ω
R1
RS
INœ
œ
IN+
+
Power-Supply
ESD Cell
RL
+
ID
œ
VIN
VSS
œVS
TVS
Figure 52. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled
ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx197 is approximately 200 ns.
7.4 Device Functional Modes
The OPAx197 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx197 is 36 V (±18 V).
26
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx197 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as
10-MHz bandwidth and high capacitive load drive. These features make the OPAx197 a robust, high-
performance operational amplifier for high-voltage industrial applications.
8.2 Typical Applications
8.2.1 16-Bit Precision Multiplexed Data-Acquisition System
Figure 53 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This
application example explains the process for optimizing the precision, high-voltage, front-end drive circuit using
the OPA197 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
1
2
3
4
High-Impedance Inputs
No Differential Input Clamps
Fast Settling-Time Requirements
Attenuate High-Voltage Input Signal
Fast-Settling Time Requirements
Stability of the Input Driver
Attenuate ADC Kickback Noise
VREF Output: Value and Accuracy
Low Temp and Long-Term Drift
Very Low Output Impedance
Input-Filter Bandwidth
Voltage
Reference
CH0+
CH0-
RC Filter
Buffer
RC Filter
+
+
±20-V,
10-kHz
Sine Wave
OPA197
OPA197
Reference Driver
Gain
Network
Gain
Network
OPA197
+
4:2
Mux
REFP
+
OPA140
VINP
Gain
Network
CH3+
+
OPA197
Antialiasing
Filter
SAR
ADC
+
+
±20-V,
10-kHz
Sine Wave
OPA197
OPA197
VINM
CH3-
n
CONV
16 Bits
High-Voltage Level Translation
400 kSPS
High-Voltage Multiplexed Input
VCM
Voltage
Divider
REF3240
OPA350
Shmidtt
Trigger
VCM Generation Circuit
Counter
Delay
n
Digital Counter For Multiplexer
5
Fast logic transition
Figure 53. OPA197 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage
Inputs With Lowest Distortion
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Typical Applications (continued)
8.2.1.1 Design Requirements
The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest
distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input.
The design requirements for this block design are:
•
•
•
•
•
System Supply Voltage: ±15 V
ADC Supply Voltage: 3.3 V
ADC Sampling Rate: 400 kSPS
ADC Reference Voltage (REFP): 4.096 V
System Input Signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
8.2.1.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for
highest system linearity and fast settling. The overall system block diagram is shown in Figure 53. The circuit is a
multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output
buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast
sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design
considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input
analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each
analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit
resolution and lowest distortion system. The diagram includes the most important specifications for each
individual analog block.
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input
stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design
is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding
helps in the decision of an appropriate input filter and selection of a mux to meet the system settling
requirements. The next important step is the design of the attenuating analog front end (AFE) used to level
translate the high-voltage input signal to a low-voltage ADC input while maintaining the amplifier stability. The
next step is to design a digital interface to switch the mux input channels with minimum delay. The final design
challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage
with low offset, drift, and noise contributions.
8.2.1.3 Application Curve
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–20
–15
–10
–5
0
5
10
15
20
ADC Differential Input (V)
Figure 54. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition
System for High Voltage Inputs with Lowest Distortion.
28
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8.2.2 Slew Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down
at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPAx197 make the device an optimal amplifier to achieve slew rate control
for both dual- and single-supply systems.Figure 55 shows the OPA197 in a slew-rate limit design.
Op Amp Gain Stage
Slew Rate Limiter
C1
R1
470 nF
1.69 kΩ
VEE
VEE
R2
1.6 MΩ
-
-
OPA197
VIN
V+
+
OPA197
V+
VOUT
+
VCC
RL
VCC
10 kΩ
Figure 55. Slew Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.
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8.2.3 Precision Reference Buffer
The OPAx197 features high output current drive capability and low input offset voltage, making the device an
excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the
10-µF ceramic capacitor shown in Figure 56, RISO, a 37.4-Ω isolation resistor, provides separation of two
feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output, VOUT
.
Feedback path number two is through RFx and CF and is connected at the output of the op amp. The optimized
stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz, while still
providing a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability
components: RF, RFx, CF, and RISO
.
RF
1 kΩ
CF
39 nF
RFx
10 kΩ
RISO
œ
37.4 Ω
OPA197
V+
VOUT
+
CL
10 µF
VCC
VREF
2.5 V
Figure 56. Precision Reference Buffer
9 Power Supply Recommendations
The OPAx197 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
30
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information refer to Circuit Board Layout Techniques, SLOA089.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Figure 57, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
+
VIN
VOUT
RG
RF
(Schematic Representation)
Place components
close to device and
to each other to
reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
RG
GND
VIN
GND
œIN
+IN
Vœ
V+
OUT
NC
Use low-ESR, ceramic
bypass capacitor
GND
Use low-ESR,
ceramic bypass
capacitor
VOUT
VSœ
Ground (GND) plane on another layer
Figure 57. Operational Amplifier Board Layout for Noninverting Configuration
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 TINA-TI™（免费软件下载）
TINA™是一款简单、功能强大且易于使用的电路仿真程序，此程序基于 SPICE 引擎。TINA-TI 是 TINA 软件的一
款免费全功能版本，除了一系列无源和有源模型外，此版本软件还预先载入了一个宏模型库。TINA-TI 提供所有传
统的 SPICE 直流、瞬态和频域分析，以及其他设计功能。
TINA-TI 可从 Analog eLab Design Center（模拟电子实验室设计中心）免费下载，它提供全面的后续处理能力，
使得用户能够以多种方式形成结果。虚拟仪器提供选择输入波形和探测电路节点、电压和波形的功能，从而创建一
个动态的快速入门工具。
注
这些文件需要安装 TINA 软件（由 DesignSoft™提供）或者 TINA-TI 软件。请从 TINA-TI 文
件夹 中下载免费的 TINA-TI 软件。
11.1.1.2 TI 高精度设计
OPA197 采用多种 TI 高精度设计，获取相关内容请访问 TI 高精度设计网站。TI 高精度设计是由 TI 公司高精度模
拟 应用 专家创建的模拟解决方案，提供了许多实用电路的工作原理、组件选择、仿真、完整印刷电路板 (PCB) 电
路原理图和布局布线、物料清单以及性能测量结果。
11.2 文档支持
11.2.1 相关文档
如需相关文档，请参阅：
•
•
《电路板布局布线技巧》（文献编号：SLOA089）
《适用于所有人的运算放大器》（文献编号：SLOD006）
11.3 相关链接
表 4 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件以及申请样片或购买产品的快速访问
链接。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
OPA197
OPA2197
OPA4197
32
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11.4 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我 进行注册，即可每周接收
产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.6 商标
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
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33
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA197ID
OPA197IDBVR
OPA197IDBVT
OPA197IDGKR
OPA197IDGKT
OPA197IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
D
DBV
DBV
DGK
DGK
D
8
5
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OPA197
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
75 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
50 RoHS & Green
2500 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SN
12MV
5
12MV
8
12ST
8
12ST
8
OPA197
2197
OPA2197ID
SOIC
D
8
OPA2197IDGKR
OPA2197IDGKT
OPA2197IDR
OPA4197ID
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
4HV
8
4HV
8
2197
SOIC
D
14
14
14
14
OPA4197
OPA4197
OPA4197
OPA4197
OPA4197IDR
OPA4197IPW
OPA4197IPWR
SOIC
D
TSSOP
TSSOP
PW
PW
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA197IDBVR
OPA197IDBVT
OPA197IDGKR
OPA197IDGKT
OPA197IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
3000
250
180.0
180.0
330.0
177.8
330.0
330.0
177.8
330.0
330.0
330.0
8.4
3.23
3.23
5.3
5.3
6.4
5.3
5.3
6.4
6.5
6.9
3.17
3.17
3.4
3.4
5.2
3.4
3.4
5.2
9.0
5.6
1.37
1.37
1.4
1.4
2.1
1.4
1.4
2.1
2.1
1.6
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
8.4
8.0
8
2500
250
12.4
12.4
12.4
12.4
12.4
12.4
16.4
12.4
12.0
12.0
12.0
12.0
12.0
12.0
16.0
12.0
8
8
2500
2500
250
OPA2197IDGKR
OPA2197IDGKT
OPA2197IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
2500
2000
OPA4197IDR
SOIC
D
14
14
OPA4197IPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA197IDBVR
OPA197IDBVT
OPA197IDGKR
OPA197IDGKT
OPA197IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
3000
250
223.0
223.0
346.0
223.0
356.0
346.0
223.0
356.0
356.0
356.0
270.0
270.0
346.0
270.0
356.0
346.0
270.0
356.0
356.0
356.0
35.0
35.0
29.0
35.0
35.0
29.0
35.0
35.0
35.0
35.0
8
2500
250
8
8
2500
2500
250
OPA2197IDGKR
OPA2197IDGKT
OPA2197IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
2500
2000
OPA4197IDR
SOIC
D
14
14
OPA4197IPWR
TSSOP
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
OPA197ID
OPA2197ID
OPA4197ID
OPA4197IPW
D
D
SOIC
SOIC
8
8
75
75
50
90
506.6
506.6
506.6
508
8
8
3940
3940
3940
3250
4.32
4.32
4.32
2.8
D
SOIC
14
14
8
PW
TSSOP
8.5
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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