OPA1637DGKR [TI]
高保真、高电压 (36V)、低噪声 (3.7nV/rtHz) Burr-Brown™ 音频全差分放大器 | DGK | 8 | -40 to 125;
| 型号： | OPA1637DGKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高保真、高电压 (36V)、低噪声 (3.7nV/rtHz) Burr-Brown™ 音频全差分放大器 | DGK | 8 | -40 to 125 放大器 光电二极管 |
| 文件： | 总36页 (文件大小：2424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA1637
ZHCSKM2B –DECEMBER 2019 –REVISED AUGUST 2020
OPA1637 高保真、低噪声、全差分、Burr-Brown™ 音频
运算放大器
1 特性
3 说明
• 低输入电压噪声：1kHz 时为3.7nV/√Hz
• 低THD + N：1 kHz 时为-120dB
• 低电源电流：±18V 下为950µA
• 输入失调电压：±200µV（最大值）
• 输入偏置电流：2nA（最大值）
• 低偏置电流噪声：10Hz 时为400fA/√Hz
• 带宽增益积：9.2MHz
• 差分输出压摆率：15V/µs
• 宽输入和输出共模范围
• 宽单电源工作电压范围：3V 至36V
• 低电源电流断电特性：< 20µA
• 过载功率限制
OPA1637 是一款具有低噪声、低总谐波失真 (THD) 的
全差分 Burr-Brown™ 音频运算放大器，可轻松过滤和
驱动全差分信号链。
OPA1637 还可将单端信号源转换为高保真模数转换器
(ADC) 所需的差分输出。双极性超级 ß 输入专为实现
出色的低噪声和 THD 而设计，在非常低的静态电流和
输入偏置电流下就可产生非常低的噪声系数。该器件设
计用于要求低功耗、高信噪比 (SNR) 和无杂散动态范
围(SFDR) 的音频电路。
OPA1637 具有高压电源功能，支持高达 ±18V 的电源
电压。高压差分信号链可通过该功能提高裕量和动态范
围，而无需为差分信号的每个极性添加单独的放大器。
极低的电压和电流噪声使得 OPA1637 可以用于高增益
配置，而对音频信号噪声的影响最小。
• 电流限制
• 封装：8 引脚VSSOP
• 温度范围：–40°C 至+125°C
OPA1637 可在 –40°C 至 +125°C 的宽温度范围内工
作，并采用8 引脚VSSOP 封装。
2 应用
• 专业音频混合器或控制平面
• 专业麦克风和无线系统
• 专业扬声器系统
• 专业音频放大器
• 条形音箱
器件信息(1)
封装尺寸（标称值）
器件型号
OPA1637
封装
VSSOP (8)
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• 转盘
• 专业摄像机
• 吉他和其他乐器放大器
• 数据采集(DAQ)
RF1
100
70
1 kꢀ
CF1
3.3 nF
50
C2
1 µF
RISO1
75 ꢀ
30
20
RI1
49 ꢀ 5 V
INPUT_A
5 V
œ
TPA3251
Class D
Amplifier
+
OPA1637
CDF
PCM1795
Audio DAC
œ 3.5 V
IOUTL/R+
IOUTL/Rœ
10
7
10 nF
C3
1 µF
C5
1 µF
œ
+
PD
5
GND
5 V
œ10 V
RI2
49 ꢀ
œ10 V
INPUT_B
RISO2
75 ꢀ
3
2
CF2
3.3 nF
RF2
1 kꢀ
GND
1
100m
1
10
100
Frequency (Hz)
1k
10k
100k
低噪声、低功耗、全差分放大器增益模块和接口
D022
低输入电压噪声
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA00
OPA1637
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ZHCSKM2B –DECEMBER 2019 –REVISED AUGUST 2020
Table of Contents
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................19
9.1 Application Information............................................. 19
9.2 Typical Applications.................................................. 23
10 Power Supply Recommendations..............................28
11 Layout...........................................................................28
11.1 Layout Guidelines................................................... 28
11.2 Layout Example...................................................... 28
12 Device and Documentation Support..........................29
12.1 Device Support....................................................... 29
12.2 Documentation Support.......................................... 29
12.3 接收文档更新通知................................................... 29
12.4 支持资源..................................................................29
12.5 Trademarks.............................................................29
12.6 静电放电警告.......................................................... 29
12.7 术语表..................................................................... 29
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................9
7 Parameter Measurement Information..........................16
7.1 Characterization Configuration................................. 16
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................18
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (May 2020) to Revision B (August 2020)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 更改了首页应用图，为RF1 显示正确的标签和值................................................................................................1
• Changed Figure 7-1 to show correct labels......................................................................................................16
• Changed Figure 9-5 to show correct label and value for RF1 .......................................................................... 23
• Changed Figure 9-8 negative rail from 0 V to –5 V.........................................................................................25
Changes from Revision * (December 2019) to Revision A (May 2020)
Page
• 将器件状态从“预告信息（预发布）”更改为“生产数据（正在供货）”.........................................................1
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ZHCSKM2B –DECEMBER 2019 –REVISED AUGUST 2020
5 Pin Configuration and Functions
IN-
8
7
6
5
IN+
1
2
3
4
VOCM
VS+
PD
VS-
OUT-
OUT+
图5-1. DGK Package, 8-Pin VSSOP, Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
IN–
NO.
1
I
Inverting (negative) amplifier input
Noninverting (positive) amplifier input
Inverting (negative) amplifier output
Noninverting (positive) amplifier output
IN+
8
I
5
O
O
OUT–
OUT+
4
Power down.
PD = logic low = power off mode.
PD = logic high = normal operation.
PD
7
I
The logic threshold is referenced to VS+.
If power down is not needed, leave PD floating.
VOCM
VS–
VS+
2
6
3
I
I
I
Ouput common-mode voltage control input
Negative power-supply input
Positive power-supply input
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Single supply
40
±20
VS
Supply voltage
Dual supply
V
IN+, IN–, Differential voltage(2)
±0.5
V
IN+, IN–, VOCM, PD, OUT+, OUT− voltage(3)
IN+, IN− current
VVS– –0.5
–10
VVS+ + 0.5
10
V
mA
mA
50
OUT+, OUT− current
–50
Output short-circuit(4)
Continuous
150
TA
Operating Temperature
Junction Temperature
°C
°C
°C
–40
–40
–65
TJ
175
Tstg
Storage Temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins IN+ and IN–are connected with anti-parallel diodes in between the two terminals. Differential input signals that are greater
than 0.5 V or less than –0.5 V must be current-limited to 10 mA or less.
(3) Input terminals are diode-clamped to the supply rails (VS+, VS–). Input signals that swing more than 0.5 V greater or less the supply
rails must be current-limited to 10 mA or less.
(4) Short-circuit to VS / 2.
6.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
36
UNIT
Single-supply
Dual-supply
VS
TA
Supply voltage
V
±1.5
–40
±18
125
Specified temperature
°C
6.4 Thermal Information
OPA1637
DGK (VSSOP)
8 PINS
181.1
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
68.3
102.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.6
ψJT
101.1
ψJB
RθJC(bot)
N/A
(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
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6.5 Electrical Characteristics
at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2 kΩ, VPD
VVS+, RL = 10 kΩ(1) (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
FREQUENCY RESPONSE
VO (2) = 100 mVPP, G = –1 V/V
VO = 100 mVPP, G = –10 V/V
SSBW
GBP
FBP
SR
Small-signal bandwidth
Gain-bandwidth product
Full-power bandwidth
Slew rate
7
9.2
2.5
15
1
MHz
MHz
MHz
V/µs
VO = –1 VPP, G = –1 V/V
G = –1, 10-V step
0.1% of final value, G = –1 V/V, VO = 10-V step
0.01% of final value, G = –1 V/V, VO= 10-V step
Settling time
µs
2
dB
%
–120
0.0001
–115
Differential input, f = 1 kHz, VO = 10 VPP
Single-ended input, f = 1 kHz, VO = 10 VPP
Differential input, f = 10 kHz, VO = 10 VPP
Single-ended input, f = 10 kHz, VO = 10 VPP
dB
%
0.00018
–112
Total harmonic distortion and
noise
THD+N
dB
%
0.00025
–107
0.00045
–126
–120
–131
–119
dB
%
Differential input, f = 1 kHz, VO = 10 VPP
Single-ended input, f = 1 kHz, VO = 10 VPP
Differential input, f = 1 kHz, VO = 10 VPP
Single-ended input, f = 1 kHz, VO = 10 VPP
G = 5 V/V, 2x output overdrive, dc-coupled
HD2
HD3
Second-order harmonic distortion
dB
Third-order harmonic distortion
Overdrive recovery time
dB
µs
3.3
NOISE
f = 1 kHz
3.7
4
nV/√Hz
µVPP
en
Input differential voltage noise
Input current noise, each input
f = 10 Hz
f = 0.1 Hz to 10 Hz
f = 1 kHz
0.1
300
400
13.4
fA/√Hz
pAPP
ei
f = 10 Hz
f = 0.1 Hz to 10 Hz
OFFSET VOLTAGE
20
±200
µV
VIO
Input-referred offset voltage
±250
TA = –40°C to +125°C
TA = –40°C to +125°C
Input offset voltage drift
0.1
±1 µV/°C
0.025
±0.5
µV/V
±1
PSRR
Power-supply rejection ratio
TA = –40°C to +125°C
INPUT BIAS CURRENT
0.2
±2
nA
±4
IB
Input bias current
TA = –40°C to +125°C
TA = –40°C to +125°C
Input bias current drift
Input offset current
2
±15 pA/°C
0.2
±1
nA
±3
IOS
TA = –40°C to +125°C
TA = –40°C to +125°C
Input offset current drift
1
±10 pA/°C
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6.5 Electrical Characteristics (continued)
at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2 kΩ, VPD
VVS+, RL = 10 kΩ(1) (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT VOLTAGE
VVS+
–
1
Common-mode voltage
VVS–+ 1
V
dB
TA = –40°C to +125°C
140
140
VVS–+ 1 V ≤VICM ≤ VVS+ –1 V
126
120
VVS–+ 1 V ≤VICM ≤ VVS+ –1 V, VS = ±18 V
CMRR
Common-mode rejection ratio
VVS– + 1 V ≤VICM ≤VVS+ –1 V, VS = ±18 V
TA = –40°C to +125°C
INPUT IMPEDANCE
Input impedance differential
VICM = 0 V
1 || 1
GΩ|| pF
mode
OPEN-LOOP GAIN
115
110
115
110
120
120
120
120
VS = ±2.5 V, VVS– + 0.2 V < VO < VVS+ –0.2 V
VS = ±2.5 V, VVS– + 0.3 V < VO < VVS+ –0.3 V,
TA = –40°C to +125°C
AOL
Open-loop voltage gain
dB
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ –0.6 V
VS = ±15 V, VVS–+ 0.6 V < VO < VVS+ –0.6 V,
TA = –40°C to +125°C
OUTPUT
VS = ±2.5 V
±100
±100
±230
±270
±31
VS = ±2.5 V, TA = –40°C to +125°C
VS = ±18 V
Output voltage difference from
supply voltage
mV
VS = ±18 V, TA = –40°C to +125°C
ISC
Short-circuit current
mA
pF
Ω
Differential capacitive load, no output Isolation
resistors, phase margin = 30°
CLOAD
ZO
Capacitive load drive
50
14
Open-loop output impedance
f = 100 kHz (differential)
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL
VVS+
–
1
VS = ±2.5 V
Input Voltage Range
VVS– + 1
VVS– + 2
VVS+
–
2
VS = ±18 V
Small-signal bandwidth from
VOCM pin
VVOCM= 100 mVPP
2
MHz
V/µs
Large-signal bandwidth from
VOCM pin
VVOCM = 0.6 VPP
5.7
VVOCM = 0.5-V step, rising
3.5
5.5
Slew rate from VOCM pin
VVOCM = 0.5-V step, falling
VVOCM fixed midsupply (VO = ±1 V)
DC output balance
78
dB
MΩ|| pF
mV
VOCM input impedance
VOCM offset from mid-supply
2.5 || 1
2
VOCM pin floating
VVOCM = VICM, VO = 0 V
±1
±6
VOCM common-mode offset
voltage
mV
±10
VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C
VOCM common-mode offset
voltage drift
±20
±60 µV/°C
VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C
POWER SUPPLY
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6.5 Electrical Characteristics (continued)
at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2 kΩ, VPD
VVS+, RL = 10 kΩ(1) (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
0.95
1.2
mA
1.6
IQ
Quiescent operating current
TA = –40°C to +125°C
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6.5 Electrical Characteristics (continued)
at TA = 25°C, VS (dual supply) = ±1.5 V to ±18 V, VVOCM = 0 V, input common mode voltage (VICM) = 0 V, RF = 2 kΩ, VPD
VVS+, RL = 10 kΩ(1) (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER DOWN
VVS+
–
VPD(HI)
Power-down enable voltage
V
V
TA = –40°C to +125°C
0.5
VVS+
–
VPD(LOW) Power-down disable voltage
TA = –40°C to +125°C
VPD = VVS+ –2 V
2.0
PD bias current
1
10
10
15
2
µA
µA
µs
µs
Powerdown quiescent current
Turn-on time delay
20
VIN = 100 mV, time to VO = 90% of final value
VIN = 100 mV, time to VO = 10% of original value
Turn-off time delay
(1) RL is connected differentially, from OUT+ to OUT–.
(2) VO refers to the differential output voltage, VOUT+ – VOUT–
.
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6.6 Typical Characteristics
at VS = ±18 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, VOUT = 2 VPP, G = 1 V/V, and V PD = VS+ (unless
otherwise noted)
100
70
5000
3000
2000
50
30
20
1000
700
10
7
500
5
300
200
3
2
100
0.1
1
100m
0.5
2 3 5 10 20
100
Frequency (Hz)
1000
10000 100000
1
10
100
Frequency (Hz)
1k
10k
100k
D014
D013
图6-2. Current Noise vs Frequency
图6-1. Input-Referred Voltage Noise vs Frequency
-90
0.1
0.01
-60
RL = 2 kW
RL = 10 kW
RL = 2 kW
RL = 10 kW
-95
RL = 600 W
-80
-100
-105
-110
-115
-120
-125
0.001
0.0001
1E-5
-100
-120
-140
10m
100m 1
Output Amplitude (VRMS
10
10
100
1k
Frequency (Hz)
10k 20k
)
D016
D015
f = 1 kHz, VS = ±15 V
VOUT = 3 VRMS, VS = ±15 V
图6-3. Total Harmonic Distortion + Noise vs Frequency
图6-4. Total Harmonic Noise + Distortion vs Amplitude
180
160
140
120
100
80
200
160
120
80
50
40
30
20
10
Gain
Phase
40
0
60
-40
-80
-120
-160
-200
40
0
20
G = 1
G = 10
-10
0
G = 100
-20
-20
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
1k
10k
100k
Frequency (Hz)
1M
10M
D068
D009
VS = ±15 V, CL = 50 pF
图6-5. Open Loop Gain vs Frequency
VS = ±15 V, CL = 50 pF
图6-6. Closed-Loop Gain vs Frequency
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6.6 Typical Characteristics (continued)
at VS = ±18 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, VOUT = 2 VPP, G = 1 V/V, and V PD = VS+ (unless
otherwise noted)
180
160
140
120
100
80
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
60
40
20
0
10m 100m
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
1
10
100 1k
Frequency (Hz)
10k 100k 1M 10M
D030
D011
VS = ±15 V
图6-8. Common Mode Rejection Ratio vs Temperature
图6-7. Common Mode Rejection Ratio vs Frequency
180
-0.01
PSRR+
PSRR-
160
140
120
100
80
-0.02
-0.03
-0.04
-0.05
60
40
20
0
10m 100m
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (oC)
1
10
100 1k
Frequency (Hz)
10k 100k 1M 10M
D031
D012
VS = ±15 V
图6-10. Power Supply Rejection Ratio vs Temperature
图6-9. Power Supply Rejection Ratio vs Frequency
40
10000
5000
35
30
25
20
15
10
5
3000
2000
1000
500
300
200
100
50
30
20
0
10
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
1
10
100
1k 10k
Frequency (Hz)
100k
1M
10M
D019
D017
VS = ±15 V
VS = ±15 V
图6-11. Maximum Output Voltage vs Frequency
图6-12. Output Impedance vs Frequency
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6.6 Typical Characteristics (continued)
at VS = ±18 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, VOUT = 2 VPP, G = 1 V/V, and V PD = VS+ (unless
otherwise noted)
15
10
5
15
10
5
0
-200 -150 -100
0
-200 -150 -100
-50
0
50
100
150
200
-50
0
50
100
150
200
Input Offset Voltage (mV)
Input Offset Voltage (mV)
D001
D061
VS = ±1.5 V
VS = ±18 V
图6-13. Input Offset Voltage Histogram
图6-14. Input Offset Voltage Histogram
25
20
15
10
5
20
15
10
5
0
0
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
-6
-4
-2
0
Common-Mode Input Offset Voltage (mV)
2
4
6
Offset Voltage Drift (mV/èC)
D002
D006
VS = ±15 V
VS = ±18 V, VOCM = floating
图6-15. Input Offset Voltage Drift Histogram
图6-16. Output Common Mode Voltage Offset
15
10
5
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40oC
25oC
85oC
125oC
0
3
6
9
12 15 18 21 24 27 30 33 36
Supply Voltage (V)
-6 -5 -4 -3 -2 -1
0
1
2
3
Common-Mode Input Offset Voltage (mV)
4
5
6
D045
D007
VS = ±18 V, VOCM = 0 V
图6-18. Quiescent Current vs Supply Voltage
图6-17. Output Common Mode Voltage Offset
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6.6 Typical Characteristics (continued)
at VS = ±18 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, VOUT = 2 VPP, G = 1 V/V, and V PD = VS+ (unless
otherwise noted)
1.5
1.4
1.3
1.2
1.1
1
1.6
1.4
1.2
1
Vs = ê1.5 V
Vs = ê18 V
0.8
0.6
0.4
0.2
0
0.9
0.8
0.7
0.6
0.5
VS = ê18 V
VS = ê1.5 V
-50
-25
0
25
50
75
100
125
150
0
0.5
1
1.5
2
2.5
3
3.5
VS+ Delta from Power Down (V)
4
4.5
5
Temperature (oC)
D065
D053
图6-19. Quiescent Current vs Temperature
图6-20. Quiescent Current vs Power-Down Delta from Supply
Voltage
250
200
150
100
50
500
400
300
200
100
0
-55oC
-40oC
25oC
85oC
125oC
150oC
0
-50
-100
-200
-100
-150
-200
-250
17 V
-17 V
IB-
IB+
IOS
-300
-400
-500
-18
-14
-10
-6
Input Common-Mode Voltage (V)
-2
2
6
10
14
18
-18
-14
-10
-6
Input Common-Mode Voltage (V)
-2
2
6
10
14
18
D023
D025
图6-21. Input Offset Voltage vs Input Common-Mode Voltage
图6-22. Input Bias Current vs Input Common-Mode Voltage
500
30
IB-
IB+
IOS
450
400
350
300
250
200
150
100
50
28
26
24
-40èC
125èC
25èC
85èC
22
20
0
-50
-100
3
6
9
12 15 18 21 24 27 30 33 36
Supply Voltage (V)
0
5
10
15
20
25
Output Current (mA)
30
35
40
D027
D028
图6-23. Input Bias Current vs Supply Voltage
图6-24. Output Voltage vs Output Current
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6.6 Typical Characteristics (continued)
at VS = ±18 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, VOUT = 2 VPP, G = 1 V/V, and V PD = VS+ (unless
otherwise noted)
-20
-22
-24
-26
-28
-30
128
126
124
122
120
118
116
114
112
110
108
-40èC
125èC
25èC
85èC
25 èC
85 èC
125 èC
-40 èC
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
-40
-35
-30
-25
-20
-15
Output Current (mA)
-10
-5
0
Output Voltage Delta from Supply Voltage, VS+/VS- (V)
D049
D029
图6-26. Open-Loop Gain vs Ouput Delta From Supply
图6-25. Output Voltage vs Output Current
20
20
RISO = 0 W
RISO = 25 W
RISO = 50 W
RISO = 0 W
RISO = 25 W
RISO = 50 W
17.5
15
15
10
5
12.5
10
7.5
5
2.5
0
0
20
40
60
80
100
120
Capacitive Load (pF)
140
160
180
0
50
100
150
200
250
Capacitive Load (pF)
300
350
400
D036
D037
AV = 1
AV = 10
图6-27. Small-Signal Overshoot vs Capacitive Load
图6-28. Small-Signal Overshoot vs Capacitive Load
20
50
40
30
20
17
14
11
I
I
I
I
OUT+ (sinking)
OUT+ (sourcing)
OUT- (sourcing)
OUT- (sinking)
10
0
-10
-20
-30
-40
-50
8
Falling Edge
Rising Edge
5
-25 -10
5
20
35
50
65
80
95 110 125
3
6
9
12 15 18 21 24 27 30 33 36
Supply Voltage (V)
Temperature (oC)
D048
D041
图6-30. Short-Circuit Current vs Temperature
图6-29. Output Slew Rate vs Supply Voltage
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6.6 Typical Characteristics (continued)
at VS = ±18 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, VOUT = 2 VPP, G = 1 V/V, and V PD = VS+ (unless
otherwise noted)
3
2.5
2
1.1
1.08
1.06
1.04
1.02
1
1.5
1
0.5
0
VOUT+
VOUT-
-0.5
-1
0.98
0.96
0.94
0.92
0.9
-1.5
-2
VVOCM
(VOUT+ + VOUT-)/2
-2.5
-3
Time (1 ms/div)
Time (5 ms /div)
D044
D054
图6-31. Large-Signal Step Response
图6-32. Output Common-Mode Step Response, Rising
0.1
0.08
0.06
0.04
0.02
0
VIN
VOUT+
VOUT-
VVOCM
(VOUT+ + VOUT-)/2
-0.02
-0.04
-0.06
-0.08
-0.1
Time (5 ms / div)
Time (500 ns/div)
D055
D043
图6-33. Output Common-Mode Step Response, Falling
图6-34. Small-Signal Step Response, Falling
+0.01%
Settling
Threshold
-0.01%
Settling
VIN
VOUT+
VOUT-
Input
Transition
Threshold
Time (500 ns/div)
Time (250 ns/div)
D042
D046
图6-35. Small-Signal Step Response, Rising
图6-36. Output Settling Time to ±0.01%
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6.6 Typical Characteristics (continued)
at VS = ±18 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, VOUT = 2 VPP, G = 1 V/V, and V PD = VS+ (unless
otherwise noted)
18
15
12
9
0.3
18
15
12
9
0.3
0.2
0.1
0
VPD
VOUT
0.25
0.2
0.15
0.1
6
6
-0.1
-0.2
-0.3
-0.4
-0.5
3
0.05
0
3
0
0
VPD
VOUT
-3
-6
-0.05
-0.1
-3
-6
Time (1 ms/div)
Time (1 ms/div)
D050
D051
图6-37. Power-Down Time (PD Low to High)
VIN
图6-38. Power-Down Time (PD High to Low)
VIN
VOUT+
VOUT-
VOUT+
VOUT-
Time (20 ms/div)
Time (20 ms/div)
D039
D040
图6-39. Output Negative Overload Recovery
图6-40. Output Positive Overload Recovery
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7 Parameter Measurement Information
7.1 Characterization Configuration
The OPA1637 provides the advantages of a fully differential amplifier (FDA) configuration that offers very low
noise and harmonic distortion in a single, low-power amplifier. The FDA is a flexible device, where the main aim
is to provide a purely differential output signal centered on a user-configurable, common-mode voltage that is
usually matched to the input common-mode voltage required by an analog-to-digital converter (ADC) or class-D
amplifier. The circuit used for characterization of the differential-to-differential performance is seen in 图7-1.
VINœ
RI
2 kꢀ
RF
2 kꢀ
VOUT+
RISO
0 ꢀ
VVS+
œ
+
VIDIFF/2
œ
+
VVOCM
+
OPA1637
RL
10 kꢀ
CL
DNP
VOUT
+
œ
RISO
0 ꢀ
VCM
œ
œ
+
+
œ
VIDIFF/2
RI
2 kꢀ
VVSœ VPD
RF
2 kꢀ
VOUTœ
VIN+
All voltages except VIN and VOUT are
referenced to ground.
图7-1. Differential Source to a Differential Gain of a 1-V/V Test Circuit
A similar circuit is used for single-ended to differential measurements, as shown in 图7-2.
VINœ
RI
2 kꢀ
RF
2 kꢀ
VOUT+
RISO
0 ꢀ
VVS+
œ
+
VVOCM
+
OPA1637
RL
10 kꢀ
CL
DNP
VOUT
œ
RISO
0 ꢀ
+
œ
RI
2 kꢀ
VPD
VVSœ
+
RF
2 kꢀ
VOUTœ
VIN
œ
VIN+
All voltages except VOUT are
referenced to ground.
图7-2. Single-Ended to Differential Gain of a 1-V/V Test Circuit
The FDA requires feedback resistor for both output pins to the input pins. These feedback resistors load the
output differentially only if the input common-mode voltage is equal to the output common-mode voltage set by
VOCM. When VOCM differs from the input common-mode range, the feedback resistors create single-ended
loading. The characterization plots fix the RF (RF1 = RF2) value at 2 kΩ, unless otherwise noted. This value can
be adjusted to match the system design parameters with the following considerations in mind:
• The current needed to drive RF from the peak output voltage to the input common-mode voltage adds to the
overall output load current. If the total load current (current through RF + current through RL) exceeds the
current limit conditions, the device enters a current limit state, causing the output voltage to collapse.
• High feedback resistor values (RF> 100 kΩ) interact with the amplifier input capacitance to create a zero in
the feedback network. Compensation must be added to account for this potential source of instability; see the
TI Precision Labs FDA Stability Training for guidance on designing an appropriate compensation network.
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8 Detailed Description
8.1 Overview
The OPA1637 is a low-noise, low-distortion fully-differential amplifier (FDA) that features Texas Instrument's
super-beta bipolar input devices. Super-beta input devices feature very low input bias current as compared to
standard bipolar technology. The low input bias current and current noise makes the OPA1637 an excellent
choice for audio applications that require low-noise differential signal processing without significant current
consumption. This device is also designed for analog-to-digital audio input circuits that require low noise in a
single fully-differential amplifier. This device achieves lower current consumption at lower noise levels than what
is achievable with two low-noise amplifiers. The OPA1637 also features high-voltage capability, which allows the
device to be used in ±15-V supply circuits without any additional voltage clamping or regulators. This feature
enables a direct, single amplifier for a 24-dBm differential output drive (commonly found on mixers and digital
audio interfaces) without any additional amplification.
8.2 Functional Block Diagram
VS+
OUT+
œ
INœ
Low Noise
Differential I/O
+
Amplifier
œ
IN+
+
OUTœ
VSœ
VS+
5 Mꢀ
œ
VCM
Error
1 µA
Amplifier
+
VOCM
PD
5 Mꢀ
VSœ
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8.3 Feature Description
8.3.1 Super-Beta Input Bipolar Transistors
The OPA1637 is designed on a modern bipolar process that features TI's super-beta input transistors. Traditional
bipolar transistors feature excellent voltage noise and offset drift, but suffer a tradeoff in high input bias current
(IB) and high input bias current noise. Super-beta transistors offer the benefits of low voltage noise and low offset
drift with an order of magnitude reduction in input bias current and reduction in input bias current noise. For
audio circuits, input bias current noise can dominate in circuits where higher resistance input resistors are used.
The OPA1637 enables a fully-differential, low-noise amplifier design without restrictions of low input resistance at
a power level unmatched by traditional single-ended amplifiers.
8.3.2 Power Down
The OPA1637 features a power-down circuit to disable the amplifier when a low-power mode is required by the
system. In the power-down state, the amplifier outputs are in a high-impedance state, and the amplifier total
quiescent current is reduced to less than 20 µA.
8.3.3 Flexible Gain Setting
The OPA1637 offers considerable flexibility in the configuration and selection of resistor values. Low input bias
current and bias current noise allows for larger gain resistor values with minimal impact to noise or offset. The
design starts with the selection of the feedback resistor value. The 2-kΩ feedback resistor value used for the
characterization curves is a good compromise among power, noise, and phase margin considerations. With the
feedback resistor values selected (and set equal on each side), the input resistors are set to obtain the desired
gain, with the input impedance also set with these input resistors. Differential I/O designs provide an input
impedance that is the sum of the two input resistors. Single-ended input to differential output designs present a
more complicated input impedance. Most characteristic curves implement the single-ended to differential design
as the more challenging requirement over differential-to-differential I/O.
8.3.4 Amplifier Overload Power Limit
In many bipolar-based amplifiers, the output stage of the amplifier can draw significant (several milliamperes) of
quiescent current if the output voltage becomes clipped (meaning the output voltage becomes limited by the
negative or positive supply voltage). This condition can cause the system to enter a high-power consumption
state, and potentially cause oscillations between the power supply and signal chain. The OPA1637 has an
advanced output stage design that eliminates this problem. When the output voltage reaches the VVS+ or VVS–
voltage, there is virtually no additional current consumption from the nominal quiescent current. This feature
helps eliminate any potential system problems when the signal chain is disrupted by a large external transient
voltage.
8.4 Device Functional Modes
The OPA1637 has two functional modes: normal operation and power-down. The power-down state is enabled
when the voltage on the power-down pin is lowered to less than the power-down threshold. In the power-down
state, the quiescent current is significantly reduced, and the output voltage is high-impedance. This high
impedance can lead to the input voltages (+IN and –IN) separating, and forward-biasing the ESD protection
diodes. See 节9 for guidance on power-down operation.
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9 Application and Implementation
Note
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
Most applications for the OPA1637 strive to deliver the best dynamic range in a design that delivers the desired
signal processing along with adequate phase margin for the amplifier. The following sections detail some of the
design issues with analysis and guidelines for improved performance.
9.1.1 Driving Capacitive Loads
The capacitive load of an ADC, or some other next-stage device, is commonly required to be driven. Directly
connecting a capacitive load to the output pins of a closed-loop amplifier such as the OPA1637 can lead to an
unstable response. One typical remedy to this instability is to add two small series resistors (RISO) at the outputs
of the OPA1637 before the capacitive load. Good practice is to leave a place for the RISO elements in a board
layout (a 0-Ωvalue initially) for later adjustment, in case the response appears unacceptable.
For applications where the OPA1637 is used as an output device to drive an unknown capacitive load, such as a
cable, RISO is required. 图 9-1 shows the required RISO value for a 40-degree phase-margin response. The peak
required RISO value occurs when CL is between 500 pF and 1 nF. As CL increases beyond 1 nF, the bandwidth
response of the device reduces, resulting in a slower response but no major degradation in phase margin. For a
typical cable type, such as Belden 8451, capacitive loading can vary from 340 pF (10-foot cable) to 1.7 nF (50-
foot cable). Selecting RISO to be 100 Ωprovides sufficient phase margin regardless of the cable length. RISO can
also be used within the loop feedback of the amplifier; however, simulation must be used to verify the stability of
the system.
100
90
80
70
60
50
40
30
20
10
0
100 p
1 n 10 n
Load Capacitance, CL (F)
100 n
D069
图9-1. Required Isolation Resistance vs Capacitive Load for a 40° Phase Margin
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9.1.2 Operating the Power-Down Feature
The power-down feature on the OPA1637 allows the device to be put into a low power-consumption state, in
which quiescent current is minimized. To force the device into the low-power state, drive the PD pin lower than
the power-down threshold voltage (VVS+ – 2 V). Driving the PD pin lower than the power-down threshold
voltage forces the internal logic to disable both the differential and common-mode amplifiers. The PD pin has an
internal pullup current that allows the pin to be used in an open-drain MOSFET configuration without an
additional pullup resistor, as seen in 图 9-2. In this configuration, the logic level can be referenced to the
MOSFET, and the voltage at the PD pin is level-shifted to account for use with high supply voltages. Be sure to
select an N-type MOSFET with a maximum BVDSS greater than the total supply voltage. For applications that do
not use the power-down feature, tie the PD pin to the positive supply voltage.
VS+
1 µA
To
amplifier
core
PD
Enabled
MOSFET
THRESHOLD
Powerdown
OPA1637
GND
图9-2. Power-Down ( PD) Pin Interface With Low-Voltage Logic Level Signals
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When PD is low (device is in power down) the output pins will be in a high-impedance state. When the device is
in the power-down state, the outputs are high impedance, and the output voltage is no longer controlled by the
amplifier, but dependant on the input and load configuration. In this case, the input voltage between IN– and
IN+ can drift to a voltage that may forward-bias the input protection diodes. Take care to avoid high currents
flowing through the input diodes by using an input resistor to limit the current to less than 10 mA. In 图 9-3, the
OPA1637 is configured in a differential gain of 5 with 100-Ω input resistors. When the device enters power
down, the voltage between IN– and IN+ increases until the internal protection diode is forward-biased. In this
case, exceeding a voltage on VIN with RIN= 0 Ω of 2.5 V (diode forward voltage estimated at 0.5 V) results in a
current greater than 10 mA. To avoid this high current, select RIN so that the maximum current flow is less than
10 mA when VIN is at maximum voltage.
500 ꢀ
100 ꢀ
+10 V
RIN
VIN
œ
Highœ Z
+
VOCM
œ
Highœ Z
+
PD
RIN
œ10 V
100 ꢀ
500 ꢀ
图9-3. Path of Input Current Flow When PD = Low
9.1.3 I/O Headroom Considerations
The starting point for most designs is to assign an output common-mode voltage for the OPA1637. For ac-
coupled signal paths, this voltage is often the default midsupply voltage to retain the most available output swing
around the voltage centered at the VOCM voltage. For dc-coupled designs, set this voltage with consideration to
the required minimum headroom to the supplies, as described in the specifications for the VOCM control. For
precision ADC drivers, this VOCM output becomes the VCM input to the ADC. Often, VCM is set to VREF / 2 to
center the differential input on the available input when precision ADCs are being driven.
From target output VOCM, the next step is to verify that the desired output differential peak-to-peak voltage,
VOUTPP, stays within the supplies. For any desired differential VOUTPP, make sure that the absolute maximum
voltage at the output pins swings with 方程式 1 and 方程式 2, and confirm that these expressions are within the
supply rails minus the output headroom required for the RRO device.
VOUTPP
VOUTMIN = VOCM
œ
4
(1)
(2)
VOUTPP
VOUTMAX = VOCM
+
4
With the output headroom confirmed, the input junctions must also stay within the operating range. The input
range limitations require a maximum 1.0-V headroom from the supply voltages (VS+ and VS–) over the full
temperature range.
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9.1.4 Noise Performance
The first step in the output noise analysis is to reduce the application circuit to the simplest form with equal
feedback and gain setting elements to ground. 图 9-4 shows the simplest analysis circuit with the FDA and
resistor noise terms to be considered.
2
2
enRg
enRf
RF
RG
2
In+
+
2
eno
œ
2
Inœ
2
eni
2
2
enRg
enRf
RG
RF
图9-4. FDA Noise Analysis Circuit
The noise powers are shown in 图 9-4 for each term. When the RF and RG (or RI) terms are matched on each
side, the total differential output noise is the root sum squared (RSS) of these separate terms. Using NG ≡ 1 +
RF / RG, the total output noise is given by 方程式 3. Each resistor noise term is a 4kT × R power (4kT = 1.6E-20
J at 290 K).
eo = e NG 2 + 2 i R 2 + 2 4kTR NG
(
)
(
)
(
)
ni
N
F
F
(3)
The first term is simply the differential input spot noise times the noise gain. The second term is the input current
noise terms times the feedback resistor (and because there are two uncorrelated current noise terms, the power
is two times one of them). The last term is the output noise resulting from both the RF and RG resistors, at again,
twice the value for the output noise power of each side added together. Running a wide sweep of gains when
holding RF to 2 kΩ gives the standard values and resulting noise listed in 表 9-1. When the gain increases, the
input-referred noise approaches only the gain of the FDA input voltage noise term at 3.7 nV/√Hz.
表9-1. Swept Gain of the Output- and Input-Referred Spot Noise Calculations
GAIN (V/V)
AV
0.1
1
RF (Ω)
2000
2000
2000
2000
2000
RG1 (Ω)
20000
2000
1000
402
EO (nV/√Hz)
EI (nV/√Hz)
0.1
1
9.4
93.9
13.6
8.9
13.6
2
2
17.8
5
4.98
10
29.5
5.9
10
200
48.6
4.9
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9.2 Typical Applications
9.2.1 Current-Output Audio DAC Buffer to Class-D Amplifier
RF1
1 kꢀ
CF1
3.3 nF
C2
1 µF
RISO1
75 ꢀ
RI1
49 ꢀ 5 V
INPUT_A
5 V
œ
TPA3251
+
OPA1637
CDF
PCM1795
Audio DAC
œ 3.5 V
IOUTL/R+
IOUTL/Rœ
Class D
10 nF
Amplifier
C5
1 µF
œ
C3
+
PD
1 µF
GND
5 V
œ10 V
RI2
49 ꢀ
œ10 V
INPUT_B
RISO2
75 ꢀ
CF2
3.3 nF
RF2
1 kꢀ
GND
图9-5. Differential Current-to-Voltage Converter
9.2.1.1 Design Requirements
The requirements for this application are:
• Differential current-to-voltage conversion and filtering
• 1-kmho transimpedance gain
• 40-kHz Butterworth response filter
• 0-V dc common-mode voltage at DAC output
9.2.1.2 Detailed Design Procedure
This design provides current-to-voltage conversion from a current-output audio DAC into a voltage-input, class-D
amplifier. The order of design priorities are as follows:
• Select feedback-resistor values based on the gain required from the current-output stage to the voltage-input
stage. For this design, the full-scale, peak-to-peak output current of the PCM1795 ( IOUTL/R+ –IOUTL/R–) is
±4 mA. A gain of 1k gives a wide voltage swing of ±4 V, allowing for high SNR without exceeding the input
voltage limit of the TPA3251.
• After the gain is fixed, select the output common-mode voltage. The output common-mode voltage
determines the input common-mode voltage in this configuration. To set the nominal output voltage of the
PCM1795 to 0 V (which corresponds to the input common mode voltage of the OPA1637), shift the output
negatively from the desired common-mode input voltage by the gain multiplied by the dc center current value
of the PCM1795 (3.5 mA). In this case, –3.5 V satisfies the design goal.
• A bypass capacitor from the VOCM pin to ground must be selected to filter noise from the voltage divider.
The capacitor selection is determined by balancing the startup time of the system with the output common-
mode noise. A higher capacitance gives a lower frequency filter cutoff on the VOCM pin, thus giving lower
noise performance, but also slows down the initial startup time of the circuit as a result of the RC delay from
the resistor divider in combination with the filter capacitor.
• Select CF so that the desired bandwidth of the active filter is achieved. The 3-dB frequency is determined by
the reciprocal of the product of RF and CF.
• Use a passive filter on the output to increase noise filtering beyond the desired bandwidth. The passive filter
formed by RD1,2 and CDF adds an additional real pole to the filter response. If the pole is designed at the
same frequency as the active filter pole, the overall 3-dB frequency shifts to a lower frequency value, and the
step response is overdamped. A trade-off must be made to give optimal transient response versus increased
filter attenuation at higher frequencies. For this design, the second pole is set to 106 kHz.
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9.2.1.3 Application Curves
The simulated response of the current-to-voltage audio DAC buffer can be seen in 图9-6 and 图9-7.
90
75
60
45
30
15
0
0
1.2
1.05
0.9
0.75
0.6
0.45
0.3
0.15
0
-0.15
-0.3
-0.45
-0.6
-0.75
-0.9
-1.05
-1.2
VOUT
VIN
Gain
Phase
-30
-60
-90
-120
-150
-180
-210
-240
-270
-300
-15
-30
-45
-60
100
1k 10k
Frequency (Hz)
100k
1M
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
C105
C105
图9-6. Gain and Phase Response for Current-to-
图9-7. Transient Response for Current-to-Voltage
Voltage Buffer
Buffer
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9.2.2 An MFB Filter Driving an ADC Application
A common application use case for fully-differential amplifiers is to easily convert a single-ended signal into a
differential signal to drive a differential input source, such as an ADC or class-D amplifier. Figure 9-8 shows an
example of the OPA1637 used to convert a single-ended, low-voltage signal audio source, such as a small
electret microphone, and deliver a low-noise differential signal that is common-mode shifted to the center of the
ADC input range. A multiple-feedback (MFB) configuration is used to provide a Butterworth filter response, giving
a 40-dB/decade rolloff with a –3-dB frequency of 30 kHz.
RF1
3.65 kꢀ
CF1
1 nF
RG1
604 ꢀ
RI1
732 ꢀ
CA1
47 pF
RO1
20 ꢀ
RA1
100 ꢀ
+5 V
VIN
œ
+
CA2
1 nF
VOCM
FDA
6.2 nF
ADC
œ
+
PD
VS+
œ5 V
RO2
20 ꢀ
RA2
100 ꢀ
CA3
47 pF
RI2
732 ꢀ
RG2
604 ꢀ
CF2
1 nF
RF2
3.65 kꢀ
图9-8. Example 30-kHz Butterworth Filter
9.2.2.1 Design Requirements
The requirements for this application are:
• Single-ended to differential conversion
• 5-V/V gain
• Active filter set to a Butterworth, 30-kHz response shape
• Output RC elements set by SAR input requirements (not part of the filter design)
• Filter element resistors and capacitors are set to limit added noise over the OPA1637 and noise peaking
9.2.2.2 Detailed Design Procedure
The design proceeds using the techniques and tools suggested in the Design Methodology for MFB Filters in
ADC Interface Applications application note. The process includes:
• Scale the resistor values to not meaningfully contribute to the output noise produced by the OPA1637.
• Select the RC ratios to hit the filter targets when reducing the noise gain peaking within the filter design.
• Set the output resistor to 100 Ωinto a 1-nF differential capacitor.
• Add 47-pF common-mode capacitors to the load capacitor to improve common noise filtering.
• Inside the loop, add 20-Ωoutput resistors after the filter feedback capacitor to increase the isolation to the
load capacitor.
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9.2.2.3 Application Curves
The gain and phase plots are shown in 图 9-9. The MFB filter features a Butterworth responses feature very flat
passband gain, with a 2-pole roll-off at 30 kHz to eliminate any higher-frequency noise from contaminating the
signal chain, and potentially alias back into the audio band.
20
16
12
8
120
90
60
30
4
0
0
-30
-60
-90
-120
-150
-180
-4
-8
-12
-16
-20
Gain
Phase
100
1k
Frequency (Hz)
10k
100k
C100
图9-9. Gain and Phase Plot for a 30-kHz Butterworth Filter
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9.2.3 Differential Microphone Input to Line Level
Professional dynamic microphones typically feature low output impedance to minimize noise coupling on the
microphone cable. Interfacing the microphone with high-impedance circuitry typically requires the use of an
impedance conversion stage, often done with a transformer or discrete amplifiers. The flexibility of the OPA1637
allows the device to be configured with a low differential input impedance and 20 dB of gain, simplifying the
impedance conversion and gain stage into a single device. 图 9-10 shows an example of a differential, low input
impedance, microphone level voltage (10 mV to 100 mV) amplifier to a line-level amplitude signal that also has
adjustable dc common-mode shift capability. This design example shows how the OPA1637 makes a great
choice for driving an ADC class-D amplifier.
RF1
750 ꢀ
Dynamic
Microphone
CF1
4.7 nF
RG1
75 ꢀ
RISO1
100 ꢀ
+15
XLR
Cable
œ
To ADC/
Class D Amplifier/
XLR output
+
VIN
VOCM
FDA
œ
+
PD
+15
-15
CF2
RISO2
100 ꢀ
RG2
75 ꢀ
4.7 nF
RF2
750 ꢀ
图9-10. Fully Differential, Low-Noise, 20-dB Microphone Gain Block With DC Shift
9.2.3.1 Application Curves
2.5
2
VOUT-
VOUT+
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Time (ms)
2
D075
VOCM = 0 V
图9-11. Output Waveform of the Microphone Amplifier
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10 Power Supply Recommendations
The OPA1637 operates from supply voltages of 3.0 V to 36 V (±1.5 V to ±18 V, dual supply). Connect ceramic
bypass capacitors from both VS+ and VS–to GND.
11 Layout
11.1 Layout Guidelines
11.1.1 Board Layout Recommendations
• Keep differential signals routed together to minimize parasitic impedance mismatch.
• Connect a 0.1-µF capacitor to the supply nodes through a via.
• Connect a 0.1-µF capacitor to the VOCM pin if no external voltage is used.
• Keep any high-frequency nodes that can couple through parasitic paths away from the VOCM node.
• Clean the PCB board after assembly to minimize any leakage paths from excess flux into the VOCM node.
11.2 Layout Example
Connect IN+/INœ through
input resistors on the top
VIN
layer. Maintain symmetry
between traces and
routing to minimize
common mode coupling.
RIN
RIN
Route the VOCM pin
connection through a via.
Connect a 0.1 µF
capacitor to VOCM if no
external voltage is used
to set the output common
mode voltage.
INœ
IN+
PD
Connect the powerdown
RF
RF
pin through a via. If
powerdown is not
needed, leave floating.
VOCM
VS+
CCM
CBYPASS
VSœ
OUT+ OUTœ
CBYPASS
Connect bypass
capacitors through a via.
VOUT
图11-1. Example Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
• OPA1637 TINA-TI™ model
• TINA-TI Gain of 0.2 100kHz Butterworth MFB Filter
• TINA-TI 100kHz MFB filter LG test
• TINA-TI Differential Transimpedance LG Sim
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias
Current Op Amp with e-trim™ data sheet
• Texas Instruments, OPA161x SoundPlus™ High-Performance, Bipolar-Input Audio Operational Amplifiers
data sheet
• Texas Instruments, Design Methodology for MFB Filters in ADC Interface Applications application report
• Texas Instruments, Design for Wideband Differential Transimpedance DAC Output application report
• Texas Instruments, PCM1795 32-Bit, 192-kHz Sampling, Advanced Segment, Stereo Audio Digital-to-Analog
Converter data sheet
• Texas Instruments, TPA3251 175-W Stereo, 350-W Mono PurePath™ Ultra-HD Analog Input Class-D
Amplifier data sheet
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索
现有解答或提出自己的问题，获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的使用条款。
12.5 Trademarks
Burr-Brown™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA1637DGKR
OPA1637DGKT
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
1637
1637
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1637DGKR
OPA1637DGKT
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
330.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Aug-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA1637DGKR
OPA1637DGKT
VSSOP
VSSOP
DGK
DGK
8
8
2500
250
366.0
366.0
364.0
364.0
50.0
50.0
Pack Materials-Page 2
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