MUX506 [TI]
1pA 开路泄漏电流、36V、16:1、单通道精密模拟多路复用器;
| 型号： | MUX506 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1pA 开路泄漏电流、36V、16:1、单通道精密模拟多路复用器 复用器 |
| 文件： | 总43页 (文件大小：1822K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MUX506, MUX507
ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
MUX50x 36V 低电容、低泄漏电流、高精度模拟多路复用器
1 特性
3 说明
1
•
低导通电容
MUX506 和 MUX507 (MUX50x) 是现代互补金属氧化
物半导体 (CMOS) 模拟多路复用器 (MUX)。MUX506
提供 16:1 单端通道，而 MUX507 提供 8:1 差分通道
或双 8:1 单端通道。MUX506 和 MUX507 在由双电源
（±5V 至 ±18V）或单电源（10V 至 36V）供电时均能
–
–
MUX506：13.5pF
MUX507：8.7pF
•
•
•
•
•
•
•
•
•
•
•
•
低输入泄漏：1pA
低电荷注入：0.31pC
轨到轨运行
正常运行。这些器件在由对称电源（如 VDD
12V，VSS = –12V）和非对称电源（如 VDD
=
=
宽电源电压范围：±5V 至 ±18V 或 10V 至 36V
低导通电阻：125Ω
12V，VSS = –5V）供电时也能保证优异性能。所有数
字输入具有兼容晶体管-晶体管逻辑电路 (TTL) 的阈
值。当器件在有效电源电压范围内运行时，该阈值可保
证 TTL 和 CMOS 逻辑电路的兼容性。
转换时间：97ns
先断后合开关操作
EN 引脚与 VDD 相连
逻辑电平：2V 至 VDD
低电源电流：45µA
MUX507 和 MUX507 的导通和关断泄漏电流较低，允
许此类多路复用器以最小误差转换高输入阻抗源传输的
信号。电源电流低至 45µA，支持其应用于功耗敏感型
应用。
ESD 保护 HBM：2000V
行业标准 TSSOP/SOIC 封装
器件信息(1)
2 应用
器件型号
MUX506
封装
TSSOP (28)
SOIC (28)
封装尺寸（标称值）
9.70mm × 6.40mm
17.9mm × 7.50mm
•
•
•
•
•
•
工厂自动化和工业过程控制
可编程逻辑控制器 (PLC)
模拟输入模块
MUX507
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
自动测试设备 (ATE)
数字万用表
电池监控系统
简化电路原理图
泄漏电流与温度间的关系
1000
ID(ON)+
IS(OFF)+
500
ID(OFF)+
Bridge Sensor
Thermocouple
0
œ
VINP
ADC
PGA/INA
+
MUX507
-500
IS(OFF)-
VINM
-1000
ID(OFF)-
Current
Sensing
-1500
ID(ON)-
Photo
LED
Detector
Optical Sensor
-2000
Copyright © 2017, Texas Instruments Incorporated
-75
-50
-25
0
25
50
75
100 125 150
Analog Inputs
Temperature (èC)
D006
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS803
MUX506, MUX507
ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
目录
7.11 Bandwidth ............................................................. 23
7.12 THD + Noise ......................................................... 23
Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagram ....................................... 24
8.3 Feature Description................................................. 25
8.4 Device Functional Modes........................................ 27
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Application ................................................. 28
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics: Dual Supply ..................... 7
6.6 Electrical Characteristics: Single Supply................... 9
6.7 Typical Characteristics............................................ 11
Parameter Measurement Information ................ 16
7.1 Truth Tables............................................................ 16
7.2 On-Resistance ........................................................ 17
7.3 Off Leakage............................................................. 17
7.4 On-Leakage Current ............................................... 18
7.5 Transition Time ....................................................... 18
7.6 Break-Before-Make Delay....................................... 19
7.7 Turn-On and Turn-Off Time .................................... 20
7.8 Charge Injection...................................................... 21
7.9 Off Isolation............................................................. 22
7.10 Channel-to-Channel Crosstalk.............................. 22
8
9
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 器件和文档支持 ..................................................... 33
12.1 文档支持................................................................ 33
12.2 相关链接................................................................ 33
12.3 接收文档更新通知 ................................................. 33
12.4 社区资源................................................................ 33
12.5 商标....................................................................... 33
12.6 静电放电警告......................................................... 33
12.7 Glossary................................................................ 33
13 机械、封装和可订购信息....................................... 33
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (November 2016) to Revision A
Page
•
•
•
•
•
已更改 将特性 列表中的转换时间从 85ns 更改成了 97ns ...................................................................................................... 1
已添加 在特性 和器件信息 部分中添加了 SOIC 封装 ............................................................................................................. 1
Added the DW (SOIC) package to the Pin Configuration and Functions section .................................................................. 3
Added SOIC package to the Thermal Information table ........................................................................................................ 7
Changed Transition time Typ value From 85: ns To: 97ns for ±15 V supplies in the Electrical Characteristics: Dual
Supply table............................................................................................................................................................................ 8
•
•
•
•
Added additional specifications for the SOIC packages (QJ, Off-isolation, and channel-to-channel crosstalk) for ±15
V supplies in Electrical Characteristics: Dual Supply ............................................................................................................. 8
Changed Transition time Typ value From: 91 To: 102 ns for 12 V supply in the Electrical Characteristics: Single
Supply table.......................................................................................................................................................................... 10
Added additional specifications for the SOIC packages (QJ, Off-isolation, and channel-to-channel crosstalk) for 12 V
supply in Electrical Characteristics: Single Supply............................................................................................................... 10
Added NOTE to the Application and Implementation section .............................................................................................. 28
2
Copyright © 2016–2017, Texas Instruments Incorporated
MUX506, MUX507
www.ti.com.cn
ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
5 Pin Configuration and Functions
MUX506: PW and DW Packages
28-Pin TSSOP and SOIC
Top View
VDD
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
2
VSS
S8
S7
S6
S5
S4
S3
S2
S1
EN
A0
A1
A2
NC
3
S16
S15
S14
S13
S12
S11
S10
S9
4
5
6
7
8
9
10
11
12
13
14
GND
NC
A3
Not to scale
Pin Functions: MUX506
PIN
FUNCTION
DESCRIPTION
NAME
A0
NO.
17
16
15
14
28
Digital input
Digital input
Digital input
Digital input
Address line 0
A1
Address line 1
Address line 2
Address line 3
A2
A3
D
Analog input or output Drain pin. Can be an input or output.
Active high digital input. When this pin is low, all switches are turned off. When this pin is
high, the A[3:0] logic inputs determine which switch is turned on.
EN
18
Digital input
GND
NC
S1
S2
S3
S4
S5
S6
S7
S8
S9
12
2, 3, 13
19
Power supply
No connect
Ground (0 V) reference
Do not connect
Analog input or output Source pin 1. Can be an input or output.
Analog input or output Source pin 2. Can be an input or output.
Analog input or output Source pin 3. Can be an input or output.
Analog input or output Source pin 4. Can be an input or output.
Analog input or output Source pin 5. Can be an input or output.
Analog input or output Source pin 6. Can be an input or output.
Analog input or output Source pin 7. Can be an input or output.
Analog input or output Source pin 8. Can be an input or output.
Analog input or output Source pin 9. Can be an input or output.
20
21
22
23
24
25
26
11
Copyright © 2016–2017, Texas Instruments Incorporated
3
MUX506, MUX507
ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Pin Functions: MUX506 (continued)
PIN
FUNCTION
DESCRIPTION
NAME
S10
S11
S12
S13
S14
S15
S16
NO.
10
9
Analog input or output Source pin 10. Can be an input or output.
Analog input or output Source pin 11. Can be an input or output.
Analog input or output Source pin 12. Can be an input or output.
Analog input or output Source pin 13. Can be an input or output.
Analog input or output Source pin 14. Can be an input or output.
Analog input or output Source pin 15. Can be an input or output.
Analog input or output Source pin 16. Can be an input or output.
8
7
6
5
4
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and GND.
VDD
VSS
1
Power supply
Power supply
Negative power supply. This pin is the most negative power-supply potential. In single-
supply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
27
MUX507: PW and DW Package
28-Pin TSSOP and SOIC
Top View
VDD
DB
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DA
2
VSS
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
EN
NC
3
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
NC
4
5
6
7
8
9
10
11
12
13
14
A0
A1
NC
A2
Not to scale
Pin Functions: MUX507
PIN
FUNCTION
DESCRIPTION
NAME
A0
NO.
17
Digital input
Digital input
Digital input
Address line 0
A1
16
Address line 1
Address line 2
A2
15
DA
28
Analog input or output Drain pin A. Can be an input or output.
4
Copyright © 2016–2017, Texas Instruments Incorporated
MUX506, MUX507
www.ti.com.cn
ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
Pin Functions: MUX507 (continued)
PIN
NAME
FUNCTION
DESCRIPTION
NO.
DB
2
Analog input or output Drain pin B. Can be an input or output.
Active high digital input. When this pin is low, all switches are turned off. When this pin is
high, the A[2:0] logic inputs determine which pair of switches is turned on.
EN
18
Digital input
GND
NC
12
Power supply
No connect
Ground (0 V) reference
Do not connect
3, 13, 14
S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A
S1B
S2B
S3B
S4B
S5B
S6B
S7B
S8B
19
20
21
22
23
24
25
26
11
10
9
Analog input or output Source pin 1A. Can be an input or output.
Analog input or output Source pin 2A. Can be an input or output.
Analog input or output Source pin 3A. Can be an input or output.
Analog input or output Source pin 4A. Can be an input or output.
Analog input or output Source pin 5A. Can be an input or output.
Analog input or output Source pin 6A. Can be an input or output.
Analog input or output Source pin 7A. Can be an input or output.
Analog input or output Source pin 8A. Can be an input or output.
Analog input or output Source pin 1B. Can be an input or output.
Analog input or output Source pin 2B. Can be an input or output.
Analog input or output Source pin 3B. Can be an input or output.
Analog input or output Source pin 4B. Can be an input or output.
Analog input or output Source pin 5B. Can be an input or output.
Analog input or output Source pin 6B. Can be an input or output.
Analog input or output Source pin 7B. Can be an input or output.
Analog input or output Source pin 8B. Can be an input or output.
8
7
6
5
4
Positive power supply. This pin is the most positive power supply potential. For reliable
VDD
VSS
1
Power supply
Power supply
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and GND.
Negative power supply. This pin is the most negative power supply potential. In single-
supply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
27
Copyright © 2016–2017, Texas Instruments Incorporated
5
MUX506, MUX507
ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–40
MAX
40
UNIT
VDD
Supply
VSS
0.3
Voltage
VDD – VSS
40
V
Digital pins(2): EN, A0, A1, A2, A3
Analog pins(2): Sx, SxA, SxB, D, DA, DB
VSS – 0.3
VSS – 2
–30
VDD + 0.3
VDD + 2
30
Current(3)
mA
°C
Operating, TA
Junction, TJ
Storage, Tstg
–55
150
Temperature
150
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage limits are valid if current is limited to ±30 mA.
(3) Only one pin at a time.
6.2 ESD Ratings
VALUE
2000
500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
5
NOM
MAX
18
UNIT
Dual supply
(1)
(2)
VDD
VSS
Positive power-supply voltage
V
Single supply
10
36
Negative power-supply voltage (dual supply)
–5
–18
36
V
V
VDD – VSS
Supply voltage
10
VS
Source pins voltage(3)
Drain pins voltage
VSS
VSS
VSS
VSS
–25
–40
VDD
VDD
VDD
VDD
25
V
VD
VEN
VA
V
Enable pin voltage
V
Address pins voltage
V
ICH
TA
Channel current (TA = 25°C)
Operating temperature
mA
°C
125
(1) When VSS = 0 V, VDD can range from 10 V to 36 V.
(2) VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 36 V.
(3) VS is the voltage on all the S pins.
6
Copyright © 2016–2017, Texas Instruments Incorporated
MUX506, MUX507
www.ti.com.cn
ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
6.4 Thermal Information
MUX50x
THERMAL METRIC(1)
PW (TSSOP)
28 PINS
79.8
DW (SOIC)
28 PINS
53.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
24.0
30.1
37.6
28.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.2
9.0
ψJB
37.1
28.4
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: Dual Supply
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG SWITCH
Analog signal range
On-resistance
TA = –40°C to +125°C
VS = 0 V, IS = –1 mA
VSS
VDD
170
200
230
250
9
V
125
145
RON
Ω
Ω
VS = ±10 V, IS = –1 mA
VS = ±10 V, IS = –1 mA
VS = 10 V, 0 V, –10 V
TA = –40°C to +85°C
TA = –40°C to +125°C
6
On-resistance
mismatch between
channels
ΔRON
TA = –40°C to +85°C
TA = –40°C to +125°C
14
16
20
45
On-resistance
flatness
RFLAT
TA = –40°C to +85°C
TA = –40°C to +125°C
53
Ω
58
On-resistance drift
VS = 0 V
0.62
Ω/°C
nA
–1
–10
–25
–1
–0.001
1
10
25
1
Switch state is off,
IS(OFF)
ID(OFF)
ID(ON)
Input leakage current VS = ±10 V, VD = ±10
TA = –40°C to +85°C
TA = –40°C to +125°C
V(1)
–0.01
–0.01
Switch state is off,
Output off-leakage
VS = ±10 V, VD = ±10
current
TA = -40°C to +85°C
TA = -40°C to +125°C
–10
–25
–1
10
25
1
nA
nA
V(1)
Output on-leakage
current
Switch state is on,
VD = ±10 V, VS = floating
TA = –40°C to +85°C
TA = –40°C to +125°C
–10
–50
10
50
LOGIC INPUT
VIH
VIL
ID
Logic voltage high
2
V
V
Logic voltage low
Input current
0.8
0.1
µA
(1) When VS is positive, VD is negative, and vice versa.
Copyright © 2016–2017, Texas Instruments Incorporated
7
MUX506, MUX507
ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Electrical Characteristics: Dual Supply (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER
SWITCH DYNAMICS(2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
82
136
145
151
78
VS = ±10 V, RL = 300 Ω,
CL= 35 pF
tON
Enable turn-on time
TA = –40°C to +85°C
TA = –40°C to +125°C
63
97
VS = ±10 V, RL = 300 Ω,
CL= 35 pF
tOFF
Enable turn-off time
Transition time
TA = –40°C to +85°C
TA = –40°C to +125°C
89
ns
97
143
151
157
VS = 10 V, RL = 300 Ω,
CL= 35 pF,
tt
TA = –40°C to +85°C
TA = –40°C to +125°C
ns
ns
Break-before-make
time delay
tBBM
VS = 10 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C
30
54
TSSOP package
SOIC package
TSSOP package
SOIC package
TSSOP package
SOIC package
TSSOP package
SOIC package
TSSOP package
SOIC package
TSSOP package
SOIC package
0.31
0.67
±0.9
±1.1
–98
–94
–94
–88
–100
–96
–88
–83
2.1
VS = 0 V
CL = 1 nF, RS = 0 Ω
QJ
Charge injection
Off-isolation
pC
dB
dB
VS = –15 V to +15 V
Nonadjacent channel to D,
DA, DB
RL = 50 Ω, VS = 1 VRMS
,
f = 1 MHz
Adjacent channel to D, DA,
DB
Nonadjacent channels
Adjacent channels
Channel-to-channel
crosstalk
RL = 50 Ω, VS = 1 VRMS
f = 1 MHz
,
CS(OFF)
CD(OFF)
Input off-capacitance f = 1 MHz, VS = 0 V
3
12.2
7.5
pF
pF
MUX506
MUX507
MUX506
MUX507
11.1
6.4
Output off-
f = 1 MHz, VS = 0 V
capacitance
13.5
8.7
15
CS(ON)
CD(ON)
,
Output on-
f = 1 MHz, VS = 0 V
capacitance
pF
10.2
POWER SUPPLY
45
26
59
62
85
34
37
58
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V,
VDD supply current
TA = –40°C to +85°C
TA = –40°C to +125°C
µA
µA
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V,
VSS supply current
TA = –40°C to +85°C
TA = –40°C to +125°C
(2) Specified by design; not subject to production testing.
8
Copyright © 2016–2017, Texas Instruments Incorporated
MUX506, MUX507
www.ti.com.cn
ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
6.6 Electrical Characteristics: Single Supply
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
235
7
MAX
UNIT
V
ANALOG SWITCH
Analog signal range
On-resistance
TA = –40°C to +125°C
VS = 10 V, IS = –1 mA
VSS
VDD
340
390
430
20
RON
TA = –40°C to +85°C
TA = –40°C to +125°C
Ω
ΔRON
On-resistance match VS = 10 V, IS = –1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
35
Ω
40
On-resistance drift
VS = 10 V
1.07
Ω/°C
nA
–1
–10
–25
–1
0.001
1
10
25
1
Switch state is off,
VS = 1 V and VD = 10 V,
or VS = 10 V and VD = 1
V(1)
IS(OFF)
ID(OFF)
ID(ON)
Input leakage current
TA = –40°C to +85°C
TA = –40°C to +125°C
0.01
0.02
Switch state is off,
VS = 1 V and VD = 10 V,
or VS = 10 V and VD = 1
V(1)
Output off leakage
current
TA = –40°C to +85°C
TA = –40°C to +125°C
–10
–25
–1
10
25
1
nA
nA
Switch state is on,
VD = 1 V and 10 V, VS
floating
Output on leakage
current
=
TA = –40°C to +85°C
TA = –40°C to +125°C
–10
–50
10
50
LOGIC INPUT
VIH
VIL
ID
Logic voltage high
2.0
V
V
Logic voltage low
Input current
0.8
0.1
µA
(1) When VS is 1 V, VD is 10 V, and vice versa.
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Electrical Characteristics: Single Supply (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
SWITCH DYNAMIC CHARACTERISTICS(2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
90
145
145
149
84
VS = 8 V, RL = 300 Ω,
CL= 35 pF
tON
Enable turn-on time
Enable turn-off time
TA = –40°C to +85°C
TA = –40°C to +125°C
66
VS = 8 V, RL = 300 Ω,
CL= 35 pF
tOFF
TA = –40°C to +85°C
TA = –40°C to +125°C
94
ns
102
147
VS = 8 V, CL= 35 pF
107
VS = 8 V, RL = 300 Ω,
CL= 35 pF,
TA = –40°C to +85°C
TA = –40°C to +125°C
153
155
tt
Transition time
ns
VS = 8 V, RL = 300 Ω,
CL= 35 pF,
Break-before-make
time delay
tBBM
VS = 8 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C
30
54
ns
TSSOP package
SOIC package
TSSOP
0.12
0.38
±0.17
±0.48
–97
–94
–94
–88
–100
–99
-88
VS = 6 V
CL = 1 nF, RS = 0 Ω
pC
QJ
Charge injection
Off-isolation
VS = 0 V to 12 V
SOIC package
TSSOP package
SOIC package
TSSOP package
SOIC package
TSSOP package
SOIC package
TSSOP
Nonadjacent channel to D,
DA, DB
RL = 50 Ω, VS = 1 VRMS
,
dB
dB
f = 1 MHz
Adjacent channel to D, DA,
DB
Nonadjacent channels
Adjacent channels
Channel-to-channel
crosstalk
RL = 50 Ω, VS = 1 VRMS
f = 1 MHz
,
SOIC package
-83
CS(OFF)
CD(OFF)
Input off-capacitance f = 1 MHz, VS = 6 V
2.4
3.4
15.4
9.1
pF
pF
MUX506
MUX507
MUX506
MUX507
14
Output off-
f = 1 MHz, VS = 6 V
capacitance
7.8
16.2
9.9
18
CS(ON)
,
Output on-
f = 1 MHz, VS = 6 V
capacitance
pF
CD(ON)
11.6
POWER SUPPLY
41
22
59
62
83
34
37
57
All VA = 0 V or 3.3 V,
VS= 0 V, VEN = 3.3 V
VDD supply current
TA = –40°C to +85°C
TA = –40°C to +125°C
µA
µA
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
VSS supply current
TA = –40°C to +85°C
TA = –40°C to +125°C
(2) Specified by design, not subject to production test.
10
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6.7 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
400
350
300
250
200
150
100
50
TA = 90èC
VDD = 10 V, VSS = -10 V
350
TA = 125èC
TA = 25èC
VDD = 16.5 V, VSS = -16.5 V
300
250
200
150
100
50
VDD = 13.5 V, VSS = -13.5 V
TA = 0èC
VDD = 15 V, VSS = -15 V
TA = -40èC
-6 -2
VDD = 18 V, VSS = -18 V
0
-18
-18
-14
-10
-6
-2
2
6
10
14
18
-14
-10
2
6
10
14
18
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D001
D002
VDD = 15 V, VSS = –15 V
图 2. On-Resistance vs Source or Drain Voltage
图 1. On-Resistance vs Source or Drain Voltage
700
600
500
400
300
200
100
700
600
500
400
300
200
100
0
TA = 85èC
TA = 125èC
VDD = 5 V, VSS = -5 V
VDD = 6 V, VSS = -6 V
TA = 25èC
VDD = 7 V, VSS = -7 V
TA = 0èC
TA = -40èC
-8
-6
-4
-2
0
2
4
6
8
0
2
4
6
8
10
12
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D003
D004
VDD = 12 V, VSS = 0 V
图 3. On-Resistance vs Source or Drain Voltage
图 4. On-Resistance vs Source or Drain Voltage
250
200
150
100
50
700
600
500
400
300
200
100
0
VDD = 14 V, VSS = 0 V
VDD = 33 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
VDD = 30 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
VDD = 10 V, VSS = 0 V
0
0
6
12
18
24
30
36
0
2
4
6
8
10
12
14
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D024
D005
图 5. On-Resistance vs Source or Drain Voltage
图 6. On-Resistance vs Source or Drain Voltage
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Typical Characteristics (接下页)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
250
250
200
150
100
50
200
150
100
50
0
0
0
6
12
18
24
-12
-6
0
6
12
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D025
D026
VDD = 24 V, VSS = 0 V
VDD = 12 V, VSS = –12 V
图 7. On-Resistance vs Source or Drain Voltage
图 8. On-Resistance vs Source or Drain Voltage
1000
900
600
300
0
ID(ON)+
IS(OFF)+
IS(OFF)+
500
0
ID(OFF)+
ID(ON)+
IS(OFF)-
-500
-1000
-1500
-2000
IS(OFF)-
ID(OFF)-
ID(OFF)+
-300
-600
-900
ID(OFF)-
ID(ON)-
ID(ON)-
75 100 125 150
-75
-50
-25
0
25
50
75
100 125 150
-75
-50
-25
0
25
50
Temperature (èC)
Temperature (èC)
D006
D007
Þ
VDD = 15 V, VSS = –15 V
图 9. Leakage Current vs Temperature
VDD = 12 V, VSS = 0 V
图 10. Leakage Current vs Temperature
2
1
2
1
VDD = 5 V, VSS = -5 V
VDD = 12 V, VSS = 0 V
VDD = 5 V, VSS = -5 V
VDD = 12 V, VSS = 0 V
0
0
VDD = 10 V, VSS = -10 V
VDD = 10 V, VSS = -10 V
-1
-1
VDD = 15 V, VSS = -15 V
VDD = 15 V, VSS = -15 V
-2
-2
-15
-10
-5
0
5
10
15
-15
-10
-5
0
5
10
15
Source Voltage (V)
Source Voltage (V)
D011
D027
MUX506, source-to-drain
图 11. Charge Injection vs Source Voltage
MUX507, source-to-drain
图 12. Charge Injection vs Source Voltage
12
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Typical Characteristics (接下页)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
150
120
90
60
30
0
9
VDD = 10 V, VSS = -10 V
tON (VDD = 12 V, VSS = 0 V)
tON (VDD = 15 V, VSS = -15 V)
6
VDD = 15 V, VSS = -15 V
3
0
-3
tOFF (VDD = 12 V, VSS = 0 V)
tOFF (VDD = 15 V, VSS = -15 V)
-6
VDD = 12 V, VSS = 0 V
-9
-15
-10
-5
0
5
10
15
-75
-50
-25
0
25
50
75
100 125 150
Drain voltage (V)
Temperature (èC)
D008
D010
Drain-to-source
图 13. Charge Injection vs Drain Voltage
图 14. Turn-On and Turn-Off Times vs Temperature
0
0
-20
-20
-40
Adjacent Channel to D (Output)
Adjacent Channels
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
Non-Adjacent Channel to D (Output)
Non-Adjacent Channels
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
D012
D013
图 15. Off Isolation vs Frequency
图 16. Crosstalk vs Frequency
5
0
100
10
-5
VDD = 5 V, VSS = -5 V
-10
-15
-20
-25
-30
1
0.1
VDD = 15 V, VSS = -15 V
0.01
10
100
1k
Frequency (Hz)
10k
100k
100k
1M
10M
Frequency (Hz)
100M
1G
D014
D021
图 17. THD+N vs Frequency
图 18. On Response vs Frequency
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Typical Characteristics (接下页)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
30
30
24
18
12
6
24
CD(ON)
CS(OFF)
CD(OFF)
18
CD(OFF)
12
CD(ON)
6
CS(OFF)
0
0
-15
-10
-5
0
5
10
15
-15
-10
-5
0
5
10
15
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D015
D016
MUX506, VDD = 15 V, VSS = –15 V
MUX507, VDD = 15 V, VSS = –15 V
图 19. Capacitance vs Source Voltage
图 20. Capacitance vs Source Voltage
30
30
24
18
12
6
24
18
12
6
CS(OFF)
CD(ON)
CD(OFF)
CD(ON)
CD(OFF)
CS(OFF)
0
0
0
6
12
18
24
30
0
6
12
18
24
30
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D017
D018
MUX506, VDD = 30 V, VSS = 0 V
MUX507, VDD = 30 V, VSS = 0 V
图 21. Capacitance vs Source Voltage
图 22. Capacitance vs Source Voltage
30
24
18
12
6
30
24
18
12
6
CD(ON)
CD(OFF)
CD(ON)
CS(OFF)
CS(OFF)
CD(OFF)
0
0
0
3
6
9
12
0
3
6
9
12
Source or Drain Voltage (V)
Source or Drain Voltage (V)
D019
D020
MUX506, VDD = 12 V, VSS = 0 V
MUX507, VDD = 12 V, VSS = 0 V
图 23. Capacitance vs Source Voltage
图 24. Capacitance vs Source Voltage
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Typical Characteristics (接下页)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
25
20
15
10
5
0
-5
-10
-15
-20
-25
-25 -20 -15 -10
-5
0
5
10
15
20
25
Source Current (mA)
D028
图 25. Source Current vs Drain Current
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7 Parameter Measurement Information
7.1 Truth Tables
表 1. MUX506
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A3
X(1)
0
A2
X(1)
0
A1
X(1)
0
A0
X(1)
0
ON-CHANNEL
All channels are off
Channel 1
0
0
0
1
Channel 2
0
0
1
0
Channel 3
0
0
1
1
Channel 4
0
1
0
0
Channel 5
0
1
0
1
Channel 6
0
1
1
0
Channel 7
0
1
1
1
Channel 8
1
0
0
0
Channel 9
1
0
0
1
Channel 10
Channel 11
Channel 12
Channel 13
Channel 14
Channel 15
Channel 16
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
(1) X denotes don't care..
表 2. MUX507
EN
0
A2
X(1)
0
A1
X(1)
A0
X(1)
ON-CHANNEL
All channels are off
Channels 1A and 1B
Channels 2A and 2B
Channels 3A and 3B
Channels 4A and 4B
Channels 5A and 5B
Channels 6A and 6B
Channels 7A and 7B
Channels 8A and 8B
1
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
(1) X denotes don't care.
16
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7.2 On-Resistance
The on-resistance of the MUX50x is the ohmic resistance across the source (Sx, SxA, or SxB) and drain (D, DA,
or DB) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is
used to denote on-resistance. The measurement setup used to measure RON is shown in 图 26. Voltage (V) and
current (ICH) are measured using this setup, and RON is computed as shown in 公式 1:
RON = V / ICH
(1)
V
S
D
ICH
VS
Copyright © 2017, Texas Instruments Incorporated
图 26. On-Resistance Measurement Setup
7.3 Off Leakage
There are two types of leakage currents associated with a switch during the OFF state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in 图 27
Is (OFF)
ID (OFF)
A
S
D
A
VS
VD
Copyright © 2017, Texas Instruments Incorporated
图 27. Off-Leakage Measurement Setup
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7.4 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the ON state. The source pin is left floating during the measurement. 图 28 shows the circuit used for measuring
the on-leakage current, denoted by ID(ON)
.
ID (ON)
A
S
D
NC
NC = No Connection
VD
Copyright © 2017, Texas Instruments Incorporated
图 28. On-Leakage Measurement Setup
7.5 Transition Time
Transition time is defined as the time taken by the output of the MUX50x to rise or fall to 90% of the transition
after the digital address signal has fallen or risen to 50% of the transition. 图 29 shows the setup used to
measure transition time, denoted by the symbol tt.
VDD
VSS
3 V
VDD
VSS
Address
Signal (VIN
50%
50%
)
S1
VS1
A0
A1
A2
A3
0 V
S2-S15
S16
D
VIN
tt
tt
VS16
VS1
90%
Output
MUX506
Output
EN
2 V
GND
300 Ω
35 pF
90%
VS16
Copyright © 2016, Texas Instruments Incorporated
图 29. Transition-Time Measurement Setup
18
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7.6 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the MUX50x is
switching. The MUX50x output first breaks from the ON-state switch before making the connection with the next
ON-state switch. The time delay between the break and the make is known as break-before-make delay. 图 30
shows the setup used to measure break-before-make delay, denoted by the symbol tBBM
.
VDD
VSS
3 V
VSS
VDD
Address
Signal (VIN
)
S1
VS
A0
A1
A2
A3
0 V
S2-S15
S16
D
VIN
Output
MUX506
80%
80%
Output
2 V
EN
GND
300 Ω
35 pF
tBBM
Copyright © 2016, Texas Instruments Incorporated
图 30. Break-Before-Make Delay Measurement Setup
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7.7 Turn-On and Turn-Off Time
Turn-on time is defined as the time taken by the output of the MUX50x to rise to 90% final value after the enable
signal has risen to 50% final value. 图 31 shows the setup used to measure turn-on time. Turn-on time is
denoted by the symbol tON
.
Turn off time is defined as the time taken by the output of the MUX50x to fall to 10% initial value after the enable
signal has fallen to 50% initial value. 图 31 shows the setup used to measure turn-off time. Turn-off time is
denoted by the symbol tOFF
.
VDD
VSS
3 V
VDD
VSS
Enable
Drive (VIN)
50%
50%
S1
VS
A0
A1
A2
A3
S2-S16
0 V
tOFF (EN)
MUX506
tON (EN)
VS
0.9 VS
Output
Output
EN
D
GND
300 Ω
35 pF
0.1 VS
VIN
0 V
Copyright © 2016, Texas Instruments Incorporated
图 31. Turn-On and Turn-Off Time Measurement Setup
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7.8 Charge Injection
The MUX50x have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QINJ. 图 32 shows the setup used to measure charge injection.
VSS
VDD
VDD
VSS
A0
A1
A2
A3
3 V
VEN
MUX506
0 V
RS
S1
D
VOUT
EN
VOUT
CL
1 nF
VOUT
VS
GND
QINJ = CL
×
VOUT
VEN
Copyright © 2016, Texas Instruments Incorporated
图 32. Charge-Injection Measurement Setup
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7.9 Off Isolation
Off isolation is defined as the voltage at the drain pin (D, DA, or DB) of the MUX50x when a 1-VRMS signal is
applied to the source pin (Sx, SxA, or SxB) of an off-channel. 图 33 shows the setup used to measure off
isolation. Use 公式 2 to compute off isolation.
VDD
VSS
0.1 µF
0.1 µF
Network Analyzer
VSS
VDD
50 ꢀ
S
50 Ω
VS
D
VOUT
RL
50 Ω
GND
Copyright © 2017, Texas Instruments Incorporated
图 33. Off Isolation Measurement Setup
≈
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
∆
«
(2)
7.10 Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx, SxA, or SxB) of an off-channel,
when a 1-VRMS signal is applied at the source pin of an on-channel. 图 34 shows the setup used to measure
channel-to-channel crosstalk. Use 公式 3 to compute, channel-to-channel crosstalk.
VDD
VSS
0.1 µF
0.1 µF
VSS
VDD
Network Analyzer
VOUT
S1
RL
50 Ω
R
S2
50 Ω
VS
GND
Copyright © 2017, Texas Instruments Incorporated
图 34. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(3)
22
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7.11 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin of an on-channel, and the output measured at the drain pin of the MUX50x. 图 35 shows the
setup used to measure bandwidth of the mux. Use 公式 4 to compute the attenuation.
VDD
VSS
0.1 µF
0.1 µF
Network Analyzer
VSS
VDD
V1
50 ꢀ
S
VS
V2
D
VOUT
RL
50 Ω
GND
Copyright © 2017, Texas Instruments Incorporated
图 35. Bandwidth Measurement Setup
≈
∆
«
’
÷
◊
V2
Attenuation = 20 ∂ Log
V
1
(4)
7.12 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the
ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux
output. The on-resistance of the MUX50x varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD+N. 图 36 shows the setup used to measure THD+N of the MUX50x.
VDD
VSS
0.1 µF
0.1 µF
Audio Precision
VSS
VDD
RS
S
IN
VS
5 VRMS
D
VIN
VOUT
RL
10 kΩ
GND
Copyright © 2017, Texas Instruments Incorporated
图 36. THD+N Measurement Setup
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8 Detailed Description
8.1 Overview
The MUX50x are a family of analog multiplexers. The Functional Block Diagram section provides a top-level
block diagram of both the MUX506 and MUX507. The MUX506 is a 16-channel, single-ended, analog mux. The
MUX507 is an 8-channel, differential or dual 8:1, single-ended, analog mux. Each channel is turned on or turned
off based on the state of the address lines and enable pin.
8.2 Functional Block Diagram
MUX507
MUX506
S1
S2
S3
S1A
S2A
S7A
S8A
DA
DB
S8
S9
D
S1B
S2B
S14
S7B
S8B
S15
S16
1-of-8
Decoder
1-of-16
Decoder
A0
A1
EN
A2
A3
A0
A1
A2
EN
Copyright © 2016, Texas Instruments Incorporated
24
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MUX506, MUX507
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ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
8.3 Feature Description
8.3.1 Ultralow Leakage Current
The MUX50x provide extremely low on- and off-leakage currents. The MUX50x are capable of switching signals
from high source-impedance inputs into a high input-impedance op amp with minimal offset error because of the
ultra-low leakage currents. 图 37 shows typical leakage currents of the MUX50x versus temperature.
1000
ID(ON)+
IS(OFF)+
500
ID(OFF)+
0
-500
IS(OFF)-
-1000
ID(OFF)-
-1500
ID(ON)-
-2000
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
D006
图 37. Leakage Current vs Temperature
8.3.2 Ultralow Charge Injection
The MUX50x have a simple transmission gate topology, as shown in 图 38. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
Copyright © 2017, Texas Instruments Incorporated
图 38. Transmission Gate Topology
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MUX506, MUX507
ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
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Feature Description (接下页)
The MUX50x have special charge-injection cancellation circuitry that reduces the source-to-drain charge injection
to as low as 0.31 pC at VS = 0 V, and ±0.9 pC in the full signal range, as shown in 图 39.
2
VDD = 5 V, VSS = -5 V
VDD = 12 V, VSS = 0 V
1
0
VDD = 10 V, VSS = -10 V
-1
VDD = 15 V, VSS = -15 V
-2
-15
-10
-5
0
5
10
15
Source Voltage (V)
D011
图 39. Source-to-Drain Charge Injection
The drain-to-source charge injection becomes important when the device is used as a demultiplexer (demux),
where D becomes the input and Sx becomes the output. 图 40 shows the drain-to-source charge injection across
the full signal range.
9
VDD = 10 V, VSS = -10 V
6
VDD = 15 V, VSS = -15 V
3
0
-3
-6
VDD = 12 V, VSS = 0 V
-9
-15
-10
-5
0
5
10
15
Drain voltage (V)
D008
图 40. Drain-to-Source Charge Injection
26
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MUX506, MUX507
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ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
Feature Description (接下页)
8.3.3 Bidirectional Operation
The MUX50x are operable as both a mux and demux. The source (Sx, SxA, SxB) and drain (D, DA, DB) pins of
the MUX50x are used either as input or output. Each MUX50x channel has very similar characteristics in both
directions.
8.3.4 Rail-to-Rail Operation
The valid analog signal for the MUX50x ranges from VSS to VDD. The input signal to the MUX50x swings from VSS
to VDD without any significant degradation in performance. The on-resistance of the MUX50x varies with input
signal, as shown in 图 41
400
VDD = 10 V, VSS = -10 V
350
VDD = 16.5 V, VSS = -16.5 V
300
250
200
150
100
50
VDD = 13.5 V, VSS = -13.5 V
VDD = 15 V, VSS = -15 V
VDD = 18 V, VSS = -18 V
-18
-14
-10
-6
-2
2
6
10
14
18
Source or Drain Voltage (V)
D001
图 41. On-resistance vs Source or Drain Voltage
8.4 Device Functional Modes
When the EN pin of the MUX50x is pulled high, one of the switches is closed based on the state of the address
lines. When the EN pin is pulled low, all the switches are in an open state irrespective of the state of the address
lines. The EN pin can be connected to VDD (as high as 36 V).
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MUX506, MUX507
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The MUX50x family offers outstanding input/output leakage currents and ultra-low charge injection. These
devices operate up to 36 V, and offer true rail-to-rail input and output. The on-capacitance of the MUX50x is very
low. These features makes the MUX50x a family of precision, robust, high-performance analog multiplexer for
high-voltage, industrial applications.
9.2 Typical Application
图 42 shows a 16-bit, differential, 8-channel, multiplexed, data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential mux. This TI Precision
Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the MUX507,
OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
Analog Inputs
REF3140
RC Filter
OPA350
RC Filter
Bridge Sensor
Thermocouple
Reference Driver
Gain Network
Gain Network
OPA192
+
REF
+
OPA140
VINP
Charge
Kickback
Filter
Gain Network
OPA192
+
ADS8864
Current Sensing
Photo
VINM
Detector
LED
High-Voltage Multiplexed Input
High-Voltage Level Translation
VCM
Optical Sensor
Copyright © 2016, Texas Instruments Incorporated
图 42. 16-Bit Precision Multiplexed Data-Acquisition System for High-Voltage Inputs With Lowest
Distortion
9.2.1 Design Requirements
The primary objective is to design a ±20 V, differential, 8-channel, multiplexed, data-acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure, sine-wave
input. The design requirements for this block design are:
•
•
•
•
•
System supply voltage: ±15 V
ADC supply voltage: 3.3 V
ADC sampling rate: 400 kSPS
ADC reference voltage (REFP): 4.096 V
System input signal: A high-voltage differential input signal with a peak amplitude of 20 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
28
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MUX506, MUX507
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ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
Typical Application (接下页)
9.2.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal, high-voltage, multiplexed, data-acquisition system
for highest system linearity and fast settling. The overall system block diagram is illustrated in 图 42. The circuit
is a multichannel, data-acquisition signal chain consisting of an input low-pass filter, mux, mux output buffer,
attenuating SAR ADC driver, and the reference driver. The architecture allows fast sampling of multiple channels
using a single ADC, providing a low-cost solution. This design systematically approaches each analog circuit
block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal input
signal at each input channel. Detailed design considerations and component selection procedure can be found in
the TI Precision Design TIPD151, 16-Bit, 400-kSPS, 4-Channel Multiplexed Data-Acquisition System for High-
Voltage Inputs with Lowest Distortion.
9.2.3 Application Curve
1.0
0.8
0.6
0.4
0.2
0.0
œ0.2
œ0.4
œ0.6
œ0.8
œ1.0
0
5
10
15
20
œ20
œ15
œ10
œ5
C030
ADC Differential Peak-to-Peak Input (V)
图 43. ADC 16-Bit Linearity Error for the Multiplexed Data-Acquisition Block
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ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
10 Power Supply Recommendations
The MUX50x operates across a wide supply range of ±5 V to ±18 V (10 V to 36 V in single-supply mode). The
devices also perform well with unsymmetric supplies such as VDD = 12 V and VSS= –5 V. For reliable operation,
use a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to ground.
The on-resistance of the MUX50x varies with supply voltage, as illustrated in 图 44
400
VDD = 10 V, VSS = -10 V
350
VDD = 16.5 V, VSS = -16.5 V
300
250
200
150
100
50
VDD = 13.5 V, VSS = -13.5 V
VDD = 15 V, VSS = -15 V
VDD = 18 V, VSS = -18 V
-18
-14
-10
-6
-2
2
6
10
14
18
Source or Drain Voltage (V)
D001
图 44. On-Resistance Variation With Supply and Input Voltage
30
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ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
11 Layout
11.1 Layout Guidelines
图 45 illustrates an example of a PCB layout with the MUX506IPW, and 图 46 illustrates an example of a PCB
layout with MUX507IPW.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as short as possible. In case of the differential signal, make sure the A inputs and B
inputs are as symmetric as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
VDD
NC
D
C
Via to
GND Plane
Via to
GND Plane
C
VSS
S8
S7
S6
S5
S4
S3
S2
S1
EN
A0
A1
A2
NC
S16
S15
S14
S13
S12
S11
S10
S9
MUX506IPW
Via to
GND Plane
GND
NC
A3
图 45. MUX506IPW Layout Example
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ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
www.ti.com.cn
Layout Example (接下页)
VDD
DB
DA
VSS
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
EN
C
Via to
GND Plane
Via to
GND Plane
C
NC
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
NC
MUX507IPW
Via to
GND Plane
A0
A1
NC
A2
图 46. MUX507IPW Layout Example
32
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MUX506, MUX507
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ZHCSFU9A –NOVEMBER 2016–REVISED NOVEMBER 2017
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
《ADS8864
号：SBAS572）
16
位、400kSPS
串行接口、微功耗、微型、单端输入、SAR
模数转换器》（文献编
《采用 e-trim 技术的 36V、轨到轨输入/输出、低失调电压、低输入偏置电流 OPAx192 运算放大器》（文献编
号：SBOS620）
《OPAx140 高精度、低噪声、轨到轨输出、11MHz JFET 运算放大器》（文献编号：SBOS498）
12.2 相关链接
下面的表格中列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品
的快速链接。
表 3. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
MUX506
MUX507
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2016–2017, Texas Instruments Incorporated
33
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MUX506IDWR
MUX506IPW
MUX506IPWR
MUX507IDWR
MUX507IPW
MUX507IPWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
TSSOP
TSSOP
SOIC
DW
PW
PW
DW
PW
PW
28
28
28
28
28
28
1000 RoHS & Green
50 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
MUX506DA
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
MUX506A
MUX506A
MUX507DA
MUX507A
MUX507A
2000 RoHS & Green
1000 RoHS & Green
TSSOP
TSSOP
50
RoHS & Green
2000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MUX506IDWR
MUX506IPWR
MUX507IDWR
MUX507IPWR
SOIC
TSSOP
SOIC
DW
PW
DW
PW
28
28
28
28
1000
2000
1000
2000
330.0
330.0
330.0
330.0
32.4
16.4
32.4
16.4
11.35 18.67
6.9 10.2
11.35 18.67
6.9 10.2
3.1
1.8
3.1
1.8
16.0
12.0
16.0
12.0
32.0
16.0
32.0
16.0
Q1
Q1
Q1
Q1
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MUX506IDWR
MUX506IPWR
MUX507IDWR
MUX507IPWR
SOIC
TSSOP
SOIC
DW
PW
DW
PW
28
28
28
28
1000
2000
1000
2000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
66.0
43.0
66.0
43.0
TSSOP
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
MUX506IPW
MUX507IPW
PW
PW
TSSOP
TSSOP
28
28
50
50
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
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