MSP430G2210ID_技术文档

MSP430G22x0

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SLAS753D –JANUARY 2012–REVISED AUGUST 2012

MIXED SIGNAL MICROCONTROLLER

1

FEATURES

23

•

Low Supply Voltage Range: 1.8 V to 3.6 V

(A/D) Conversion (MSP430G2210 Only)

•

Ultra-Low Power Consumption

•

10-Bit 200-ksps Analog-to-Digital (A/D)

Converter With Internal Reference, Sample-

and-Hold, and Autoscan (MSP430G2230 Only)

–

Active Mode: 220 µA at 1 MHz, 2.2 V

Standby Mode: 0.5 µA

Universal Serial Interface (USI) Supports SPI

and I2C (MSP430G2230 Only)

Off Mode (RAM Retention): 0.1 µA

•

Five Power-Saving Modes

•

Brownout Detector

Ultra-Fast Wake-Up From Standby Mode in

Less Than 1 µs

Serial Onboard Programming, No External

Programming Voltage Needed, Programmable

Code Protection by Security Fuse

•

16-Bit RISC Architecture, 62.5-ns Instruction

Cycle Time

•

On-Chip Emulation Logic With Spy-Bi-Wire

Interface

Basic Clock Module Configurations

–

Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1%

Family Members:

–

MSP430G22x0

–

Internal Very-Low-Power Low-Frequency

Oscillator

–

2KB + 256B Flash Memory

128B RAM

•

16-Bit Timer_A With Two Capture/Compare

Registers

•

Available in 8-Pin Plastic Packages (D)

For Complete Module Descriptions, See the

MSP430x2xx Family User's Guide (SLAU144)

On-Chip Comparator for Analog Signal

Compare Function or Slope Analog-to-Digital

DESCRIPTION

The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430G22x0 series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer and four

I/O pins. In addition, the MSP430G2230 has a built-in communication capability using synchronous protocols

(SPI or I2C) and a 10-bit A/D converter. The MSP430G2210 has a versatile analog comparator.

Table 1. Available Options⁽¹⁾

PACKAGED DEVICES⁽²⁾

T_A

PLASTIC 8-PIN (D)

MSP430G2230ID

-40°C to 85°C

MSP430G2210ID

(1) For the most current package and ordering information, see the

Package Option Addendum at the end of this document, or see the

TI web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at

www.ti.com/packaging

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

MSP430 is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

MSP430G22x0

SLAS753D –JANUARY 2012–REVISED AUGUST 2012

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Device Pinout and Functional Block Diagram, MSP430G2210

See Application Information for detailed I/O information.

D PACKAGE

(TOP VIEW)

DVSS

DVCC

8

7

6

5

1

2

3

4

TEST/SBWTCK

RST/NMI/SBWTDIO

P1.7/CAOUT/CA7

P1.2/TA0.1/CA2

P1.5/TA0.0/CA5

P1.6/TA0.1/CA6

Figure 1. Device Pinout, MSP430G2210

P1.2, P1.5,

P1.6, P1.7

4

VCC

VSS

XIN

XOUT

Port P1

ACLK

Basic Clock

System+

COMP_A+

Flash

2kB

RAM

128B

4 I/O

Interrupt

SMCLK

4 Channel

input MUX

capability,

pull−up/down

resistors

MCLK

MAB

16MHz

CPU

incl. 16

Registers

MDB

Emulation

(2BP)

Watchdog

WDT+

Timer_A2

JTAG

Interface

Brownout

Protection

2 CC

Registers

15/16−Bit

Spy−Bi Wire

RST/NMI

Figure 2. Functional Block Diagram, MSP430G2210

2

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Device Pinout and Functional Block Diagram, MSP430G2230

See Application Information for detailed I/O information.

D PACKAGE

(TOP VIEW)

DVSS

TEST/SBWTCK

DVCC

8

7

6

5

1

2

3

4

P1.2/TA0.1/A2

P1.5/TA0.0/A5/SCLK

RST/NMI/SBWTDIO

P1.7/A7/SDI/SDA

P1.6/TA0.1/A6/SDO/SCL

Figure 3. Device Pinout, MSP430G2230

P1.2, P1.5,

P1.6, P1.7

4

VCC

VSS

XIN

XOUT

Port P1

ADC

ACLK

Basic Clock

System+

Flash

2kB

RAM

128B

4 I/O

Interrupt

10-Bit

SMCLK

4 Channel

Autoscan

1 ch DMA

capability,

pull−up/down

resistors

MCLK

MAB

16MHz

CPU

incl. 16

Registers

MDB

Emulation

(2BP)

USI

Watchdog

WDT+

Timer_A2

JTAG

Interface

Brownout

Protection

Universal

Serial

2 CC

Registers

15/16−Bit

Interface

SPI, I2C

Spy−Bi Wire

RST/NMI

Figure 4. Functional Block Diagram, MSP430G2230

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Table 2. Terminal Functions, MSP430G2210⁽¹⁾

TERMINAL

NO.

DESCRIPTION

NAME

I/O

D

P1.2/

TA0.1/

CA2

General-purpose digital I/O pin

2

I/O

Timer_A, capture: CCI1A input, compare Out1 output

Comparator_A+, CA2 input

P1.5/

TA0.0/

CA5

General-purpose digital I/O pin

Timer_A, compare Out0 output

Comparator_A+, CA5 input

3

4

5

I/O

P1.6/

TA0.1/

CA6

General-purpose digital I/O pin

Timer_A, compare: Out1 output

Comparator_A+, CA6 input

P1.7/

General-purpose digital I/O pin

Comparator_A+, output

CAOUT/

CA7

Comparator_A+, CA7 input

RST/

Reset input

6

7

I

NMI/

Nonmaskable interrupt input

SBWTDIO

Spy-Bi-Wire test data input/output during programming and test

TEST/

Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.

Spy-Bi-Wire test clock input during programming and test

Digital supply voltage

SBWTCK

DVCC

1

8

DVSS

Digital ground reference

(1) The GPIOs P1.0, P1.1, P1.3, P1.4, P2.6, and P2.7 are implemented but not available on the device pinout. To avoid floating inputs,

these digital I/Os should be properly configured. The pullup or pulldown resistors of the unbounded P1.x GPIOs should be enabled, and

the VLO should be selected as the ACLK source (see the MSP430x2xx Family User's Guide (SLAU144)).

4

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Table 3. Terminal Functions, MSP430G2230⁽¹⁾

TERMINAL

NO.

D

DESCRIPTION

NAME

I/O

P1.2/

General-purpose digital I/O pin

2

I/O

TA0.1/

A2

Timer_A, capture: CCI1A input, compare Out1 output

ADC10 analog input A2

P1.5/

TA0.0/

A5/

General-purpose digital I/O pin

Timer_A, compare Out0 output

3

I/O

ADC10 analog input A5

SCLK

USI: clock input in I2C mode; clock input/output in SPI mode

P1.6/

TA0.1/

A6/

General-purpose digital I/O pin

Timer_A, capture: CCI1B input, compare: Out1 output

ADC10 analog input A6

4

5

SDO/

SCL

USI: Data output in SPI mode

USI: I2C clock in I2C mode

P1.7/

A7/

General-purpose digital I/O pin

ADC10 analog input A7

SDI/

SDA

USI: Data input in SPI mode

USI: Data input in I2C mode

RST/

Reset input

6

7

I

NMI/

Nonmaskable interrupt input

SBWTDIO

Spy-Bi-Wire test data input/output during programming and test

TEST/

Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.

Spy-Bi-Wire test clock input during programming and test

Digital supply voltage

SBWTCK

DVCC

1

8

DVSS

Digital ground reference

(1) The GPIOs P1.0, P1.1, P1.3, P1.4, P2.6, and P2.7 are implemented but not available on the device pinout. To avoid floating inputs,

these digital I/Os should be properly configured. The pullup or pulldown resistors of the unbounded P1.x GPIOs should be enabled, and

the VLO should be selected as the ACLK source (see the MSP430x2xx Family User's Guide (SLAU144)).

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SHORT-FORM DESCRIPTION

Program Counter

Stack Pointer

PC/R0

CPU

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions, are

performed as register operations in conjunction with

seven addressing modes for source operand and four

addressing modes for destination operand.

SP/R1

SR/CG1/R2

CG2/R3

R4

Status Register

Constant Generator

General-Purpose Register

The CPU is integrated with 16 registers that provide

reduced instruction execution time. The register-to-

register operation execution time is one cycle of the

CPU clock.

R5

R6

R7

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register, and

constant generator, respectively. The remaining

registers are general-purpose registers.

R8

R9

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled with

all instructions.

R10

R11

Instruction Set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 4 shows examples of the three types of

instruction formats; Table 5 shows the address

modes.

R12

R13

R14

R15

Table 4. Instruction Word Formats

INSTRUCTION FORMAT

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

EXAMPLE

ADD R4,R5

CALL R8

JNE

OPERATION

R4 + R5 ---> R5

PC -->(TOS), R8--> PC

Jump-on-equal bit = 0

Table 5. Address Mode Descriptions

ADDRESS MODE

Register

S⁽¹⁾

✓

D⁽¹⁾

✓

SYNTAX

MOV Rs,Rd

EXAMPLE

MOV R10,R11

MOV 2(R5),6(R6)

OPERATION

R10 --> R11

Indexed

✓

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV &MEM,&TCDAT

MOV @Rn,Y(Rm)

M(2+R5)--> M(6+R6)

M(EDE) --> M(TONI)

M(MEM) --> M(TCDAT)

M(R10) --> M(Tab+R6)

Symbolic (PC relative)

Absolute

✓

Indirect

✓

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

M(R10) --> R11

R10 + 2--> R10

Indirect autoincrement

Immediate

✓

MOV @Rn+,Rm

MOV #X,TONI

#45 --> M(TONI)

(1) S = source, D = destination

6

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Operating Modes

The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt

event can wake the device from any of the five low-power modes, service the request, and restore back to the

low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

•

Active mode (AM)

All clocks are active

Low-power mode 0 (LPM0)

–

•

–

CPU is disabled

ACLK and SMCLK remain active

MCLK is disabled

•

Low-power mode 1 (LPM1)

–

CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

DCO's dc-generator is disabled if DCO not used in active mode

Low-power mode 2 (LPM2)

–

CPU is disabled

MCLK and SMCLK are disabled

DCO's dc-generator remains enabled

ACLK remains active

•

Low-power mode 3 (LPM3)

–

CPU is disabled

MCLK and SMCLK are disabled

DCO's dc-generator is disabled

ACLK remains active

Low-power mode 4 (LPM4)

–

CPU is disabled

ACLK is disabled

MCLK and SMCLK are disabled

DCO's dc-generator is disabled

Crystal oscillator is stopped

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Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0x0FFFF to

0x0FFC0. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0x0FFFE) contains 0x0FFFF (for example, flash is not programmed) the

CPU goes into LPM4 immediately after power-up.

Table 6. Interrupt Sources

SYSTEM

INTERRUPT

INTERRUPT SOURCE

INTERRUPT FLAG

WORD ADDRESS

PRIORITY

Power-up

External reset

Watchdog Timer+

Flash key violation

PC out-of-range⁽¹⁾

PORIFG

RSTIFG

WDTIFG

KEYV⁽²⁾

Reset

0xFFFE

31, highest

NMI

Oscillator fault

Flash memory access violation

NMIIFG

OFIFG

(non)-maskable,

(non)-maskable

0xFFFC

30

ACCVIFG⁽²⁾⁽³⁾

0xFFFA

0xFFF8

29

28

Comparator_A+

(MSP430G2210 Only)

(4)

CAIFG

0xFFF6

27

Watchdog Timer+

Timer_A2

WDTIFG

TACCR0 CCIFG⁽⁴⁾

TACCR1 CCIFG, TAIFG⁽²⁾⁽⁴⁾

maskable

0xFFF4

0xFFF2

0xFFF0

0xFFEE

0xFFEC

0xFFEA

0xFFE8

0xFFE6

26

25

24

23

22

21

20

19

Timer_A2

ADC10 (MSP430G2230 Only)

USI (MSP430G2230 Only)

ADC10IFG⁽⁴⁾

USIIFG, USISTTIFG⁽²⁾⁽⁴⁾

maskable

P1IFG.2, P1IFG.5, P1IFG.6, and

P1IFG.7^(2)(4)(5)

I/O Port P1(four flags)

maskable

0xFFE4

18

0xFFE2

0xFFE0

17

16

(6)

See

0xFFDE to 0xFFC0

15 to 0, lowest

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address ranges.

(2) Multiple source flags

(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

(4) Interrupt flags are located in the module.

(5) All eight interrupt flags P1IFG.0 to P1IFG.7 are implemented while four are connected to pins.

(6) The interrupt vectors at addresses 0xFFDE to 0xFFC0 are not used in this device and can be used for regular program code if

necessary.

8

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Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

Legend

rw:

Bit can be read and written.

rw-0,1:

rw-(0,1):

Bit can be read and written. It is reset or set by PUC.

Bit can be read and written. It is reset or set by POR.

SFR bit is not present in device.

Table 7. Interrupt Enable Register 1 and 2

Address

00h

7

6

5

4

3

2

1

0

ACCVIE

rw-0

NMIIE

rw-0

OFIE

rw-0

WDTIE

rw-0

WDTIE

Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval

timer mode.

OFIE

Oscillator fault interrupt enable. Set to 0.

(Non)maskable interrupt enable

NMIIE

ACCVIE

Flash access violation interrupt enable

Address

7

6

5

4

3

2

1

0

01h

Table 8. Interrupt Flag Register 1 and 2

Address

02h

7

6

5

4

3

2

1

0

NMIIFG

rw-0

RSTIFG

rw-(0)

PORIFG

rw-(1)

OFIFG

rw-1

WDTIFG

rw-(0)

WDTIFG

Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V_CCpower-on or a reset condition at the RST/NMI pin in reset mode.

OFIFG

Flag set on oscillator fault. The XIN/XOUT pins are not available as device terminals.

Power-On Reset interrupt flag. Set on V_CCpower-up.

PORIFG

RSTIFG

NMIIFG

External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V_CCpower-up.

Set by RST/NMI pin

Address

03h

7

6

5

4

3

2

1

0

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Memory Organization

Table 9. Memory Organization

MSP430G22x0

Memory

Main: interrupt vector

Main: code memory

Size

Flash

2KB Flash

0xFFFF-0xFFC0

0xFFFF-0xF800

Size

Flash

256 Byte

0x10FF - 0x1000

Information memory

RAM

128 Byte

0x027F - 0x0200

Size

16-bit

8-bit

8-bit SFR

0x01FF - 0x0100

0x00FF - 0x0010

0x000F - 0x0000

Peripherals

Flash Memory

The flash memory can be programmed by the Spy-Bi-Wire or JTAG port, or in-system by the CPU. The CPU can

perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also

called information memory.

•

Segment A contains calibration data. After reset segment A is protected against programming and erasing. It

can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is

required.

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Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal very-low-power low-frequency oscillator and an internal digitally-controlled oscillator (DCO).

The basic clock module is designed to meet the requirements of both low system cost and low power

consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic

clock module provides the following clock signals:

•

Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF (VLOCLK) oscillator.

Main clock (MCLK), the system clock used by the CPU.

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

NOTE

The LFXT1 oscillator is not available. LFXT1Sx bits of the BCSCTL3 register should be

configured to use VLOCLK (see the MSP430x2xx Family User's Guide (SLAU144)).

Table 10. DCO Calibration Data (Provided From

Factory in Flash Information Memory Segment A)

DCO

FREQUENCY

CALIBRATION

REGISTER

SIZE

ADDRESS

CALBC1_1MHZ

CALDCO_1MHZ

CALBC1_8MHZ

CALDCO_8MHZ

CALBC1_12MHZ

CALDCO_12MHZ

CALBC1_16MHZ

CALDCO_16MHZ

byte

010FFh

010FEh

010FDh

010FCh

010FBh

010FAh

010F9h

010F8h

1 MHz

8 MHz

12 MHz

16 MHz

Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and

power off.

Digital I/O

There are four pins of one 8-bit I/O port implemented—port P1:

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt condition is possible.

Edge-selectable interrupt input capability for all the four bits of port P1.

Read/write access to port-control registers is supported by all instructions.

Each I/O has an individually programmable pullup/pulldown resistor.

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Watchdog Timer (WDT+)

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be disabled or configured as an interval timer and can

generate interrupts at selected time intervals.

Timer_A2

Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Table 11. Timer_A2 Signal Connections - MSP430G2210

INPUT PIN

NUMBER

OUTPUT PIN

NUMBER

MODULE

OUTPUT

SIGNAL

DEVICE INPUT

SIGNAL

MODULE

INPUT NAME

MODULE

BLOCK

D

-

TACLK

ACLK

TACLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

CCR0

CCR1

NA

TA0

TA1

SMCLK

TACLK

TA0

-

3 - P1.5

ACLK (internal)

V_SS

V_CC

2 - P1.2

TA1

CCI1A

2 - P1.2

4 - P1.6

CAOUT

(internal)

CCI1B

V_SS

V_CC

GND

V_CC

Table 12. Timer_A2 Signal Connections - MSP430G2230

INPUT PIN

NUMBER

OUTPUT PIN

NUMBER

MODULE

OUTPUT

SIGNAL

DEVICE INPUT

SIGNAL

MODULE

INPUT NAME

MODULE

BLOCK

D

-

TACLK

ACLK

SMCLK

TACLK

TA0

TACLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

CCR0

CCR1

NA

TA0

TA1

-

ACLK (internal)

V_SS

V_CC

2 - P1.2

4 - P1.6

TA1

CCI1A

CCI1B

GND

2 - P1.2

4 - P1.6

TA1

V_SS

V_CC

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USI (MSP430G2230 Only)

The universal serial interface (USI) module is used for serial data communication and provides the basic

hardware for synchronous communication protocols like SPI and I2C.

ADC10 (MSP430G2230 Only)

The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion

result handling, allowing ADC samples to be converted and stored without any CPU intervention.

Comparator_A+ (MSP430G2210 Only)

The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,

battery-voltage supervision, and monitoring of external analog signals

Peripheral File Map

Table 13. Peripherals With Word Access

ADC10

(MSP430G2230 Only)

ADC control 0

ADC10 control 1

ADC memory

ADC10CTL0

ADC10CTL1

ADC10MEM

01B0h

01B2h

01B4h

Timer_A

Capture/compare register

Timer_A register

Capture/compare control

Timer_A control

TACCR1

TACCR0

TAR

TACCTL1

TACCTL0

TACTL

0174h

0172h

0170h

0164h

0162h

0160h

012Eh

Timer_A interrupt vector

TAIV

Flash Memory

Flash control 3

Flash control 2

Flash control 1

FCTL3

FCTL2

FCTL1

012Ch

012Ah

0128h

Watchdog Timer+

Watchdog/timer control

WDTCTL

0120h

Table 14. Peripherals With Byte Access

ADC10

(MSP430G2230 Only)

Analog Enable

ADC10AE

04Ah

USI

USI control 0

USI control 1

USI clock control

USI bit counter

USI shift register

USICTL0

USICTL1

USICKCTL

USICNT

USISR

078h

079h

07Ah

07Bh

07Ch

(MSP430G2230 Only)

Comparator_A+

(MSP430G2210 Only)

Comparator_A+ port disable

Comparator_A+ control 2

Comparator_A+ control 1

CAPD

CACTL2

CACTL1

05Bh

05Ah

059h

Basic Clock System+

Port P1

Basic clock system control 3

Basic clock system control 2

Basic clock system control 1

DCO clock frequency control

BCSCTL3

BCSCTL2

BCSCTL1

DCOCTL

053h

058h

057h

056h

Port P1 resistor enable

Port P1 selection

Port P1 interrupt enable

Port P1 interrupt edge select

Port P1 interrupt flag

Port P1 direction

P1REN

P1SEL

P1IE

P1IES

P1IFG

P1DIR

P1OUT

P1IN

027h

026h

025h

024h

023h

022h

021h

020h

Port P1 output

Port P1 input

Special Function

SFR interrupt flag 2

SFR interrupt flag 1

SFR interrupt enable 2

SFR interrupt enable 1

IFG2

IFG1

IE2

003h

002h

001h

000h

IE1

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Absolute Maximum Ratings⁽¹⁾

Voltage applied at V_CCto V_SS

-0.3 V to 4.1 V

Voltage applied to any pin⁽²⁾

-0.3 V to V_CC+ 0.3 V

±2 mA

Diode current at any device terminal

Unprogrammed device

Programmed device

-55°C to 150°C

-40°C to 150°C

T_stg

Storage temperature⁽³⁾

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS. The JTAG fuse-blow voltage, V_FB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

Recommended Operating Conditions

MIN NOM

MAX UNIT

During program execution

During flash program/erase

1.8

2.2

0

3.6

V

V_CC

Supply voltage

3.6

V_SS

T_A

Supply voltage

V

Operating free-air temperature

-40

85

6

°C

V_CC= 1.8 V,

Duty cycle = 50% ± 10%

dc

V_CC= 2.7 V,

Duty cycle = 50% ± 10%

f_SYSTEM

Processor frequency (maximum MCLK frequency)⁽¹⁾⁽²⁾

12 MHz

16

V_CC≥ 3.3 V,

Duty cycle = 50% ± 10%

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the

specified maximum frequency.

(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

Legend :

16 MHz

Supply voltage range,

during flash memory

programming

12 MHz

Supply voltage range,

during program execution

6 MHz

1.8 V

2.2 V

2.7 V

3.3 V 3.6 V

Supply Voltage −V

Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V_CC

of 2.2 V.

Figure 5. Safe Operating Area

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Electrical Characteristics

Active Mode Supply Current Into V_CCExcluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

f_DCO= f_MCLK= f_SMCLK= 1 MHz,

f_ACLK= 0 Hz,

2.2 V

220

Program executes in flash,

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 0, SCG0 = 0,

SCG1 = 0, OSCOFF = 0

Active mode (AM)

current (1 MHz)

I_AM,1MHz

µA

3 V

300

370

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

Typical Characteristics – Active Mode Supply Current (Into V_CC)

ACTIVE MODE CURRENT

vs

V_CC

ACTIVE MODE CURRENT

vs

(T_A= 25°C)

DCO FREQUENCY

4.0

3.0

2.0

1.0

0.0

5.0

4.0

3.0

2.0

1.0

0.0

f

= 16 MHz

DCO

T_A= 85°C

T_A= 25°C

f

= 12 MHz

DCO

T_A= 85°C

V_CC= 3 V

f

= 8 MHz

DCO

2.0

T_A= 25°C

V_CC= 2.2 V

f

= 1 MHz

DCO

0.0

4.0

f

8.0

12.0

16.0

1.5

2.5

3.0

3.5

4.0

− DCO Frequency − MHz

V

CC

− Supply Voltage − V

DCO

Figure 6.

Figure 7.

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Low-Power Mode Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

f_MCLK= 0 MHz,

f_SMCLK= f_DCO= 1 MHz,

f_ACLK= 32,768 Hz,

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0,

SCG1 = 0, OSCOFF = 0

Low-power mode 0

(LPM0) current⁽²⁾

I_LPM0,1MHz

25°C

2.2 V

65

µA

f_MCLK= f_SMCLK= 0 MHz, f_DCO= 1

MHz,

f_ACLK= 32,768 Hz,

Low-power mode 2

(LPM2) current⁽³⁾

I_LPM2

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0,

SCG1 = 1, OSCOFF = 0

25°C

2.2 V

22

29

µA

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLKfrom internal LF oscillator

(VLO),

CPUOFF = 1, SCG0 = 1,

SCG1 = 1, OSCOFF = 0

Low-power mode 3

(LPM3) current⁽³⁾

I_LPM3,VLO

2.2 V

0.5

0.7

µA

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLK= 0 Hz,

CPUOFF = 1, SCG0 = 1,

SCG1 = 1, OSCOFF = 1

25°C

85°C

0.1

0.8

0.5

1.5

Low-power mode 4

(LPM4) current⁽⁴⁾

I_LPM4

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Current for brownout and WDT clocked by SMCLK included.

(3) Current for brownout and WDT clocked by ACLK included.

(4) Current for brownout included.

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Schmitt-Trigger Inputs (Port P1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

0.45 V_CC

1.35

TYP

MAX UNIT

0.75 V_CC

V

V_IT+

Positive-going input threshold voltage

3 V

2.25

0.55 V_CC

1.65

0.25 V_CC

0.75

V_IT-

Negative-going input threshold voltage

Input voltage hysteresis

V

3 V

V_hys

0.3

20

1.0

50

(V_IT+- V_IT-

)

For pullup: V_IN= V_SS

,

R_Pull

C_I

Pullup/pulldown resistor

Input capacitance

35

5

kΩ

For pulldown: V_IN= V_CC

V_IN= V_SSor V_CC

pF

Leakage Current (Port P1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

±50 nA

(1) (2)

I_lkg(Px.y)

High-impedance leakage current

/3 V

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

Outputs (Port P1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

High-level output voltage

Low-level output voltage

TEST CONDITIONS

I_(OHmax)= -6 mA⁽¹⁾

I_(OLmax)= 6 mA⁽¹⁾

V_CC

3 V

MIN

V_CC- 0.6

V_SS

TYP

MAX UNIT

V_OH

V_OL

V_CC

V

V_SS+ 0.6

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

Output Frequency (Port P1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

C_L= 20 pF, R_L= 1 kΩ^{(1) (2)}

C_L= 20 pF⁽²⁾

V_CC

3 V

MIN

TYP

MAX UNIT

12 MHz

16 MHz

Port output frequency

(with load)

f_Px.y

f_Port°CLK

Clock output frequency

(1) A resistive divider with two 0.5-kΩ resistors between V_CCand V_SSis used as load. The output is connected to the center tap of the

divider.

(2) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

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Typical Characteristics – Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

50.0

40.0

30.0

20.0

10.0

0.0

30.0

25.0

20.0

15.0

10.0

5.0

V

CC

= 2.2 V

V

CC

= 3 V

T

A

= 25°C

T

= 25°C

= 85°C

P1.7

A

P1.7

T

A

= 85°C

A

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

OL

− Low-Level Output Voltage − V

V

OL

− Low-Level Output Voltage − V

Figure 8.

Figure 9.

HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0.0

−5.0

0.0

−10.0

−20.0

−30.0

−40.0

−50.0

V

= 2.2 V

V

= 3 V

CC

P1.7

−10.0

−15.0

−20.0

−25.0

T

A

= 85°C

T

= 85°C

A

T

A

= 25°C

0.5

T

= 25°C

0.5

A

0.0

1.0

1.5

2.0

2.5

0.0

1.0

1.5

2.0

2.5

3.0

3.5

V

OH

− High-Level Output Voltage − V

V

OH

− High-Level Output Voltage − V

Figure 10.

Figure 11.

18

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POR/Brownout Reset (BOR)⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

0.7 ×

V_{(B_IT–)}

V_CC(start)

See Figure 12

dV_CC/dt ≤ 3 V/s

V

V_{(B_IT–)}

V_{hys(B_IT–)}

t_d(BOR)

See Figure 12 through Figure 14

See Figure 12

dV_CC/dt ≤ 3 V/s

1.35

140

1

V

mV

µs

See Figure 12

2000

Pulse duration needed at RST/NMI pin to

accept reset internally

t_(reset)

3 V

2

µs

(1) The current consumption of the brownout module is already included in the I_CCcurrent consumption data. The voltage level V_{(B_IT–)}

+

V_{hys(B_IT–)}is ≤ 1.8 V.

V

CC

V

hys(B_IT−)

V

(B_IT−)

V

CC(start)

1

0

t

d(BOR)

Figure 12. POR/Brownout Reset (BOR) vs Supply Voltage

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Typical Characteristics – POR/Brownout Reset (BOR)

V

t

CC

pw

2

3 V

V

= 3 V

Typical Conditions

CC

1.5

1

V

CC(drop)

0.5

0

0.001

1

1000

1 ns

− Pulse Width − µs

t

− Pulse Width − µs

t

pw

Figure 13. V_CC(drop)Level With a Square Voltage Drop to Generate a POR/Brownout Signal

V

t

CC

pw

2

1.5

1

3 V

V

= 3 V

CC

Typical Conditions

V

CC(drop)

0.5

t = t

f

r

0

0.001

1

1000

t

r

f

t

− Pulse Width − µs

t

− Pulse Width − µs

pw

Figure 14. V_CC(drop)Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

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Main DCO Characteristics

•

All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14

overlaps RSELx = 15.

•

DCO control bits DCOx have a step size as defined by parameter S_DCO.

Modulation control bits MODx select how often f_{DCO(RSEL,DCO+1)}is used within the period of 32 DCOCLK

cycles. The frequency f_{DCO(RSEL,DCO)}is used for the remaining cycles. The frequency is an average equal to:

32 × f

× f

DCO(RSEL,DCO+1)

DCO(RSEL,DCO)

f

=

average

MOD × f

+ (32 – MOD) × f

DCO(RSEL,DCO+1)

DCO(RSEL,DCO)

DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

1.8

TYP

MAX UNIT

RSELx < 14

RSELx = 14

RSELx = 15

3.6

V_CC

Supply voltage

2.2

3.6

V

3.0

f_DCO(0,0)

f_DCO(0,3)

f_DCO(1,3)

f_DCO(2,3)

f_DCO(3,3)

f_DCO(4,3)

f_DCO(5,3)

f_DCO(6,3)

f_DCO(7,3)

f_DCO(8,3)

f_DCO(9,3)

f_DCO(10,3)

f_DCO(11,3)

f_DCO(12,3)

f_DCO(13,3)

f_DCO(14,3)

f_DCO(15,3)

f_DCO(15,7)

DCO frequency (0, 0)

DCO frequency (0, 3)

DCO frequency (1, 3)

DCO frequency (2, 3)

DCO frequency (3, 3)

DCO frequency (4, 3)

DCO frequency (5, 3)

DCO frequency (6, 3)

DCO frequency (7, 3)

DCO frequency (8, 3)

DCO frequency (9, 3)

DCO frequency (10, 3)

DCO frequency (11, 3)

DCO frequency (12, 3)

DCO frequency (13, 3)

DCO frequency (14, 3)

DCO frequency (15, 3)

DCO frequency (15, 7)

RSELx = 0, DCOx = 0, MODx = 0

RSELx = 0, DCOx = 3, MODx = 0

RSELx = 1, DCOx = 3, MODx = 0

RSELx = 2, DCOx = 3, MODx = 0

RSELx = 3, DCOx = 3, MODx = 0

RSELx = 4, DCOx = 3, MODx = 0

RSELx = 5, DCOx = 3, MODx = 0

RSELx = 6, DCOx = 3, MODx = 0

RSELx = 7, DCOx = 3, MODx = 0

RSELx = 8, DCOx = 3, MODx = 0

RSELx = 9, DCOx = 3, MODx = 0

RSELx = 10, DCOx = 3, MODx = 0

RSELx = 11, DCOx = 3, MODx = 0

RSELx = 12, DCOx = 3, MODx = 0

RSELx = 13, DCOx = 3, MODx = 0

RSELx = 14, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 3, MODx = 0

RSELx = 15, DCOx = 7, MODx = 0

3 V

0.06

0.14 MHz

MHz

0.12

0.15

0.21

0.30

0.41

0.58

0.80

MHz

0.80

1.50 MHz

MHz

1.6

2.3

MHz

3.4

MHz

4.25

MHz

4.3

8.6

7.30 MHz

MHz

7.8

13.9 MHz

MHz

15.25

21

MHz

Frequency step between

range RSEL and RSEL+1

S_RSEL

S_DCO

S_RSEL= f_{DCO(RSEL+1,DCO)}/f_{DCO(RSEL,DCO)}

S_DCO= f_{DCO(RSEL,DCO+1)}/f_{DCO(RSEL,DCO)}

3 V

1.35

ratio

Frequency step between tap

DCO and DCO+1

3 V

1.08

50

ratio

%

Duty cycle

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Calibrated DCO Frequencies - Tolerance Over Temperature 0°C to 85°C

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX

UNIT

BCSCTL1= CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

calibrated at 30°C and 3 V

1-MHz tolerance over temperature

0°C to 85°C

3 V

-3

±0.5

3

%

BCSCTL1= CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

calibrated at 30°C and 3 V

8-MHz tolerance over temperature

12-MHz tolerance over temperature

16-MHz tolerance over temperature

0°C to 85°C

3 V

-3

±1.0

±2.0

%

BCSCTL1= CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

calibrated at 30°C and 3 V

BCSCTL1= CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

calibrated at 30°C and 3 V

Calibrated DCO Frequencies - Tolerance Over Supply Voltage V_CC

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

BCSCTL1= CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

calibrated at 30°C and 3 V

1-MHz tolerance over V_CC

25°C

1.8 V to 3.6 V

-3

±2

+3

%

BCSCTL1= CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

calibrated at 30°C and 3 V

8-MHz tolerance over V_CC

12-MHz tolerance over V_CC

16-MHz tolerance over V_CC

25°C

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

-3

-6

±2

BCSCTL1= CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

calibrated at 30°C and 3 V

BCSCTL1= CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

calibrated at 30°C and 3 V

Calibrated DCO Frequencies - Overall Tolerance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

BCSCTL1= CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

calibrated at 30°C and 3 V

1-MHz tolerance overall

I: -40°C to 85°C

1.8 V to 3.6 V

-5

±2

+5

+6

%

BCSCTL1= CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

calibrated at 30°C and 3 V

8-MHz tolerance overall

12-MHz tolerance overall

16-MHz tolerance overall

I: -40°C to 85°C

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

-5

-6

±2

±3

BCSCTL1= CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

calibrated at 30°C and 3 V

BCSCTL1= CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

calibrated at 30°C and 3 V

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Wake-Up From Lower-Power Modes (LPM3/4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ

2

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ

2.2 V, 3 V

1.5

1

DCO clock wake-up time

t_DCO,LPM3/4

µs

from LPM3/4⁽¹⁾

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ

3 V

1

CPU wake-up time from

LPM3/4⁽²⁾

1 / f_MCLK

t_Clock,LPM3/4

+

t_CPU,LPM3/4

(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock

edge observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4

DCO WAKE-UP TIME FROM LPM3

vs

DCO FREQUENCY

10.00

RSELx = 0...11

RSELx = 12...15

1.00

0.10

1.00

10.00

DCO Frequency − MHz

Figure 15.

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Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

T_A

V_CC

3 V

MIN

TYP

12

MAX UNIT

20 kHz

%/°C

f_VLO

VLO frequency

-40°C to 85°C

25°C

4

df_VLO/dT

df_VLO/dV_CC

VLO frequency temperature drift⁽¹⁾

VLO frequency supply voltage drift⁽²⁾

3 V

0.5

4

1.8 V to 3.6 V

%/V

(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))

(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)

Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK

f_TA

Timer_A clock frequency

External: TACLK, INCLK

Duty cycle = 50% ± 10%

f_SYSTEM

MHz

ns

t_TA,capTimer_A capture timing

TAx

3 V

20

USI, Universal Serial Interface (MSP430G2230 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

f_USI

USI clock frequency

External: SCLK,

f_SYSTEM

MHz

Duty cycle = 50% ±10%,

SPI slave mode USI module in I²C mode,

I_(OLmax)= 1.5 mA

V_OL,I2Low-level output voltage on SDA

3 V

V_SS

V_SS+ 0.4

V

and SCL

C

Typical Characteristics, USI Low-Level Output Voltage on SDA and SCL (MSP430G2230 Only)

USI LOW-LEVEL OUTPUT VOLTAGE

vs

OUTPUT CURRENT

5.0

4.0

3.0

2.0

1.0

0.0

5.0

4.0

3.0

2.0

1.0

0.0

T

A

= 25°C

= 85°C

V

CC

= 2.2 V

V

CC

= 3 V

T

= 25°C

= 85°C

A

T

A

T

A

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0

V

OL

− Low-Level Output Voltage − V

V

OL

− Low-Level Output V oltage − V

Figure 16.

Figure 17.

24

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Comparator_A+ (MSP430G2210 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

(1)

I_(DD)

CAON = 1, CARSEL = 0, CAREF = 0

3 V

45

µA

I_(Refladder/

RefDiode)

V_(IC)

CAON = 1, CARSEL = 0, CAREF = 1/2/3,

No load at CA0 and CA1

3 V

45

µA

Common–mode input voltage

CAON = 1

0

V_CC-1

V

PCA0 = 1, CARSEL = 1, CAREF = 1,

No load at CA0 and CA1

V_(Ref025)

V_(Ref050)

V_(RefVT)

(Voltage at 0.25 V_CCnode) / V_CC

0.24

0.48

490

PCA0 = 1, CARSEL = 1, CAREF = 2,

No load at CA0 and CA1

(Voltage at 0.5 V_CCnode) / V_CC

See Figure 18 and Figure 19

3 V

PCA0 = 1, CARSEL = 1, CAREF = 3,

No load at CA0 and CA1, TA = 85°C

mV

V_(offset)

V_hys

Offset voltage⁽²⁾

Input hysteresis

3 V

±10

0.7

mV

CAON = 1

T_A= 25°C, Overdrive 10 mV,

Without filter: CAF = 0

120

1.5

ns

µs

Response time

(low-to-high and high-to-low)

t_(response)

3 V

T_A= 25°C, Overdrive 10 mV,

With filter: CAF = 1

(1) The leakage current for the Comparator_A+ terminals is identical to I_lkg(Px.y)specification.

(2) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements. The

two successive measurements are then summed together.

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MSP430G22x0

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Typical Characteristics – Comparator_A+ (MSP430G2210 Only)

650

600

550

500

450

400

650

600

550

500

450

400

V

CC

= 3 V

V

CC

= 2.2 V

Typical

−45 −25

−5

T − Free-Air Temperature − °C

A

15

35

55

75

95

115

−45 −25

−5

15

35

55

75

95

115

T

− Free-Air Temperature − °C

A

Figure 18. V_(RefVT)vs Temperature, V_CC= 3 V

Figure 19. V_(RefVT)vs Temperature, V_CC= 2.2 V

100.00

V

CC

= 1.8V

V

= 2.2V

= 3.0V

CC

V

CC

10.00

V

CC

= 3.6V

1.00

0.0

0.2

0.4

0.6

0.8

1.0

V /V − Normalized Input Voltage − V/V

IN CC

Figure 20. Short Resistance vs V_IN/V_CC

26

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SLAS753D –JANUARY 2012–REVISED AUGUST 2012

10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2230 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_SS= 0 V

T_A

V_CC

3 V

MIN

TYP

MAX UNIT

V_CC

V_Ax

Analog supply voltage

2.2

3.6

V

All Ax terminals, Analog inputs

selected in ADC10AE register

Analog input voltage⁽²⁾

ADC10 supply current⁽³⁾

0

V_CC

V

f_ADC10CLK= 5.0 MHz,

ADC10ON = 1, REFON = 0,

ADC10SHT0 = 1, ADC10SHT1 = 0,

ADC10DIV = 0

I_ADC10

25°C

0.6

mA

f_ADC10CLK= 5.0 MHz,

ADC10ON = 0, REF2_5V = 0,

REFON = 1, REFOUT = 0

0.25

Reference supply current,

reference buffer disabled⁽⁴⁾

I_REF+

3 V

f_ADC10CLK= 5.0 MHz,

ADC10ON = 0, REF2_5V = 1,

REFON = 1, REFOUT = 0

f_ADC10CLK= 5.0 MHz,

Reference buffer supply

ADC10ON = 0, REFON = 1,

I_REFB,0

25°C

3 V

1.1

0.5

mA

current with ADC10SR = 0⁽⁴⁾REF2_5V = 0, REFOUT = 1,

ADC10SR = 0

f_ADC10CLK= 5.0 MHz,

ADC10ON = 0, REFON = 1,

Reference buffer supply

I_REFB,1

current with ADC10SR = 1⁽⁴⁾REF2_5V = 0, REFOUT = 1,

ADC10SR = 1

Only one terminal Ax can be selected

C_I

R_I

Input capacitance

at one time

25°C

3 V

27

pF

Input MUX ON resistance

0 V ≤ V_Ax≤ V_CC

1000

Ω

(1) The leakage current is defined in the leakage current table with Px.y/Ax parameter.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results.

(3) The internal reference supply current is not included in current consumption parameter I_ADC10

.

(4) The internal reference current is supplied by terminal V_CC. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

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MSP430G22x0

SLAS753D –JANUARY 2012–REVISED AUGUST 2012

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10-Bit ADC, Built-In Voltage Reference (MSP430G2230 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

_VREF+≤ 1 mA, REF2_5V = 0

V_CC

MIN

2.2

TYP

MAX UNIT

I

Positive built-in reference

analog supply voltage range

V_CC,REF+

V

_VREF+≤ 1 mA, REF2_5V = 1

2.9

_VREF+≤ I_VREF+max, REF2_5V = 0

_VREF+≤ I_VREF+max, REF2_5V = 1

1.41

2.35

1.5

2.5

1.59

V

Positive built-in reference

voltage

V_REF+

3 V

2.65

Maximum VREF+ load

current

I_LD,VREF+

±1

±2

mA

I_VREF+= 500 µA ± 100 µA,

Analog input voltage V_Ax≈ 0.75 V,

REF2_5V = 0

VREF+ load regulation

3 V

LSB

I_VREF+= 500 µA ± 100 µA,

Analog input voltage V_Ax≈ 1.25 V,

REF2_5V = 1

±2

I_VREF+= 100 µA→900 µA,

V_Ax≈ 0.5 × VREF+,

Error of conversion result ≤ 1 LSB,

V_REF+load regulation

response time

400

ns

ADC10SR = 0

Maximum capacitance at

pin VREF+

C_VREF+

TC_REF+

I

_VREF+≤ ±1 mA, REFON = 1, REFOUT = 1

3 V

100

pF

ppm/

°C

Temperature coefficient⁽¹⁾

I_VREF+= const with 0 mA ≤ I_VREF+≤ 1 mA

±100

Settling time of internal

reference voltage to 99.9%

VREF

I_VREF+= 0.5 mA, REF2_5V = 0,

REFON = 0 → 1

t_REFON

3.6 V

3 V

30

2

µs

I_VREF+= 0.5 mA,

REF2_5V = 1, REFON = 1,

REFBURST = 1, ADC10SR = 0

Settling time of reference

buffer to 99.9% VREF

t_REFBURST

(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))

28

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10-Bit ADC, External Reference (MSP430G2230 Only)⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

VEREF+ > VEREF–,

SREF1 = 1, SREF0 = 0

1.4

V_CC

Positive external reference input

voltage range

VEREF+

V

(2)

VEREF– ≤ VEREF+ ≤ V_CC– 0.15 V,

SREF1 = 1, SREF0 = 1

1.4

0

3

(3)

Negative external reference input

VEREF–

VEREF+ > VEREF–

1.2

V

(4)

voltage range

Differential external reference

input voltage range,

(5)

ΔVEREF

VEREF+ > VEREF–

1.4

V_CC

ΔVEREF = VEREF+ – VEREF–

0 V ≤ VEREF+ ≤ V_CC

SREF1 = 1, SREF0 = 0

,

3 V

±1

I_VEREF+

Static input current into VEREF+

Static input current into VEREF–

µA

0 V ≤ VEREF+ ≤ V_CC– 0.15 V ≤ 3 V,

3 V

0

SREF1 = 1, SREF0 = 1⁽³⁾

I_VEREF–

0 V ≤ VEREF– ≤ V_CC

±1

(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C_I, is also the

dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply

current I_REFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.

(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

10-Bit ADC, Timing Parameters (MSP430G2230 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

0.45

TYP

MAX

6.3

UNIT

ADC10SR = 0

ADC10SR = 1

ADC10 input clock

frequency

For specified performance of

ADC10 linearity parameters

f_ADC10CLK

f_ADC10OSC

3 V

MHz

1.5

ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0,

3 V

3.7

6.3

MHz

µs

frequency

f_ADC10CLK= f_ADC10OSC

ADC10 built-in oscillator, ADC10SSELx = 0,

f_ADC10CLK= f_ADC10OSC

2.06

3.51

t_CONVERT

Conversion time

13 ×

f_ADC10CLKfrom ACLK, MCLK, or SMCLK:

ADC10DIV ×

1/f_ADC10CLK

ADC10SSELx ≠ 0

Turn-on settling time of

the ADC

(1)

t_ADC10ON

100

ns

(1) The condition is that the error in a conversion started after t_ADC10ONis less than ±0.5 LSB. The reference and input signal are already

settled.

10-Bit ADC, Linearity Parameters (MSP430G2230 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Integral linearity error

Differential linearity error

Offset error

TEST CONDITIONS

V_CC

3 V

MIN

TYP

MAX UNIT

±1 LSB

±2 LSB

±5 LSB

E_I

E_D

E_O

E_G

E_T

Source impedance R_S< 100 Ω

Gain error

±1.1

±2

Total unadjusted error

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MSP430G22x0

SLAS753D –JANUARY 2012–REVISED AUGUST 2012

www.ti.com

10-Bit ADC, Temperature Sensor and Built-In V_MID(MSP430G2230 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

3 V

MIN

TYP

60

MAX UNIT

Temperature sensor supply

current⁽¹⁾

REFON = 0, INCHx = 0Ah,

T_A= 25°C

I_SENSOR

TC_SENSOR

t_{Sensor(sample)}

I_VMID

µA

mV/°C

µs

(2)

ADC10ON = 1, INCHx = 0Ah

ADC10ON = 1, INCHx = 0Ah,

Error of conversion result ≤ 1 LSB

3.55

Sample time required if channel

30

(3)

10 is selected

(4)

Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh

µA

ADC10ON = 1, INCHx = 0Bh,

V_CCdivider at channel 11

V_MID

1.5

V

_MID≈ 0.5 × V_CC

Sample time required if channel

11 is selected

ADC10ON = 1, INCHx = 0Bh,

Error of conversion result ≤ 1 LSB

t_VMID(sample)

3 V

1220

ns

(5)

(1) The sensor current I_SENSORis consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is

high). When REFON = 1, I_SENSORis included in I_REF+. When REFON = 0, I_SENSORapplies during conversion of the temperature sensor

input (INCH = 0Ah).

(2) The following formula can be used to calculate the temperature sensor output voltage:

V_Sensor,typ= TC_Sensor(273 + T [°C] ) + V_{Offset,sensor}[mV] or

V_Sensor,typ= TC_SensorT [°C] + V_Sensor(T_A= 0°C) [mV]

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

(4) No additional current is needed. The V_MIDis used during sampling.

.

(5) The on-time t_VMID(on)is included in the sampling time t_VMID(sample); no additional on time is needed.

30

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Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST

CONDITIONS

V_CC

MIN

TYP

MAX UNIT

V_{CC(PGM/ERASE)}Program and erase supply voltage

2.2

3.6

V

f_FTG

Flash timing generator frequency

Supply current from V_CCduring program

Supply current from V_CCduring erase

Cumulative program time⁽¹⁾

257

476 kHz

I_PGM

2.2 V, 3.6 V

1

5

7

mA

I_ERASE

t_CPT

10

ms

t_CMErase

Cumulative mass erase time

20

10⁴

100

ms

Program and erase endurance

Data retention duration

10⁵

cycles

years

t_FTG

t_Retention

t_Word

T_J= 25°C

(2)

Word or byte program time

30

25

(2)

t_{Block, 0}

Block program time for first byte or word

Block program time for each additional byte or

word

t_{Block, 1-63}

18

t_FTG

(2)

t_{Block, End}

t_{Mass Erase}

t_{Seg Erase}

Block program end-sequence wait time

Mass erase time

6

10593

4819

t_FTG

Segment erase time

(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word or byte write and block write modes.

(2) These values are hardwired into the Flash Controller's state machine (t_FTG= 1/f_FTG).

RAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

CPU halted

MIN

MAX UNIT

(1)

V_(RAMh)

RAM retention supply voltage

1.6

V

(1) This parameter defines the minimum supply voltage V_CCwhen the data in RAM remains unchanged. No program execution should

happen during this supply voltage condition.

Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Spy-Bi-Wire input frequency

V_CC

MIN

0

TYP

MAX UNIT

f_SBW

2.2 V, 3 V

20 MHz

t_SBW,Low

Spy-Bi-Wire low clock pulse duration

0.025

15

µs

Spy-Bi-Wire enable time

t_SBW,En

2.2 V, 3 V

1

µs

(TEST high to acceptance of first clock edge⁽¹⁾

)

t_SBW,Ret

R_Internal

Spy-Bi-Wire return to normal operation time

Internal pulldown resistance on TEST

2.2 V, 3 V

15

25

100

90

µs

60

kΩ

(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t_SBW,Entime after pulling the TEST/SBWCLK pin high before

applying the first SBWCLK clock edge.

JTAG Fuse⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Supply voltage during fuse-blow condition

Voltage level on TEST for fuse blow

Supply current into TEST during fuse blow

Time to blow fuse

TEST CONDITIONS

MIN

2.5

6

MAX UNIT

V_CC(FB)

V_FB

T_A= 25°C

V

7

100

1

V

I_FB

mA

ms

t_FB

(1) After the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to

bypass mode.

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MSP430G22x0

SLAS753D –JANUARY 2012–REVISED AUGUST 2012

www.ti.com

APPLICATION INFORMATION

Port (P1.2 and P1.5) Pin Schematics - MSP430G2210

To Comparator

from Comparator

CAPD.y

PxDIR.y

0

1

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

0

1

PxSEL.y

PxOUT.y

0

1

From Module

Bus

Keeper

EN

P1.2/TA0.1/CA2

P1.5/TA0.0/CA5

PxIN.y

EN

To Module

PxIRQ.y

D

PxIE.y

EN

Set

Q

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

Figure 21.

Table 15. Port P1 (P1.2 to P1.5) Pin Functions - MSP430G2210

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P1.x)

x

FUNCTION

P1DIR.x

P1SEL.x

CAPD.y

P1.2/

P1.x (I/O)

TA0.1

I: 0; O: 1

0

1

0

TA0.1/

1

0

2

TA0.CCI1A

CA2

0

1

0

CA2

X

0

1 (y = 2)

P1.5/

TA0.0/

CA5

P1.x (I/O)

TA0.0

I: 0; O: 1

0

5

1

CA5

X

Xx

1 (y = 5)

(1) X = don't care

32

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Port P1 (P1.6 and 1.7) Pin Schematic - MSP430G2210

To Comparator

From Comparator

CAPD.y

PxSEL.y

PxDIR.y

1

0

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

0

1

PxSEL.y

1

PxOUT.y

0

1

From Module

P1.6/TA0.1/CA6

PxIN.y

To Module

PxIRQ.y

PxIE.y

EN

Set

Q

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

Figure 22.

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MSP430G22x0

SLAS753D –JANUARY 2012–REVISED AUGUST 2012

www.ti.com

To Comparator

From Comparator

CAPD.y

PxSEL.y

PxDIR.y

1

0

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

0

1

PxSEL.y

1

PxOUT.y

0

1

From Module

P1.7/CAOUT/CA7

PxIN.y

To Module

PxIRQ.y

PxIE.y

EN

Set

Q

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

Figure 23.

Table 16. Port P1 (P1.6 and P1.7) Pin Functions - MSP430G2210

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P1.x)

P1.6/

x

FUNCTION

P1DIR.x

P1SEL.x

CAPD.y

P1.x (I/O)

I: 0; O: 1

0

1

X

0

X

1

0

TA0.1/

CA6

6

TA0.1

CA6

1

0

X

1 (y = 6)

P1.7/

P1.x (I/O)

CA7

I: 0; O: 1

0

1 (y = 7)

0

CA7/

7

X

1

CAOUT

(1) X = don't care

34

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Port P1 (P1.2 ) Pin Schematics - MSP430G2230

To ADC10

INCHx = y

ADC10AE.y

PxDIR.y

0

1

Direction

0: Input

1: Output

PxREN.y

DV_SS

DV_CC

0

1

PxSEL.y

PxOUT.y

0

1

From Module

Bus

Keeper

EN

P1.2/TA0.1/A2

PxIN.y

EN

To Module

PxIRQ.y

D

PxIE.y

EN

Set

Q

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

Figure 24.

Table 17. Port P1 (P1.2) Pin Functions - MSP430G2230

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME (P1.x)

x

FUNCTION

ADC10AE.x

(INCH.y = 1)

P1DIR.x

P1SEL.x

P1.2/

P1.x (I/O)

TA0.1

I: 0; O: 1

0

1

X

0

TA0.1/

1

0

X

0

2

TA0.CCI1A

A2

1 (y = 2)

(1) X = don't care

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MSP430G22x0

SLAS753D –JANUARY 2012–REVISED AUGUST 2012

www.ti.com

Port P1 (P1.5 ) Pin Schematics - MSP430G2230

To ADC10

INCHx = y

ADC10AE.y

PxDIR.y

0

1

Direction

0: Input

1: Output

USI Module Direction

USIPE5

PxREN.y

PxSEL.y

DV_SS

DV_CC

0

1

PxOUT.y

0

1

From Module

Bus

Keeper

EN

P1.5/TA0.0/SCLK/A5

PxIN.y

EN

To Module

PxIRQ.y

D

PxIE.y

EN

Set

Q

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

Figure 25.

Table 18. Port P1 (P1.5) Pin Functions - MSP430G2230

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME

(P1.x)

x

FUNCTION

ADC10AE.x

(INCH.y = 1)

P1DIR.x

P1SEL.x

USIP.x

INCHx

P1.5/

P1.x (I/O)

I: 0; O: 1

0

1

0

1

X

0

X

5

TA0.0/

SCLK/

A5

TA0.0

SCLK

A5

1

X

0

X

5

X

1 (y = 5)

(1) X = don't care

36

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MSP430G22x0

www.ti.com

SLAS753D –JANUARY 2012–REVISED AUGUST 2012

Port P1 (P1.6 and 1.7) Pin Schematic - MSP430G2230

To ADC10

INCHx

ADC10AE0.y

USIPE6

PxDIR.y

1

0

Direction

0: Input

1: Output

from USI

PxREN.y

PxSEL.y or

USIPE6

DV_SS

DV_CC

0

1

PxOUT.y

0

1

From USI

Bus

Keeper

EN

P1.6/TA0.1/SDO/SCL/A6

PxSEL.y

PxIN.y

To Module

PxIRQ.y

PxIE.y

EN

Set

Q

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

USI in I2C mode: Output driver drives low level only.

Figure 26.

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37

MSP430G22x0

SLAS753D –JANUARY 2012–REVISED AUGUST 2012

www.ti.com

To ADC10

INCHx

ADC10AE0.y

USIPE7

PxDIR.y

1

0

Direction

0: Input

1: Output

from USI

PxSEL.y

PxREN.y

PxSEL.y or

USIPE7

DV_SS

DV_CC

0

1

PxOUT.y

0

1

From USI

Bus

Keeper

EN

P1.7/SDI/SDA/A7

PxSEL.y

PxIN.y

To Module

PxIRQ.y

PxIE.y

EN

Set

Q

PxIFG.y

Interrupt

Edge

Select

PxSEL.y

PxIES.y

USI in I2C mode: Output driver drives low level only.

Figure 27.

Table 19. Port P1 (P1.6 and P1.7) Pin Functions - MSP430G2230

CONTROL BITS AND SIGNALS⁽¹⁾

PIN NAME

(P1.x)

x

FUNCTION

ADC10AE.x

(INCH.y = 1)

P1DIR.x

P1SEL.x

USIP.x

P1.6/

P1.x (I/O)

TA0.CCI1A

TA0.1

I: 0; O: 1

0

1

X

0

1

X

0

1

0

1

0

TA0.1/

0

1

0

6

SDO/

SCL/

A6

SPI Mode

I2C Mode

A6

from USI

0

from USI

0

X

1 (y = 6)

P1.7/

SDI/

SDA/

A7

P1.x (I/O)

SDI

I: 0; O: 1

0

X

0

7

SDA

A7

1 (y = 7)

(1) X = don't care

38

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SLAS753D –JANUARY 2012–REVISED AUGUST 2012

REVISION HISTORY

Literature

Number

Comments

SLAS753

Production Data release

Changed Table 11.

Added Table 12.

SLAS753A

Corrected "Basic Clock Module Configurations" list in Features.

SLAS753B

SLAS753C

Added note to TC_REF+in 10-Bit ADC, Built-In Voltage Reference (MSP430G2230 Only).

Added Flash Memory.

Table 15, Removed ADC10AE.x column and removed A2 and A5 rows (no ADC on this device).

Table 18, Added USIP.x column.

SLAS753D

Table 19, Added "(INCH.y = 1)" to ADC10AE.x column header.

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39

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型号：	MSP430G2210ID
厂家：	TEXAS INSTRUMENTS
描述：	MIXED SIGNAL MICROCONTROLLER 混合信号微控制器微控制器
文件：	总44页 (文件大小：627K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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