MSP430FR5739-EP [TI]
具有 16KB FRAM、1KB SRAM、32 个 IO、10 位 ADC 和比较器的 MSP430FR5739 24MHz ULP 微控制器;
| 型号： | MSP430FR5739-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 16KB FRAM、1KB SRAM、32 个 IO、10 位 ADC 和比较器的 MSP430FR5739 24MHz ULP 微控制器 控制器 微控制器 静态存储器 比较器 |
| 文件： | 总96页 (文件大小：2207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MSP430FR5739-EP
ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
MSP430FR5739-EP 混合信号微控制器
1 器件概述
1.1 特性
1
•
速率高达 10Mbps 的串行外设接口 (SPI)
• 嵌入式微控制器
– eUSCI_B0 支持：
– 时钟频率高达 24MHz 的 16 位精简指令集
(RISC) 架构
– 宽电源电压范围（2V 至 3.6V）
– 工作温度范围 -55°C 至 85°C
•
•
支持多个从器件寻址的 I2C
速率高达 10Mbps 的串行外设接口 (SPI)
– 硬件通用异步收发器 (UART) 引导加载程序
(BSL)
• 经优化超低功率模式
• 电源管理系统
– 激活模式：81.4µA/MHz（典型值）
– 待机（具有 VLO 的 LPM3）：6.3µA（典型值）
– 实时时钟（具有晶振的 LPM3.5）：1.5µA（典型
值）
– 完全集成的低压降稳压器 (LDO)
– 具有复位功能的内核与电源电压监控器
– 常开模式的零功率欠压检测
– 无需外部电压的串行板上程序设计
• 灵活的时钟系统
– 关断 (LPM4.5)：0.32µA（典型值）
• 超低功率铁电 RAM (FRAM)
– 高达 16KB 的非易失性存储器
– 超低功率写入
– 具有 6 个可选出厂校准频率的固定频率数控振荡
器 (DCO)（视器件而定）
– 低功率低频内部时钟源 (VLO)
– 32kHz 晶振 (LFXT)
– 高频晶振 (HFXT)
– 125ns 每个字的快速写入（1ms 内写入 16KB）
– 内置纠错编码 (ECC) 和存储器保护单元 (MPU)
– 通用内存 = 程序 + 数据 + 存储
– 1015 写入周期持耐久性
• 开发工具和软件
– 免费专业开发环境 (
Code Composer Studio ™ IDE)
– 低成本全功能套件
– 抗辐射和非磁性
• 智能数字外设
– 32 位硬件乘法器 (MPY)
– 3 通道内部直接存储器访问 (DMA)
– 具有日历和报警功能的实时时钟 (RTC)
– 5 个具有多达 3 个捕捉/比较寄存器的 16 位定时
器
()
– 完全开发套件(MSP-FET430U40A)
– 目标板 (MSP-TS430RHA40A)
• 系列产品成员
– 在 中汇总的变量和可用封装
– 如需了解完整的模块说明, 请查阅
《MSP430FR57xx 系列用户指南》 (SLAU272)
• 支持国防、航天和医疗应用
– 受控基线
– 16 位循环冗余校验器 (CRC)
• 高性能模拟
– 支持电压基准和可编程滞后的 16 通道模拟比较
器
– 具有内部基准、采样与保持功能的 14 通道、10
位模数转换器
– 同一组装和测试场所
– 同一制造场所
•
在流耗为 100µA 时为 200ksps
– 支持扩展温度范围（-55°C 至 85°C）
（一些注释的参数仅支持 –40°C 至 85°C）
– 延长的产品生命周期
– 延长的产品变更通知
– 产品可追溯性
• 增强型串行通信
– eUSCI_A0 和 eUSCI_A1 支持：
•
支持自动波特率侦测的通用异步收发器
(UART)
•
IrDA 编码和解码
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSCN6
MSP430FR5739-EP
ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
www.ti.com.cn
1.2 应用范围
•
•
家庭自动化
安全性
•
•
传感器管理
数据采集
注意事项
注意事项
这些产品采用 FRAM 非易失性存储器技术。 FRAM 保持对于极端温度环境敏感，例如那些回流焊接或者手工焊接时产
生的温度。 更多信息，请参见 最大绝对额定值。
必须采用与器件级 ESD 规范兼容的系统级 ESD 保护以防止电气过载或者数据或代码内存的干扰。 要获得更多信息，
请参阅应用报告 《MSP430™ 系统级 ESD 注意事项》 (SLAA530)
1.3 说明
德州仪器 (TI) 573MSP430FRx 系列超低功率微控制器包含多个器件，该系列器件具有嵌入式 FRAM 非易失
性存储器，超低功率 16 位 MSP430™ CPU，以及针对多种应用的不同外设。 此架构，FRAM，和外设，与
7 种低功率模式组合在一起，针对在便携式和无线感测应用中实现延长电池寿命进行了优化。 FRAM 是一款
全新的非易失性存储器，此存储器将 SRAM 的速度，灵活性，和耐久性与闪存的稳定性和可靠性结合在一
起，总体能耗更低。 其外设包括：1 个 10 位模数转换器 (ADC)、1 个具有基准电压生成和滞后功能的 16
通道比较器、3 个支持 I2C、SPI 或 UART 协议的增强型串行通道、1 个内部直接存储器访问 (DMA)、1 个
硬件乘法器、1 个实时时钟 (RTC)、5 个 16 位定时器和数字 I/O。
器件信息(1)
封装
器件型号
MSP430FR5739-EP
封装尺寸(2)
VQFN (40)
6.00mm x 6.00mm
(1) 要获得最新的产品、封装和订购信息，请参见 节 9 中的封装选项附录，或者浏览 TI 网站 www.ti.com.cn。
(2) 这里显示的尺寸为近似值。 要获得包含容差值的封装尺寸，请参见节 9中的机械数据。
1.4 功能框图
本节给出了 MSP430FR5739 器件采用 RHA 封装时的功能框图。
PA
PB
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x P3.x P4.x
16 KB
(FR5739)
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3/P4
ACLK
SMCLK
SYS
8 KB
(FR5735)
Clock
System
Power
Management
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1 KB
Boot
ROM
4 KB
(FR5731)
Watchdog
REF
Interrupt
& Wakeup
PA
SVS
FRAM
RAM
MCLK
Memory
Protection
Unit
1×16 I/Os
1×10 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
eUSCI_A0: eUSCI_A1:
UART,
IrDA, SPI
TA0
TA1
TB0
TB1
TB2
ADC10_B
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
10 Bit
200KSPS
Comp_D
RTC_B
MPY32
CRC
eUSCI_B0:
SPI, I2C
(2) Timer_A (3) Timer_B
3 CC
Registers
16 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
3 CC
Registers
14 channels
(12 ext/2 int)
2
器件概述
版权 © 2014, Texas Instruments Incorporated
MSP430FR5739-EP
www.ti.com.cn
ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
内容
1
器件概述.................................................... 1
4.31 REF, External Reference ........................... 30
4.32 REF, Built-In Reference............................. 30
4.33 REF, Temperature Sensor and Built-In VMID ....... 31
4.34 Comparator_D....................................... 32
4.35 FRAM................................................ 32
4.36 JTAG and Spy-Bi-Wire Interface.................... 33
Detailed Description ................................... 34
5.1 Functional Block Diagram........................... 34
5.2 CPU ................................................. 34
5.3 Operating Modes.................................... 34
5.4 Interrupt Vector Addresses.......................... 36
5.5 Memory Organization ............................... 38
5.6 Bootstrap Loader (BSL)............................. 39
5.7 JTAG Operation ..................................... 39
5.8 FRAM ............................................... 40
5.9 Memory Protection Unit (MPU) ..................... 40
5.10 Peripherals .......................................... 40
Input/Output Schematics ............................ 60
1.1 特性 ................................................... 1
1.2 应用范围 .............................................. 2
1.3 说明 ................................................... 2
1.4 功能框图 .............................................. 2
修订历史记录............................................... 4
Pin Configuration and Functions..................... 5
3.1 Pin Diagram .......................................... 5
3.2 Signal Descriptions ................................... 6
Specifications ........................................... 10
4.1 Absolute Maximum Ratings ........................ 10
4.2 Recommended Operating Conditions............... 10
4.3 Thermal Information................................. 10
2
3
5
4
4.4
4.5
4.6
Active Mode Supply Current Into VCC Excluding
External Current..................................... 11
Low-Power Mode Supply Currents (Into VCC
)
Excluding External Current.......................... 13
Schmitt-Trigger Inputs – General Purpose I/O
6
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5, RST/NMI)....................... 14
6.1
6.2
6.3
6.4
6.5
6.6
Port P1, P1.0 to P1.2, Input/Output With Schmitt
Trigger............................................... 60
Port P1, P1.3 to P1.5, Input/Output With Schmitt
Trigger............................................... 62
Port P1, P1.6 to P1.7, Input/Output With Schmitt
Trigger............................................... 64
Port P2, P2.0 to P2.2, Input/Output With Schmitt
Trigger............................................... 65
Port P2, P2.3 to P2.4, Input/Output With Schmitt
Trigger............................................... 66
Port P2, P2.5 to P2.6, Input/Output With Schmitt
Trigger............................................... 68
4.7
4.8
Inputs – Ports P1 and P2
(P1.0 to P1.7, P2.0 to P2.7) ........................ 14
Leakage Current – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5, RST/NMI)....................... 14
Outputs – General Purpose I/O
4.9
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5) ................................. 15
4.10 Output Frequency – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to
P4.1, PJ.0 to PJ.5) ................................. 15
4.11 Typical Characteristics – Outputs................... 16
6.7
6.8
Port P2, P2.7, Input/Output With Schmitt Trigger... 69
Port P3, P3.0 to P3.3, Input/Output With Schmitt
Trigger............................................... 70
Port P3, P3.4 to P3.6, Input/Output With Schmitt
Trigger............................................... 72
4.12 Crystal Oscillator, XT1, Low-Frequency (LF) Mode 18
4.13 Crystal Oscillator, XT1, High-Frequency (HF) Mode
...................................................... 19
4.14 Internal Very-Low-Power Low-Frequency Oscillator
(VLO) ................................................ 20
6.9
6.10 Port P3, P3.7, Input/Output With Schmitt Trigger... 73
6.11 Port P4, P4.0, Input/Output With Schmitt Trigger... 74
6.12 Port P4, P4.1, Input/Output With Schmitt Trigger... 75
4.15 DCO Frequencies ................................... 21
4.16 MODOSC............................................ 21
4.17 PMM, Core Voltage ................................. 22
4.18 PMM, SVS, BOR.................................... 22
4.19 Wake-Up from Low Power Modes .................. 22
4.20 Timer_A ............................................. 23
4.21 Timer_B ............................................. 23
4.22 eUSCI (UART Mode) Recommended Operating
Conditions ........................................... 23
6.13 Port J, J.0 to J.3 JTAG pins TDO, TMS, TCK,
TDI/TCLK, Input/Output With Schmitt Trigger or
Output ............................................... 76
6.14 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt
Trigger............................................... 79
7
8
Device Descriptors (TLV) ............................. 81
器件和文档支持 .......................................... 84
8.1 器件支持............................................. 84
8.2 文档支持............................................. 86
8.3 Community Resources.............................. 87
8.4 商标.................................................. 87
8.5 静电放电警告 ........................................ 87
8.6 术语表 ............................................... 87
机械封装和可订购信息 .................................. 87
9.1 封装信息............................................. 87
4.23 eUSCI (UART Mode)................................ 23
4.24 eUSCI (SPI Master Mode) Recommended
Operating Conditions................................ 24
4.25 eUSCI (SPI Master Mode) .......................... 24
4.26 eUSCI (SPI Slave Mode) ........................... 26
4.27 eUSCI (I2C Mode)................................... 28
4.28 10-Bit ADC, Power Supply and Input Range
9
Conditions ........................................... 29
4.29 10-Bit ADC, Timing Parameters .................... 29
4.30 10-Bit ADC, Linearity Parameters .................. 29
版权 © 2014, Texas Instruments Incorporated
内容
3
MSP430FR5739-EP
ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
www.ti.com.cn
2 修订历史记录
Changes from Original (November 2014) to Revision A
Page
•
器件状态更新为生产数据............................................................................................................. 1
4
修订历史记录
Copyright © 2014, Texas Instruments Incorporated
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MSP430FR5739-EP
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
3 Pin Configuration and Functions
3.1 Pin Diagram
Figure 3-1 shows the pin diagram for the MSP430FR5739-EP device in the 40-pin RHA package.
RHA PACKAGE
(TOP VIEW)
AVSS
PJ.4/XIN
PJ.5/XOUT
AVSS
P2.4/TA1.0/UCA1CLK/A7*/CD11
P2.3/TA0.0/UCA1STE/A6*/CD10
P2.7
DVCC
DVSS
AVCC
1
2
30
29
28
27
26
25
24
23
22
21
P1.0/TA0.1/DMAE0/RTCCLK/A0*/CD0/VeREF-*
P1.1/TA0.2/TA1CLK/CDOUT/A1*/CD1/VeREF+*
P1.2/TA1.1/TA0CLK/CDOUT/A2*/CD2
P3.0/A12*/CD12
VCORE
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
3
4
P3.7/TB2.2
5
P3.1/A13*/CD13
P3.6/TB2.1/TB1CLK
6
P3.2/A14*/CD14
P3.5/TB1.2/CDOUT
7
P3.3/A15*/CD15
P3.4/TB1.1/TB2CLK/SMCLK
P2.2/TB2.2/UCB0CLK/TB1.0
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
8
P1.3/TA1.2/UCB0STE/A3*/CD3
P1.4/TB0.1/UCA0STE/A4*/CD4
P1.5/TB0.2/UCA0CLK/A5*/CD5
9
10
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJ.3/TCK/CD9
P2.6/TB1.0/UCA1RXD/UCA1SOMI
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P4.1
P4.0/TB2.0
* Not available on MSP430FR5739-EP
Note: Exposed thermal pad connection to VSS recommended.
Figure 3-1. 40-Pin RHA Package (Top View)
Copyright © 2014, Texas Instruments Incorporated
Pin Configuration and Functions
5
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3.2 Signal Descriptions
Table 3-1 describes the signals.
Table 3-1. Signal Descriptions
PIN
NAME
(1)
I/O
DESCRIPTION
NO.
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA0 CCR1 capture: CCI1A input, compare: Out1
External DMA trigger
P1.0/TA0.1/DMAE0/
RTCCLK/A0/CD0/VeREF-
1
I/O
RTC clock calibration output
Analog input A0 – ADC (not available on devices without ADC)
Comparator_D input CD0
External applied reference voltage (not available on devices without ADC)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA0 CCR2 capture: CCI2A input, compare: Out2
TA1 input clock
P1.1/TA0.2/TA1CLK/
CDOUT/A1/CD1/VeREF+
2
I/O
Comparator_D output
Analog input A1 – ADC (not available on devices without ADC)
Comparator_D input CD1
Input for an external reference voltage to the ADC (not available on devices without ADC)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA1 CCR1 capture: CCI1A input, compare: Out1
TA0 input clock
P1.2/TA1.1/TA0CLK/ CDOUT/A2/CD2
3
I/O
Comparator_D output
Analog input A2 – ADC (not available on devices without ADC)
Comparator_D input CD2
General-purpose digital I/O with port interrupt and wake up from LPMx.5
Analog input A12 – ADC (not available on devices without ADC)
Comparator_D input CD12
P3.0/A12/CD12
P3.1/A13/CD13
P3.2/A14/CD14
P3.3/A15/CD15
4
5
6
7
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and wake up from LPMx.5
Analog input A13 – ADC
Comparator_D input CD13
General-purpose digital I/O with port interrupt and wake up from LPMx.5
Analog input A14 – ADC (not available on devices without ADC)
Comparator_D input CD14
General-purpose digital I/O with port interrupt and wake up from LPMx.5
Analog input A15 – ADC (not available on devices without ADC)
Comparator_D input CD15
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA1 CCR2 capture: CCI2A input, compare: Out2
Slave transmit enable – eUSCI_B0 SPI mode
P1.3/TA1.2/UCB0STE/ A3/CD3
8
I/O
Analog input A3 – ADC (not available on devices without ADC)
Comparator_D input CD3
(1) I = input, O = output, N/A = not available
Pin Configuration and Functions
6
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
Table 3-1. Signal Descriptions (continued)
PIN
NAME
(1)
I/O
DESCRIPTION
NO.
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB0 CCR1 capture: CCI1A input, compare: Out1
Slave transmit enable – eUSCI_A0 SPI mode
P1.4/TB0.1/UCA0STE/ A4/CD4
9
I/O
Analog input A4 – ADC (not available on devices without ADC)
Comparator_D input CD4
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB0 CCR2 capture: CCI2A input, compare: Out2
Clock
signal
input
–
eUSCI_A0
SPI
slave
mode,
P1.5/TB0.2/UCA0CLK/ A5/CD5
10
I/O
Clock signal output – eUSCI_A0 SPI master mode
Analog input A5 – ADC (not available on devices without ADC)
Comparator_D input CD5
General-purpose digital I/O
Test data output port
(2)
PJ.0/TDO/TB0OUTH/ SMCLK/CD6
11
I/O
Switch all PWM outputs high impedance input – TB0
SMCLK output
Comparator_D input CD6
General-purpose digital I/O
Test data input or test clock input
PJ.1/TDI/TCLK/TB1OUTH/
MCLK/CD7
12
I/O
(2)
Switch all PWM outputs high impedance input – TB1 (not available on devices without TB1)
MCLK output
Comparator_D input CD7
General-purpose digital I/O
Test mode select
(2)
PJ.2/TMS/TB2OUTH/ ACLK/CD8
13
14
I/O
I/O
Switch all PWM outputs high impedance input – TB2 (not available on devices without TB2)
ACLK output
Comparator_D input CD8
General-purpose digital I/O
Test clock
(2)
PJ.3/TCK/CD9
Comparator_D input CD9
General-purpose digital I/O with port interrupt and wake up from LPMx.5
P4.0/TB2.0
P4.1
15
16
I/O
I/O
TB2 CCR0 capture: CCI0B input, compare: Out0 (not available on devices without TB2)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB0 CCR0 capture: CCI0A input, compare: Out0
P2.5/TB0.0/UCA1TXD/ UCA1SIMO
P2.6/TB1.0/UCA1RXD/ UCA1SOMI
17
18
I/O
I/O
Transmit data – eUSCI_A1 UART mode, Slave in, master out – eUSCI_A1 SPI mode (not available
on devices without UCSI_A1)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1)
Receive data – eUSCI_A1 UART mode, Slave out, master in – eUSCI_A1 SPI mode (not available
on devices without UCSI_A1)
(2) See Section 5.7 for use with JTAG function.
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Table 3-1. Signal Descriptions (continued)
PIN
NAME
(1)
I/O
DESCRIPTION
NO.
Test mode pin – enable JTAG pins
Spy-Bi-Wire input clock
(2) (3)
TEST/SBWTCK
19
I
Reset input active low
(2) (3)
RST/NMI/SBWTDIO
20
21
I/O
I/O
Non-maskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB2)
P2.0/TB2.0/UCA0TXD/
UCA0SIMO/TB0CLK/ACLK
Transmit data – eUSCI_A0 UART mode
Slave in, master out – eUSCI_A0 SPI mode
TB0 clock input
(3)
ACLK output
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB2)
Receive data – eUSCI_A0 UART mode
P2.1/TB2.1/UCA0RXD/
UCA0SOMI/TB0.0
22
I/O
(3)
Slave out, master in – eUSCI_A0 SPI mode
TB0 CCR0 capture: CCI0A input, compare: Out0
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB2)
P2.2/TB2.2/UCB0CLK/ TB1.0
23
I/O
Clock
signal
input
–
eUSCI_B0
SPI
slave
mode,
Clock signal output – eUSCI_B0 SPI master mode
TB1 CCR0 capture: CCI0A input, compare: Out0 (not available on devices without TB1)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without TB1)
TB2 clock input (not available on devices without TB2)
SMCLK output
P3.4/TB1.1/TB2CLK/ SMCLK
P3.5/TB1.2/CDOUT
24
25
I/O
I/O
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without TB1)
Comparator_D output
General-purpose digital I/O with port interrupt and wake up from LPMx.5 (not available on package
options PW, RGE)
P3.6/TB2.1/TB1CLK
P3.7/TB2.2
26
27
I/O
I/O
TB2 CCR1 capture: CCI1B input, compare: Out1 (not available on devices without TB2)
TB1 clock input (not available on devices without TB1)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB2 CCR2 capture: CCI2B input, compare: Out2 (not available on devices without TB2)
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR1 capture: CCI1A input, compare: Out1 (not available on devices without TB1)
Slave in, master out – eUSCI_B0 SPI mode
P1.6/TB1.1/UCB0SIMO/
UCB0SDA/TA0.0
28
I/O
I2C data – eUSCI_B0 I2C mode
TA0 CCR0 capture: CCI0A input, compare: Out0
(3) See Section 5.6 and Section 5.7 for use with BSL and JTAG functions.
Pin Configuration and Functions
8
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Table 3-1. Signal Descriptions (continued)
PIN
NAME
(1)
I/O
DESCRIPTION
NO.
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TB1 CCR2 capture: CCI2A input, compare: Out2 (not available on devices without TB1)
Slave out, master in – eUSCI_B0 SPI mode
P1.7/TB1.2/UCB0SOMI/
UCB0SCL/TA1.0
29
I/O
I2C clock – eUSCI_B0 I2C mode
TA1 CCR0 capture: CCI0A input, compare: Out0
Regulated core power supply (internal use only, no external current loading)
Digital ground supply
(4)
VCORE
30
31
32
33
DVSS
DVCC
P2.7
Digital power supply
I/O
I/O
General-purpose digital I/O with port interrupt and wake up from LPMx.5
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA0 CCR0 capture: CCI0B input, compare: Out0
P2.3/TA0.0/UCA1STE/ A6/CD10
34
Slave transmit enable – eUSCI_A1 SPI mode (not available on devices without eUSCI_A1)
Analog input A6 – ADC (not available on devices without ADC)
Comparator_D input CD10
General-purpose digital I/O with port interrupt and wake up from LPMx.5
TA1 CCR0 capture: CCI0B input, compare: Out0
Clock signal input – eUSCI_A1 SPI slave mode, Clock signal output – eUSCI_A1 SPI master mode
(not available on devices without eUSCI_A1)
P2.4/TA1.0/UCA1CLK/ A7/CD11
35
I/O
Analog input A7 – ADC (not available on devices without ADC)
Comparator_D input CD11
Analog ground supply
AVSS
36
37
General-purpose digital I/O
PJ.4/XIN
I/O
I/O
Input terminal for crystal oscillator XT1
General-purpose digital I/O
PJ.5/XOUT
38
Output terminal of crystal oscillator XT1
Analog ground supply
AVSS
39
40
AVCC
Analog power supply
QFN Pad
Pad
QFN package pad. Connection to VSS recommended.
(4) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE
.
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4 Specifications
4.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
MAX
UNIT
V
Voltage applied at VCC to VSS
4.1
VCC + 0.3 V
±2
(2)
Voltage applied to any pin (excluding VCORE)
V
Diode current at any device pin
mA
°C
TJ
Maximum junction temperature
95
Tstg
Storage temperature range(3) (4) (5)
–55
125
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Data retention on FRAM memory cannot be ensured when exceeding the specified maximum storage temperature, Tstg
.
(4) For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
(5) Programming of devices with user application code should only be performed after reflow or hand soldering. Factory programmed
information, such as calibration values, are designed to withstand the temperatures reached in the current JEDEC J-STD-020
specification.
4.2 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN NOM
MAX UNIT
(1)
VCC
VSS
TA
Supply voltage during program execution and FRAM programming (AVCC = DVCC)
Supply voltage (AVSS = DVSS)
2.0
3.6
V
V
0
Operating free-air temperature
–55
–55
470
85
85
°C
°C
nF
TJ
Operating junction temperature
Required capacitor at VCORE(2)
CVCORE
CVCC
CVCORE
/
Capacitor ratio of VCC to VCORE
10
0
No FRAM wait states(4), 2 V ≤ VCC ≤ 3.6 V
8.0
With FRAM wait states(4)
NACCESS = {2},
NPRECHG = {1},
,
Processor frequency (maximum
MCLK frequency)(3)
ƒSYSTEM
MHz
0
24.0
2 V ≤ VCC ≤ 3.6 V
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) A capacitor tolerance of ±20% or better is required.
(3) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(4) When using manual wait state control, see the MSP430FR57xx Family User's Guide (SLAU272) for recommended settings for common
system frequencies.
4.3 Thermal Information
MSP430FR5739-EP
THERMAL METRIC(1)
VQFN
40 PINS
37.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
27.4
12.6
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
12.6
RθJC(bot)
3.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
10
Specifications
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4.4 Active Mode Supply Current Into VCC Excluding External Current
(2) (3)
over recommended operating free-air temperature (unless otherwise noted)(1)
(4)
Frequency (ƒMCLK = ƒSMCLK
8 MHz 16 MHz
TYP MAX TYP MAX
1.0 1.53
)
EXECUTION
MEMORY
PARAMETER
VCC
1 MHz
TYP MAX
0.27
4 MHz
TYP MAX
0.58
20 MHz
TYP MAX
24 MHz
TYP MAX
UNIT
(5)
IAM, FRAM_UNI
FRAM
3 V
3 V
1.9
2.2
mA
FRAM
0% cache hit
ratio
(6)
IAM,0%
0.42
0.31
0.27
0.25
0.75
1.2
0.73
0.58
0.5
1.7
2.2
1.3
2.9
2.3
1.75
1.55
1.3
3.0
2.8
3.7
3.45
4.3
FRAM
50% cache hit
ratio
(6) (7)
IAM,50%
3 V
3 V
3 V
2.1
1.9
1.6
2.5
2.2
1.8
FRAM
66% cache hit
ratio
(6) (7)
IAM,66%
1.0
mA
FRAM
75% cache hit
ratio
(6) (7)
IAM,75%
0.82
FRAM
100% cache hit
ratio
(6) (7)
IAM,100%
3 V
3 V
0.2
0.2
0.44
0.41
0.3
0.56
0.56
0.42
0.55
0.81
0.77
0.73
1.0
1.17
1.27
0.88
1.20
1.32
1.47
1.0
1.53
1.8
(7) (8)
IAM, RAM
RAM
0.35
1.45
mA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Characterized with program executing typical data processing.
(4) At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency,
ƒMCLK,eff, decreases. The effective MCLK frequency is also dependent on the cache hit ratio. SMCLK is not affected by the number of
wait states or the cache hit ratio. The following equation can be used to compute ƒMCLK,eff
:
fMCLK,eff,MHZ= fMCLK,MHZ x 1 / [# of wait states x ((1 - cache hit ratio percent/100)) + 1]
(5) Program and data reside entirely in FRAM. No wait states enabled. DCORSEL = 0, DCOFSELx = 3 (ƒDCO = 8 MHz). MCLK = SMCLK.
(6) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 25% ratio implies one of every
four accesses is from cache, the remaining are FRAM accesses.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (ƒDCO = 8 MHz). MCLK = SMCLK. No wait states enabled.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (ƒDCO = 16 MHz). MCLK = SMCLK. One wait state enabled.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (ƒDCO = 20 MHz). MCLK = SMCLK. Three wait states enabled.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (ƒDCO = 24 MHz). MCLK = SMCLK. Three wait states enabled.
(7) See Figure 4-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Section 4.4.
ƒACLK = 32786 Hz, ƒMCLK = ƒSMCLK at specified frequency. No peripherals active.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
(8) All execution is from RAM.
For 1, 4, and 8 MHz, DCORSEL = 0, DCOFSELx = 3 (ƒDCO = 8 MHz). MCLK = SMCLK.
For 16 MHz, DCORSEL = 1, DCOFSELx = 0 (ƒDCO = 16 MHz). MCLK = SMCLK.
For 20 MHz, DCORSEL = 1, DCOFSELx = 2 (ƒDCO = 20 MHz). MCLK = SMCLK.
For 24 MHz, DCORSEL = 1, DCOFSELx = 3 (ƒDCO = 24 MHz). MCLK = SMCLK.
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Typical Active Mode Supply Current, No Wait States
2.50
2.00
1.50
1.00
0.50
0.00
IAM,0% (mA) = 0.2541 * (f, MHz) + 0.1724
IAM,50% (mA) = 0.1415 * (f, MHz) + 0.1669
IAM,66%(mA) = 0.1043 * (f, MHz) + 0.1646
IAM,75% (mA) = 0.0814 * (f, MHz) + 0.1708
IAM,RAM (mA) = 0.05 * (f, MHz) + 0.150
IAM,100% (mA) = 0.0314 * (f, MHz) + 0.1708
0
1
2
3
4
5
6
7
8
9
fMCLK = fSMCLK, MHz
Figure 4-1. Typical Active Mode Supply Currents, No Wait States
12
Specifications
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4.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1) (2)
–55°C
25°C
85°C
PARAMETER
VCC
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
2 V,
3 V
(3) (4)
(5) (4)
(6) (4)
(7) (8)
ILPM0,1MHz
Low-power mode 0
Low-power mode 0
Low-power mode 0
Low-power mode 2
166
175
225
µA
µA
µA
µA
µA
µA
µA
µA
µA
2 V,
3 V
170
274
56
177
285
61
244
225
340
110
48
360
LPM0,8MHz
2 V,
3 V
340
80
455
210
150
150
150
5.0
LPM0,24MHz
2 V,
3 V
ILPM2
Low-power mode 3, crystal
2 V,
3 V
ILPM3,XT1LF
ILPM3,VLO
ILPM4
3.4
3.3
2.9
1.3
0.3
6.4
15
(9) (8)
mode
Low-power mode 3, VLO mode
2 V,
3 V
6.3
15
48
(10) (8)
2 V,
3 V
(11) (8)
Low-power mode 4
5.9
15
48
2 V,
3 V
(12)
ILPM3.5
Low-power mode 3.5
1.5
2.2
0.66
2.8
0.57
2 V,
3 V
(13)
ILPM4.5
Low-power mode 4.5
0.32
2.55
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), ƒACLK = 32768 Hz, ƒMCLK = 0 MHz, ƒSMCLK = 1 MHz. DCORSEL = 0,
DCOFSELx = 3 (ƒDCO = 8 MHz)
(4) Current for brownout, high-side supervisor (SVSH) and low-side supervisor (SVSL) included.
(5) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), ƒACLK = 32768 Hz, ƒMCLK = 0 MHz, ƒSMCLK = 8 MHz. DCORSEL = 0,
DCOFSELx = 3 (ƒDCO = 8 MHz)
(6) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), ƒACLK = 32768 Hz, ƒMCLK = 0 MHz, ƒSMCLK = 24 MHz. DCORSEL = 1,
DCOFSELx = 3 (ƒDCO = 24 MHz)
(7) Current for watchdog timer (clocked by ACLK) and RTC (clocked by XT1 LF mode) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), ƒACLK = 32768 Hz, ƒMCLK = 0 MHz, ƒSMCLK = ƒDCO = 0 MHz, DCORSEL = 0,
DCOFSELx = 3, DCO bias generator enabled.
(8) Current for brownout, high-side supervisor (SVSH) included. Low-side supervisor disabled (SVSL).
(9) Current for watchdog timer (clocked by ACLK) and RTC (clocked by XT1 LF mode) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), ƒACLK = 32768 Hz, ƒMCLK = ƒSMCLK = ƒDCO = 0 MHz
(10) Current for watchdog timer (clocked by ACLK) included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), ƒACLK = ƒVLO, ƒMCLK = ƒSMCLK = ƒDCO = 0 MHz
(11) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), ƒDCO = ƒACLK = ƒMCLK = ƒSMCLK = 0 MHz
(12) Internal regulator disabled. No data retention. RTC active clocked by XT1 LF mode.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM3.5), ƒDCO = ƒACLK = ƒMCLK = ƒSMCLK = 0 MHz
(13) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), ƒDCO = ƒACLK = ƒMCLK = ƒSMCLK = 0 MHz
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4.6 Schmitt-Trigger Inputs – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
MIN
0.7
TYP
MAX UNIT
1.7
V
VIT+
VIT–
Vhys
Positive-going input threshold voltage
1.45
0.41
0.72
0.24
0.27
2.12
1.101
V
Negative-going input threshold voltage
1.68
0.855
V
Input voltage hysteresis (VIT+ – VIT–
)
1.02
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI
Pullup or pulldown resistor
Input capacitance
19
35
5
51
kΩ
VIN = VSS or VCC
pF
(1)
4.7 Inputs – Ports P1 and P2
(P1.0 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
(2)
t(int)
External interrupt timing
External trigger pulse duration to set interrupt flag
2 V, 3 V
20
ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
4.8 Leakage Current – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1) (2)
VCC
MIN
MAX UNIT
65 nA
Ilkg(Px.x)
High-impedance leakage current
2 V, 3 V
–65
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
14
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4.9 Outputs – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
(1)
I(OHmax) = –1 mA
VCC
2 V
(2)
(1)
(2)
I(OHmax) = –3 mA
I(OHmax) = –2 mA
I(OHmax) = –6 mA
VCC
VOH
High-level output voltage
V
VCC
3 V
2 V
3 V
VCC
(1)
I(OLmax) = 1 mA
I(OLmax) = 3 mA
I(OLmax) = 2 mA
I(OLmax) = 6 mA
VSS VSS + 0.25
(2)
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1)
(2)
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
4.10 Output Frequency – General Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.1, PJ.0 to PJ.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
MIN
MAX UNIT
16
Port output frequency
(with load)
(1) (2)
ƒPx.y
Px.y
MHz
24
16
ACLK, SMCLK, or MCLK at configured output port,
ƒPort_CLK
Clock output frequency
MHz
24
(2)
CL = 20 pF, no DC loading
(1) A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
CL = 20 pF is connected from the output to VSS
.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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4.11 Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
16
TA = -40 °C
14
TA = 25 °C
12
TA = 85 °C
10
8
6
4
2
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
VOL Low-Level Output Voltage - V
VCC = 2.0 V
Measured at Px.y
Figure 4-2. Typical Low-Level Output Current vs Low-Level Output Voltage
35
30
25
20
15
10
5
TA = -40 °C
TA = 25 °C
TA = 85 °C
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
VOL Low-Level Output Voltage - V
VCC = 3.0 V
Measured at Px.y
Figure 4-3. Typical Low-Level Output Current vs Low-Level Output Voltage
16
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0
-2
-4
-6
-8
-10
-12
-14
-16
TA = 85 °C
TA = 25 °C
TA = -40 °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
VOH High-Level Output Voltage - V
VCC = 2.0 V
Measured at Px.y
Figure 4-4. Typical High-Level Output Current vs High-Level Output Voltage
0
-5
-10
-15
-20
-25
-30
-35
-40
TA = 85 °C
TA = 25 °C
TA = -40 °C
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
VOH High-Level Output Voltage - V
VCC = 3.0 V
Measured at Px.y
Figure 4-5. Typical High-Level Output Current vs High-Level Output Voltage
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4.12 Crystal Oscillator, XT1, Low-Frequency (LF) Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
ƒOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {1},
CL,eff = 9 pF, TA = 25°C,
3 V
60
Additional current consumption
XT1 LF mode from lowest drive
setting
ƒOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {2},
TA = 25°C, CL,eff = 9 pF
ΔIVCC.LF
3 V
3 V
90
nA
ƒOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 12 pF
140
XT1 oscillator crystal frequency,
LF mode
ƒXT1,LF0
XTS = 0, XT1BYPASS = 0
32768
Hz
XT1 oscillator logic-level square-
wave input frequency, LF mode
(3) (4)
ƒXT1,LF,SW
XTS = 0, XT1BYPASS = 1
10 32.768
210
50 kHz
XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
ƒXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
OALF
kΩ
(5)
LF crystals
XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
ƒXT1,LF = 32768 Hz, CL,eff = 12 pF
300
XTS = 0, Measured at ACLK,
ƒXT1,LF = 32768 Hz
Duty cycle, LF mode
30
10
70
%
Oscillator fault frequency, LF mode
(7)
ƒFault,LF
tSTART,LF
CL,eff
XTS = 0
10000
Hz
(6)
ƒOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 6 pF
1000
(8)
Startup time, LF mode
3 V
ms
pF
ƒOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 12 pF
1000
1
Integrated effective load
XTS = 0
(9) (10)
capacitance, LF mode
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) –40°C to 85°C
(3) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
(4) Maximum frequency of operation of the entire device cannot be exceeded.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVE
settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but
should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For XT1DRIVE = {0}, CL,eff ≤ 6 pF.
For XT1DRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
For XT1DRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
For XT1DRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
(6) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(7) Measured with logic-level input frequency but also applies to operation with crystals.
(8) Includes startup counter of 4096 clock cycles.
(9) Requires external capacitors at both terminals.
(10) Values are specified by crystal manufacturers. Include parasitic bond and package capacitance (approximately 2 pF per pin).
Recommended values supported are 6 pF, 9 pF, and 12 pF. Maximum shunt capacitance of 1.6 pF.
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4.13 Crystal Oscillator, XT1, High-Frequency (HF) Mode(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
ƒOSC = 4 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 16 pF
175
ƒOSC = 8 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {1},
TA = 25°C, CL,eff = 16 pF
300
350
550
XT1 oscillator crystal current HF
mode
IVCC,HF
3 V
µA
ƒOSC = 16 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {2},
TA = 25°C, CL,eff = 16 pF
ƒOSC = 24 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 16 pF
XT1 oscillator crystal frequency,
HF mode 0
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0}
ƒXT1,HF0
ƒXT1,HF1
ƒXT1,HF2
ƒXT1,HF3
ƒXT1,HF,SW
4
6
6
MHz
(3)
(3)
(3)
(3)
XT1 oscillator crystal frequency,
HF mode 1
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {1}
10 MHz
16 MHz
24 MHz
24 MHz
XT1 oscillator crystal frequency,
HF mode 2
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {2}
10
16
1
XT1 oscillator crystal frequency,
HF mode 3
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3}
XT1 oscillator logic-level square-
wave input frequency, HF mode
XTS = 1,
XT1BYPASS = 1
(4) (3)
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0},
ƒXT1,HF = 4 MHz, CL,eff = 16 pF
450
320
200
200
8
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {1},
ƒXT1,HF = 8 MHz, CL,eff = 16 pF
Oscillation allowance for
HF crystals
OAHF
Ω
(5)
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {2},
ƒXT1,HF = 16 MHz, CL,eff = 16 pF
XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3},
ƒXT1,HF = 24 MHz, CL,eff = 16 pF
ƒOSC = 4 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {0},
TA = 25°C, CL,eff = 16 pF
(6)
tSTART,HF
Startup time, HF mode
3 V
ms
ƒOSC = 24 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVE = {3},
TA = 25°C, CL,eff = 16 pF
2
(1) To improve EMI on the XT1 oscillator the following guidelines should be observed.
•
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) –40°C to 85°C
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes startup counter of 4096 clock cycles.
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Crystal Oscillator, XT1, High-Frequency (HF) Mode(1) (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Integrated effective load
capacitance
CL,eff
XTS = 1
1
pF
(7) (8)
XTS = 1, Measured at ACLK,
ƒXT1,HF2 = 24 MHz
Duty cycle, HF mode
40
50
60
%
Oscillator fault frequency, HF mode
(10)
ƒFault,HF
XTS = 1
145
900 kHz
(9)
(7) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
(8) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are 14
pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.
(9) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
4.14 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
TEST CONDITIONS
VCC
MIN
TYP
8.3
MAX UNIT
13.3 kHz
%/°C
ƒVLO
Measured at ACLK
2 V to 3.6 V
2 V to 3.6 V
4.3
(1)
(2)
dƒVLO/dT
VLO frequency temperature drift
VLO frequency supply voltage drift
Duty cycle
Measured at ACLK
Measured at ACLK
Measured at ACLK
0.5
dƒVLO/dVC
C
2 V to 3.6 V
2 V to 3.6 V
4
%/V
65%
ƒVLO,DC
35%
50%
(1) Calculated using the box method: (MAX(–55 to 85°C) – MIN(–55 to 85°C)) / MIN(–55 to 85°C) / (85°C – (–55°C))
(2) Calculated using the box method: (MAX(2.0 to 3.6 V) – MIN(2.0 to 3.6 V)) / MIN(2.0 to 3.6 V) / (3.6 V – 2 V)
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4.15 DCO Frequencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
TA
PARAMETER
TEST CONDITIONS
MIN
TYP
5.37
16.2
6.67
20
MAX UNIT
±5% MHz
±5% MHz
±5% MHz
±5% MHz
±5% MHz
±5% MHz
Measured at ACLK,
DCORSEL = 0
2 V to 3.6 V
–55°C to 85°C
ƒDCO,LO
DCO frequency low, trimmed
Measured at ACLK,
DCORSEL = 1
2 V to 3.6 V
–55°C to 85°C
Measured at ACLK,
DCORSEL = 0
2 V to 3.6 V
–55°C to 85°C
ƒDCO,MID
DCO frequency mid, trimmed
Measured at ACLK,
DCORSEL = 1
2 V to 3.6 V
–55°C to 85°C
Measured at ACLK,
DCORSEL = 0
2 V to 3.6 V
–55°C to 85°C
8
ƒDCO,HI
DCO frequency high, trimmed
Duty cycle
Measured at ACLK,
DCORSEL = 1
2 V to 3.6 V
–55°C to 85°C
23.8
Measured at ACLK, divide by 1,
No external divide, all DCO
settings
2 V to 3.6 V
–55°C to 85°C
ƒDCO,DC
35%
50%
65%
4.16 MODOSC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Current consumption
MODOSC frequency
Duty cycle
TEST CONDITIONS
VCC
MIN
TYP
44
MAX UNIT
µA
IMODOSC
Enabled
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
ƒMODOSC
ƒMODOSC,DC
4.2
5.0
5.7 MHz
65%
Measured at ACLK, divide by 1
35%
50%
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4.17 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2 V ≤ DVCC ≤ 3.6 V
2 V ≤ DVCC ≤ 3.6 V
MIN
TYP
1.5
MAX UNIT
VCORE(AM)
Core voltage, active mode
Core voltage, low-current mode
V
V
VCORE(LPM)
1.5
4.18 PMM, SVS, BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 3.6 V
MIN
TYP
MAX UNIT
ISVSH,AM
ISVSH,LPM
VSVSH-
SVSH current consumption, active mode
SVSH current consumption, low power modes
SVSH on voltage level, falling supply voltage
SVSH off voltage level, rising supply voltage
SVSH propagation delay, active mode
SVSH propagation delay, low power modes
SVSL current consumption
5
0.8
µA
µA
VCC = 3.6 V
1.81
1.85
1.88
1.93
10
1.95
2
V
V
VSVSH+
tPD,SVSH, AM
tPD,SVSH, LPM
ISVSL
dVCC/dt = 10 mV/µs
dVCC/dt = 1 mV/µs
µs
µs
µA
V
30
0.3
VSVSL–
SVSL on voltage level
1.42
1.47
VSVSL+
SVSL off voltage level
V
4.19 Wake-Up from Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC
TA
PARAMETER
TEST CONDITIONS
MIN
TYP
0.58
12
MAX UNIT
Wake-up time from LPM0 to active
2 V, 3 V
–55°C to 85°C
tWAKE-UP LPM0
tWAKE-UP LPM12
tWAKE-UP LPM34
1.1
25
µs
µs
µs
µs
µs
µs
ms
ns
(1)
mode
Wake-up time from LPM1, LPM2 to
2 V, 3 V
–55°C to 85°C
(1)
active mode
Wake-up time from LPM3 or LPM4 to
2 V, 3 V
–55°C to 85°C
78
165
575
1100
(1)
active mode
2 V, 3 V
0°C to 85°C
310
310
230
1.6
Wake-up time from LPM3.5 or
LPM4.5 to active mode
tWAKE-UP LPMx.5
(1)
2 V, 3 V
–55°C to 85°C
Wake-up time from RST to active
2 V, 3 V
–55°C to 85°C
tWAKE-UP RESET
tWAKE-UP BOR
tRESET
VCC stable
(2)
mode
Wake-up time from BOR or power-up
to active mode
2 V, 3 V
–55°C to 85°C
dVCC/dt = 2400 V/s
Pulse duration required at RST/NMI
terminal to accept a reset event(3)
2 V, 3 V
–55°C to 85°C
4
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
(2) The wake-up time is measured from the rising edge of the RST signal until the first instruction of the user program is executed.
(3) Meeting or exceeding this time makes sures a reset event occurs. Pulses shorter than this minimum time may or may not cause a reset
event to occur.
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4.20 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
ƒTA
Timer_A input clock frequency
External: TACLK
2 V, 3 V
24 MHz
Duty cycle = 50% ± 10%
All capture inputs, Minimum pulse
duration required for capture
tTA,cap
Timer_A capture timing
2 V, 3 V
20
ns
4.21 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
ƒTB
Timer_B input clock frequency
External: TBCLK
2 V, 3 V
24 MHz
Duty cycle = 50% ± 10%
All capture inputs, Minimum pulse
duration required for capture
tTB,cap
Timer_B capture timing
2 V, 3 V
20
ns
4.22 eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
ƒeUSCI
eUSCI input clock frequency
ƒSYSTEM MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
(equals baud rate in MBaud)
ƒBITCLK
5
MHz
4.23 eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
MIN
5
TYP
15
MAX UNIT
20
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
20
35
50
45
60
ns
tt
UART receive deglitch time(1)
2 V, 3 V
80
120
110
180
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
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4.24 eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
ƒeUSCI eUSCI input clock frequency
ƒSYSTEM MHz
4.25 eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
1
UCxCLK
cycles
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
STE lead time, STE active to clock
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
1
1
1
UCSTEM = 0,
UCMODEx = 01 or 10
STE lag time, Last clock to STE
inactive
UCxCLK
cycles
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
UCMODEx = 01 or 10
55
35
40
30
STE access time, STE active to SIMO
data out
ns
ns
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
UCMODEx = 01 or 10
STE disable time, STE inactive to
SIMO high impedance
UCSTEM = 1,
UCMODEx = 01 or 10
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
35
35
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
ns
ns
ns
ns
tHD,MI
0
30
30
UCLK edge to SIMO valid,
CL = 20 pF
(2)
tVALID,MO
SIMO output data valid time
0
0
(3)
tHD,MO
SIMO output data hold time
CL = 20 pF
(1) ƒUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 4-6 and Figure 4-7.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 4-
6 and Figure 4-7.
24
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UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tSTE,ACC
tVALID,MO
tSTE,DIS
Figure 4-6. SPI Master Mode, CKPH = 0
UCMODEx = 01
STE
tSTE,LEAD
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tSTE,ACC
tVALID,MO
tSTE,DIS
Figure 4-7. SPI Master Mode, CKPH = 1
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4.26 eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN
7
TYP
MAX UNIT
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE active to clock
ns
7
0
STE lag time, Last clock to STE inactive
ns
0
65
ns
40
STE access time, STE active to SOMI data out
40
ns
35
STE disable time, STE inactive to SOMI high
impedance
2
2
5
5
SIMO input data setup time
SIMO input data hold time
ns
ns
tHD,SI
30
ns
30
UCLK edge to SOMI valid,
CL = 20 pF
(2)
tVALID,SO
SOMI output data valid time
4
4
(3)
tHD,SO
SOMI output data hold time
CL = 20 pF
ns
(1) ƒUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 4-8 and Figure 4-9.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 4-8
and Figure 4-9.
26
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UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SIMO
tHD,SIMO
tLOW/HIGH
tLOW/HIGH
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
Figure 4-8. SPI Slave Mode, CKPH = 0
UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 4-9. SPI Slave Mode, CKPH = 1
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4.27 eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4-10)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
ƒeUSCI
eUSCI input clock frequency
ƒSYSTEM MHz
Duty cycle = 50% ±10%
ƒSCL
SCL clock frequency
2 V, 3 V
2 V, 3 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
ƒSCL = 100 kHz
ƒSCL > 100 kHz
ƒSCL = 100 kHz
ƒSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2 V, 3 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2 V, 3 V
2 V, 3 V
ns
ns
250
4.0
0.6
50
ƒSCL = 100 kHz
ƒSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
tSU,STO
Setup time for STOP
2 V, 3 V
µs
600
300
150
75
ns
ns
25
Pulse duration of spikes suppressed by
input filter
tSP
2 V, 3 V
12.5
6.25
ns
ns
27
30
33
ms
ms
ms
tTIMEOUT
Clock low timeout
2 V, 3 V
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 4-10. I2C Mode Timing
28
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4.28 10-Bit ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.0
0
TYP
MAX UNIT
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
Analog supply voltage
Analog input voltage range
3.6
V
V
V(Ax)
All ADC10 pins
AVCC
150
Operating supply current into ƒADC10CLK = 5 MHz, ADC10ON = 1,
AVCC terminal, reference
current not included
2 V
3 V
90
IADC10_A
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0
µA
100
170
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad
CI
RI
Input capacitance
2.2 V
6
pF
Input MUX ON resistance
AVCC ≥ 2 V, 0 V ≤ VAx ≤ AVCC
36
kΩ
4.29 10-Bit ADC, Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC10 linearity
parameters
2 V to
3.6 V
ƒADC10CLK
ƒADC10OSC
0.45
5
5.5 MHz
Internal ADC10 oscillator
(MODOSC)
2 V to
3.6 V
ADC10DIV = 0, ƒADC10CLK = ƒADC10OSC
4.2
4.5
5.7 MHz
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode,
ƒADC10OSC = 4.5 MHz to 5.5 MHz
2 V to
3.6 V
2.18
2.67
µs
tCONVERT
Conversion time
External ƒADC10CLK from ACLK, MCLK, or SMCLK,
ADC10SSEL ≠ 0
2 V to
3.6 V
(1)
The error in a conversion started after tADC10ON is
less than ±0.5 LSB,
Reference and input signal already settled
Turn on settling time of
the ADC
tADC10ON
100
ns
µs
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,
Approximately eight Tau (τ) are required to get an
error of less than ±0.5 LSB
2 V
3 V
1.5
2.0
tSample
Sampling time
(1) 12 × ADC10DIV × 1/ƒADC10CLK
4.30 10-Bit ADC, Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
VCC
MIN
–1.4
–1.3
TYP
MAX UNIT
1.4
Integral
linearity error
EI
3.6 V
LSB
1.3
Differential
linearity error
ED
EO
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
)
)
)
3.6 V
3.6 V
3.6 V
–1.2
1.2 LSB
mV
Offset error
±2.5
Gain error, external
reference
–1.4
1.4 LSB
EG
Gain error, internal
±4
(1)
reference
Total unadjusted
error, external
reference
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–
)
3.6 V
±2.3
LSB
ET
Total unadjusted
error, internal
±4
(1)
reference
(1) Error is dominated by the internal reference.
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MAX UNIT
4.31 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.4
0
TYP
(2)
VeREF+
VeREF–
(VeREF+
Positive external reference voltage input
Negative external reference voltage input
VeREF+ > VeREF–
AVCC
1.2
V
V
(3)
(4)
VeREF+ > VeREF–
–
Differential external reference voltage input
VeREF+ > VeREF–
1.4
AVCC
V
VREF–/VeREF–
)
1.4 V ≤ VeREF+ ≤ VAVCC
VeREF– = 0 V,
,
ƒADC10CLK = 5 MHz,
ADC10SHTx = 1h,
Conversion rate 200 ksps
2.2 V, 3 V
2.2 V, 3 V
±6
µA
IVeREF+
IVeREF–
,
Static input current
1.4 V ≤ VeREF+ ≤ VAVCC
VeREF– = 0 V,
ƒADC10CLK = 5 MHz,
ADC10SHTx = 8h,
,
±1
10
µA
µF
Conversion rate 20 ksps
CVREF+
CVREF-
,
Capacitance at VREF+ or VREF- terminal(5)
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_B. Also see the MSP430FR57xx Family User's Guide (SLAU272).
4.32 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2 V, REFON = 1
REFVSEL = {0} for 1.5 V, REFON = 1
REFVSEL = {0} for 1.5 V
VCC
3 V
3 V
3 V
MIN
2.39
1.91
1.43
2.0
TYP
2.5
2.0
1.5
MAX UNIT
2.61
Positive built-in reference
voltage output
VREF+
2.09
1.57
V
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
REFVSEL = {1} for 2 V
2.2
V
REFVSEL = {2} for 2.5 V
2.7
Operating supply current into ƒADC10CLK = 5 MHz,
IREF+
3 V
33
µA
(1)
AVCC terminal
REFON = 1, REFBURST = 0
Temperature coefficient of
built-in reference
ppm/
°C
TREF+
REFVSEL = (0, 1, 2}, REFON = 1
±35
AVCC = AVCC (min) - AVCC(max)
TA = 25°C, REFON = 1,
REFVSEL = (0} for 1.5 V
,
,
,
,
1600
1900
AVCC = AVCC (min) - AVCC(max)
TA = 25°C, REFON = 1,
REFVSEL = (1} for 2 V
Power supply rejection ratio
(DC)
PSRR_DC
µV/V
AVCC = AVCC (min) - AVCC(max)
TA = 25°C, REFON = 1,
REFVSEL = (2} for 2.5 V
3600
30
Settling time of reference
voltage
AVCC = AVCC (min) - AVCC(max)
REFVSEL = (0, 1, 2}, REFON = 0 → 1
tSETTLE
µs
(2)
(1) The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
(2) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
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4.33 REF, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
790
MAX UNIT
mV
ADC10ON = 1, INCH = 0Ah,
TA = 0°C
(1)
VSENSOR
See
2 V, 3 V
TCSENSOR
ADC10ON = 1, INCH = 0Ah
2 V, 3 V
2 V
2.55
mV/°C
30
30
Sample time required if
channel 10 is selected
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
tSENSOR(sample)
µs
(2)
3 V
2 V
0.96
1.43
1.0
1.5
1.04
V
ADC10ON = 1, INCH = 0Bh,
VMID is ~0.5 × VAVCC
VMID
AVCC divider at channel 11
Sample time required if
3 V
1.57
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
tVMID(sample)
2 V, 3 V
1000
ns
(3)
channel 11 is selected
(1) The temperature sensor offset can vary significantly. A single-point calibration is recommended to minimize the offset error of the built-in
temperature sensor.
(2) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
.
(3) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
1050
1000
950
900
850
800
750
700
650
600
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Ambient Temperature - Degrees Celsius
Figure 4-11. Typical Temperature Sensor Voltage
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MAX UNIT
4.34 Comparator_D
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Overdrive = 10 mV,
VIN- = (VIN+ – 400 mV) to (VIN+ + 10 mV)
49
100
202
ns
ns
ns
Propagation delay,
AVCC = 2 V to 3.6 V
Overdrive = 100 mV,
VIN- = (VIN+ – 400 mV) to (VIN+ + 100 mV)
tpd
80
50
Overdrive = 250 mV,
(VIN+ – 400 mV) to (VIN+ + 250 mV)
CDF = 1, CDFDLY = 00
CDF = 1, CDFDLY = 01
CDF = 1, CDFDLY = 10
CDF = 1, CDFDLY = 11
AVCC = 2 V to 3.6 V
0.28
0.49
0.85
1.59
–26
0.5
0.9
1.6
3.0
1.1
1.8
µs
µs
Filter timer added to the
propagation delay of the
comparator
tfilter
3.31
6.5
µs
µs
Voffset
Input offset
26
mV
Common mode input
range
Vic
AVCC = 2 V to 3.6 V
0
AVCC – 1
V
Icomp(AVCC)
Iref(AVCC)
Comparator only
CDON = 1, AVCC = 2 V to 3.6 V
CDREFLx = 01, AVCC = 2 V to 3.6 V
28
20
µA
µA
Reference buffer and R-
ladder
CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V
tenable,comp
Comparator enable time
1.1
2.3
µs
µs
Resistor ladder enable
time
CDON = 0 to CDON = 1,
AVCC = 2 V to 3.6 V
tenable,rladder
1.1
2.3
VIN ×
(n + 0.49)
/ 32
VIN ×
(n + 1) (n + 1.51)
/ 32 / 32
VIN ×
Reference voltage for a
tap
VIN = voltage input to the R-ladder,
n = 0 to 31
VCB_REF
V
4.35 FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Write supply voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
DVCC(WRITE)
tWRITE
2.0
3.6
120
60
V
ns
Word or byte write time
(1)
tACCESS
Read access time
ns
(1)
tPRECHARGE
tCYCLE
Precharge time
60
ns
(1)
Cycle time, read or write operation
Read and write endurance
120
1015
100
40
ns
cycles
TJ = 25°C
TJ = 70°C
TJ = 85°C
tRetention
Data retention duration
years
10
(1) When using manual wait state control, see the MSP430FR57xx Family User's Guide (SLAU272) for recommended settings for common
system frequencies.
32
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4.36 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Spy-Bi-Wire input frequency
VCC
MIN
0
TYP
MAX UNIT
ƒSBW
2 V, 3 V
2 V, 3 V
2 V, 3 V
20 MHz
tSBW,Low
tSBW, En
tSBW,Rst
Spy-Bi-Wire low clock pulse duration
0.025
15
1
µs
µs
(1)
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
Spy-Bi-Wire return to normal operation time
18
0
37
5
µs
2 V
3 V
MHz
(2)
ƒTCK
TCK input frequency, 4-wire JTAG
0
10 MHz
51.5 kΩ
Rinternal
Internal pulldown resistance on TEST
2 V, 3 V
19
35
(1) Tools accessing the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) ƒTCK may be restricted to meet the timing requirements of the module selected.
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5 Detailed Description
5.1 Functional Block Diagram
This section shows the functional block diagram for the MSP430FR5739-EP in the RHA package.
PA
PB
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x P3.x P4.x
16 KB
(FR5739)
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3/P4
ACLK
SMCLK
SYS
8 KB
(FR5735)
Clock
System
Power
Management
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1 KB
Boot
ROM
4 KB
(FR5731)
Watchdog
REF
Interrupt
& Wakeup
PA
SVS
FRAM
RAM
MCLK
Memory
Protection
Unit
1×16 I/Os
1×10 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
eUSCI_A0: eUSCI_A1:
UART,
IrDA, SPI
TA0
TA1
TB0
TB1
TB2
ADC10_B
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
10 Bit
200KSPS
Comp_D
RTC_B
MPY32
CRC
eUSCI_B0:
SPI, I2C
(2) Timer_A (3) Timer_B
3 CC
Registers
16 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
3 CC
Registers
14 channels
(12 ext/2 int)
5.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
5.3 Operating Modes
The MSP430 has one active mode and seven software-selectable low-power modes of operation. An
interrupt event can wake up the device from low-power modes LPM0 through LPM4, service the request,
and restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5
and LPM4.5 disable the core supply to minimize power consumption.
The following eight operating modes can be configured by software:
34
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•
•
Active mode (AM)
All clocks are active
Low-power mode 0 (LPM0)
•
Low-power mode 3 (LPM3)
–
–
–
–
–
–
CPU is disabled
ACLK active
MCLK and SMCLK disabled
DCO disabled
–
–
–
–
–
CPU is disabled
ACLK active
Complete data retention
MCLK disabled
SMCLK optionally active
Complete data retention
•
•
Low-power mode 4 (LPM4)
–
–
–
CPU is disabled
ACLK, MCLK, SMCLK disabled
Complete data retention
•
•
Low-power mode 1 (LPM1)
–
–
–
–
–
–
CPU is disabled
ACLK active
Low-power mode 3.5 (LPM3.5)
MCLK disabled
–
–
–
–
–
RTC operation
SMCLK optionally active
DCO disabled
Internal regulator disabled
No data retention
Complete data retention
I/O pad state retention
Wakeup from RST, general-purpose
I/O, RTC events
Low-power mode 2 (LPM2)
–
–
–
–
–
–
CPU is disabled
•
Low-power mode 4.5 (LPM4.5)
ACLK active
–
–
–
–
Internal regulator disabled
No data retention
MCLK disabled
SMCLK optionally active
DCO disabled
I/O pad state retention
Wakeup from RST and general-purpose
I/O
Complete data retention
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Detailed Description
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5.4 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 5-1. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power-Up, Brownout, Supply
Supervisors
SVSLIFG, SVSHIFG
PMMRSTIFG
External Reset RST
WDTIFG
Watchdog Timeout (Watchdog
mode)
WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
DBDIFG
Reset
0FFFEh
63, highest
WDT, FRCTL MPU, CS, PMM
Password Violation
MPUSEGIIFG, MPUSEG1IFG, MPUSEG2IFG,
MPUSEG3IFG
FRAM double bit error detection
MPU segment violation
Software POR, BOR
PMMPORIFG, PMMBORIFG
(1) (2)
(SYSRSTIV)
System NMI
Vacant Memory Access
JTAG Mailbox
VMAIFG
JMBNIFG, JMBOUTIFG
ACCTIMIFG
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
62
61
FRAM access time error
FRAM single, double bit error
detection
SBDIFG, DBDIFG
(1)
(SYSSNIV)
User NMI
External NMI
Oscillator Fault
NMIIFG, OFIFG
(1) (2)
(SYSUNIV)
Comparator_D interrupt flags
Comparator_D
TB0
Maskable
Maskable
0FFF8h
0FFF6h
60
59
(1) (3)
(CBIV)
(3)
TB0CCR0 CCIFG0
TB0CCR1 CCIFG1 to TB0CCR2 CCIFG2,
TB0IFG
TB0
Maskable
Maskable
0FFF4h
0FFF2h
58
57
(1) (3)
(TB0IV)
Watchdog Timer
(Interval Timer Mode)
WDTIFG
UCA0RXIFG, UCA0TXIFG (SPI mode)
UCA0STTIFG, UCA0TXCPTIFG, UCA0RXIFG,
UXA0TXIFG (UART mode)
eUSCI_A0 Receive and Transmit
eUSCI_B0 Receive and Transmit
ADC10_B
Maskable
Maskable
Maskable
0FFF0h
0FFEEh
0FFECh
56
55
54
(1) (3)
(UCA0IV)
UCB0STTIFG, UCB0TXCPTIFG, UCB0RXIFG,
UCB0TXIFG (SPI mode)
UCB0ALIFG, UCB0NACKIFG, UCB0STTIFG,
UCB0STPIFG, UCB0RXIFG0, UCB0TXIFG0,
UCB0RXIFG1, UCB0TXIFG1, UCB0RXIFG2,
UCB0TXIFG2, UCB0RXIFG3, UCB0TXIFG3,
UCB0CNTIFG, UCB0BIT9IFG (I2C mode)
(1) (3)
(UCB0IV)
ADC10OVIFG, ADC10TOVIFG, ADC10HIIFG,
ADC10LOIFG
ADC10INIFG, ADC10IFG0
(1) (3) (4)
(ADC10IV)
(3)
TA0
TA0
TA0CCR0 CCIFG0
Maskable
Maskable
0FFEAh
0FFE8h
53
52
TA0CCR1 CCIFG1 to TA0CCR2 CCIFG2,
TA0IFG
(1) (3)
(TA0IV)
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with ADC, otherwise reserved.
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Table 5-1. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
UCA1RXIFG, UCA1TXIFG (SPI mode)
UCA1STTIFG, UCA1TXCPTIFG, UCA1RXIFG,
UXA1TXIFG (UART mode)
eUSCI_A1 Receive and Transmit
Maskable
0FFE6h
51
(1) (3)
(UCA1IV)
DMA0IFG, DMA1IFG, DMA2IFG
DMA
TA1
Maskable
Maskable
0FFE4h
0FFE2h
50
49
(1) (3)
(DMAIV)
(3)
TA1CCR0 CCIFG0
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG
TA1
Maskable
0FFE0h
48
(1) (3)
(TA1IV)
P1IFG.0 to P1IFG.7
I/O Port P1
TB1
Maskable
Maskable
0FFDEh
0FFDCh
47
46
(1) (3)
(P1IV)
(3)
TB1CCR0 CCIFG0
TB1CCR1 CCIFG1 to TB1CCR2 CCIFG2,
TB1IFG
TB1
Maskable
0FFDAh
45
(1) (3)
(TB1IV)
P2IFG.0 to P2IFG.7
I/O Port P2
TB2
Maskable
Maskable
0FFD8h
0FFD6h
44
43
(1) (3)
(P2IV)
(3)
TB2CCR0 CCIFG0
TB2CCR1 CCIFG1 to TB2CCR2 CCIFG2,
TB2IFG
TB2
Maskable
0FFD4h
42
(1) (3)
(TB2IV)
P3IFG.0 to P3IFG.7
I/O Port P3
I/O Port P4
Maskable
Maskable
0FFD2h
0FFD0h
41
40
(1) (3)
(P3IV)
P4IFG.0 to P4IFG.2
(1) (3)
(P4IV)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG, RTCOFIFG
RTC_B
Maskable
0FFCEh
39
(1) (3)
(RTCIV)
0FFCCh
⋮
38
(5)
Reserved
Reserved
⋮
0FF80h
0, lowest
(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
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5.5 Memory Organization
Table 5-2 describes the memory organization.
Table 5-2. Memory Organization(1)(2)
MSP430FR5739-EP
Memory (FRAM)
Total Size
15.5 KB
Main: interrupt vectors
Main: code memory
00FFFFh–00FF80h
00FF7Fh–00C200h
1 KB
001FFFh–001C00h
RAM
Device Descriptor Info (TLV)
(FRAM)
128 B
001A7Fh–001A00h
N/A
N/A
0019FFh–001980h
Address space mirrored to Info A
00197Fh–001900h
Address space mirrored to Info B
Information memory (FRAM)
Info A
Info B
BSL 3
BSL 2
BSL 1
BSL 0
Size
128 B
0018FFh–001880h
128 B
00187Fh–001800h
512 B
0017FFh–001600h
512 B
0015FFh–001400h
Bootstrap loader (BSL) memory
(ROM)
512 B
0013FFh–001200h
512 B
0011FFh–001000h
4 KB
000FFFh–0h
Peripherals
(1) N/A = Not available
(2) All address space not listed in this table is considered vacant memory.
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5.6 Bootstrap Loader (BSL)
The BSL enables users to program the FRAM or RAM using a UART serial interface. Access to the device
memory by the BSL is protected by an user-defined password. Use of the BSL requires four pins (see
Table 5-3). BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK
pins. For complete description of the features of the BSL and its implementation, see the MSP430
Programming Via the Bootstrap Loader User's Guide (SLAU319).
Table 5-3. BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
RST/NMI/SBWTDIO
TEST/SBWTCK
P2.0
P2.1
VCC
VSS
Data receive
Power supply
Ground supply
5.7 JTAG Operation
5.7.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to
enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. The JTAG pin requirements are summarized in
Table 5-4. For further details on interfacing to development tools and device programmers, see the
MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG
interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).
Table 5-4. JTAG Pin Requirements and Functions
DEVICE SIGNAL
PJ.3/TCK
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
IN
Power supply
VSS
Ground supply
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5.7.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.
The Spy-Bi-Wire interface pin requirements are summarized in Table 5-5. For further details on interfacing
to development tools and device programmers, see the MSP430 Hardware Tools User's Guide
(SLAU278). For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming Via the JTAG Interface (SLAU320).
Table 5-5. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
IN
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN, OUT
VSS
Ground supply
5.8 FRAM
The FRAM can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
•
•
•
•
Low-power ultra-fast write nonvolatile memory
Byte and word access capability
Programmable and automated wait state generation
Error Correction Coding (ECC) with single bit detection and correction, double bit detection
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the Memory Protection Unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
the application report MSP430™ FRAM Technology – How To and Best Practices (SLAA628).
5.9 Memory Protection Unit (MPU)
The FRAM can be protected from inadvertent CPU execution or write access by the MPU. Features of the
MPU include:
•
•
•
Main memory partitioning programmable up to three segments
Each segment's (main and information memory) access rights can be individually selected
Access violation flags with interrupt capability for easy servicing of access violations
5.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using
all instructions. For complete module descriptions, see the MSP430FR57xx Family User's Guide
(SLAU272).
5.10.1 Digital I/O
There are up to four 8-bit I/O ports implemented:
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for all ports.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise or word-wise in pairs.
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5.10.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch crystal oscillator XT1 (LF mode), an internal very-
low-power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT1 (HF mode). The clock system module is designed to meet the
requirements of both low system cost and low power consumption. A fail-safe mechanism exists for all
crystal sources. The clock system module provides the following clock signals:
•
•
•
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1 LF mode), a high-frequency crystal
(XT1 HF mode), the internal VLO, or the internal DCO.
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by the same sources
made available to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by the same sources made available to ACLK.
5.10.3 Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary and core supplies.
5.10.4 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs
operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module supports signed and unsigned
multiplication as well as signed and unsigned multiply-and-accumulate operations.
5.10.5 Real-Time Clock (RTC_B)
The RTC_B module contains an integrated real-time clock (RTC) (calendar mode). Calendar mode
integrates an internal calendar which compensates for months with fewer than 31 days and includes leap
year correction. The RTC_B also supports flexible alarm functions and offset-calibration hardware. RTC
operation is available in LPM3.5 mode to minimize power consumption.
5.10.6 Watchdog Timer (WDT_A)
The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart
after a software problem occurs. If the selected time interval expires, a system reset is generated. If the
watchdog function is not needed in an application, the module can be configured as an interval timer and
can generate interrupts at selected time intervals.
5.10.7 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators, bootstrap loader entry mechanisms, and configuration management (device descriptors). It
also includes a data exchange mechanism using JTAG called a JTAG mailbox that can be used in the
application.
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Table 5-6. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
SYSRSTIV,
System Reset
019Eh
No interrupt pending
Brownout (BOR)
00h
02h
Highest
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
LPMx.5 wake up (BOR)
06h
08h
Security violation (BOR)
0Ah
SVSLIFG SVSL event (BOR)
SVSHIFG SVSH event (BOR)
Reserved
0Ch
0Eh
10h
Reserved
12h
PMMSWPOR software POR (POR)
WDTIFG watchdog timeout (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
DBDIFG FRAM double bit error (PUC)
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
MPUPW MPU password violation (PUC)
CSPW CS password violation (PUC)
MPUSEGIIFG information memory segment violation (PUC)
MPUSEG1IFG segment 1 memory violation (PUC)
MPUSEG2IFG segment 2 memory violation (PUC)
MPUSEG3IFG segment 3 memory violation (PUC)
Reserved
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
Reserved
30h to 3Eh
00h
Lowest
Highest
SYSSNIV, System NMI
019Ch
No interrupt pending
DBDIFG FRAM double bit error
ACCTIMIFG access time error
Reserved
02h
04h
0Eh
VMAIFG Vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
SBDIFG FRAM single bit error
Reserved
10h
12h
14h
16h
18h to 1Eh
00h
Lowest
Highest
SYSUNIV, User NMI
019Ah
No interrupt pending
NMIFG NMI pin
02h
OFIFG oscillator fault
04h
Reserved
06h
Reserved
08h
Reserved
0Ah to 1Eh
Lowest
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5.10.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral.
(1)
Table 5-7. DMA Trigger Assignments
TRIGGER
0
CHANNEL 0
DMAREQ
CHANNEL 1
DMAREQ
CHANNEL 2
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
Reserved
2
3
4
5
6
Reserved
Reserved
Reserved
7
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
8
(2)
(2)
(2)
9
TB1CCR0 CCIFG
TB1CCR2 CCIFG
TB2CCR0 CCIFG
TB2CCR2 CCIFG
Reserved
TB1CCR0 CCIFG
TB1CCR2 CCIFG
TB2CCR0 CCIFG
TB2CCR2 CCIFG
Reserved
TB1CCR0 CCIFG
TB1CCR2 CCIFG
TB2CCR0 CCIFG
TB2CCR2 CCIFG
Reserved
(2)
(3)
(3)
(2)
(3)
(3)
(2)
(3)
(3)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
(4)
(4)
(4)
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
(4)
(4)
(4)
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
UCB0RXIFG0
UCB0TXIFG0
UCB0RXIFG1
UCB0TXIFG1
UCB0RXIFG2
UCB0TXIFG2
UCB0RXIFG3
UCB0TXIFG3
UCB0RXIFG0
UCB0TXIFG0
UCB0RXIFG1
UCB0TXIFG1
UCB0RXIFG2
UCB0TXIFG2
UCB0RXIFG3
UCB0TXIFG3
UCB0RXIFG0
UCB0TXIFG0
UCB0RXIFG1
UCB0TXIFG1
UCB0RXIFG2
UCB0TXIFG2
UCB0RXIFG3
UCB0TXIFG3
(5)
(5)
(5)
ADC10IFGx
ADC10IFGx
ADC10IFGx
Reserved
Reserved
MPY ready
DMA2IFG
DMAE0
Reserved
Reserved
MPY ready
DMA0IFG
DMAE0
Reserved
Reserved
MPY ready
DMA1IFG
DMAE0
(1) If a reserved trigger source is selected, no trigger is generated.
(2) Only on devices with TB1, otherwise reserved
(3) Only on devices with TB2, otherwise reserved
(4) Only on devices with eUSCI_A1, otherwise reserved
(5) Only on devices with ADC, otherwise reserved
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5.10.9 Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each eUSCI module
contains two portions, A and B.
The eUSCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.
The eUSCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.
The MSP430FR5739-EP series include one or two eUSCI_An modules (eUSCI_A0, eUSCI_A1) and one
eUSCI_Bn module (eUSCI_B).
5.10.10 TA0, TA1
TA0 and TA1 are 16-bit timers/counters (Timer_A type) with three capture/compare registers each. Each
can support multiple capture/compares, PWM outputs, and interval timing. Each has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 5-8. TA0 Signal Connections
MODULE INPUT
SIGNAL
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
INPUT PIN NUMBER
DEVICE INPUT SIGNAL
MODULE BLOCK
OUTPUT PIN NUMBER
3-P1.2
TA0CLK
ACLK (internal)
SMCLK (internal)
TA0CLK
TA0.0
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
N/A
TA0
N/A
3-P1.2
28-P1.6
34-P2.3
28-P1.6
34-P2.3
TA0.0
CCR0
CCR1
CCR2
TA0.0
DVSS
DVCC
VCC
1-P1.0
2-P1.1
TA0.1
CCI1A
1-P1.0
(1)
ADC10 (internal)
ADC10SHSx = {1}
CDOUT (internal)
CCI1B
TA1
TA2
TA0.1
TA0.2
DVSS
DVCC
GND
VCC
TA0.2
CCI2A
CCI2B
GND
VCC
2-P1.1
ACLK (internal)
DVSS
DVCC
(1) Only on devices with ADC
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Table 5-9. TA1 Signal Connections
MODULE INPUT
MODULE OUTPUT
DEVICE OUTPUT
SIGNAL
INPUT PIN NUMBER
DEVICE INPUT SIGNAL
MODULE BLOCK
OUTPUT PIN NUMBER
SIGNAL
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
SIGNAL
2-P1.1
TA1CLK
ACLK (internal)
SMCLK (internal)
TA1CLK
TA1.0
Timer
N/A
N/A
2-P1.1
29-P1.7
35-P2.4
29-P1.7
35-P2.4
TA1.0
CCR0
CCR1
CCR2
TA0
TA1
TA2
TA1.0
TA1.1
TA1.2
DVSS
DVCC
VCC
3-P1.2
8-P1.3
TA1.1
CCI1A
CCI1B
GND
3-P1.2
8-P1.3
CDOUT (internal)
DVSS
DVCC
VCC
TA1.2
CCI2A
CCI2B
GND
ACLK (internal)
DVSS
DVCC
VCC
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5.10.11 TB0, TB1, TB2
TB0, TB1, and TB2 are 16-bit timers/counters (Timer_B type) with three capture/compare registers each.
Each can support multiple capture/compares, PWM outputs, and interval timing. Each has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each
of the capture/compare registers.
Table 5-10. TB0 Signal Connections
MODULE INPUT
SIGNAL
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
INPUT PIN NUMBER
DEVICE INPUT SIGNAL
MODULE BLOCK
OUTPUT PIN NUMBER
21-P2.0
TB0CLK
ACLK (internal)
SMCLK (internal)
TB0CLK
TBCLK
ACLK
Timer
N/A
TB0
N/A
SMCLK
TBCLK
CCI0A
CCI0B
21-P2.0
22-P2.1
17-P2.5
TB0.0
22-P2.1
17-P2.5
TB0.0
(1)
CCR0
TB0.0
ADC10 (internal)
DVSS
GND
ADC10SHSx = {2}
DVCC
VCC
9-P1.4
TB0.1
CCI1A
9-P1.4
(1)
ADC10 (internal)
CDOUT (internal)
CCI1B
ADC10SHSx = {3}
CCR1
CCR2
TB1
TB2
TB0.1
TB0.2
DVSS
DVCC
GND
VCC
10-P1.5
TB0.2
CCI2A
CCI2B
GND
VCC
10-P1.5
ACLK (internal)
DVSS
DVCC
(1) Only on devices with ADC
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(1)
Table 5-11. TB1 Signal Connections
MODULE INPUT
SIGNAL
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
INPUT PIN NUMBER
DEVICE INPUT SIGNAL
MODULE BLOCK
OUTPUT PIN NUMBER
26-P3.6
TB1CLK
ACLK (internal)
SMCLK (internal)
TB1CLK
TB1.0
TBCLK
ACLK
SMCLK
TBCLK
CCI0A
CCI0B
GND
Timer
N/A
TB0
TB1
TB2
N/A
26-P3.6
23-P2.2
18-P2.6
23-P2.2
18-P2.6
TB1.0
CCR0
CCR1
CCR2
TB1.0
TB1.1
TB1.2
DVSS
DVCC
VCC
28-P1.6
24-P3.4
TB1.1
CCI1A
CCI1B
GND
28-P1.6
24-P3.4
TB1.1
DVSS
DVCC
VCC
29-P1.7
25-P3.5
TB1.2
CCI2A
CCI2B
GND
29-P1.7
25-P3.5
TB1.2
DVSS
DVCC
VCC
(1) TB1 is not present on all device types.
(1)
Table 5-12. TB2 Signal Connections
MODULE INPUT
SIGNAL
MODULE OUTPUT
DEVICE OUTPUT
SIGNAL
INPUT PIN NUMBER
DEVICE INPUT SIGNAL
MODULE BLOCK
OUTPUT PIN NUMBER
SIGNAL
24-P3.4
TB2CLK
ACLK (internal)
SMCLK (internal)
TB2CLK
TB2.0
TBCLK
ACLK
SMCLK
TBCLK
CCI0A
CCI0B
GND
Timer
N/A
N/A
24-P3.4
21-P2.0
15-P4.0
21-P2.0
15-P4.0
TB2.0
CCR0
CCR1
CCR2
TB0
TB1
TB2
TB2.0
TB2.1
TB2.2
DVSS
DVCC
VCC
22-P2.1
26-P3.6
TB2.1
CCI1A
CCI1B
GND
22-P2.1
26-P3.6
TB2.1
DVSS
DVCC
VCC
23-P2.2
27-P3.7
TB2.2
CCI2A
CCI2B
GND
23-P2.2
27-P3.7
TB2.2
DVSS
DVCC
VCC
(1) TB2 is not present on all device types.
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5.10.12 ADC10_B
The ADC10_B module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit
SAR core, sample select control, reference generator, and a conversion result buffer. A window
comparator with a lower limit and an upper limit allows CPU-independent result monitoring with three
window comparator interrupt flags.
5.10.13 Comparator_D
The primary function of the Comparator_D module is to support precision slope analog-to-digital
conversions, battery voltage supervision, and monitoring of external analog signals.
5.10.14 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
5.10.15 Shared Reference (REF)
The reference module (REF) is responsible for generation of all critical reference voltages that can be
used by the various analog peripherals in the device.
5.10.16 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The S version of the EEM implemented on all devices
has the following features:
•
•
•
•
•
Three hardware triggers or breakpoints on memory access
One hardware trigger or breakpoint on CPU register write access
Up to four hardware triggers can be combined to form complex triggers or breakpoints
One cycle counter
Clock control on module level
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5.10.17 Peripheral File Map
Table 5-13 provides the base address and offset range of all available peripherals.
Table 5-13. Peripherals
OFFSET ADDRESS
RANGE
MODULE NAME
BASE ADDRESS
Special Functions (see Table 5-14)
PMM (see Table 5-15)
0100h
0120h
0140h
0150h
015Ch
0160h
0180h
01B0h
0200h
0220h
0320h
0340h
0380h
03C0h
0400h
0440h
04A0h
04C0h
0500h
0510h
0520h
0530h
05A0h
05C0h
05E0h
0640h
0700h
08C0h
000h-01Fh
000h-010h
000h-00Fh
000h-007h
000h-001h
000h-00Fh
000h-01Fh
000h-001h
000h-01Fh
000h-01Fh
000h-01Fh
000h-02Fh
000h-02Fh
000h-02Fh
000h-02Fh
000h-02Fh
000h-01Fh
000h-02Fh
000h-00Fh
000h-00Ah
000h-00Ah
000h-00Ah
000h-00Fh
000h-01Fh
000h-01Fh
000h-02Fh
000h-03Fh
000h-00Fh
FRAM Control (see Table 5-16)
CRC16 (see Table 5-17)
Watchdog (see Table 5-18)
CS (see Table 5-19)
SYS (see Table 5-20)
Shared Reference (see Table 5-21)
Port P1, P2 (see Table 5-22)
Port P3, P4 (see Table 5-23)
Port PJ (see Table 5-24)
TA0 (see Table 5-25)
TA1 (see Table 5-26)
TB0 (see Table 5-27)
TB1 (see Table 5-28)
TB2 (see Table 5-29)
Real-Time Clock (RTC_B) (see Table 5-30)
32-Bit Hardware Multiplier (see Table 5-31)
DMA General Control (see Table 5-32)
DMA Channel 0 (see Table 5-32)
DMA Channel 1 (see Table 5-32)
DMA Channel 2 (see Table 5-32)
MPU Control (see Table 5-33)
eUSCI_A0 (see Table 5-34)
eUSCI_A1 (see Table 5-35)
eUSCI_B0 (see Table 5-36)
ADC10_B (see Table 5-37)
Comparator_D (see Table 5-38)
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Table 5-14. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
SFRIE1
OFFSET
SFR interrupt enable
SFR interrupt flag
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
Table 5-15. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMMCTL0
OFFSET
OFFSET
OFFSET
PMM Control 0
PMM interrupt flags
PM5 Control 0
00h
0Ah
10h
PMMIFG
PM5CTL0
Table 5-16. FRAM Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
FRCTLCTL0
FRAM control 0
General control 0
General control 1
00h
04h
06h
GCCTL0
GCCTL1
Table 5-17. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC16DI
CRC data input
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
Table 5-18. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
WDTCTL
OFFSET
OFFSET
Watchdog timer control
00h
Table 5-19. CS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
CSCTL0
CS control 0
CS control 1
CS control 2
CS control 3
CS control 4
CS control 5
CS control 6
00h
02h
04h
06h
08h
0Ah
0Ch
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
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Table 5-20. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
SYSRSTIV
Table 5-21. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
REFCTL
OFFSET
OFFSET
Shared reference control
00h
Table 5-22. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
Port P1 input
P1IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P1 output
Port P1 direction
P1OUT
P1DIR
P1REN
Port P1 pullup/pulldown enable
Port P1 selection 0
P1SEL0
P1SEL1
P1IV
Port P1 selection 1
Port P1 interrupt vector word
Port P1 complement selection
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
P1SELC
P1IES
P1IE
P1IFG
P2IN
Port P2 input
Port P2 output
P2OUT
P2DIR
P2REN
P2SEL0
P2SEL1
P2SELC
P2IV
Port P2 direction
Port P2 pullup/pulldown enable
Port P2 selection 0
Port P2 selection 1
Port P2 complement selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
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Table 5-23. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
0Ah
0Ch
0Eh
16h
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
0Dh
17h
1Eh
19h
1Bh
1Dh
Port P3 output
Port P3 direction
P3OUT
P3DIR
P3REN
Port P3 pullup/pulldown enable
Port P3 selection 0
P3SEL0
P3SEL1
P3IV
Port P3 selection 1
Port P3 interrupt vector word
Port P3 complement selection
Port P3 interrupt edge select
Port P3 interrupt enable
Port P3 interrupt flag
P3SELC
P3IES
P3IE
P3IFG
P4IN
Port P4 input
Port P4 output
P4OUT
P4DIR
P4REN
P4SEL0
P4SEL1
P4SELC
P4IV
Port P4 direction
Port P4 pullup/pulldown enable
Port P4 selection 0
Port P4 selection 1
Port P4 complement selection
Port P4 interrupt vector word
Port P4 interrupt edge select
Port P4 interrupt enable
Port P4 interrupt flag
P4IES
P4IE
P4IFG
Table 5-24. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
0Ah
0Ch
16h
Port PJ output
PJOUT
PJDIR
PJREN
Port PJ direction
Port PJ pullup/pulldown enable
Port PJ selection 0
Port PJ selection 1
Port PJ complement selection
PJSEL0
PJSEL1
PJSELC
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Table 5-25. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
OFFSET
TA0 control
TA0CTL
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter register
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TA0 expansion register 0
TA0 interrupt vector
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
TA0IV
Table 5-26. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
TA1CTL
TA1 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter register
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TA1 expansion register 0
TA1 interrupt vector
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1IV
Table 5-27. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
TB0CTL
TB0 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB0 register
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TB0 expansion register 0
TB0 interrupt vector
TB0CCR0
TB0CCR1
TB0CCR2
TB0EX0
TB0IV
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Table 5-28. TB1 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
TB1CTL
OFFSET
TB1 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB1 register
TB1CCTL0
TB1CCTL1
TB1CCTL2
TB1R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TB1 expansion register 0
TB1 interrupt vector
TB1CCR0
TB1CCR1
TB1CCR2
TB1EX0
TB1IV
Table 5-29. TB2 Registers (Base Address: 0440h)
REGISTER DESCRIPTION
REGISTER
TB2CTL
OFFSET
TB2 control
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TB2 register
TB2CCTL0
TB2CCTL1
TB2CCTL2
TB2R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TB2 expansion register 0
TB2 interrupt vector
TB2CCR0
TB2CCR1
TB2CCR2
TB2EX0
TB2IV
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Table 5-30. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
RTCCTL0
OFFSET
RTC control 0
00h
01h
02h
03h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Eh
RTC control 1
RTCCTL1
RTC control 2
RTCCTL2
RTC control 3
RTCCTL3
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTC prescaler 1
RTC interrupt vector word
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTCPS1
RTCIV
RTC seconds, RTC counter register 1
RTC minutes, RTC counter register 2
RTC hours, RTC counter register 3
RTC day of week, RTC counter register 4
RTC days
RTCSEC, RTCNT1
RTCMIN, RTCNT2
RTCHOUR, RTCNT3
RTCDOW, RTCNT4
RTCDAY
RTC month
RTCMON
RTC year low
RTCYEARL
RTCYEARH
RTCAMIN
RTC year high
RTC alarm minutes
RTC alarm hours
RTCAHOUR
RTCADOW
RTCADAY
RTC alarm day of week
RTC alarm days
Binary-to-BCD conversion register
BCD-to-binary conversion register
BIN2BCD
BCD2BIN
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Table 5-31. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension register
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control register 0
RES3
MPY32CTL0
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Table 5-32. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
DMA0CTL
OFFSET
DMA channel 0 control
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA module control 0
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
Table 5-33. MPU Control Registers (Base Address: 05A0h)
REGISTER DESCRIPTION
REGISTER
MPUCTL0
OFFSET
MPU control 0
00h
02h
04h
06h
MPU control 1
MPUCTL1
MPUSEG
MPUSAM
MPU Segmentation Register
MPU access management
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Table 5-34. eUSCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
eUSCI_A baud rate 1
eUSCI_A modulation control
eUSCI_A status
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA0CTLW1
UCA0BR0
UCA0BR1
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
UCA0IFG
eUSCI_A interrupt vector word
UCA0IV
Table 5-35. eUSCI_A1 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
UCA1CTLW0
OFFSET
eUSCI_A control word 0
eUSCI _A control word 1
eUSCI_A baud rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
UCA1CTLW1
UCA1BR0
eUSCI_A baud rate 1
UCA1BR1
eUSCI_A modulation control
eUSCI_A status
UCA1MCTLW
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
UCA1IFG
UCA1IV
58
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Table 5-36. eUSCI_B0 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
UCB0CTLW0
OFFSET
eUSCI_B control word 0
eUSCI_B control word 1
eUSCI_B bit rate 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
UCB0CTLW1
UCB0BR0
eUSCI_B bit rate 1
UCB0BR1
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B received address
eUSCI_B address mask
eUSCI I2C slave address
eUSCI interrupt enable
eUSCI interrupt flags
UCB0IFG
eUSCI interrupt vector word
UCB0IV
Table 5-37. ADC10_B Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
ADC10CTL0
OFFSET
ADC10_B Control register 0
00h
02h
04h
06h
08h
0Ah
12h
1Ah
1Ch
1Eh
ADC10_B Control register 1
ADC10CTL1
ADC10CTL2
ADC10LO
ADC10_B Control register 2
ADC10_B Window Comparator Low Threshold
ADC10_B Window Comparator High Threshold
ADC10_B Memory Control Register 0
ADC10_B Conversion Memory Register
ADC10_B Interrupt Enable
ADC10HI
ADC10MCTL0
ADC10MEM0
ADC10IE
ADC10_B Interrupt Flags
ADC10IGH
ADC10IV
ADC10_B Interrupt Vector Word
Table 5-38. Comparator_D Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
Comparator_D control register 0
REGISTER
CDCTL0
OFFSET
00h
02h
04h
06h
0Ch
0Eh
Comparator_D control register 1
Comparator_D control register 2
Comparator_D control register 3
Comparator_D interrupt register
Comparator_D interrupt vector word
CDCTL1
CDCTL2
CDCTL3
CDINT
CDIV
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6 Input/Output Schematics
6.1 Port P1, P1.0 to P1.2, Input/Output With Schmitt Trigger
Pad Logic
External ADC reference
(P1.0, P1.1)
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P1REN.x
P1DIR.x
0 0
0 1
1 0
1 1
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
DVSS
P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
P1SEL0.x
P1SEL1.x
P1IN.x
Bus
Keeper
EN
D
To modules
60
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
Table 6-1. Port P1 (P1.0 to P1.2) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.0/TA0.1/DMAE0/RTCCLK/A0/CD0/VeREF-
P1.1/TA0.2/TA1CLK/CDOUT/A1/CD1/VeREF+
P1.2/TA1.1/TA0CLK/CDOUT/A2/CD2
0
P1.0 (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
0
0
0
1
0
1
0
1
1
DMAE0
0
1
RTCCLK
(1) (2)
A0
(1) (3)
CD0
X
1
(1) (2)
VeREF-
P1.1 (I/O)
TA0.CCI2A
TA0.2
1
I: 0; O: 1
0
0
0
1
0
1
0
1
TA1CLK
CDOUT
1
1
0
1
(1) (2)
A1
(1) (3)
CD1
X
(1) (2)
VeREF+
P1.2 (I/O)
TA1.CCI1A
TA1.1
2
I: 0; O: 1
0
0
0
1
0
1
0
1
TA0CLK
CDOUT
1
1
0
1
(1) (2)
A2
X
(1) (3)
CD2
(1) Setting P1SEL1.x and P1SEL0.x disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(2) Not available on all devices and package types.
(3) Setting the CDPD.x bit of the comparator disables the output driver as well as the input Schmitt trigger to prevent parasitic cross
currents when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically
disables output driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
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Input/Output Schematics
61
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6.2 Port P1, P1.3 to P1.5, Input/Output With Schmitt Trigger
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P1REN.x
0 0
0 1
1 0
1 1
P1DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
DVSS
P1.3/TA1.2/UCB0STE/A3/CD3
P1.4/TB0.1/UCA0STE/A4/CD4
P1.5/TB0.2/UCA0CLK/A5/CD5
P1SEL0.x
P1SEL1.x
P1IN.x
Bus
Keeper
EN
D
To modules
62
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
Table 6-2. Port P1 (P1.3 to P1.5) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.3/TA1.2/UCB0STE/A3/CD3
P1.4/TB0.1/UCA0STE/A4/CD4
P1.5/TB0.2/UCA0CLK/A5/CD5
3
P1.3 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
0
0
0
0
1
1
(1)
UCB0STE
X
1
1
0
0
1
0
(2) (3)
A3
X
(2) (4)
CD3
4
5
P1.4 (I/O)
TB0.CCI1A
TB0.1
I: 0; O: 1
0
0
1
1
(5)
UCA0STE
X
1
1
0
0
1
0
(2) (3)
A4
X
(2) (4)
CD4
P1.5(I/O)
TB0.CCI2A
TB0.2
I: 0; O: 1
0
1
0
1
(5)
UCA0CLK
X
1
1
0
1
(2) (3)
A5
X
(2) (4)
CD5
(1) Direction controlled by eUSCI_B0 module.
(2) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Not available on all devices and package types.
(4) Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit
(5) Direction controlled by eUSCI_A0 module.
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Input/Output Schematics
63
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6.3 Port P1, P1.6 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P1REN.x
P1DIR.x
0 0
0 1
1 0
1 1
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P1OUT.x
From module 1
From module 2
From module 3
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
P1SEL0.x
P1SEL1.x
P1IN.x
Bus
Keeper
EN
D
To modules
Table 6-3. Port P1 (P1.6 to P1.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.6/TB1.1/UCB0SIMO/UCB0SDA/TA0.0
6
P1.6 (I/O)
I: 0; O: 1
0
0
(1)
TB1.CCI1A
0
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
(1)
TB1.1
(2)
UCB0SIMO/UCB0SDA
TA0.CCI0A
X
0
TA0.0
1
P1.7/TB1.2/UCB0SOMI/UCB0SCL/TA1.0
7
P1.7 (I/O)
I: 0; O: 1
(1)
TB1.CCI2A
0
1
X(2)
(1)
TB1.2
UCB0SOMI/UCB0SCL
TA1.CCI0A
0
TA1.0
1
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_B0 module.
64
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
6.4 Port P2, P2.0 to P2.2, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P2REN.x
P2DIR.x
0 0
0 1
1 0
1 1
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
From module 3
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
Table 6-4. Port P2 (P2.0 to P2.2) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.0/TB2.0/UCA0TXD/UCA0SIMO/TB0CLK/ACLK
P2.1/TB2.1/UCA0RXD/UCA0SOMI/TB0.0
P2.2/TB2.2/UCB0CLK/TB1.0
0
P2.0 (I/O)
I: 0; O: 1
0
0
1
0
1
0
1
0
1
0
1
0
1
(1)
TB2.CCI0A
0
1
0
1
1
0
0
1
1
0
0
1
1
(1)
TB2.0
(2)
UCA0TXD/UCA0SIMO
TB0CLK
X
0
ACLK
1
1
2
P2.1 (I/O)
I: 0; O: 1
(1)
TB2.CCI1A
0
1
(1)
TB2.1
(2)
UCA0RXD/UCA0SOMI
TB0.CCI0A
X
0
TB0.0
1
P2.2 (I/O)
I: 0; O: 1
(1)
TB2.CCI2A
0
1
(1)
TB2.2
(3)
UCB0CLK
X
(1)
TB1.CCI0A
0
1
(1)
TB1.0
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_A0 module.
(3) Direction controlled by eUSCI_B0 module.
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Input/Output Schematics
65
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6.5 Port P2, P2.3 to P2.4, Input/Output With Schmitt Trigger
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
DVSS
P2.3/TA0.0/UCA1STE/A6/CD10
P2.4/TA1.0/UCA1CLK/A7/CD11
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
66
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
Table 6-5. Port P2 (P2.3 to P2.4) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL1.x
P2SEL0.x
P2.3/TA0.0/UCA1STE/A6/CD10
3
P2.3 (I/O)
TA0.CCI0B
TA0.0
I: 0; O: 1
0
0
0
0
1
1
(1)
UCA1STE
X
1
1
0
0
1
0
(2) (3)
A6
X
(2) (4)
CD10
P2.4/TA1.0/UCA1CLK/A7/CD11
4
P2.4 (I/O)
TA1.CCI0B
TA1.0
I: 0; O: 1
0
0
1
1
(1)
UCA1CLK
X
1
1
0
1
(2) (3)
A7
X
(2) (4)
CD11
(1) Direction controlled by eUSCI_A1 module.
(2) Setting P2SEL1.x and P2SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(3) Not available on all devices and package types.
(4) Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
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Input/Output Schematics
67
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6.6 Port P2, P2.5 to P2.6, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
From module 2
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
From module 1
From module 2
DVSS
P2.5/TB0.0/UCA1TXD/UCA1SIMO
P2.6/TB1.0/UCA1RXD/UCA1SOMI
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
Table 6-6. Port P2 (P2.5 to P2.6) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x P2SEL1.x P2SEL0.x
(1)
P2.5/TB0.0/UCA1TXD/UCA1SIMO
5
P2.5(I/O)
I: 0; O: 1
0
0
(1)
TB0.CCI0B
0
1
0
1
(1)
TB0.0
(1)
(2)
UCA1TXD/UCA1SIMO
X
1
0
0
0
(1)
P2.6/TB1.0/UCA1RXD/UCA1SOMI
6
P2.6(I/O)
I: 0; O: 1
(1)
TB1.CCI0B
0
0
1
1
0
(1)
TB1.0
1
(2)
(1)
UCA1RXD/UCA1SOMI
X
(1) Not available on all devices and package types.
(2) Direction controlled by eUSCI_A1 module.
68
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
6.7 Port P2, P2.7, Input/Output With Schmitt Trigger
Pad Logic
P2REN.x
0 0
0 1
1 0
1 1
P2DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P2OUT.x
DVSS
DVSS
P2.7
DVSS
P2SEL0.x
P2SEL1.x
P2IN.x
Bus
Keeper
EN
D
To modules
Table 6-7. Port P2 (P2.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x P2SEL1.x P2SEL0.x
(1)
P2.7
7
P2.7(I/O)
I: 0; O: 1
0
0
(1) Not available on all devices and package types.
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Input/Output Schematics
69
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6.8 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
Pad Logic
To ADC
From ADC
To Comparator
From Comparator
CDPD.x
P3REN.x
0 0
0 1
1 0
1 1
P3DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P3OUT.x
DVSS
DVSS
DVSS
P3.0/A12/CD12
P3.1/A13/CD13
P3.2/A14/CD14
P3.3/A15/CD15
P3SEL0.x
P3SEL1.x
P3IN.x
Bus
Keeper
EN
D
To modules
70
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
Table 6-8. Port P3 (P3.0 to P3.3) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x P3SEL1.x P3SEL0.x
P3.0/A12/CD12
P3.1/A13/CD13
P3.2/A14/CD14
P3.3/A15/CD15
0
P3.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(1) (2)
A12
X
(1) (3)
CD12
1
2
3
P3.1 (I/O)
I: 0; O: 1
(1) (2)
A13
X
I: 0; O: 1
X
(1) (3)
CD13
P3.2 (I/O)
(1) (2)
A14
(1) (3)
CD14
P3.3 (I/O)
I: 0; O: 1
X
(1) (2)
A15
(1) (3)
CD15
(1) Setting P1SEL1.x and P1SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(2) Not available on all devices and package types.
(3) Setting the CDPD.x bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the CDx input pin to the comparator multiplexer with the CDx bits automatically disables output
driver and input buffer for that pin, regardless of the state of the associated CDPD.x bit.
Copyright © 2014, Texas Instruments Incorporated
Input/Output Schematics
71
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6.9 Port P3, P3.4 to P3.6, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P3REN.x
0 0
0 1
1 0
1 1
P3DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P3OUT.x
From module 1
DVSS
P3.4/TB1.1/TB2CLK/SMCLK
P3.5/TB1.2/CDOUT
P3.6/TB2.1/TB1CLK
From module 2
P3SEL0.x
P3SEL1.x
P3IN.x
Bus
Keeper
EN
D
To modules
Table 6-9. Port P3 (P3.4 to P3.6) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x P3SEL1.x P3SEL0.x
(1)
P3.4/TB1.1/TB2CLK/SMCLK
4
P3.4 (I/O)
I: 0; O: 1
0
0
(1)
TB1.CCI1B
0
0
1
(1)
TB1.1
1
(1)
TB2CLK
0
1
0
0
1
0
1
(1)
SMCLK
1
(1)
P3.5/TB1.2/CDOUT
P3.6/TB2.1/TB1CLK
5
6
P3.5 (I/O)
I: 0; O: 1
(1)
TB1.CCI2B
0
(1)
TB1.2
1
(1)
CDOUT
1
1
0
1
0
(1)
P3.6 (I/O)
I: 0; O: 1
(1)
TB2.CCI1B
0
1
0
0
1
1
1
(1)
TB2.1
(1)
TB1CLK
(1) Not available on all devices and package types.
72
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
6.10 Port P3, P3.7, Input/Output With Schmitt Trigger
Pad Logic
P3REN.x
0 0
0 1
1 0
1 1
P3DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P3OUT.x
From module 1
DVSS
DVSS
P3.7/TB2.2
P3SEL0.x
P3SEL1.x
P3IN.x
Bus
Keeper
EN
D
To modules
Table 6-10. Port P3 (P3.7) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P3.x)
x
FUNCTION
P3DIR.x P3SEL1.x P3SEL0.x
(1)
P3.7/TB2.2
7
P3.7 (I/O)
I: 0; O: 1
0
0
(1)
TB2.CCI2B
0
1
0
1
(1)
TB2.2
(1) Not available on all devices and package types.
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Input/Output Schematics
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6.11 Port P4, P4.0, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
0 0
0 1
1 0
1 1
P4DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P4OUT.x
From module 1
DVSS
DVSS
P4.0/TB2.0
P4SEL0.x
P4SEL1.x
P4IN.x
Bus
Keeper
EN
D
To modules
Table 6-11. Port P4 (P4.0) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x P4SEL1.x P4SEL0.x
(1)
P4.0/TB2.0
0
P4.0 (I/O)
I: 0; O: 1
0
0
(1)
TB2.CCI0B
0
1
0
1
(1)
TB2.0
(1) Not available on all devices and package types.
74
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
6.12 Port P4, P4.1, Input/Output With Schmitt Trigger
Pad Logic
P4REN.x
0 0
0 1
1 0
1 1
P4DIR.x
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
P4OUT.x
DVSS
DVSS
P4.1
DVSS
P4SEL0.x
P4SEL1.x
P4IN.x
Bus
Keeper
EN
D
To modules
Table 6-12. Port P4 (P4.1) Pin Functions
CONTROL BITS/SIGNALS
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x P4SEL1.x P4SEL0.x
(1)
P4.1
1
P4.1 (I/O)
I: 0; O: 1
0
0
(1) Not available on all devices and package types.
Copyright © 2014, Texas Instruments Incorporated
Input/Output Schematics
75
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6.13 Port J, J.0 to J.3 JTAG pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt
Trigger or Output
To Comparator
From Comparator
CDPD.x
From JTAG
From JTAG
From JTAG
Pad Logic
1
0
PJREN.x
PJDIR.x
0 0
0 1
1 0
1 1
1
0
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
JTAG enable
0 0
0 1
1 0
1 1
PJOUT.x
From module 1
DVSS
1
0
PJ.0/TDO/TB0OUTH/SMCLK/CD6
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
DVSS
PJSEL0.x
PJSEL1.x
PJIN.x
Bus
Keeper
EN
D
To modules
and JTAG
76
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
To Comparator
From Comparator
CDPD.x
Pad Logic
From JTAG
From JTAG
From JTAG
1
0
PJREN.x
PJDIR.x
0 0
0 1
1 0
1 1
1
0
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
JTAG enable
0 0
0 1
1 0
1 1
PJOUT.x
DVSS
1
0
DVSS
DVSS
PJ.3/TCK/CD9
PJSEL0.x
PJSEL1.x
PJIN.x
Bus
Keeper
EN
D
To modules
and JTAG
Copyright © 2014, Texas Instruments Incorporated
Input/Output Schematics
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Table 6-13. Port PJ (PJ.0 to PJ.3) Pin Functions
(1)
CONTROL BITS/ SIGNALS
PJDIR.x PJSEL1.x PJSEL0.x
PIN NAME (PJ.x)
x
FUNCTION
(2)
PJ.0/TDO/TB0OUTH/SMCLK/CD6
0
PJ.0 (I/O)
I: 0; O: 1
0
0
(3)
TDO
X
X
X
TB0OUTH
SMCLK
CD6
0
0
1
1
X
1
0
X
1
0
X
(2)
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
PJ.2/TMS/TB2OUTH/ACLK/CD8
PJ.3/TCK/CD9
1
2
3
PJ.1 (I/O)
TDI/TCLK
TB1OUTH
MCLK
I: 0; O: 1
(3) (4)
X
0
0
1
1
CD7
X
1
0
X
1
0
X
(2)
PJ.2 (I/O)
I: 0; O: 1
(3) (4)
TMS
X
TB2OUTH
ACLK
0
0
1
1
CD8
X
1
0
X
1
1
0
X
1
(2)
PJ.3 (I/O)
I: 0; O: 1
(3) (4)
TCK
X
X
CD9
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made by the SYS module or by the Spy-Bi-Wire four-wire
entry sequence. PJSEL1.x and PJSEL0.x have no effect in these cases.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
78
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
6.14 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
Pad Logic
To XT1 XIN
PJREN.4
0 0
0 1
1 0
1 1
PJDIR.4
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.4
DVSS
DVSS
DVSS
PJ.4/XIN
PJSEL0.4
PJSEL1.4
PJIN.4
Bus
Keeper
EN
D
To modules
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Input/Output Schematics
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Pad Logic
To XT1 XOUT
PJSEL0.4
XT1BYPASS
PJREN.5
0 0
0 1
1 0
1 1
PJDIR.5
DVSS
DVCC
0
1
Direction
0: Input
1: Output
1
0 0
0 1
1 0
1 1
PJOUT.5
DVSS
DVSS
DVSS
PJ.5/XOUT
PJSEL0.5
PJSEL1.5
PJIN.5
Bus
Keeper
EN
D
To modules
Table 6-14. Port PJ (PJ.4 and PJ.5) Pin Functions
(1)
CONTROL BITS/SIGNALS
PIN NAME (P7.x)
x
FUNCTION
PJ.4 (I/O)
XT1
BYPASS
PJDIR.x PJSEL1.5 PJSEL0.5 PJSEL1.4 PJSEL0.4
PJ.4/XIN
4
I: 0; O: 1
X
X
X
0
X
X
X
0
0
0
0
0
0
1
1
0
X
0
1
X
(2)
XIN crystal mode
XIN bypass mode
PJ.5 (I/O)
X
X
(2)
PJ.5/XOUT
5
I: 0; O: 1
XOUT crystal mode
X
X
X
X
X
0
0
1
1
0
1
(2)
(3)
PJ.5 (I/O)
I: 0; O: 1
(1) X = Don't care
(2) Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When XT1BYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are do not care. When XT1BYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
(3) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
80
Input/Output Schematics
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
7 Device Descriptors (TLV)
Table 7-1 and Table 7-2 list the complete contents of the device descriptor tag-length-value (TLV)
structure for each device type.
(1)
Table 7-1. Device Descriptor Table
FR5739
Value
05h
FR5738
Value
05h
FR5737
Value
05h
FR5736
Value
05h
FR5735
Value
05h
Description
Address
Info Block
Info length
01A00h
01A01h
01A02h
01A03h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
CRC length
05h
05h
05h
05h
05h
per unit
per unit
03h
per unit
per unit
02h
per unit
per unit
01h
per unit
per unit
77h
per unit
per unit
76h
CRC value
Device ID
Device ID
81h
81h
81h
81h
81h
Hardware revision
Firmware revision
Die Record Tag
Die Record length
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
Die Record
0Ah
0Ah
0Ah
0Ah
0Ah
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Lot/Wafer ID
Die X position
Die Y position
Test results
ADC10
Calibration
ADC10 Calibration
Tag
01A14h
01A15h
13h
10h
13h
10h
13h
10h
05h
10h
13h
10h
ADC10 Calibration
length
01A16h
01A17h
01A18h
01A19h
01A1Ah
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
ADC Gain Factor
ADC Offset
ADC 1.5-V
Reference
01A1Bh
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Temp. Sensor 30°C
ADC 1.5-V
Reference
Temp. Sensor 85°C
ADC 2.0-V
Reference
Temp. Sensor 30°C
ADC 2.0-V
Reference
Temp. Sensor 85°C
ADC 2.5-V
Reference
Temp. Sensor 30°C
(1) NA = Not applicable
Copyright © 2014, Texas Instruments Incorporated
Device Descriptors (TLV)
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Table 7-1. Device Descriptor Table (1) (continued)
FR5739
Value
FR5738
Value
FR5737
Value
NA
FR5736
Value
NA
FR5735
Value
Description
Address
ADC 2.5-V
Reference
Temp. Sensor 85°C
01A24h
01A25h
per unit
per unit
per unit
per unit
12h
per unit
12h
NA
NA
per unit
12h
REF
Calibration
REF Calibration Tag
01A26h
01A27h
12h
12h
REF Calibration
length
06h
06h
06h
06h
06h
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 1.5-V
Reference
REF 2.0-V
Reference
REF 2.5-V
Reference
(1)
Table 7-2. Device Descriptor Table
FR5734
Value
05h
FR5733
Value
05h
FR5732
Value
05h
FR5731
Value
05h
FR5730
Value
05h
Description
Address
Info Block
Info length
01A00h
01A01h
01A02h
01A03h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Bh
01A0Ch
01A0Dh
01A0Eh
01A0Fh
01A10h
01A11h
01A12h
01A13h
CRC length
05h
05h
05h
05h
05h
per unit
per unit
00h
per unit
per unit
7Fh
per unit
per unit
75h
per unit
per unit
7Eh
per unit
per unit
7Ch
CRC value
Device ID
Device ID
81h
80h
81h
80h
80h
Hardware revision
Firmware revision
Die Record Tag
Die Record length
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
per unit
per unit
08h
Die Record
0Ah
0Ah
0Ah
0Ah
0Ah
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
Lot/Wafer ID
Die X position
Die Y position
Test results
ADC10
Calibration
ADC10 Calibration
Tag
01A14h
01A15h
13h
10h
13h
10h
13h
10h
05h
10h
13h
10h
ADC10 Calibration
length
01A16h
01A17h
01A18h
01A19h
01A1Ah
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC Gain Factor
ADC Offset
ADC 1.5-V
Reference
Temp. Sensor 30°C
01A1Bh
per unit
NA
NA
per unit
per unit
(1) NA = Not applicable
82 Device Descriptors (TLV)
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ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
Table 7-2. Device Descriptor Table (1) (continued)
FR5734
Value
FR5733
Value
NA
FR5732
Value
NA
FR5731
Value
FR5730
Value
Description
Address
ADC 1.5-V
Reference
Temp. Sensor 85°C
01A1Ch
01A1Dh
01A1Eh
01A1Fh
01A20h
01A21h
01A22h
01A23h
01A24h
01A25h
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
ADC 2.0-V
Reference
Temp. Sensor 30°C
ADC 2.0-V
Reference
Temp. Sensor 85°C
ADC 2.5-V
Reference
Temp. Sensor 30°C
ADC 2.5-V
Reference
Temp. Sensor 85°C
REF
Calibration
REF Calibration Tag
01A26h
01A27h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
REF Calibration
length
01A28h
01A29h
01A2Ah
01A2Bh
01A2Ch
01A2Dh
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
per unit
REF 1.5-V
Reference
REF 2.0-V
Reference
REF 2.5-V
Reference
版权 © 2014, Texas Instruments Incorporated
Device Descriptors (TLV)
83
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8 器件和文档支持
8.1 器件支持
8.1.1 开始使用
TI 还提供了立即入门必备的所有硬件平台和软件组件以及工具！ 不仅如此，TI 还拥有众多辅助组件以满足
您的需求。 要获得 MSP430™ MCU 产品线、可用开发工具和评估套件，以及高级开发资源，请访问
MSP430 入门网页。
8.1.2 Development Tools Support
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development
tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
8.1.2.1 Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
Break-
points
(N)
Range
Break-
points
LPMx.5
Debugging
Support
MSP430
Architecture
4-Wire
JTAG
2-Wire
JTAG
Clock
Control
State
Sequencer
Trace
Buffer
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
Yes
8.1.2.2 Recommended Hardware Options
8.1.2.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also
feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the
JTAG programmer and debugger included. The following table shows the compatible target boards and
the supported packages.
Package
Target Board and Programmer Bundle
Target Board Only
40-pin VQFN (RHA)
MSP-FET430U40A
MSP-TS430RHA40A
8.1.2.2.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. See
www.ti.com/msp430tools for details.
8.1.2.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See
the full list of available tools at www.ti.com/msp430tools.
8.1.2.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
Part Number
PC Port
Features
Provider
MSP-GANG
Serial and USB
Program up to eight devices at a time. Works with PC or standalone.
Texas Instruments
8.1.2.3 Recommended Software Options
8.1.2.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also
available.
This device is supported by Code Composer Studio™ IDE (CCS).
84
器件和文档支持
版权 © 2014, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5739-EP
MSP430FR5739-EP
www.ti.com.cn
ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
8.1.2.3.2 MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430
devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware also includes a high-level API called MSP430 Driver Library.
This library makes it easy to program MSP430 hardware. MSP430Ware is available as a component of
CCS or as a standalone package.
8.1.2.3.3 Command-Line Programmer
MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers
through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher
can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the
need for an IDE.
8.1.3 器件和开发工具命名规则
为了指明产品开发周期所处的阶段，TI 为所有 MSP430 MCU 器件和支持工具的产品型号分配了前缀。 每
个
MSP430
MCU
商用系列产品成员具有以下三个前缀中的一个：MSP，PMS
或
XMS（例
如，MSP430F5259）。 德州仪器 (TI) 建议为其支持的工具使用三个可能前缀指示符中的两个：MSP 和
MSPX。 这些前缀代表了产品从工程原型机（其中 XMS 针对器件，而 MSPX 针对工具）直到完全合格的生
产器件和工具（其中 MSP 针对器件，而 MSP 针对工具）的产品开发进化阶段。
器件开发进化流程：
XMS - 试验器件不一定代表最终器件的电气技术规格
PMS - 最终的芯片模型符合器件的电气技术规格，但是未经完整的质量和可靠性验证
MSP - 完全合格的生产器件
支持工具开发进化流程：
MSPX - 还未经德州仪器 (TI) 完整内部质量测试的开发支持产品。
MSP – 完全合格的开发支持产品
XMS 和 PMS 器件和 MSPX 开发支持工具在供货时附带如下免责条款：
“开发的产品用于内部评估用途。”
MSP 器件和 MSP 开发支持工具已进行完全特性描述，并且器件的质量和可靠性已经完全论证。 TI 的标准
保修证书适用。
预测显示原型器件（XMS 和 PMS）的故障率大于标准生产器件。 由于它们的预计的最终使用故障率仍未定
义，德州仪器 (TI) 建议不要将这些器件用于任何生产系统。 只有合格的产品器件将被使用。
TI 器件的命名规则也包括一个带有器件系列名称的后缀。 这个后缀包括封装类型（例如，PZP）和温度范
围（如，T）。图 8-1 提供了读取任一系列产品成员完整器件名称的图例。
版权 © 2014, Texas Instruments Incorporated
器件和文档支持
85
提交文档反馈意见
产品主页链接: MSP430FR5739-EP
MSP430FR5739-EP
ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
www.ti.com.cn
MSP 430 F 5 438 A I ZQW T XX
Processor Family
430 MCU Platform
Device Type
Series
Feature Set
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: A = Revision
Processor Family
CC = Embedded RF Radio
MSP = Mixed Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
430 MCU Platform
Device Type
TI’s Low Power Microcontroller Platform
Memory Type
C = ROM
F = Flash
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
FR = FRAM
G = Flash or FRAM (Value Line) CG = ROM Medical
L = No Nonvolatile Memory
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz w/ LCD
0 = Low Voltage Series
4 Series = Up to 16 MHz w/ LCD
Feature Set
Various Levels of Integration Within a Series
N/A
Optional: A = Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = -40°C to 85°C
T = -40°C to 105°C
Packaging
www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel
R = Large Reel
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (-40°C to 105°C)
-HT = Extreme Temperature Parts (-55°C to 150°C)
-Q1 = Automotive Q100 Qualified
图 8-1. 器件命名规则
8.2 文档支持
以下文档描述了 MSP430FR5739-EP MCU。 www.ti.com.cn 网站上提供了这些文档的副本。
SLAU272
SLAZ392
MSP430FR57xx 系列用户指南。 这款器件系列内所提供的全部模块和外设的详细信息。
MSP430FR5739 器件勘误表。 描述了针对这款器件每个芯片修订版本功能技术规格的已知例
外情况。
SLAZ391
SLAZ390
SLAZ389
SLAZ388
SLAZ387
MSP430FR5738 器件勘误表。 描述了针对这款器件每个芯片修订版本功能技术规格的已知例
外情况。
MSP430FR5737 器件勘误表。 描述了针对这款器件每个芯片修订版本功能技术规格的已知例
外情况。
MSP430FR5736 器件勘误表。 描述了针对这款器件每个芯片修订版本功能技术规格的已知例
外情况。
MSP430FR5735 器件勘误表。 描述了针对这款器件每个芯片修订版本功能技术规格的已知例
外情况。
MSP430FR5734 器件勘误表。 描述了针对这款器件每个芯片修订版本功能技术规格的已知例
外情况。
SLAZ386
MSP430FR5733 器件勘误表。 描述了针对这款器件每个芯片修订版本功能技术规格的已知例
86
器件和文档支持
版权 © 2014, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: MSP430FR5739-EP
MSP430FR5739-EP
www.ti.com.cn
ZHCSD33A –NOVEMBER 2014–REVISED DECEMBER 2014
外情况。
SLAZ385
MSP430FR5732 器件勘误表。 描述了针对这款器件每个芯片修订版本功能技术规格的已知例
外情况。
SLAZ384
SLAZ383
MSP430FR5731 器件勘误表。 描述了针对这款器件每个芯片修订版本功能技术规格的已知例
外情况。
MSP430FR5730 器件勘误表。 描述了针对这款器件每个芯片修订版本功能技术规格的已知例
外情况。
8.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.4 商标
MSP430, Code Composer Studio, E2E are trademarks of Texas Instruments.
is a trademark of ~ Texas Instruments.
All other trademarks are the property of their respective owners.
8.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
9 机械封装和可订购信息
9.1 封装信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知
且不对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014, Texas Instruments Incorporated
机械封装和可订购信息
87
提交文档反馈意见
产品主页链接: MSP430FR5739-EP
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
250
250
(1)
(2)
(3)
(4/5)
(6)
M430FR5739SRHATEP
V62/14644-01XE
ACTIVE
VQFN
VQFN
RHA
40
40
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 85
-55 to 85
M430
FR5739EP
ACTIVE
RHA
NIPDAU
M430
FR5739EP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
OTHER QUALIFIED VERSIONS OF MSP430FR5739-EP :
Catalog: MSP430FR5739
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Feb-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
M430FR5739SRHATEP
VQFN
RHA
40
250
180.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Feb-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RHA 40
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
M430FR5739SRHATEP
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHA 40
6 x 6, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225870/A
www.ti.com
PACKAGE OUTLINE
RHA0040D
VQFN - 1 mm max height
S
C
A
L
E
2
.
2
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
0.5
0.3
6.1
5.9
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 4.5
(0.1) TYP
2.9 0.1
EXPOSED
THERMAL PAD
11
20
36X 0.5
10
21
2X
41
SYMM
4.5
1
30
SEE TERMINAL
DETAIL
0.3
0.2
0.1
40X
40
31
SYMM
C A
B
PIN 1 ID
(OPTIONAL)
0.5
0.3
40X
0.05
4225822/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHA0040D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.9)
SYMM
40
31
40X (0.6)
1
30
40X (0.25)
(1.2)
TYP
41
SYMM
(5.8)
36X (0.5)
(
0.2) TYP
VIA
21
10
(R0.05)
TYP
11
20
(5.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225822/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view.
www.ti.com
EXAMPLE STENCIL DESIGN
RHA0040D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(R0.05) TYP
SYMM
40
31
40X (0.6)
1
30
4X ( 1.27)
40X (0.25)
(0.735) TYP
(0.735)
TYP
41
SYMM
(5.8)
36X (0.5)
METAL
TYP
21
10
20
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
76.46% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4225822/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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相关型号：
MSP430FR58471IRHAR
具有 32KB FRAM、1KB SRAM、12 位 ADC、比较器、DMA、UART/SPI/I2C 和计时器的 16MHz MCU | RHA | 40 | -40 to 85
TI
MSP430FR58471IRHAT
具有 32KB FRAM、1KB SRAM、12 位 ADC、比较器、DMA、UART/SPI/I2C 和计时器的 16MHz MCU | RHA | 40 | -40 to 85
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