MSP430FR4132IG48R [TI]
具有 8KB FRAM、1KB SRAM、10 位 ADC、LCD、UART/SPI/I2C、红外逻辑和计时器的 16MHz MCU | DGG | 48 | -40 to 85;型号: | MSP430FR4132IG48R |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 8KB FRAM、1KB SRAM、10 位 ADC、LCD、UART/SPI/I2C、红外逻辑和计时器的 16MHz MCU | DGG | 48 | -40 to 85 时钟 CD 微控制器 静态存储器 光电二极管 外围集成电路 装置 |
文件: | 总109页 (文件大小:3072K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MSP430FR4133, MSP430FR4132, MSP430FR4131
ZHCSDF6F –OCTOBER 2014 –REVISED DECEMBER 2021
MSP430FR413x 混合信号微控制器
• 时钟系统(CS)
1 特性
– 片上32kHz RC 振荡器(REFO)
– 带有锁频环(FLL) 的片上16MHz 数控振荡器
(DCO)
• 嵌入式微控制器
– 频率高达16MHz 的16 位精简指令集计算机
(RISC) 架构
– 1.8V 至3.6V 的宽电源电压范围(最低电源电压
受限于SVS 电平,请参阅节8.12.1.1)
• 经优化的低功耗模式(3V)
– 工作模式:126µA/MHz
• 室温下的精度为±1%(具有片上基准)
– 片上超低频10kHz 振荡器(VLO)
– 片上高频调制振荡器时钟(MODCLK)
– 外部32kHz 晶振(XT1)
– 可编程MCLK 预分频器(1 至128)
– 通过可编程预分频器(1、2、4 或8)从MCLK
获得的SMCLK
– 待机模式:<1µA,实时时钟(RTC) 计数器和液
晶显示器(LCD) 处于工作状态
– 关断(LPM4.5):15nA
• 通用输入/输出和引脚功能
• 高性能模拟
– 60 个I/O(64 引脚封装)
– 16 个中断引脚(P1 和P2)可以将MCU 从
LPM 唤醒
– 10 通道10 位模数转换器(ADC)
• 1.5V 的内部基准电压
• 采样与保持200ksps
– 低功耗LCD 驱动器
– 所有I/O 均为电容式触摸I/O
• 开发工具和软件
– 开发套件(MSP-EXP430FR4133 LaunchPad™
开发套件和MSP‑TS430PM64D 目标开发板)
– 免费软件(MSP430Ware™ 软件)
• 系列成员(另请参阅节6)
• 支持高达4×36 段或8×32 段LCD 配置
• 片上电荷泵,在待机模式(LPM3.5) 下可使
LCD 保持激活状态
• 每个LCD 引脚均可通过软件配置为SEG 或
COM
• 在2.6V 至3.5V 范围内提供对比度控制(阶
跃为0.06V)
– MSP430FR4133:15KB 程序FRAM + 512B 信
息FRAM + 2KB RAM
– MSP430FR4132:8KB 程序FRAM + 512B 信
息FRAM + 1KB RAM
• 低功耗铁电RAM (FRAM)
– 容量高达15.5KB 的非易失性存储器
– 内置错误修正码(ECC)
– 可配置的写保护
– MSP430FR4131:4KB 程序FRAM + 512B 信
息FRAM + 512B RAM
• 封装选项
– 对程序、常量和存储的统一存储
– 耐写次数达1015 次
– 抗辐射和非磁性
– 64 引脚:LQFP (PM)
– 56 引脚:TSSOP (G56)
– 48 引脚:TSSOP (G48)
• 智能数字外设
2 应用
– 红外调制逻辑
– 两个16 位定时器,每个定时器有3 个捕捉/比较
寄存器(Timer_A3)
• 遥控
• 恒温器
– 一个仅用作计数器的16 位RTC 计数器
– 16 位循环冗余校验器(CRC)
• 增强型串行通信
• 水表
• 热量计
• 燃气表
• 一次性密码令牌
• 血糖监测仪
• 血压监护仪
– 增强型USCI A (eUSCI_A) 支持UART、IrDA
和SPI
– 增强型USCI B (eUSCI_B) 支持SPI 和I2C
3 说明
MSP430FR41xx 超低功耗 (ULP) 微控制器系列支持低成本 LCD 应用,如远程控制、恒温器、智能仪表、血糖监
测仪和血压监测仪等,该系列器件的集成 10 位 ADC 对这些应用的性能提升大有帮助。MCU 具有功能强大的 16
位RISC CPU、16 位寄存器和常数发生器,有助于实现最大编码效率。数控振荡器(DCO) 可使器件在不到10μs
的时间内从低功耗模式唤醒至活动模式。此架构与多种低功耗模式配合使用,是延长便携式测量应用电池寿命的
最优选择。
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLAS865
MSP430FR4133, MSP430FR4132, MSP430FR4131
ZHCSDF6F –OCTOBER 2014 –REVISED DECEMBER 2021
www.ti.com.cn
MSP430™ 微控制器平台将独特的嵌入式铁电随机存取存储器 (FRAM) 和全面的超低功耗系统架构相结合,从而
使系统设计人员能够在降低能耗的同时提升性能。FRAM 技术将 RAM 的低功耗快速写入、灵活性和耐用性与闪
存的非易失性相结合。
MSP430FR41x MCU 由一个由各种软、硬件资源组成的生态系统提供支持,并配套提供有参考设计和代码示例,
可帮助您快速开展设计。适用于 MSP430FR41xx 的开发套件包括 MSP-EXP430FR4133 LaunchPad™ 开发套件
和 MSP-TS430PM64D 64 引脚目标开发板。TI 还提供免费的 MSP430Ware™ 软件,该软件以 Code Composer
Studio™ IDE 桌面和云版本组件的形式提供(位于TI Resource Explorer 中)。我们为MSP430 MCU 提供广泛的
在线配套资料(例如内务处理型示例系列、MSP Academy 培训),也通过TI E2E™ 支持论坛提供在线支持。
有关完整的模块说明,请参阅《MSP430FR4xx 和MSP430FR2xx 系列器件用户指南》。
器件信息
器件型号(1)
MSP430FR4133IPM
MSP430FR4133IG56
MSP430FR4133IG48
封装尺寸(2)
10mm x 10mm
14mm x 6.1mm
12.5mm x 6.1mm
封装
LQFP (64)
TSSOP (56)
TSSOP (48)
(1) 要获得最新的产品、封装和订购信息,请参阅节12 中的封装选项附录,或者访问德州仪器(TI) 网站
www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸,请参阅机械数据(节12 中)。
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4 功能方框图
图4-1 给出了功能方框图。
XIN
XOUT
P1.x/P2.x
P3.x/P4.x
P5.x/P6.x
P7.x/P8.x
Capacitive Touch I/O
XT1
ADC
FRAM
RAM
I/O Ports
P1, P2
2×8 IOs
Interrupt
and Wakeup
PA
I/O Ports
P3, P4
2×8 IOs
I/O Ports
P5, P6
2×8 IOs
I/O Ports
P7, P8
1×8 IOs
1×4 IOs
PD
DVCC
Up to 10-ch
Single-end
10-bit
Clock
System
Control
Power
Management
Module
15KB+512B
8KB+512B
4KB+512B
2KB
1KB
512B
DVSS
PB
1×16 IOs
PC
1×16 IOs
200 ksps
RST/NMI
1×12 IOs
1×16 IOs
MAB
MDB
16-MHZ CPU
inc.
16 Registers
EEM
RTC
Counter
LCD
TA0
TA1
eUSCI_A0
eUSCI_B0
(SPI, I2C)
CRC16
TCK
TMS
TDI/TCLK
TDO
SBWTCK
SBWTDIO
4×36
8×32
Segments
SYS
16-bit
Real-Time
Clock
16-bit
Cyclic
Redundancy
Check
JTAG
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
(UART,
IrDA, SPI)
Watchdog
LPM3.5 Domain
SBW
图4-1. 功能方框图
• 该器件具有一对主电源(DVCC 和DVSS),分别为数字和模拟模块供电。推荐的旁路和去耦电容分别为
4.7μF 至10μF 和0.1μF,精度为±5%。
• P1 和P2 特有引脚中断功能,可将MCU 从LPM3.5 模式唤醒。
• 每个Timer_A3 均有3 个CC 寄存器,不过只有CCR1 和CCR2 从外部连接。CCR0 寄存器仅用于内部周期
时序和产生中断。
• 在LPM3.5 模式下,RTC 计数器与LCD 可继续工作,而其余外设会停止工作。
• 所有I/O 均可配置为电容式触摸I/O。
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Table of Contents
9 Detailed Description......................................................37
9.1 CPU.......................................................................... 37
9.2 Operating Modes...................................................... 37
9.3 Interrupt Vector Addresses....................................... 38
9.4 Bootloader (BSL)...................................................... 39
9.5 JTAG Standard Interface.......................................... 39
9.6 Spy-Bi-Wire Interface (SBW).................................... 40
9.7 FRAM........................................................................40
9.8 Memory Protection....................................................40
9.9 Peripherals................................................................41
9.10 Device Descriptors (TLV)........................................67
9.11 Memory................................................................... 68
9.12 Identification............................................................76
10 Applications, Implementation, and Layout............... 77
10.1 Device Connection and Layout Fundamentals....... 77
10.2 Peripheral- and Interface-Specific Design
Information.................................................................. 80
10.3 Typical Applications................................................ 85
11 Device and Documentation Support..........................86
11.1 Getting Started........................................................86
11.2 Device Nomenclature..............................................86
11.3 Tools and Software..................................................87
11.4 Documentation Support.......................................... 89
11.5 支持资源..................................................................90
11.6 Trademarks............................................................. 91
11.7 Electrostatic Discharge Caution..............................91
11.8 Export Control Notice..............................................91
11.9 术语表..................................................................... 91
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 功能方框图.........................................................................3
5 Revision History.............................................................. 5
6 Device Comparison.........................................................7
6.1 Related Products........................................................ 7
7 Terminal Configuration and Functions..........................8
7.1 Pin Diagrams ............................................................. 8
7.2 Signal Descriptions................................................... 11
7.3 Pin Multiplexing.........................................................13
7.4 Connection of Unused Pins...................................... 14
8 Specifications................................................................ 15
8.1 Absolute Maximum Ratings...................................... 15
8.2 ESD Ratings............................................................. 15
8.3 Recommended Operating Conditions.......................15
8.4 Active Mode Supply Current Into VCC Excluding
External Current.......................................................... 16
8.5 Active Mode Supply Current Per MHz...................... 16
8.6 Low-Power Mode LPM0 Supply Currents Into
VCC Excluding External Current.................................. 16
8.7 Low-Power Mode LPM3, LPM4 Supply Currents
(Into VCC) Excluding External Current.........................17
8.8 Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current................................. 18
8.9 Typical Characteristics, Low-Power Mode
Supply Currents...........................................................19
8.10 Current Consumption Per Module.......................... 20
8.11 Thermal Characteristics.......................................... 20
8.12 Timing and Switching Characteristics..................... 21
Information.................................................................... 92
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5 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from revision E to revision F
Changes from December 9, 2019 to December 8, 2021
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
• Added 节10.2.3.1 Generate Accurate PWM Using Internal Oscillator ............................................................83
Changes from revision D to revision E
Changes from January 22, 2019 to December 9, 2019
Page
• Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in 节
8.3, Recommended Operating Conditions .......................................................................................................15
• Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in 节
8.3, Recommended Operating Conditions .......................................................................................................15
• Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in 节8.3,
Recommended Operating Conditions ..............................................................................................................15
• Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to
节8.12.3.1, XT1 Crystal Oscillator (Low Frequency) ...................................................................................... 23
• Changed the note that begins "Requires external capacitors at both terminals..." in 节8.12.3.1, XT1 Crystal
Oscillator (Low Frequency) ..............................................................................................................................23
• Added the t(int) parameter in 节8.12.4.1, Digital Inputs ................................................................................... 26
• Added the tTA,capparameter in 节8.12.5.1, Timer_A ........................................................................................27
• Corrected the test conditions for the RI,MUX parameter in 节8.12.7.1, ADC, Power Supply and Input Range
Conditions ........................................................................................................................................................33
• Added the note that begins "tSample = ln(2n+1) × τ..." in 节8.12.7.2, ADC, 10-Bit Timing Parameters ..........33
Changes from revision C to revision D
Changes from August 30, 2018 to January 21, 2019
Page
• 通篇将“调制振荡器(MODOSC)”更改为“调制振荡器时钟(MODCLK)”...................................................... 1
• Added "or memory corruption" in table that starts "Stresses beyond those listed..." of 节8.1, Absolute
Maximum Ratings ............................................................................................................................................15
• Added note of VLO clock frequency shift in LPM3 and LPM4 mode in 节8.12.3.4, Internal Very-Low-Power
Low-Frequency Oscillator (VLO) ..................................................................................................................... 24
• Changed from RI to RI,MUX in 节8.12.7.1, ADC, Power Supply and Input Range Conditions .........................33
• Added RI,Misc TYP value 34kΩin 节8.12.7.1, ADC, Power Supply and Input Range Conditions ..................33
• Removed ADCDIV from the conversion time formula because ADCCLK is after division in 节8.12.7.2, ADC,
10-Bit Timing Parameters ................................................................................................................................33
• Added formula for RI calculation in 节8.12.7.2, ADC, 10-Bit Timing Parameters ........................................... 33
• Remove description of "±3°C" in table note that starts "The device descriptor structure ..." of 节8.12.7.3,
ADC, 10-Bit Linearity Parameters ....................................................................................................................34
• Add "10b" for ADCSSEL bit in 表9-6, Clock Distribution ................................................................................ 41
• Added "Clock Distribution Block Diagram" in 节9.9.2, Clock System (CS) and Clock Distribution .................41
• Corrected bitfield from IRDSEL to IRDSSEL in 节9.9.8, Timers (Timer0_A3, Timer1_A3), in the description
that starts "The interconnection of Timer0_A3 and ..."..................................................................................... 46
• Corrected the ADCINCHx column heading in 表9-12, ADC Channel Connections ........................................48
• Added word "Sensor" in 表9-27, Device Descriptors ......................................................................................67
• Added word "Sensor" in 表9-27, Device Descriptors ......................................................................................67
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Changes from revision B to revision C
Changes from August 15, 2015 to August 29, 2018
Page
• 节1 特性、节2 应用和节3 说明中的编辑更改和其他信息...............................................................................1
• Updated 节6.1, Related Products .....................................................................................................................7
• Added note to VSVSH- and VSVSH+ parameters in 节8.12.1.1, PMM, SVS and BOR ...................................... 21
• Changed all instances of "bootstrap loader" to "bootloader"............................................................................ 39
• Updates to text and figure in 节11.2, Device Nomenclature ........................................................................... 86
Changes from revision A to revision B
Changes from December 20, 2014 to August 14, 2015
Page
• 将特性“待机模式”电流消耗从770nA 更改为1µA...........................................................................................1
• Added 节8.2, ESD Ratings ............................................................................................................................. 15
• Added ILPM3.5, LCD, CP TYP values at –40°C (0.90 µA) and at 85°C (1.27 µA)................................................ 18
• Added the paragraph that starts "The graphs in this section..."........................................................................19
• Changed all graphs in 节8.9, Typical Characteristics, Low-Power Mode Supply Currents, for new
measurements .................................................................................................................................................19
• Added VREF, 1.2V parameter to 节8.12.1.1, PMM, SVS and BOR ................................................................... 21
• Changed tSTE,LEAD MIN value at 2 V from 40 ns to 50 ns.................................................................................30
• Changed tSTE,LEAD MIN value at 3 V from 24 ns to 45 ns.................................................................................30
• Changed tVALID,SO MAX value at 2 V from 55 ns to 65 ns................................................................................ 30
• Changed tVALID,SO MAX value at 3 V from 30 ns to 40 ns................................................................................ 30
• Changed fADCOSC TYP value from 4.5 MHz to 5.0 MHz...................................................................................33
• In 表9-1, Operating Modes, changed the entry for "Power Consumption at 25°C, 3 V" in AM from
100 µA/MHz to 126 µA/MHz.............................................................................................................................37
• In 表9-1, Operating Modes, added "with RTC only" to the entry for "Power Consumption at 25°C, 3 V" in
LPM3.5............................................................................................................................................................. 37
• In 表9-2, Interrupt Sources, Flags, and Vectors, removed "FRAM access time error" (ACCTEIFG) from the
"System NMI" row ............................................................................................................................................38
• In 表9-8, System Module Interrupt Vector Registers, changed the interrupt event in the SYSSNIV row with a
VALUE of 06h from "ACCTEIFG access time error" to "Reserved"..................................................................43
• In 表9-27, Device Descriptors, added note to "CRC value".............................................................................67
Changes from initial release to revision A
Changes from October 3, 2014 to December 19, 2014
Page
• Moved Tstg to Absolute Maximum Ratings table and added note (3)............................................................... 15
• Changed link to BSL user's guide in 节9.4 ..................................................................................................... 39
• Added note (1) to 表9-6 .................................................................................................................................. 41
• Changed the values of ADC Calibration Tag and ADC Calibration Length in the ADC Calibration row...........67
• Added Calibration Tag, Calibration Length, and 1.5-V Reference in the Reference and DCO Calibration row....
67
• Added row for BSL memory to 表9-28 ............................................................................................................68
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6 Device Comparison
表6-1 summarizes the features of the available family members.
表6-1. Device Comparison
PROGRAM FRAM
+ INFORMATION
FRAM (BYTES)
SRAM
(BYTES)
10-BIT ADC
CHANNELS SEGMENTS
LCD
PACKAGE
TYPE
DEVICE(1) (2)
TA0, TA1
eUSCI_A
eUSCI_B
I/O
4 × 36
8 × 32
64 PM
(LQFP)
MSP430FR4133IPM
MSP430FR4132IPM
MSP430FR4131IPM
MSP430FR4133IG56
MSP430FR4132IG56
MSP430FR4131IG56
MSP430FR4133IG48
MSP430FR4132IG48
MSP430FR4131IG48
15360 + 512
8192 + 512
4096 + 512
15360 + 512
8192 + 512
4096 + 512
15360 + 512
8192 + 512
4096 + 512
2048
1024
512
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
3 × CCR(3)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10
60
60
60
52
52
52
44
44
44
4 × 36
8 × 32
64 PM
(LQFP)
10
4 × 36
8 × 32
64 PM
(LQFP)
10
4 × 30
8 × 26
56 DGG
(TSSOP56)
2048
1024
512
8
4 × 30
8 × 26
56 DGG
(TSSOP56)
8
4 × 30
8 × 26
56 DGG
(TSSOP56)
8
4 × 24
8 × 20
48 DGG
(TSSOP48)
2048
1024
512
8
4 × 24
8 × 20
48 DGG
(TSSOP48)
8
4 × 24
8 × 20
48 DGG
(TSSOP48)
8
(1) For the most current device, package, and ordering information, see the Package Option Addendum in 节12, or see the TI website at
www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/
packaging.
(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs.
6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing and measurement microcontrollers
One platform. One ecosystem. Endless possibilities.
Reference designs for MSP430FR4133
Find reference designs leveraging the best in TI technology – from analog and power management to
embedded processors
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7 Terminal Configuration and Functions
7.1 Pin Diagrams
图7-1 shows the pinout of the 64-pin PM package.
P4.7/R13
P4.6/R23
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P6.0/L16
P6.1/L17
P6.2/L18
P6.3/L19
P6.4/L20
P6.5/L21
P6.6/L22
P6.7/L23
P2.0/L24
P2.1/L25
P2.2/L26
P2.3/L27
P2.4/L28
P2.5/L29
P2.6/L30
P2.7/L31
2
P4.5/R33
3
P4.4/LCDCAP1
P4.3/LCDCAP0
P4.2/XOUT
4
5
6
P4.1/XIN
7
DVSS
8
DVCC
9
RST/NMI/SBWTDIO
TEST/SBWTCK
P4.0/TA1.1
10
11
12
13
14
15
16
P8.3/TA1.2
P8.2/TA1CLK
P8.1/ACLK/A9
P8.0/SMCLK/A8
图7-1. 64-Pin PM (LQFP) (Top View)
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图7-2 shows the pinout of the 56-pin DGG package.
P7.5/L5
P7.4/L4
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P3.0/L8
2
P3.1/L9
P7.3/L3
3
P3.2/L10
P7.2/L2
4
P3.3/L11
P7.1/L1
5
P3.4/L12
P7.0/L0
6
P3.5/L13
P4.7/R13
7
P3.6/L14
P4.6/R23
8
P3.7/L15
P4.5/R33
9
P6.0/L16
P4.4/LCDCAP1
P4.3/LCDCAP0
P4.2/XOUT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P6.1/L17
P6.2/L18
P6.3/L19
P4.1/XIN
P6.4/L20
DVSS
P6.5/L21
DVCC
P2.0/L24
RST/NMI/SBWTDIO
TEST/SBWTCK
P4.0/TA1.1
P2.1/L25
P2.2/L26
P2.3/L27
P8.3/TA1.2
P2.4/L28
P8.2/TA1CLK
P2.5/L29
P1.7/TA0.1/TDO/A7
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
P1.4/MCLK/TCK/A4/VREF+
P1.3/UCA0STE/A3
P1.2/UCA0CLK/A2
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–
P2.6/L30
P2.7/L31
P5.0/UCB0STE/L32
P5.1/UCB0CLK/L33
P5.2/UCB0SIMO/UCB0SDA/L34
P5.3/UCB0SOMI/UCB0SCL/L35
P5.4/L36
P5.5/L37
图7-2. 56-Pin DGG (TSSOP) (Top View)
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图7-3 shows the pinout of the 48-pin DGG package.
P3.1/L9
P3.0/L8
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P3.2/L10
2
P3.3/L11
P7.3/L3
3
P3.4/L12
P7.2/L2
4
P3.5/L13
P7.1/L1
5
P3.6/L14
P7.0/L0
6
P3.7/L15
P4.7/R13
7
P6.0/L16
P4.6/R23
8
P6.1/L17
P4.5/R33
9
P6.2/L18
P4.4/LCDCAP1
P4.3/LCDCAP0
P4.2/XOUT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P6.3/L19
P2.0/L24
P2.1/L25
P4.1/XIN
P2.2/L26
DVSS
P2.3/L27
DVCC
P2.4/L28
RST/NMI/SBWTDIO
TEST/SBWTCK
P4.0/TA1.1
P2.5/L29
P2.6/L30
P2.7/L31
P1.7/TA0.1/TDO/A7
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
P1.4/MCLK/TCK/A4/VREF+
P1.3/UCA0STE/A3
P1.2/UCA0CLK/A2
P5.0/UCB0STE/L32
P5.1/UCB0CLK/L33
P5.2/UCB0SIMO/UCB0SDA/L34
P5.3/UCB0SOMI/UCB0SCL/L35
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
图7-3. 48-Pin DGG (TSSOP) Designation
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7.2 Signal Descriptions
节7.2 describes the signals for all device variants and package options.
表7-1. Signal Descriptions
TERMINAL
PACKAGE SUFFIX
I/O
DESCRIPTION
NAME
PM
G56
G48
General-purpose I/O
Input/output port of third most positive analog LCD voltage V4
P4.7/R13
P4.6/R23
P4.5/R33
1
2
3
7
7
8
9
I/O
I/O
I/O
General-purpose I/O
Input/output port of second most positive analog LCD voltage V2
8
9
General-purpose I/O
Input/output port of first most positive analog LCD voltage V1
General-purpose I/O
P4.4/LCDCAP1
P4.3/LCDCAP0
4
5
10
11
10
11
I/O
I/O
LCD charge pump external port connecting to LCDCAP0 pin by 0.1‑µF
capacitor
General-purpose I/O
LCD charge pump external port connecting to LCDCAP1 pin by 0.1‑µF
capacitor
General-purpose I/O
Output terminal for crystal oscillator
P4.2/XOUT
P4.1/XIN
6
7
12
13
12
13
I/O
I/O
General-purpose I/O
Input terminal for crystal oscillator
DVSS
DVCC
8
9
14
15
14
15
Power ground
Power supply
Reset input active low
RST/NMI/SBWTDIO
10
16
16
I/O
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
Test Mode pin –selected digital I/O on JTAG pins
Spy-Bi-Wire input clock
TEST/SBWTCK
P4.0/TA1.1
11
12
13
14
17
18
19
20
17
18
–
–
I
General-purpose I/O
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
I/O
I/O
I/O
General-purpose I/O
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
P8.3/TA1.2(1)
P8.2/TA1CLK(1)
General-purpose I/O
Timer clock input TACLK for TA1
General-purpose I/O
ACLK output
Analog input A9
P8.1/ACLK/A9(1)
15
16
I/O
I/O
–
–
–
–
General-purpose I/O
SMCLK output
P8.0/SMCLK/A8(1)
Analog input A8
General-purpose I/O(2)
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
Test data output
Analog input A7
P1.7/TA0.1/TDO/A7
17
18
19
21
22
23
19
20
21
I/O
I/O
I/O
General-purpose I/O(2)
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
Test data input or test clock input
Analog input A6
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
General-purpose I/O(2)
Timer clock input TACLK for TA0
Test mode select
Analog input A5
General-purpose I/O(2)
MCLK output
P1.4/MCLK/TCK/A4/VREF+
P1.3/UCA0STE/A3
20
21
24
25
22
23
I/O
I/O
Test clock
Analog input A4
Output of positive reference voltage with ground as reference
General-purpose I/O
eUSCI_A0 SPI slave transmit enable
Analog input A3
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表7-1. Signal Descriptions (continued)
TERMINAL
PACKAGE SUFFIX
I/O
I/O
I/O
DESCRIPTION
NAME
PM
G56
G48
General-purpose I/O
P1.2/UCA0CLK/A2
22
23
26
24
25
eUSCI_A0 SPI clock input/output
Analog input A2
General-purpose I/O
P1.1/UCA0RXD/UCA0SOMI/ A1/
Veref+
eUSCI_A0 UART receive data
eUSCI_A0 SPI slave out/master in
Analog input A1, and ADC positive reference
27
28
General-purpose I/O
P1.0/UCA0TXD/UCA0SIMO/ A0/
Veref-
eUSCI_A0 UART transmit data
eUSCI_A0 SPI slave in/master out
Analog input A0, and ADC negative reference
24
26
I/O
General-purpose I/O
LCD drive pin; either segment or common output
P5.7/L39(1)
P5.6/L38(1)
P5.5/L37(1)
P5.4/L36(1)
25
26
27
28
I/O
I/O
I/O
I/O
–
–
29
30
–
–
–
–
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
P5.3/UCB0SOMI/UCB0SCL/L35
P5.2/UCB0SIMO/UCB0SDA/L34
P5.1/UCB0CLK/L33
29
30
31
32
31
32
33
34
27
28
29
30
I/O
I/O
I/O
I/O
eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock
LCD drive pin; either segment or common output
General-purpose I/O
eUSCI_B0 SPI slave in/master out; eUSCI_B0 I2C data
LCD drive pin; either segment or common output
General-purpose I/O
eUSCI_B0 clock input/output
LCD drive pin; either segment or common output
General-purpose I/O
eUSCI_B0 slave transmit enable
LCD drive pin; either segment or common output
P5.0/UCB0STE/L32
General-purpose I/O
LCD drive pin; either segment or common output
P2.7/L31
P2.6/L30
P2.5/L29
P2.4/L28
P2.3/L27
P2.2/L26
P2.1/L25
P2.0/L24
P6.7/L23(1)
P6.6/L22(1)
P6.5/L21(1)
P6.4/L20(1)
P6.3/L19
P6.2/L18
33
34
35
36
37
38
39
40
41
42
43
44
45
46
35
36
37
38
39
40
41
42
31
32
33
34
35
36
37
38
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
–
–
43
44
45
46
–
–
–
–
39
40
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
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表7-1. Signal Descriptions (continued)
TERMINAL
PACKAGE SUFFIX
I/O
DESCRIPTION
NAME
PM
G56
G48
General-purpose I/O
LCD drive pin; either segment or common output
P6.1/L17
P6.0/L16
P3.7/L15
P3.6/L14
P3.5/L13
P3.4/L12
P3.3/L11
P3.2/L10
P3.1/L9
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
47
41
42
43
44
45
46
47
48
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose I/O
LCD drive pin; either segment or common output
48
49
50
51
52
53
54
55
56
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
P3.0/L8
2
General-purpose I/O
LCD drive pin; either segment or common output
P7.7/L7(1)
P7.6/L6(1)
P7.5/L5(1)
P7.4/L4(1)
P7.3/L3
–
–
1
–
–
–
–
3
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
General-purpose I/O
LCD drive pin; either segment or common output
2
General-purpose I/O
LCD drive pin; either segment or common output
3
General-purpose I/O
LCD drive pin; either segment or common output
P7.2/L2
4
4
General-purpose I/O
LCD drive pin; either segment or common output
P7.1/L1
5
5
General-purpose I/O
LCD drive pin; either segment or common output
P7.0/L0
6
6
(1) Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.
(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
7.3 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the
device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see 节
9.9.13.
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7.4 Connection of Unused Pins
表7-2 shows the correct termination of unused pins.
表7-2. Connection of Unused Pins
PIN(1)
Px.0 to Px.7
RST/NMI
TEST
POTENTIAL
Open
COMMENT
Switched to port function, output direction (PxDIR.n = 1)
47-kΩ pullup or internal pullup selected with 10-nF (1.1-nF) pulldown(2)
This pin always has an internal pulldown enabled.
DVCC
Open
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Voltage applied at DVCC pin to VSS
Voltage applied to any pin(2)
4.1
V
–0.3
VCC + 0.3
(4.1 Max)
V
–0.3
Diode current at any device pin
±2
85
mA
°C
Maximum junction temperature, TJ
(3)
Storage temperature, Tstg
125
°C
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage or memory corruption to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
(2) All voltages referenced to VSS
.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
8.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.
8.3 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
NOM
MAX UNIT
VCC
VSS
TA
Supply voltage applied at DVCC pin(1) (2) (3)
Supply voltage applied at DVSS pin
Operating free-air temperature
1.8(6)
3.6
V
V
0
85
85
°C
°C
µF
–40
–40
4.7
TJ
Operating junction temperature
CDVCC
Recommended capacitor at DVCC(5)
10
No FRAM wait states
(NWAITSx = 0)
0
0
8
fSYSTEM Processor frequency (maximum MCLK frequency)(6) (4)
MHz
kHz
With FRAM wait states
(NWAITSx = 1)(7)
16(8)
40
fACLK
Maximum ACLK frequency
Maximum SMCLK frequency
fSMCLK
16(8) MHz
(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following
the data sheet recommendation for capacitor CDVCC limits the slopes accordingly.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding
the specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.
(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(5) A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as
possible (within a few millimeters) to the respective pin pair.
(6) The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in 节8.12.1.1.
(7) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
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(8) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
8.4 Active Mode Supply Current Into VCC Excluding External Current
See (1)
Frequency (fMCLK = fSMCLK
)
1 MHz
0 WAIT STATES
(NWAITSx = 0)
8 MHz
0 WAIT STATES
(NWAITSx = 0)
16 MHz
1 WAIT STATE
(NWAITSx = 1)
EXECUTION
MEMORY
TEST
CONDITIONS
PARAMETER
UNIT
TYP
504
516
209
217
231
MAX
TYP
2874
2919
633
MAX
TYP
3156
3205
1056
1074
1450
MAX
3 V, 25°C
3 V, 85°C
3 V, 25°C
3 V, 85°C
3 V, 25°C
3700
1298
FRAM
0% cache hit ratio
IAM, FRAM(0%)
µA
FRAM
100% cache hit ratio
IAM, FRAM(100%)
µA
µA
647
(2)
IAM, RAM
RAM
809
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32786 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
(2) Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
8.5 Active Mode Supply Current Per MHz
VCC = 3 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
UNIT
((IAM, 75% cache hit rate at 8 MHz) –
(IAM, 75% cache hit rate at 1 MHz))
/ 7 MHz
Active mode current consumption per MHz,
execution from FRAM, no wait states(1)
dIAM,FRAM/df
126
µA/MHz
(1) All peripherals are turned on in default settings.
8.6 Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
VCC = 3 V, TA = 25°C (unless otherwise noted)(1) (2)
FREQUENCY (fSMCLK
)
PARAMETER
VCC
1 MHz
TYP
8 MHz
16 MHz
UNIT
MAX
TYP
307
318
MAX
TYP
MAX
2 V
3 V
158
169
415
427
ILPM0
Low-power mode LPM0 supply current
µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
fACLK = 32786 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
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8.7 Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
25°C
85°C
–40°C
TYP MAX
PARAMETER
VCC
UNIT
µA
TYP
MAX
TYP
MAX
3 V
2 V
3 V
2 V
3 V
3 V
3 V
2 V
3 V
2 V
1.13
1.06
0.92
0.86
1.07
1.08
0.65
0.63
0.51
0.50
1.31
1.21
1.00
1.00
1.25
1.25
0.75
0.73
0.58
0.57
1.99
3.00
2.94
2.89
2.75
3.04
3.04
1.88
1.85
1.51
1.49
ILPM3,XT1
Low-power mode 3, includes SVS(2) (3) (4)
Low-power mode 3, VLO, excludes SVS(5)
1.75
ILPM3,VLO
µA
ILPM3, LCD, CP
ILPM3, RTC
Low-power mode 3, LCD, excludes SVS(6)
Low-power mode 3, RTC, excludes SVS(7)
µA
µA
ILPM4, SVS
Low-power mode 4, includes SVS
Low-power mode 4, excludes SVS
µA
µA
ILPM4
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a Golledge MS1V-TK/I_32.768KHZ crystal with a load capacitance chosen to closely match the required load.
(4) Low-power mode 3, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(6) LCD works in LPM3 if internal charge pump and VREF switch mode are enabled. LCD driver pins are configured as 4 × 36 at 32‑Hz
frame frequency with external 32768‑Hz clock source.
(7) RTC periodically wakes up every second with external 32768‑Hz as source.
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8.8 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
25°C
85°C
–40°C
TYP MAX
PARAMETER
VCC
UNIT
MAX
TYP
MAX
TYP
Low-power mode 3.5, includes SVS(1) (2) (3)
(also see 图8-3)
3 V
2 V
3 V
3 V
2 V
3 V
2 V
0.71
0.66
0.77
0.70
0.94
1.25
1.06
0.95
1.27
0.32
0.24
2.06
µA
ILPM3.5, XT1
ILPM3.5, LCD, CP
ILPM4.5, SVS
Low-power mode 3.5, excludes SVS(6)
0.90
µA
0.23
0.25 0.375
0.20
0.43
µA
Low-power mode 4.5, includes SVS(4)
0.20
0.010
0.008
0.015 0.070 0.073 0.140
0.013 0.060
ILPM4.5
Low-power mode 4.5, excludes SVS(5)
µA
(1) Not applicable for devices with HF crystal oscillator only.
(2) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance chosen to closely match the required load.
(3) Low-power mode 3.5, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
(4) Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(5) Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
(6) LCD works in LPM3.5 if the internal charge pump and VREF switch mode are enabled. The LCD driver pins are configured as 4x36 at
32‑Hz frame frequency with an external 32768‑Hz clock source.
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8.9 Typical Characteristics, Low-Power Mode Supply Currents
The graphs in this section show only board-level test result on a small number of samples. A MS1V-T1K crystal from Micro-
Crystal was populated for 32-kHz clock generation. LCD is configured in 4xCOM mode without LCD panel populated.
5
4.5
4
5
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (°C)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (°C)
LPM3
RTC counter on
图8-2. LPM3 Supply Current vs Temperature
DVCC = 3 V
LPM3
DVCC = 3 V
SVS disabled
SVS disabled
LCD on
图8-1. LPM3 Supply Current vs Temperature
3
2.5
2
0.5
0.45
0.4
0.35
0.3
1.5
1
0.25
0.2
0.15
0.1
0.5
0
0.05
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (°C)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80
Temperature (°C)
LPM3.5
12.5-pF crystal on XT1
图8-3. LPM3.5 Supply Current vs Temperature
DVCC = 3 V
LPM4.5
DVCC = 3 V
SVS enabled
SVS enabled
图8-4. LPM4.5 Supply Current vs Temperature
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8.10 Current Consumption Per Module
MODULE
Timer_A
TEST CONDITIONS
REFERENCE CLOCK
Module input clock
TYP
5
UNIT
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
nA
eUSCI_A
eUSCI_A
eUSCI_B
eUSCI_B
RTC
UART mode
SPI mode
SPI mode
Module input clock
Module input clock
Module input clock
Module input clock
32 kHz
7
5
5
I2C mode, 100 kbaud
5
85
8.5
CRC
From start to end of operation
MCLK
µA/MHz
8.11 Thermal Characteristics
PARAMETER
VALUE
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-ambient thermal resistance, still air(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
61.7
25.4
32.7
32.4
2.5
θJA
θJC, (TOP)
θJB
LQFP-64 (PM)
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-ambient thermal resistance, still air((1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
ΨJB
ΨJT
62.4
18.7
31.4
31.1
0.8
θJA
θJC, (TOP)
θJB
TSSOP-56 (DGG56)
TSSOP-48 (DGG48)
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-ambient thermal resistance, still air((1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
ΨJB
ΨJT
68.9
23
θJA
θJC, (TOP)
θJB
35.8
35.3
1.1
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
ΨJB
ΨJT
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board,
as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold place test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold place fixture to control the PCB
temperature, as described in JESD51-8.
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8.12 Timing and Switching Characteristics
8.12.1 Power Supply Sequencing
图8-5 shows the power cycle, SVS, and BOR reset conditions.
V
Power Cycle Reset
VSVS+
SVS Reset
BOR Reset
VSVS–
VBOR
tBOR
t
图8-5. Power Cycle, SVS, and BOR Reset Conditions
节8.12.1.1 lists the characteristics of the SVS and BOR.
8.12.1.1 PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.1
10
TYP
MAX UNIT
VBOR, safe
tBOR, safe
ISVSH,AM
Safe BOR power-down level(1)
Safe BOR reset delay(2)
V
ms
SVSH current consumption, active mode
SVSH current consumption, low-power modes
SVSH power-down level(4)
VCC = 3.6 V
VCC = 3.6 V
1.5 µA
nA
ISVSH,LPM
VSVSH-
240
1.81
1.88
70
1.71
1.76
1.87
1.99
V
V
VSVSH+
SVSH power-up level(4)
VSVSH_hys
tPD,SVSH, AM
tPD,SVSH, LPM
VREF, 1.2V
SVSH hysteresis
mV
µs
µs
V
SVSH propagation delay, active mode
SVSH propagation delay, low-power modes
1.2-V REF voltage(3)
10
100
1.158
1.20
1.242
(1) A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.
(2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches
VSVSH+
(3) This is a characterized result with external 1-mA load to ground from –40°C to 85°C.
.
(4) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO reference
design.
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8.12.2 Reset Timing
节8.12.2.1 lists the device wake-up times.
8.12.2.1 Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
3 V
3 V
MIN
TYP
MAX UNIT
Additional wake-up time to activate the FRAM in
AM if previously disabled by the FRAM controller or
from a LPM if immediate activation is selected for
wake-up(1)
tWAKE-UP FRAM
10
µs
200 ns +
2.5/fDCO
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode (1)
tWAKE-UP LPM3
tWAKE-UP LPM4
Wake-up time from LPM3 to active mode (2)
Wake-up time from LPM4 to active mode
3 V
3 V
3 V
3 V
3 V
10
10
µs
µs
µs
µs
ms
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode (2)
350
350
1
SVSHE = 1
SVSHE = 0
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode (2)
Wake-up time from RST or BOR event to active
tWAKE-UP-RESET
tRESET
3 V
3 V
1
ms
µs
mode (2)
Pulse duration required at RST/NMI pin to accept a
reset
2
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
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8.12.3 Clock Specifications
节8.12.3.1 lists the characteristics of XT1.
8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
XT1 oscillator crystal, low
frequency
fXT1, LF
LFXTBYPASS = 0
32768
Hz
Measured at MCLK,
fLFXT = 32768 Hz
DCXT1, LF
fXT1,SW
DCXT1, SW
OALFXT
CL,eff
XT1 oscillator LF duty cycle
30%
70%
XT1 oscillator logic-level square-
wave input frequency
LFXTBYPASS = 1(3) (4)
32768
Hz
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
40%
60%
Oscillation allowance for
LF crystals (5)
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
200
1
kΩ
Integrated effective load
capacitance (6)
See (7)
pF
fOSC = 32768 Hz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
tSTART,LFXT Start-up time (9)
fFault,LFXT
Oscillator fault frequency (10)
1000
ms
XTS = 0(8)
0
3500
Hz
(1) To improve EMI on the LFXT oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing.
(3) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW
(4) Maximum frequency of operation of the entire device cannot be exceeded.
.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
For LFXTDRIVE = {1}, 6 pF ≤CL,eff ≤9 pF.
For LFXTDRIVE = {2}, 6 pF ≤CL,eff ≤10 pF.
For LFXTDRIVE = {3}, 6 pF ≤CL,eff ≤12 pF.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers.
Recommended effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF.
The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective
load capacitance of the selected crystal is met.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
(9) Includes startup counter of 1024 clock cycles.
(10) Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition sets the flag.
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8.12.3.2 DCO FLL, Frequency
Over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
MIN
–1.0%
–2.0%
TYP
MAX UNIT
1.0%
FLL lock frequency, 16 MHz, 25°C
FLL lock frequency, 16 MHz, –40°C to 85°C
Measured at MCLK, Internal
trimmed REFO as reference
2.0%
fDCO, FLL
Measured at MCLK, XT1
crystal as reference
3 V
0.5%
60%
FLL lock frequency, 16 MHz, –40°C to 85°C
–0.5%
fDUTY
Duty cycle
3 V
3 V
3 V
3 V
40%
50%
0.25%
0.022%
120
Jittercc
Jitterlong
tFLL, lock
Cycle-to-cycle jitter, 16 MHz
Long-term jitter, 16 MHz
FLL lock time
Measured at MCLK, XT1
crystal as reference
ms
节8.12.3.3 lists the characteristics of the REFO.
8.12.3.3 REFO
Over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
MIN
TYP
15
MAX UNIT
IREFO
REFO oscillator current consumption
REFO calibrated frequency
TA = 25°C
µA
Hz
Measured at MCLK
TA = –40°C to 85°C
Measured at MCLK(1)
32768
fREFO
REFO absolute calibrated tolerance
REFO frequency temperature drift
1.8 V to 3.6 V
3 V
+3.5%
%/°C
–3.5%
dfREFO/dT
0.01
1
dfREFO
dVCC
/
Measured at MCLK at
25°C(2)
REFO frequency supply voltage drift
1.8 V to 3.6 V
1.8 V to 3.6 V
%/V
fDC
REFO duty cycle
Measured at MCLK
40%
50%
50
60%
µs
tSTART
REFO startup time
40% to 60% duty cycle
(1) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C –(–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)
节8.12.3.4 lists the characteristics of the VLO.
8.12.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
MIN
TYP
10
MAX UNIT
kHz
fVLO
Measured at MCLK
3 V
dfVLO/dT
Measured at MCLK(1)
Measured at MCLK(2)
Measured at MCLK
3 V
0.5
4
%/°C
dfVLO/dVCC VLO frequency supply voltage drift
fVLO,DC Duty cycle
1.8 V to 3.6 V
3 V
%/V
50%
(1) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C –(–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)
备注
The VLO clock frequency is reduced by 15% (typical) when the device switches from active mode to
LPM3 or LPM4, because the reference changes. This lower frequency is not a violation of the VLO
specifications (see 节8.12.3.4).
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节8.12.3.5 lists the characteristics of the MODCLK.
8.12.3.5 Module Oscillator Clock (MODCLK)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX UNIT
5.8 MHz
%/℃
fMODCLK
MODCLK frequency
3 V
3.8
4.8
fMODCLK/dT
fMODCLK/dVCC
fMODCLK,DC
MODCLK frequency temperature drift
MODCLK frequency supply voltage drift
Duty cycle
3 V
0.102
1.02
50%
1.8 V to 3.6 V
3 V
%/V
40%
60%
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8.12.4 Digital I/Os
节8.12.4.1 lists the characteristics of the digital inputs.
8.12.4.1 Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
MIN
0.90
1.35
0.50
0.75
0.3
TYP
MAX UNIT
1.50
V
2.25
VIT+
VIT–
Vhys
Positive-going input threshold voltage
1.10
V
1.65
Negative-going input threshold voltage
0.8
V
1.2
Input voltage hysteresis (VIT+ –VIT–
)
0.4
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI,dig
CI,ana
Pullup or pulldown resistor
20
35
3
50
kΩ
pF
pF
Input capacitance, digital only port pins
VIN = VSS or VCC
VIN = VSS or VCC
Input capacitance, port pins with shared analog
functions
5
High-impedance leakage current (also see (1)
Ilkg(Px.y)
2 V, 3 V
2 V, 3 V
+20
nA
ns
–20
and (2)
)
Ports with interrupt capability
External interrupt timing (external trigger pulse (see block diagram and
t(int)
50
duration to set interrupt flag)(3)
terminal function
descriptions)
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
节8.12.4.2 lists the characteristics of the digital outputs.
8.12.4.2 Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
I(OHmax) = –5 mA(1)
I(OLmax) = 3 mA(1)
VCC
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN
1.4
2.4
0.0
0.0
16
TYP
MAX UNIT
2.0
V
3.0
VOH
High-level output voltage
0.60
V
0.60
VOL
Low-level output voltage
I(OHmax) = 5 mA(1)
fPort_CLK
trise,dig
tfall,dig
Clock output frequency
CL = 20 pF(2)
CL = 20 pF
CL = 20 pF
MHz
ns
16
10
7
Port output rise time, digital only port pins
Port output fall time, digital only port pins
10
5
ns
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The port can output frequencies at least up to the specified limit and might support higher frequencies.
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8.12.4.3 Digital I/O Typical Characteristics
25
10
7.5
5
TA = 85°C
TA = 85°C
TA = 25°C
20
TA = 25°C
15
10
5
2.5
0
0
0
0.5
1
1.5
2
2.5
3
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Low-Level Output Voltage (V)
Low-Level Output Voltage (V)
DVCC = 3 V
DVCC = 2 V
图8-6. Typical Low-Level Output Current vs Low-Level Output
图8-7. Typical Low-Level Output Current vs Low-Level Output
Voltage
Voltage
0
0
TA = 85°C
TA = 85°C
-5
TA = 25°C
TA = 25°C
-2.5
-10
-15
-20
-25
-5
-7.5
-10
0
0.5
1
1.5
2
2.5
3
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
High-Level Output Voltage (V)
High-Level Output Voltage (V)
DVCC = 3 V
DVCC = 2 V
图8-8. Typical High-Level Output Current vs High-Level Output 图8-9. Typical High-Level Output Current vs High-Level Output
Voltage
Voltage
8.12.5 Timer_A
节8.12.5.1 lists the operating frequency of Timer_A.
8.12.5.1 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN MAX UNIT
Internal: SMCLK, ACLK
fTA
Timer_A input clock frequency
External: TACLK
2 V, 3 V
16 MHz
Duty cycle = 50% ±10%
All capture inputs, minimum pulse
duration required for capture
tTA,cap Timer_A capture timing
2 V, 3 V
20
ns
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8.12.6 eUSCI
节8.12.6.1 lists the operating conditions of the eUSCI in UART mode.
8.12.6.1 eUSCI (UART Mode) Operating Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
feUSCI
eUSCI input clock frequency
2 V, 3 V
2 V, 3 V
16 MHz
fBITCLK
BITCLK clock frequency (equals baud rate in Mbaud)
5
MHz
节8.12.6.2 lists the switching characteristics of the eUSCI in UART mode.
8.12.6.2 eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TYP UNIT
UCGLITx = 0
12
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
40
ns
68
tt
UART receive deglitch time (1)
2 V, 3 V
110
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
节8.12.6.3 lists the operating conditions of the eUSCI in SPI master mode.
8.12.6.3 eUSCI (SPI Master Mode) Operating Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal: SMCLK, MODCLK
Duty cycle = 50% ±10%
MIN
MAX UNIT
MHz
feUSCI
eUSCI input clock frequency
8
节8.12.6.4 lists the switching characteristics of the eUSCI in SPI master mode.
8.12.6.4 eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
UCxCLK
cycles
tSTE,LEAD
tSTE,LAG
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
STE lag time, Last clock to STE inactive UCSTEM = 1, UCMODEx = 01 or 10
SOMI input data setup time
1
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
45
35
0
tSU,MI
ns
ns
ns
ns
tHD,MI
SOMI input data hold time
0
20
20
UCLK edge to SIMO valid,
tVALID,MO
SIMO output data valid time(2)
CL = 20 pF
0
0
tHD,MO
SIMO output data hold time(3)
CL = 20 pF
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in 图8-10 and 图8-11.
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(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in 图8-10
and 图8-11.
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tVALID,MO
图8-10. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tVALID,MO
图8-11. SPI Master Mode, CKPH = 1
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节8.12.6.5 lists the switching characteristics of the eUSCI in SPI slave mode.
8.12.6.5 eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN
MAX UNIT
55
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE active to clock
ns
45
20
STE lag time, Last clock to STE inactive
ns
20
65
ns
40
STE access time, STE active to SOMI data out
40
ns
35
STE disable time, STE inactive to SOMI high
impedance
4
4
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
SOMI output data hold time (3)
ns
ns
12
12
tHD,SI
65
ns
40
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
5
5
tHD,SO
CL = 20 pF
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in 图8-12 and 图8-13.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in 图8-12
and 图8-13.
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UCMODEx = 01
UCMODEx = 10
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SIMO
tHD,SIMO
tLOW/HIGH
tLOW/HIGH
SIMO
tACC
tVALID,SOMI
tDIS
SOMI
图8-12. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
SOMI
tACC
tDIS
tVALID,SO
图8-13. SPI Slave Mode, CKPH = 1
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节8.12.6.6 lists the switching characteristics of the eUSCI in I2C mode.
8.12.6.6 eUSCI (I2C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图8-14)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, MODCLK
External: UCLK
feUSCI
eUSCI input clock frequency
16 MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2 V, 3 V
2 V, 3 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2 V, 3 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2 V, 3 V
2 V, 3 V
ns
ns
250
4.0
0.6
50
fSCL = 100 kHz
fSCL > 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
tSU,STO
Setup time for STOP
2 V, 3 V
µs
600
25
300
ns
150
Pulse duration of spikes suppressed by
input filter
tSP
2 V, 3 V
12.5
6.3
75
27
30
33
tTIMEOUT
Clock low time-out
2 V, 3 V
ms
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
图8-14. I2C Mode Timing
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8.12.7 ADC
节8.12.7.1 lists the power supply and input conditions of the ADC.
8.12.7.1 ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.0
0
TYP
MAX UNIT
DVCC
V(Ax)
ADC supply voltage
Analog input voltage range
3.6
V
V
All ADC pins
DVCC
Operating supply current into
DVCC terminal, reference
current not included, repeat-
single-channel mode
2 V
3 V
185
207
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0, ADCDIV
= 0, ADCCONSEQx = 10b
IADC
µA
pF
Only one terminal Ax can be selected at one
time from the pad to the ADC capacitor array,
including wiring and pad
CI
Input capacitance
2.2 V
1.6
34
2.0
2
RI,MUX
RI,Misc
Input MUX ON resistance
DVCC = 2 V, 0 V ≤VAx ≤DVCC
kΩ
kΩ
Input miscellaneous resistance
节8.12.7.2 lists the timing parameters of the ADC.
8.12.7.2 ADC, 10-Bit Timing Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC linearity
parameters
fADCCLK
fADCOSC
2 V to 3.6 V
0.45
5
5.5 MHz
Internal ADC oscillator
(MODCLK)
ADCDIV = 0, fADCCLK = fADCOSC
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
4.5
5.0
5.5 MHz
REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode,
fADCOSC = 4.5 MHz to 5.5 MHz
2.18
2.67
µs
tCONVERT
Conversion time
External fADCCLK from ACLK, MCLK, or SMCLK,
ADCSSEL ≠0
(1)
The error in a conversion started after tADCON is
less than ±0.5 LSB,
Reference and input signal already settled
Turn-on settling time of
the ADC
tADCON
100
ns
µs
RS = 1000 Ω, RI (2) = 36000 Ω, CI = 3.5 pF,
Approximately 8 Tau (t) are required for an error of
less than ±0.5 LSB(3)
2 V
3 V
1.5
2.0
tSample
Sampling time
(1) 12 × 1/fADCCLK
(2) RI = RI,MUX + RI,Misc
(3) tSample = ln(2n+1) × τ, where n = ADC resolution, τ= (RI + RS) × CI
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节8.12.7.3 lists the linearity parameters of the ADC.
8.12.7.3 ADC, 10-Bit Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
2.4 V to
3.6 V
Integral linearity error (10-bit mode)
2
–2
EI
VDVCC as reference
VDVCC as reference
VDVCC as reference
LSB
2
2 V to
3.6 V
Integral linearity error (8-bit mode)
Differential linearity error (10-bit mode)
Differential linearity error (8-bit mode)
Offset error (10-bit mode)
–2
–1
2.4 V to
3.6 V
1
ED
LSB
1
2 V to
3.6 V
–1
2.4 V to
3.6 V
6.5
mV
6.5
–6.5
EO
2 V to
3.6 V
Offset error (8-bit mode)
–6.5
–2.0
VDVCC as reference
2.0 LSB
3.0%
2.4 V to
3.6 V
Gain error (10-bit mode)
–
3.0%
Internal 1.5-V reference
VDVCC as reference
EG
2.0 LSB
3.0%
–2.0
2 V to
3.6 V
Gain error (8-bit mode)
–
3.0%
Internal 1.5-V reference
VDVCC as reference
2.0 LSB
3.0%
–2.0
2.4 V to
3.6 V
Total unadjusted error (10-bit mode)
–
3.0%
Internal 1.5-V reference
VDVCC as reference
ET
2.0 LSB
3.0%
–2.0
2 V to
3.6 V
Total unadjusted error (8-bit mode)
See (1)
–
3.0%
Internal 1.5-V reference
VSENSOR
ADCON = 1, INCH = 0Ch, TA = 0°C
ADCON = 1, INCH = 0Ch
3 V
3 V
1.013
3.35
mV
TCSENSOR See (2)
mV/°C
ADCON = 1, INCH = 0Ch, Error of
conversion result ≤1 LSB, AM and all
LPM above LPM3
3 V
3 V
30
tSENSOR
Sample time required if channel 12 is
selected(3)
µs
(sample)
ADCON = 1, INCH = 0Ch, Error of
conversion result ≤1 LSB, LPM3
100
(1) The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
(2) The device descriptor structure contains calibration values for 30°C and 85°C for each of the available reference voltage levels. The
sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR can be
computed from the calibration values for higher accuracy.
(3) The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
.
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8.12.8 LCD Controller
节8.12.8.1 lists the operating conditions of the LCD controller.
8.12.8.1 LCD Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
LCDCPEN = 1, 0000 < VLCDx ≤1111,
LCDREFEN = 1 (charge pump enabled,
Supply voltage range, charge
pump enabled, VLCD ≤3.6 V
VCC,LCD,CP en,3.6
VCC,LCD,ext. bias
VCC,LCD,VLCDEXT
1.8
3.6
3.6
3.6
V
V
V
V
LCD ≤3.6 V)
Supply voltage range, external
biasing, charge pump enabled
LCDCPEN = 1, LCDREFEN = 0
LCDCPEN = 0, LCDSELVDD = 0
1.8
1.8
Supply voltage range, external
LCD voltage, external biasing,
charge pump disabled
External LCD voltage at LCDCAP/
R33, external biasing, charge
pump disabled
VR33
LCDCPEN = 0, LCDSELVDD = 0
2.4
3.6
V
CLCDCAP
CR33
0.1
0.1
0.1
0.1
µF
µF
µF
µF
CR23
CR13
fLCD = 2 × mux × fFRAME with
mux = 1 (static), 2, 3, 4
fFrame
LCD frame frequency range
16
30
32
32
64
Hz
fACLK,in
CPanel
ACLK input frequency range
Panel capacitance
40 kHz
32-Hz frame frequency
8000
pF
V
LCDCPEN = 0, LCDSELVDD = 0,
LCDREFEN = 0
VR33
Analog input voltage at R33
Analog input voltage at R23
2.4
1.2
0.0
0.8
3.6
2.4
1.2
1.2
LCDCPEN = 0, LCDSELVDD = 0,
LCDREFEN = 0
VR23,1/3bias
VR13,1/3bias
VLCDREF/R13
V
V
V
Analog input voltage at R13 with
1/3 biasing
External LCD reference voltage
applied at LCDREF/R13
LCDCPEN = 1, LCDSELVDD = 0,
LCDREFEN = 0
1.0
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8.12.9 FRAM
节8.12.9.1 lists the characteristics of the FRAM.
8.12.9.1 FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
1015
100
40
MAX UNIT
Read and write endurance
cycles
TJ = 25°C
tRetention
Data retention duration
TJ = 70°C
TJ = 85°C
years
10
8.12.10 Emulation and Debug
节8.12.10.1 lists the characteristics of the JTAG and SBW interface.
8.12.10.1 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX UNIT
fSBW
Spy-Bi-Wire input frequency
2 V, 3 V
2 V, 3 V
2 V, 3 V
0
10 MHz
tSBW,Low
tSBW, En
tSBW,Rst
Spy-Bi-Wire low clock pulse duration
0.028
15
110
100
µs
µs
µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1)
Spy-Bi-Wire return to normal operation time
15
0
2 V
3 V
16 MHz
16 MHz
fTCK
TCK input frequency, 4-wire JTAG (2)
Internal pulldown resistance on TEST
0
Rinternal
2 V, 3 V
20
35
50
kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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9 Detailed Description
9.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register (SR),
and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
9.2 Operating Modes
The devices have one active mode and several software-selectable low-power modes of operation. An interrupt
event can wake up the device from low-power mode LPM0 or LPM3, service the request, and restore back to the
low-power mode on return from the interrupt program. Low-power modes LPM3.5 and LPM4.5 disable the core
supply to minimize power consumption.
表9-1. Operating Modes
AM
LPM0
LPM3
LPM4
OFF
0
LPM3.5
LPM4.5
SHUTDOWN
0
ONLY RTC
COUNTER
AND LCD
MODE
ACTIVE
MODE
CPU OFF
STANDBY
Maximum System Clock
16 MHz
126 µA/MHz
N/A
16 MHz
20 µA/MHz
Instant
40 kHz
1.2 µA
10 µs
All
40 kHz
0.6 µA
without SVS
0.77 µA with
RTC only
13 nA
without SVS
Power Consumption at 25°C, 3 V
Wake-up time
10 µs
I/O
150 µs
150 µs
I/O
RTC Counter
I/O
Wake-up events
N/A
All
Full
Regulation
Full
Regulation
Partial Power Partial Power Partial Power
Regulator
Power Down
Down
Optional
On
Down
Optional
On
Down
Optional
On
Power
SVS
Brown Out
MCLK
On
On
On
On
Optional
On
Active
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
On
Off
Off
Off
Off
Off
SMCLK
FLL
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
DCO
Off
Off
Off
Off
Clock
MODCLK
REFO
Off
Off
Off
Off
Optional
Optional
Optional
Optional
Off
Off
Off
Off
ACLK
Off
Off
Off
XT1CLK
VLOCLK
CPU
Off
Optional
Optional
Off
Off
Off
Off
Off
Off
FRAM
On
On
Off
Off
Off
Off
Core
RAM
On
On
On
On
Off
Off
Backup Memory(1)
On
On
On
On
On
Off
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表9-1. Operating Modes (continued)
AM
LPM0
LPM3
LPM4
OFF
LPM3.5
LPM4.5
ONLY RTC
COUNTER
AND LCD
MODE
ACTIVE
MODE
CPU OFF
STANDBY
SHUTDOWN
Timer0_A3
Timer1_A3
WDT
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
eUSCI_A0
eUSCI_B0
CRC
Off
Peripherals
Off
Off
Off
Off
ADC
Optional
Optional
Optional
Off
LCD
Optional
Optional
RTC Counter
General Digital Input/
Output
On
Optional
Optional
State Held
Optional
State Held
Off
State Held
Off
State Held
Off
I/O
Capacitive Touch I/O
Optional
(1) Backup memory contains one 32-byte register in the peripheral memory space. See 表9-29 and 表9-48 for its memory allocation.
9.3 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
表9-2. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power-up, Brownout, Supply Supervisor
External Reset RST
SVSHIFG
PMMRSTIFG
Watchdog Time-out, Key Violation
FRAM uncorrectable bit error detection
Software POR,
WDTIFG
PMMPORIFG, PMMBORIFG
SYSRSTIV
Reset
FFFEh
63, Highest
FLL unlock error
FLLUNLOCKIFG
System NMI
Vacant Memory Access
JTAG Mailbox
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
Nonmaskable
Nonmaskable
FFFCh
FFFAh
62
61
FRAM bit error detection
User NMI
External NMI
Oscillator Fault
NMIIFG
OFIFG
Timer0_A3
Timer0_A3
Timer1_A3
Timer1_A3
TA0CCR0 CCIFG0
Maskable
Maskable
Maskable
Maskable
FFF8h
FFF6h
FFF4h
FFF2h
60
59
58
57
TA0CCR1 CCIFG1, TA0CCR2
CCIFG2, TA0IFG (TA0IV)
TA1CCR0 CCIFG0
TA1CCR1 CCIFG1, TA1CCR2
CCIFG2, TA1IFG (TA1IV)
RTC Counter
RTCIFG
WDTIFG
Maskable
Maskable
FFF0h
FFEEh
56
55
Watchdog Timer Interval mode
UCTXCPTIFG, UCSTTIFG, UCRXIFG,
UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
eUSCI_A0 Receive or Transmit
Maskable
FFECh
54
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表9-2. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG, UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1, UCRXIFG2,
UCTXIFG2, UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I2C mode)
(UCB0IV)
eUSCI_B0 Receive or Transmit
Maskable
FFEAh
53
ADCIFG0, ADCINIFG, ADCLOIFG,
ADCHIIFG, ADCTOVIFG, ADCOVIFG
(ADCIV)
ADC
Maskable
FFE8h
52
P1
P2
P1IFG.0 to P1IFG.7 (P1IV)
P2IFG.0 to P2IFG.7 (P2IV)
Maskable
Maskable
FFE6h
FFE4h
51
50
LCDBLKOFFIFG, LCDBLKONIFG,
LCDFRMIFG (LCDEIV)
LCD
Maskable
Maskable
FFE2h
49, Lowest
Reserved
Reserved
FFE0h to FF88h
0FF86h
BSL Signature 2
BSL Signature 1
JTAG Signature 2
JTAG Signature 1
0FF84h
Signatures
0FF82h
0FF80h
9.4 Bootloader (BSL)
The BSL lets users program the FRAM or RAM using a UART serial interface. Access to the device memory
through the BSL is protected by an user-defined password. Use of the BSL requires four pins as shown in 表
9-3. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a
complete description of the features of the BSL and its implementation, see the MSP430 FRAM Devices
Bootloader (BSL) User's Guide.
表9-3. BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.0
P1.1
VCC
VSS
Data receive
Power supply
Ground supply
9.5 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in
表 9-4. For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its
implementation, see MSP430 Programming With the JTAG Interface.
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表9-4. JTAG Pin Requirements and Function
DEVICE SIGNAL
P1.4/MCLK/TCK/A4/VREF+
P1.5/TA0CLK/TMS/A5
P1.6/TA0.2/TDI/TCLK/A6
P1.7/TA0.1/TDO/A7
TEST/SBWTCK
DIRECTION
JTAG FUNCTION
JTAG clock input
JTAG state control
JTAG data input/TCLK input
JTAG data output
Enable JTAG pins
External reset
IN
IN
IN
OUT
IN
RST/NMI/SBWTDIO
VCC
IN
Power supply
VSS
Ground supply
9.6 Spy-Bi-Wire Interface (SBW)
The MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with
MSP430 development tools and device programmers. 表 9-5 shows the Spy-Bi-Wire interface pin requirements.
For further details on interfacing to development tools and device programmers, see the MSP430 Hardware
Tools User's Guide.
表9-5. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
SBW FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Power supply
IN
IN, OUT
VSS
Ground supply
9.7 FRAM
The FRAM can be programmed using the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU.
Features of the FRAM include:
• Byte and word access capability
• Programmable wait state generation
• Error correction code (ECC) generation
9.8 Memory Protection
The device features memory protection that can restrict user access and enable write protection:
• Securing the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing JTAG
and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
• Write protection enabled to prevent unwanted write operation to FRAM contents by setting the control bits in
System Configuration register 0. For more detailed information, see the SYS chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide.
备注
The FRAM is protected by default on PUC. To write to FRAM during code execution, the application
must first clear the corresponding PFWP or DFWP bit in System Configuration Register 0 to unprotect
the FRAM.
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9.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be handled
by using all instructions in the memory map. For complete module description, see the MSP430FR4xx and
MSP430FR2xx Family User's Guide.
9.9.1 Power Management Module (PMM) and On-Chip Reference Voltages
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also
includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR) is
implemented to provide the proper internal reset signal to the device during power on and power off. The SVS
circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is available on the
primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC channel
15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily represent as 方程
式1 by using ADC sampling 1.5-V reference without any external components support.
DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result
(1)
A 1.2-V reference voltage can be buffered and output to P1.4/MCLK/TCK/A4/VREF+, when the ADC channel 4
is selected as the function. For more detailed information, see the MSP430FR4xx and MSP430FR2xx Family
User's Guide.
9.9.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz crystal oscillator (XT1), an internal very low-power low-frequency oscillator
(VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator (DCO) that
may use frequency-locked loop (FLL) locking with internal or external 32-kHz reference clock, and on-chip
asynchronous high-speed clock (MODCLK). The clock system is designed to target cost-effective designs with
minimal external components. A fail-safe mechanism is designed for XT1. The clock system module offers the
following clock signals.
• Main Clock (MCLK): the system clock used by the CPU and all relevant peripherals accessed by the bus. All
clock sources except MODCLK can be selected as the source with a predivider of 1, 2, 4, 8, 16, 32, 64, or
128.
• Sub-Main Clock (SMCLK): the subsystem clock used by the peripheral modules. SMCLK derives from the
MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
• Auxiliary Clock (ACLK): this clock is derived from the external XT1 clock or internal REFO clock up to 40 kHz.
All peripherals may have one or several clock sources depending on specific functionality. 表 9-6 shows the
clock distribution used in this device.
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EXTERNAL PIN
表9-6. Clock Distribution
CLOCK
SOURCE
SELECT
BITS
MCLK
SMCLK
ACLK
MODCLK
XT1CLK(1)
VLOCLK
Frequency
Range
DC to
16 MHz
DC to
16 MHz
DC to 40 kHz 5 MHz ±10% DC to 40 kHz 10 kHz ±50%
CPU
N/A
N/A
Default
Default
Default
Default
Default
FRAM
RAM
N/A
CRC
N/A
I/O
N/A
TA0
TASSEL
TASSEL
UCSSELx
UCSSELx
WDTSSEL
ADCSSEL
LCDSSEL
RTCSS
10b
10b
01b
01b
01b
01b
00b (TA0CLK pin)
00b (TA1CLK pin)
00b (UCA0CLK pin)
00b (UCB0CLK pin)
TA1
eUSCI_A0
eUSCI_B0
WDT
ADC
10b or 11b
10b or 11b
00b
01b
01b
01b
10b
10b or 11b
00b
LCD
00b
10b
10b
11b
RTC
01b
(1) To enable XT1 functionality, configure P4SEL0.1 (XIN) and P4SEL0.2 (XOUT) before configuring the Clock System registers.
CPU
FRAM
SRAM
CRC
I/O
MCLK
Timer_A
0
Timer_A
1
eUSCI_
A0
eUSCI_
B0
WDT
RTC
ADC10
LCD_E
Clock System (CS)
SMCLK
ACLK
VLOCLK
MODCLK
XT1CLK
图9-1. Clock Distribution Block Diagram
9.9.3 General-Purpose Input/Output Port (I/O)
Up to 60 I/O ports are implemented.
• P1, P2, P3, P4, P5, P6, and P7 are full 8-bit ports; P8 has 4 bits implemented.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
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• Capacitive Touch IO functionality is supported on all pins.
备注
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance with
Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR reset, the
ports must be configured first and then the LOCKLPM5 bit must be cleared. For details, see the
Configuration After Reset section in the Digital I/O chapter of the MSP430FR4xx and MSP430FR2xx
Family User's Guide.
9.9.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as interval timer and can generate interrupts at selected time
intervals.
表9-7. WDT Clocks
NORMAL OPERATION
WDTSSEL
(WATCHDOG AND INTERVAL TIMER
MODE)
00
01
10
11
SMCLK
ACLK
VLOCLK
VLOCLK
9.9.5 System Module (SYS)
The SYS module handles many of the system functions within the device. These include Power-On Reset (POR)
and Power-Up Clear (PUC) handling, NMI source selection and management, reset interrupt vector generators,
bootloader entry mechanisms, and configuration management (device descriptors). SYS also includes a data
exchange mechanism through SBW called a JTAG mailbox mail box that can be used in the application.
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表9-8. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
No interrupt pending
Brownout (BOR)
00h
02h
Highest
RSTIFG RST/NMI (BOR)
PMMSWBOR software BOR (BOR)
LPMx.5 wakeup (BOR)
Security violation (BOR)
Reserved
04h
06h
08h
0Ah
0Ch
0Eh
SVSHIFG SVSH event (BOR)
Reserved
10h
Reserved
12h
SYSRSTIV, System Reset
015Eh
PMMSWPOR software POR (POR)
WDTIFG watchdog time-out (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
Uncorrectable FRAM bit error detection
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
Reserved
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
FLL unlock (PUC)
24h
Reserved
26h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVS low-power reset entry
Uncorrectable FRAM bit error detection
Reserved
02h
04h
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
0Eh
SYSSNIV, System NMI
015Ch
Reserved
Reserved
10h
VMAIFG Vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
Reserved
12h
14h
16h
18h
1Ah to 1Eh
00h
Lowest
Highest
Lowest
No interrupt pending
NMIIFG NMI pin or SVSH event
OFIFG oscillator fault
Reserved
02h
SYSUNIV, User NMI
015Ah
04h
06h to 1Eh
9.9.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data values
and can be used for data checking purposes. The CRC generation polynomial is compliant with CRC-16-CCITT
standard of x16 + x12 + x5 + 1.
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9.9.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either UART or
SPI communications. The eUSCI_B module supports either SPI or I2C communications. Additionally, eUSCI_A
supports automatic baud-rate detection and IrDA.
表9-9. eUSCI Pin Configurations
PIN
P1.0
P1.1
P1.2
P1.3
PIN
UART
SPI
SIMO
SOMI
SCLK
STE
TXD
eUSCI_A0
eUSCI_B0
RXD
I2C
SPI
P5.0
P5.1
P5.2
P5.3
STE
SCLK
SIMO
SOMI
SDA
SCL
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9.9.8 Timers (Timer0_A3, Timer1_A3)
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare registers
each. Each can support multiple captures or compares, PWM outputs, and interval timing. Each has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers. The CCR0 registers on both TA0 and TA1 are not externally connected and can only
be used for hardware period timing and interrupt generation. In Up Mode, they can be used to set the overflow
value of the counter.
表9-10. Timer0_A3 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PORT PIN
MODULE BLOCK
P1.5
TA0CLK
TACLK
ACLK
ACLK (internal)
SMCLK (internal)
Timer
N/A
TA0
TA1
SMCLK
from Capacitive
Touch IO (internal)
INCLK
CCI0A
CCI0B
Timer1_A3 CCI0B
input
CCR0
CCR1
DVSS
DVCC
TA0.1
GND
VCC
P1.7
P1.6
CCI1A
TA0.1
Timer1_A3 CCI1B
input
from RTC (internal)
CCI1B
DVSS
DVCC
TA0.2
GND
VCC
CCI2A
TA0.2
Timer1_A3 INCLK
Timer1_A3 CCI2B
input,
from Capacitive
Touch I/O (internal)
CCI2B
CCR2
TA2
IR Input
DVSS
DVCC
GND
VCC
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表9-11. Timer1_A3 Signal Connections
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
PORT PIN
MODULE BLOCK
P8.2
TA1CLK
TACLK
ACLK
ACLK (internal)
SMCLK (internal)
Timer
N/A
TA0
TA1
TA2
SMCLK
Timer0_A3 CCR2B
output (internal)
INCLK
CCI0A
CCI0B
Timer0_A3 CCR0B
output (internal)
CCR0
CCR1
CCR2
DVSS
DVCC
TA1.1
GND
VCC
P4.0
P8.3
CCI1A
TA1.1
Timer0_A3 CCR1B
output (internal)
CCI1B
to ADC trigger
DVSS
DVCC
TA1.2
GND
VCC
CCI2A
TA1.2
Timer0_A3 CCR2B
output (internal)
CCI2B
IR Input
DVSS
DVCC
GND
VCC
The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of UCA0TXD/
UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated infrared command for
directly driving an external IR diode. The IR functions are fully controlled by SYS configuration registers 1
including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA
(data) bits. For more information, see the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's
Guide.
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9.9.9 Real-Time Clock (RTC) Counter
The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. This module
may periodically wake up the CPU from LPM0, LPM3, and LPM3.5 based on timing from a low-power clock
source such as the XT1 and VLO clocks. In AM, RTC can be driven by SMCLK to generate high-frequency
timing events and interrupts. The RTC overflow events trigger:
• Timer0_A3 CCR1B
• ADC conversion trigger when ADCSHSx bits are set as 01b
9.9.10 10-Bit Analog Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The module
implements a 10-bit SAR core, sample select control, reference generator and a conversion result buffer. A
window comparator with a lower and upper limit allows CPU independent result monitoring with three window
comparator interrupt flags.
The ADC supports 10 external inputs and four internal inputs (see 表9-12).
表9-12. ADC Channel Connections
ADCINCHx
ADC CHANNELS
EXTERNAL PIN OUT
0
1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P8.0(1)
P8.1(1)
N/A
A0/Veref–
A1/Veref+
2
A2
3
A3
4
A4(2)
5
A5
6
A6
7
A7
8
A8
9
A9
Not Used
10
11
12
13
14
15
Not Used
N/A
On-chip Temperature Sensor
Reference Voltage (1.5 V)
DVSS
N/A
N/A
N/A
DVCC
N/A
(1) P8.0 and P8.1 are only available in the LQFP-64 package.
(2) When A4 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM
control register. The 1.2-V voltage can be directly measured by A4 channel.
The AD conversion can be started by software or a hardware trigger. 表 9-13 shows the trigger sources that are
available.
表9-13. ADC Trigger Signal Connections
ADCSHSx
TRIGGER SOURCE
Binary
00
Decimal
0
1
2
3
ADCSC bit (software trigger)
01
RTC event
TA1.1B
10
11
TA1.2B
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9.9.11 Liquid Crystal Display (LCD)
The LCD driver generates the segment and common signals to drive segment liquid crystal display (LCD) glass.
The LCD controller has dedicated data memories to hold segment drive information. Common and segment
signals are generated as defined by the mode. Static, 2-mux, 3-mux, up to 8-mux LCDs are supported. The
module can provide an LCD voltage independent from the main supply voltage with its integrated charge pump.
The LCD display contrast can be trimmed by setting the LCD drive voltage. The LCD module can be fully
functional in any power mode from AM to LPM3.5.
When supplied by the on-chip charge pump with on-chip regulator reference, the LCD driver needs five pins and
four external 0.1-µF capacitors to achieve low-power consumption during operation. 图 9-2 shows the
recommended connections.
R13
R23
R33
LCDCAP1
0.1 μF 0.1 μF 0.1 μF 0.1 μF
LCDCAP0
图9-2. LCD Power Supply Configuration With On-Chip Charge Pump and Regulator Reference
The LCD contains 20 16-bit words (40 bytes) display memory. The use of memory is flexible, depending on the
selected mode:
• 4-mux mode
– LCDM0 to LCDM19 can be used for LCD display contents. If it is not used as LCD drive pin, the
corresponding LCDMx can be used for user data (up to 20 bytes).
– LCDBM0 to LCDBM19 can be used for LCD blinking contents. If it is not used as blinking, the
corresponding LCDBMx can be used for user data (up to 20 bytes).
• 8-mux mode
– LCDM0 to LCDM39 can be used for LCD display contents. If it is not used as LCD drive pin, the
corresponding LCDMx can be used for user data (up to 40 bytes).
9.9.12 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
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9.9.13 Input/Output Schematics
9.9.13.1 Port P1 Input/Output With Schmitt Trigger
图9-3 shows the port schematic. 表9-14 summarizes the selection of the pin functions.
A0 to A7
From ADC A
P1REN.x
P1DIR.x
0
1
From Module
DVSS
DVCC
0
1
P1OUT.x
0
1
From Module
P1SEL0.x
EN
D
To module
P1IN.x
P1IE.x
Bus
Keeper
P1 Interrupt
D
S
Q
P1.0/UCA0TXD/UCA0SIMO/A0
P1.1/UCA0RXD/UCA0SOMI/A1
P1.2/UCA0CLK/A2
P1IFG.x
P1.3/UCA0STE/A3
Edge
Select
P1.4/MCLK/TCK/A4/VREF+
P1.5/TA0CLK/TMS/A5
P1.6/TA0.2/TDI/TCLK/A6
P1.7/TA0.1/TDO/A7
P1IES.x
From JTAG
To JTAG
图9-3. Port P1 Input/Output With Schmitt Trigger
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表9-14. Port P1 Pin Functions
CONTROL BITS AND SIGNALS(2)
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL0.x
ADCPCTLx(1)
JTAG
N/A
P1.0 (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
0
P1.0/UCA0TXD/
UCA0SIMO/A0
0
UCA0TXD/UCA0SIMO
A0
X
0
N/A
X
1 (x = 0)
N/A
P1.1 (I/O)
UCA0RXD/UCA0SOMI
A1
I: 0; O: 1
0
N/A
P1.1/UCA0RXD/
UCA0SOMI/A1
1
2
3
X
0
N/A
X
1 (x = 1)
N/A
P1.2 (I/O)
UCA0CLK
A2
I: 0; O: 1
0
N/A
P1.2/UCA0CLK/A2
P1.3/UCA0STE/A3
X
0
N/A
X
1 (x = 2)
N/A
P1.3 (I/O)
UCA0STE
A3
I: 0; O: 1
0
N/A
X
0
1 (x = 3)
0
N/A
X
N/A
P1.4 (I/O)
VSS
I: 0; O: 1
Disabled
0
1
0
Disabled
P1.4/MCLK/TCK/A4/
VREF+
4
5
6
7
MCLK
1
A4, VREF+
JTAG TCK
P1.5 (I/O)
TA0CLK
VSS
X
X
X
0
1 (x = 4)
Disabled
TCK
X
X
0
I: 0; O: 1
Disabled
0
1
0
Disabled
P1.5/TA0CLK/TMS/A5
P1.6/TA0.2/TDI/TCLK/ A6
P1.7/TA0.1/TDO/A7
1
A5
X
X
X
0
1 (x = 5)
Disabled
TMS
JTAG TMS
P1.6 (I/O)
TA0.CCI2A
TA0.2
X
X
0
I: 0; O: 1
Disabled
0
1
0
Disabled
1
A6
X
X
X
0
1 (x = 6)
Disabled
TDI/TCLK
Disabled
JTAG TDI/TCLK
P1.7 (I/O)
TA0.CCI1A
TA0.1
X
X
0
I: 0; O: 1
0
1
1
0
Disabled
A7
X
X
X
X
1 (x = 7)
X
Disabled
TDO
JTAG TDO
(1) Setting the ADCPCTLx bit in SYSCFG2 register will disable both the output driver and input Schmitt trigger to prevent leakage when
analog signals are applied.
(2) X = don't care
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9.9.13.2 Port P2 Input/Output With Schmitt Trigger
图9-4 shows the port schematic. 表9-15 summarizes the selection of the pin functions.
L24 to L31
From LCD
P2REN.x
P2DIR.x
DVSS
DVCC
0
1
P2OUT.x
P2IN.x
P2IE.x
Bus
Keeper
P2 Interrupt
1
D
S
Q
P2.0/L24
P2.1/L25
P2.2/L26
P2.3/L27
P2.4/L28
P2.5/L29
P2.6/L30
P2.7/L31
P2IFG.x
P2IES.x
1
Edge
Select
图9-4. Port P2 Input/Output With Schmitt Trigger
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表9-15. Port P2 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
LCDSy
P2.0 (I/O)
L24
I: 0; O: 1
0
P2.0/L24
P2.1/L25
P2.2/L26
P2.3/L27
P2.4/L28
P2.5/L29
P2.6/L30
0
1
X
1 (y = 24)
P2.1 (I/O)
L25
I: 0; O: 1
0
X
1 (y = 25)
P2.2 (I/O)
L26
I: 0; O: 1
0
2
3
4
5
6
7
X
1 (y = 26)
P2.3 (I/O)
L27
I: 0; O: 1
0
X
1 (y = 27)
P2.4 (I/O)
L28
I: 0; O: 1
0
X
1 (y = 28)
P2.5 (I/O)
L29
I: 0; O: 1
0
X
I: 0; O: 1
X
1 (y = 29)
0
P2.6 (I/O)
L30
1 (y = 30)
0
P2.7 (I/O)
L31
I: 0; O: 1
X
P2.7/L31
1 (y = 31)
(1) X= don't care
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9.9.13.3 Port P3 Input/Output With Schmitt Trigger
图9-5 shows the port schematic. 表9-16 summarizes the selection of the pin functions.
L8 to L15
From LCD E
P3REN.x
P3DIR.x
DVSS
DVCC
0
1
P3OUT.x
P3IN.x
Bus
Keeper
P3.0/L8
P3.1/L9
P3.2/L10
P3.3/L11
P3.4/L12
P3.5/L13
P3.6/L14
P3.7/L15
图9-5. Port P3 Input/Output With Schmitt Trigger
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表9-16. Port P3 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P3.x)
x
0
1
2
3
4
5
6
7
FUNCTION
P3DIR.x
LCDSy
P3.0 (I/O)
L8
I: 0; O: 1
0
P3.0/L8
X
1 (y = 8)
P3.1 (I/O)
L9
I: 0; O: 1
0
P3.1/L9
X
1 (y = 9)
P3.2 (I/O)
L10
I: 0; O: 1
0
P3.2/L10
P3.3/L11
P3.4/L12
P3.5/L13
P3.6/L14
X
1 (y = 10)
P3.3 (I/O)
L11
I: 0; O: 1
0
X
1 (y = 11)
P3.4 (I/O)
L12
I: 0; O: 1
0
X
1 (y = 12)
P3.5 (I/O)
L13
I: 0; O: 1
0
X
I: 0; O: 1
X
1 (y = 13)
0
P3.6 (I/O)
L14
1 (y = 14)
0
P3.7 (I/O)
L15
I: 0; O: 1
X
P3.7/L15
1 (y = 15)
(1) X= don't care
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9.9.13.4 Port P4.0 Input/Output With Schmitt Trigger
图9-6 shows the port schematic. 表9-17 summarizes the selection of the pin functions.
P4REN.x
P4DIR.x
0
1
From Module
DVSS
DVCC
0
1
P4OUT.x
0
1
From Module
P4SEL0.x
EN
D
To module
P4IN.x
Bus
Keeper
P4.0/TA1.1
图9-6. Port P4.0 Input/Output With Schmitt Trigger
表9-17. Port P4.0 Pin Functions
CONTROL BITS AND SIGNALS
PIN NAME (P4.x)
x
FUNCTION
P4DIR.x
P4SEL0.x
P4.0 (I/O)
TA1.CCI1A
TA1.1
I: 0; O: 1
0
P4.0/TA1.1
0
0
1
1
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9.9.13.5 Port P4.1 and P4.2 Input/Output With Schmitt Trigger
图9-7 shows the port schematic. 表9-18 summarizes the selection of the pin functions.
XIN, XOUT
P4REN.x
P4DIR.x
DVSS
DVCC
0
1
P4OUT.x
P4SEL0.x
P4IN.x
Bus
Keeper
P4.1/XIN
P4.2/XOUT
图9-7. Port P4.1 and P4.2 Input/Output With Schmitt Trigger
表9-18. Port P4.1 and P4.2 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P4.x)
x
1
2
FUNCTION
P4DIR.x
I: 0; O: 1
X
P4SEL0.x
P4.1 (I/O)
XIN
0
1
0
1
P4.1/XIN
P4.2 (I/O)
XOUT
I: 0; O: 1
X
P4.2/XOUT
(1) X= don't care
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9.9.13.6 Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
图9-8 shows the port schematic. 表9-19 summarizes the selection of the pin functions.
LCDCAP0, LCDCAP1
R13, R23, R33
From LCD
P4REN.x
P4DIR.x
DVSS
DVCC
0
1
P4OUT.x
P4IN.x
Bus
Keeper
P4.3/LCDCAP0
P4.4/LCDCAP1
P4.5/R33
P4.6/R23
P4.7/R13
图9-8. Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
表9-19. Port P4.3, P4.4, P4.5, P4.6, and P4.7 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P4.x)
x
3
4
5
6
7
FUNCTION
P4DIR.x
LCDPCTL(2)
P4.3 (I/O)
LCDCAP0
P4.4 (I/O)
LCDCAP1
P4.5 (I/O)
R33
I: 0; O: 1
X
1
0
1
0
1
0
1
0
1
P4.3/LCDCAP0
X
I: 0; O: 1
P4.4/LCDCAP1
P4.5/R33
X
I: 0; O: 1
X
I: 0; O: 1
X
P4.6 (I/O)
R23
P4.6/R23
P4.7 (I/O)
R13
I: 0; O: 1
X
P4.7/R13
(1) X= don't care
(2) Setting the LCDPCTL bit in SYSCFG2 register will disable both the output driver and input Schmitt trigger to prevent leakage when
analog signals are applied.
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9.9.13.7 Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
图9-9 shows the port schematic. 表9-20 summarizes the selection of the pin functions.
L32 to L35
From LCD E
P5REN.x
P5DIR.x
0
1
From Module
DVSS
DVCC
0
1
P5OUT.x
0
1
From Module
P5SEL0.x
EN
D
To module
P5IN.x
Bus
Keeper
P5.0/UCB0STE/L32
P5.1/UCB0CLK/L33
P5.2/UCB0SIMO/UCB0SDA/L34
P5.3/UCB0SOMI/UCB0SCL/L35
图9-9. Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
表9-20. Port P5.0, P5.1, P5.2, and P5.3 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL0.x
LCDSy
P5.0 (I/O)
UCB0STE
L32
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
P5.0/UCB0STE/L32
0
0
0
X
1 (y = 32)
P5.1 (I/O)
UCB0CLK
L33
I: 0; O: 1
0
P5.1/UCB0CLK/L33
1
2
3
0
0
X
1 (y = 33)
P5.2 (I/O)
I: 0; O: 1
0
P5.2/UCB0SIMO/
UCB0SDA/L34
UCB0SIMO/UCB0SDA
0
0
L34
X
1 (y = 34)
P5.3 (I/O)
I: 0; O: 1
0
0
P5.3/UCB0SOMI/
UCB0SCL/L35
UCB0SOMI/UCB0SCL
L35
0
X
1 (y = 35)
(1) X= don't care
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9.9.13.8 Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
图9-10 shows the port schematic. 表9-21 summarizes the selection of the pin functions.
L36 to L39
From LCD E
P5REN.x
P5DIR.x
DVSS
DVCC
0
1
P5OUT.x
P5IN.x
Bus
Keeper
P5.4/L36
P5.5/L37
P5.6/L38
P5.7/L39
图9-10. Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
表9-21. Port P5.4, P5.5, P5.6, and P5.7 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P5.x)
x
4
5
6
7
FUNCTION
P5DIR.x
I: 0; O: 1
X
LCDSy
P5.4 (I/O)
L36
0
P5.4/L36
1 (y = 36)
P5.5 (I/O)
L37
I: 0; O: 1
X
0
P5.5/L37
P5.6/L38
1 (y = 37)
0
P5.6 (I/O)
L38
I: 0; O: 1
X
1 (y = 38)
0
P5.7 (I/O)
L39
I: 0; O: 1
X
P5.7/L39
1 (y = 39)
(1) X= don't care
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9.9.13.9 Port P6 Input/Output With Schmitt Trigger
图9-11 shows the port schematic. 表9-22 summarizes the selection of the pin functions.
L16 to L23
From LCD E
P6REN.x
P6DIR.x
DVSS
DVCC
0
1
P6OUT.x
P6IN.x
Bus
Keeper
P6.0/L16
P6.1/L17
P6.2/L18
P6.3/L19
P6.4/L20
P6.5/L21
P6.6/L22
P6.7/L23
图9-11. Port P6 Input/Output With Schmitt Trigger
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表9-22. Port P6 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P6.x)
x
0
1
2
3
4
5
6
7
FUNCTION
P6DIR.x
LCDSy
P6.0 (I/O)
L16
I: 0; O: 1
0
P6.0/L16
X
1 (y = 16)
P6.1 (I/O)
L17
I: 0; O: 1
0
P6.1/L17
P6.2/L18
P6.3/L19
P6.4/L20
P6.5/L21
P6.6/L22
X
1 (y = 17)
P6.2 (I/O)
L18
I: 0; O: 1
0
X
1 (y = 18)
P6.3 (I/O)
L19
I: 0; O: 1
0
X
1 (y = 19)
P6.4 (I/O)
L20
I: 0; O: 1
0
X
1 (y = 20)
P6.5 (I/O)
L21
I: 0; O: 1
0
X
I: 0; O: 1
X
1 (y = 21)
0
P6.6 (I/O)
L22
1 (y = 22)
0
P6.7 (I/O)
L23
I: 0; O: 1
X
P6.7/L23
1 (y = 23)
(1) X= don't care
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9.9.13.10 Port P7 Input/Output With Schmitt Trigger
图9-12 shows the port schematic. 表9-23 summarizes the selection of the pin functions.
L0 to L7
From LCD_E
P7REN.x
P7DIR.x
DVSS
DVCC
0
1
P7OUT.x
P7IN.x
Bus
Keeper
P7.0/L0
P7.1/L1
P7.2/L2
P7.3/L3
P7.4/L4
P7.5/L5
P7.6/L6
P7.7/L7
图9-12. Port P7 Input/Output With Schmitt Trigger
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表9-23. Port P7 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P7.x)
x
0
1
2
3
4
5
6
7
FUNCTION
P7DIR.x
LCDSy
P7.0 (I/O)
L0
I: 0; O: 1
0
P7.0/L0
X
1 (y = 0)
P7.1 (I/O)
L1
I: 0; O: 1
0
P7.1/L1
P7.2/L2
P7.3/L3
P7.4/L4
P7.5/L5
P7.6/L6
X
1 (y = 1)
P7.2 (I/O)
L2
I: 0; O: 1
0
X
1 (y = 2)
P7.3 (I/O)
L3
I: 0; O: 1
0
1 (y = 3)
0
X
P7.4 (I/O)
L4
I: 0; O: 1
X
1 (y = 4)
0
P7.5 (I/O)
L5
I: 0; O: 1
X
I: 0; O: 1
X
1 (y = 5)
0
P7.6 (I/O)
L6
1 (y = 6)
0
P7.7 (I/O)
L7
I: 0; O: 1
X
P7.7/L7
1 (y = 7)
(1) X= don't care
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9.9.13.11 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
图9-13 shows the port schematic. 表9-24 summarizes the selection of the pin functions.
A8, A9
From ADC A
P8REN.x
P8DIR.x
0
1
From Module
DVSS
DVCC
0
1
P8OUT.x
0
1
From MCLK, ACLK
P8SEL0.x
EN
D
To module
P8IN.x
Bus
Keeper
P8.0/SMCLK/A8
P8.1/ACLK/A9
图9-13. Port P8.0 and P8.1 Input/Output With Schmitt Trigger
表9-24. Port P8.0 and P8.1 Pin Functions
CONTROL BITS AND SIGNALS(1)
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL0.x
ADCPCTLx(2)
P8.0 (I/O)
VSS
I: 0; O: 1
0
0
0
P8.0/SMCLK/A8
0
1
0
SMCLK
A8
1
X
X
0
1 (x = 8)
0
P8.1 (I/O)
VSS
I: 0; O: 1
0
1
X
P8.1/ACLK/A9
1
1
0
ACLK
A9
X
1 (x = 9)
(1) X= don't care
(2) Setting the ADCPCTLx bit in SYSCFG2 register will disable both the output driver and input Schmitt trigger to prevent leakage when
analog signals are applied.
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9.9.13.12 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
图9-14 shows the port schematic. 表9-25 summarizes the selection of the pin functions.
P8REN.x
P8DIR.x
0
1
From Module
DVSS
DVCC
0
1
P8OUT.x
0
1
From Module
P8SEL0.x
EN
D
To module
P8IN.x
Bus
Keeper
P8.2/TA1CLK
P8.3/TA1.2
图9-14. Port P8.2 and P8.3 Input/Output With Schmitt Trigger
表9-25. Port P8.2 and P8.3 Pin Functions
CONTROL BITS AND SIGNALS
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL0.x
P8.2 (I/O)
TA1 CLK
VSS
I: 0; O: 1
0
1
0
1
P8.2/TA1CLK
2
0
1
P8.3 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
P8.3/TA1.2
3
0
1
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9.10 Device Descriptors (TLV)
表 9-26 lists the Device IDs of the MSP430FR413x devices. 表 9-27 lists the contents of the device descriptor
tag-length-value (TLV) structure for the MSP430FR413x devices.
表9-26. Device IDs
DEVICE ID
DEVICE
1A04h
1A05h
81h
MSP430FR4133
MSP430FR4132
MSP430FR4131
F0h
F1h
81h
F2h
81h
表9-27. Device Descriptors
MSP430FR413x
ADDRESS
DESCRIPTION
VALUE
06h
Info length
1A00h
1A01h
1A02h
1A03h
1A04h
1A05h
1A06h
1A07h
1A08h
1A09h
1A0Ah
1A0Bh
1A0Ch
1A0Dh
1A0Eh
1A0Fh
1A10h
1A11h
1A12h
1A13h
1A14h
1A15h
1A16h
1A17h
1A18h
1A19h
1A1Ah
1A1Bh
1A1Ch
1A1Dh
CRC length
06h
Per unit
Per unit
CRC value(2)
Information Block
Device ID
See 表9-26
Hardware revision
Firmware revision
Die Record Tag
Per unit
Per unit
08h
Die Record length
0Ah
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
11h
Lot Wafer ID
Die Record
Die X position
Die Y position
Test Result
ADC Calibration Tag
ADC Calibration Length
08h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC Gain Factor
ADC Calibration
ADC Offset
ADC 1.5-V Reference Temperature Sensor 30°C
ADC 1.5-V Reference Temperature Sensor 85°C
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表9-27. Device Descriptors (continued)
MSP430FR413x
DESCRIPTION
ADDRESS
1A1Eh
1A1Fh
1A20h
VALUE
Calibration Tag
12h
Calibration Length
04h
Per unit
Per unit
Per unit
Per unit
Reference and DCO Calibration 1.5-V Reference Factor
1A21h
1A22h
DCO Tap Settings for 16 MHz, Temperature 30°C(1)
1A23h
(1) This value can be directly loaded into DCO bits in CSCTL0 register to get accurate 16-MHz frequency at room temperature, especially
when MCU exits from LPM3 and below. It is also suggested to use predivider to decrease the frequency if the temperature drift might
result an overshoot beyond 16 MHz.
(2) The CRC value covers the checksum from 1A04h to 1A77h by applying the CRC-CCITT-16 polynomial of x16 + x12 + x5 + 1.
9.11 Memory
表9-28 shows the memory organization of the MSP430FR413x devices.
表9-28. Memory Organization
ACCESS
MSP430FR4133
MSP430FR4132
MSP430FR4131
Memory (FRAM)
Main: interrupt vectors and
signatures
Read/Write
15KB
FFFFh to FF80h
FFFFh to C400h
8KB
FFFFh to FF80h
FFFFh to E000h
4KB
FFFFh to FF80h
FFFFh to F000h
(Optional Write Protect)
(1)
Main: code memory
2KB
27FFh to 2000h
1KB
23FFh to 2000h
512 bytes
21FFh to 2000h
RAM
Read/Write
Read/Write
512 bytes
19FFh to 1800h
512 bytes
19FFh to 1800h
512 bytes
19FFh to 1800h
Information Memory (FRAM)
(Optional Write Protect)
(2)
1KB
13FFh to 1000h
1KB
13FFh to 1000h
1KB
13FFh to 1000h
Bootloader (BSL) Memory (ROM)
Peripherals
Read only
4KB
0FFFh to 0000h
4KB
0FFFh to 0000h
4KB
0FFFh to 0000h
Read/Write
(1) The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See the SYS chapter in the MSP430FR4xx and
MSP430FR2xx Family User's Guide for more details.
(2) The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. See the SYS chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide for more details.
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9.11.1 Peripheral File Map
表9-29 shows the base address and the memory size of the registers of each peripheral, and 表9-30 through 表
9-49 show all of the available registers for each peripheral and their address offsets.
表9-29. Peripherals Summary
MODULE NAME
Special Functions (see 表9-30)
BASE ADDRESS
SIZE
0100h
0010h
0020h
0030h
0020h
0010h
0008h
0002h
0020h
0020h
0020h
0020h
0010h
0030h
0030h
0010h
0020h
0030h
0060h
0020h
0040h
0120h
PMM (see 表9-31)
0140h
SYS (see 表9-32)
0180h
CS (see 表9-33)
01A0h
01C0h
01CCh
0200h
FRAM (see 表9-34)
CRC (see 表9-35)
WDT (see 表9-36)
Port P1, P2 (see 表9-37)
Port P3, P4 (see 表9-38)
Port P5, P6 (see 表9-39)
Port P7, P8 (see 表9-40)
Capacitive Touch I/O (see 表9-41)
Timer0_A3 (see 表9-42)
Timer1_A3 (see 表9-43)
RTC (see 表9-44)
0220h
0240h
0260h
02E0h
0300h
0340h
03C0h
0500h
eUSCI_A0 (see 表9-45)
eUSCI_B0 (see 表9-46)
LCD (see 表9-47)
0540h
0600h
0660h
Backup Memory (see 表9-48)
ADC (see 表9-49)
0700h
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表9-30. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFR interrupt flag
SFRIE1
00h
02h
04h
SFRIFG1
SFRRPCR
SFR reset pin control
表9-31. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMMCTL0
PMMCTL1
PMMCTL2
PMMIFG
OFFSET
00h
PMM control 0
PMM control 1
PMM control 2
PMM interrupt flags
PM5 Control 0
02h
04h
0Ah
PM5CTL0
10h
表9-32. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
System control
SYSCTL
Bootloader configuration area
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
System configuration 0
System configuration 1
System configuration 2
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
20h
SYSRSTIV
SYSCFG0
SYSCFG1
SYSCFG2
22h
24h
表9-33. CS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
CSCTL0
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
CSCTL7
CSCTL8
OFFSET
00h
CS control register 0
CS control register 1
CS control register 2
CS control register 3
CS control register 4
CS control register 5
CS control register 6
CS control register 7
CS control register 8
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
表9-34. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
FRAM control 0
General control 0
General control 1
FRCTL0
GCCTL0
GCCTL1
04h
06h
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表9-35. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
CRC data input
CRC16DI
CRCDIRB
CRCINIRES
CRCRESR
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
02h
04h
06h
表9-36. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
REGISTER
OFFSET
Watchdog timer control
WDTCTL
00h
表9-37. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port P1 input
P1IN
Port P1 output
P1OUT
P1DIR
P1REN
P1SEL0
P1IV
02h
Port P1 direction
04h
Port P1 pulling register enable
Port P1 selection 0
06h
0Ah
0Eh
18h
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IES
P1IE
1Ah
1Ch
01h
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2SEL0
P2IV
03h
Port P2 direction
05h
Port P2 pulling register enable
Port P2 selection 0(1)
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
07h
0Bh
1Eh
19h
P2IES
P2IE
1Bh
1Dh
P2IFG
(1) Port P2 selection register does not feature any valid bits. P2SEL0 presents for 16-bit Port A operation with P1SEL0.
表9-38. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port P3 input
P3IN
Port P3 output
Port P3 direction
P3OUT
P3DIR
02h
04h
Port P3 pulling register enable
Port P3 selection 0(1)
Port P4 input
P3REN
P3SEL0
P4IN
06h
0Ah
01h
Port P4 output
P4OUT
P4DIR
03h
Port P4 direction
05h
Port P4 pulling register enable
Port P4 selection 0
P4REN
P4SEL0
07h
0Bh
(1) Port P3 selection register does not feature any valid bits. P3SEL0 presents for 16-bit Port B operation with P4SEL0.
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表9-39. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
0Ah
01h
03h
05h
07h
0Bh
Port P5 output
Port P5 direction
P5OUT
P5DIR
Port P5 pulling register enable
Port P5 selection 0
Port P6 input
P5REN
P5SEL0
P6IN
Port P6 output
P6OUT
P6DIR
Port P6 direction
Port P6 pulling register enable
Port P6 selection 0(1)
P6REN
P6SEL0
(1) Port P6 selection register does not feature any valid bits. P6SEL0 presents for 16-bit Port C operation with P5SEL0.
表9-40. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port P7 input
P7IN
Port P7 output
Port P7 direction
P7OUT
P7DIR
02h
04h
Port P7 pulling register enable
Port P7 selection 0(1)
Port P8 input
P7REN
P7SEL0
P8IN
06h
0Ah
01h
Port P8 output
P8OUT
P8DIR
03h
Port P8 direction
05h
Port P8 pulling register enable
Port P8 selection 0
P8REN
P8SEL0
07h
0Bh
(1) Port P7 selection register does not feature any valid bits. P7SEL0 presents for 16-bit Port D operation with P8SEL0.
表9-41. Capacitive Touch IO Registers (Base Address: 02E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Capacitive Touch IO 0 control
CAPTIO0CTL
0Eh
表9-42. Timer0_A3 Registers (Base Address: 0300h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
TA0 control
TA0CTL
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter register
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
02h
04h
06h
10h
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TA0 expansion register 0
TA0 interrupt vector
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
12h
14h
16h
20h
TA0IV
2Eh
表9-43. Timer1_A3 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
TA1 control
TA1CTL
Capture/compare control 0
TA1CCTL0
02h
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表9-43. Timer1_A3 Registers (Base Address: 0340h) (continued)
REGISTER DESCRIPTION
REGISTER
TA1CCTL1
TA1CCTL2
TA1R
OFFSET
04h
Capture/compare control 1
Capture/compare control 2
TA1 counter register
06h
10h
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TA1 expansion register 0
TA1 interrupt vector
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
12h
14h
16h
20h
TA1IV
2Eh
表9-44. RTC Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
RTCCTL
RTCIV
OFFSET
00h
RTC control
RTC interrupt vector
RTC modulo
04h
RTCMOD
RTCCNT
08h
RTC counter
0Ch
表9-45. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
REGISTER
UCA0CTLW0
UCA0CTLW1
UCA0BR0
OFFSET
00h
eUSCI_A control word 0
eUSCI_A control word 1
eUSCI_A control rate 0
eUSCI_A control rate 1
eUSCI_A modulation control
eUSCI_A status
02h
06h
UCA0BR1
07h
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
lUCA0IRTCTL
IUCA0IRRCTL
UCA0IE
08h
0Ah
0Ch
0Eh
10h
eUSCI_A receive buffer
eUSCI_A transmit buffer
eUSCI_A LIN control
eUSCI_A IrDA transmit control
eUSCI_A IrDA receive control
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
12h
13h
1Ah
1Ch
1Eh
UCA0IFG
UCA0IV
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表9-46. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER DESCRIPTION
REGISTER
UCB0CTLW0
UCB0CTLW1
UCB0BR0
OFFSET
eUSCI_B control word 0
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
eUSCI_B control word 1
eUSCI_B bit rate 0
eUSCI_B bit rate 1
UCB0BR1
eUSCI_B status word
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
eUSCI_B byte counter threshold
eUSCI_B receive buffer
eUSCI_B transmit buffer
eUSCI_B I2C own address 0
eUSCI_B I2C own address 1
eUSCI_B I2C own address 2
eUSCI_B I2C own address 3
eUSCI_B receive address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
UCB0IFG
UCB0IV
表9-47. LCD Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
LCDCTL0
LCDCTL1
LCDBLKCTL
LCDMEMCTL
LCDVCTL
LCDPCTL0
LCDPCTL1
LCDPCTL2
LCDCSS0
LCDCSS1
LCDCSS2
LCDIV
OFFSET
00h
LCD control register 0
LCD control register 1
LCD blink control register
LCD memory control register
LCD voltage control register
LCD port control 0
02h
04h
06h
08h
0Ah
0Ch
0Eh
14h
LCD port control 1
LCD port control 2
LCD COM/SEG select register
LCD COM/SEG select register
LCD COM/SEG select register
LCD interrupt vector
Display memory Static and 2 to 4 mux modes
LCD memory 0
16h
18h
1Eh
LCDM0
LCDM1
LCDM2
20h
21h
22h
LCD memory 1
LCD memory 2
⋮
⋮
⋮
LCD memory 19
LCDM19
33h
34h
Reserved(1)
⋮
⋮
⋮
Reserved(1)
3Fh
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表9-47. LCD Registers (Base Address: 0600h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
Blinking memory for Static and 2 to 4 mux modes
LCD blinking memory 0
LCDBM0
LCDBM1
40h
41h
LCD blinking memory 1
⋮
⋮
⋮
LCD blinking memory 19
LCDBM19
53h
54h
Reserved(1)
⋮
⋮
⋮
Reserved(1)
5Fh
Display memory for 5 to 8 mux modes
LCD memory 0
LCD memory 1
LCD memory 2
⋮
LCDM0
LCDM1
LCDM2
20h
21h
22h
⋮
⋮
LCD memory 39
Reserved(2)
⋮
LCDM39
47h
48h
⋮
⋮
Reserved(2)
5Fh
(1) In static and 2-mux to 4-mux modes, LCD memory and blink memory 40 to 63 are not physically implemented.
(2) In 5-mux to 8-mux modes, LCD memory and blink memory 40 to 63 are not physically implemented.
表9-48. Backup Memory Registers (Base Address: 0660h)
REGISTER DESCRIPTION
REGISTER
BAKMEM0
BAKMEM1
BAKMEM2
BAKMEM3
BAKMEM4
BAKMEM5
BAKMEM6
BAKMEM7
BAKMEM8
BAKMEM9
BAKMEM10
BAKMEM11
BAKMEM12
BAKMEM13
BAKMEM14
BAKMEM15
OFFSET
00h
Backup memory 0
Backup memory 1
Backup memory 2
Backup memory 3
Backup memory 4
Backup memory 5
Backup memory 6
Backup memory 7
Backup memory 8
Backup memory 9
Backup memory 10
Backup memory 11
Backup memory 12
Backup memory 13
Backup memory 14
Backup memory 15
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
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表9-49. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
ADCCTL0
ADCCTL1
ADCCTL2
ADCLO
OFFSET
ADC control register 0
00h
02h
04h
06h
08h
0Ah
12h
1Ah
1Ch
1Eh
ADC control register 1
ADC control register 2
ADC window comparator low threshold
ADC window comparator high threshold
ADC memory control register 0
ADC conversion memory register
ADC interrupt enable
ADCHI
ADCMCTL0
ADCMEM0
ADCIE
ADC interrupt flags
ADCIFG
ADC interrupt vector word
ADCIV
9.12 Identification
9.12.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The device-
specific errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see 节11.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on
this value, see the "Hardware Revision" entries in 节9.10.
9.12.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific errata
sheet describes these markings. For links to all of the errata sheets for the devices in this data sheet, see 节
11.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details
on this value, see the "Device ID" entries in 节9.10.
9.12.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in MSP430
Programming With the JTAG Interface.
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10 Applications, Implementation, and Layout
备注
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
10.1 Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430FR413x devices. These
guidelines are to make sure that the device has proper connections for powering, programming, debugging, and
optimum analog performance.
10.1.1 Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling capacitor to
the DVCC and DVSS pins (see 图 10-1). Higher-value capacitors may be used but can impact supply rail ramp-
up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few
millimeters).
DVCC
+
Power Supply
Decoupling
DVSS
10 µF
100 nF
图10-1. Power Supply Decoupling
10.1.2 External Oscillator
This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass
capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the respective
oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT pin can be used
for other purposes. If they are left unused, they must be terminated according to 节7.4.
图10-2 shows a typical connection diagram.
XIN
XOUT
CL1
CL2
图10-2. Typical Crystal Connection
See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
10.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or MSP-
FET430UIF) can be used to program and debug code on the target board. In addition, the connections also
support the MSP-GANG production programmers, thus providing an easy way to program prototype boards, if
desired. 图 10-3 shows the connections between the 14-pin JTAG connector and the target device required to
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support in-system programming and debugging for 4-wire JTAG communication. 图 10-4 shows the connections
for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are identical.
Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-FET430UIF
interface modules and MSP-GANG have a VCC-sense feature that, if used, requires an alternate connection (pin
4 instead of pin 2). The VCC-sense feature senses the local VCC present on the target board (that is, a battery or
other local power supply) and adjusts the output signals accordingly. 图 10-3 and 图 10-4 show a jumper block
that supports both scenarios of supplying VCC to the target board. If this flexibility is not required, the desired VCC
connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be connected at the same
time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s Guide.
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL
TDO/TDI
TDI
TDO/TDI
TDI
2
1
VCC TARGET
4
3
TMS
TMS
6
5
7
TEST
TCK
8
TCK
GND
RST
10
12
14
9
11
13
TEST/SBWTCK
DVSS
C1
1 nF
(see Note B)
A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection
J2.
B. The upper limit for C1 is 1.1 nF when using current TI tools.
图10-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
DVCC
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
VCC TARGET
TDO/TDI
2
1
3
5
7
9
RST/NMI/SBWTDIO
4
6
TCK
8
GND
10
12
14
11
13
TEST/SBWTCK
DVSS
C1
1 nF
(see Note B)
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or
programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and
any capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is
1.1 nF when using current TI tools.
图10-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
10.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge
sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI.
When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either pullup or
pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not. If the RST/NMI
pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-kΩpullup
resistor to the RST/NMI pin with a 1.1-nF pulldown capacitor. The pulldown capacitor should not exceed 1.1 nF
when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like
FET interfaces or GANG programmers.
See the MSP430FR4xx and MSP430FR2xx Family User's Guide for more information on the referenced control
registers and bits.
10.1.5 Unused Pins
For details on the connection of unused pins, see 节7.4.
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10.1.6 General Layout Recommendations
• Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430 32-kHz
Crystal Oscillators for recommended layout guidelines.
• Proper bypass capacitors on DVCC and reference pins, if used.
• Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching
signals such as PWM or JTAG signals away from the oscillator circuit.
• Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
10.1.7 Do's and Don'ts
During power up, power down, and device operation, DVCC must not exceed the limits specified in 节 8.1.
Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and
FRAM.
10.2 Peripheral- and Interface-Specific Design Information
10.2.1 ADC Peripheral
10.2.1.1 Partial Schematic
图10-5 shows the recommended circuit for ADC grounding and noise reduction.
DVSS
Using an external
VREF+/VEREF+
positive reference
+
100 nF
10 µF
Using an external
negative reference
VEREF-
+
10 µF
100 nF
图10-5. ADC Grounding and Noise Considerations
10.2.1.2 Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be
followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with other
analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can
add to or subtract from the reference or input voltages of the ADC. The general guidelines in 节10.1.1 combined
with the connections shown in 节10.2.1.1 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital switching or
switching power supplies can corrupt the conversion result. TI recommends a noise-free design using separate
analog and digital ground planes with a single-point connection to achieve high accuracy.
图 10-5 shows the recommended decoupling circuit when an external voltage reference is used. The internal
reference module has a maximum drive current as described in the sections ADC Pin Enable and 1.2-V
Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-μF capacitor buffers the reference pin and filters low-frequency ripple. A
100-nF bypass capacitor filters out high-frequency noise.
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10.2.1.3 Layout Guidelines
Components that are shown in the partial schematic (see 图 10-5) should be placed as close as possible to the
respective device pins to avoid long traces, because they add additional parasitic capacitance, inductance, and
resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM), because
the high-frequency switching can be coupled into the analog signal.
10.2.2 LCD_E Peripheral
10.2.2.1 Partial Schematic
Required LCD connections greatly vary by the type of display that is used (static or multiplexed), whether
external or internal biasing is used, and also whether the on-chip charge pump is employed. For any display
used, LCD_E has configurable segment (Sx) or common (COMx) signals connected to the MCU which allows
optimal PCB layout and for the design of the application software.
Because LCD connections are application specific, it is difficult to provide a single one-fits-all schematic.
However, for an example of connecting a 4-mux LCD with 27 segment lines that has a total of 4 × 27 = 108
individually addressable LCD segments to an MSP430FR4133, see the MSP-EXP430FR4133 LaunchPad™
development kit as a reference.
10.2.2.2 Design Requirements
Due to the flexibility of the LCD_E peripheral module to accommodate various segment-based LCDs, selecting
the right display for the application in combination with determining specific design requirements is often an
iterative process. There can be well-defined requirements in terms of how many individually addressable LCD
segments must be controlled, what the requirements for LCD contrast are, which device pins are available for
LCD use and which are required by other application functions, and what the power budget is, to name just a
few. TI strongly recommends reviewing the LCD_E peripheral module chapter in the MSP430FR4xx and
MSP430FR2xx Family User's Guide during the initial design requirements and decision process. 表 10-1
provides a brief overview over different choices that can be made and their impact.
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表10-1. LCD_E Design Options
OPTION OR FEATURE
IMPACT OR USE CASE
Multiplexed LCD
•
•
•
•
•
Enable displays with more segments
Use fewer device pins
LCD contrast decreases as mux level increases
Power consumption increases with mux level
Requires multiple intermediate bias voltages
Static LCD
•
•
•
•
Limited number of segments that can be addressed
Use a relatively large number of device pins
Use the least amount of power
Use only VCC and GND to drive LCD signals
Internal Bias Generation
External Bias Generation
•
•
•
Simpler solution –no external circuitry
Independent of VLCD source
Somewhat higher power consumption
•
•
•
Requires external resistor ladder divider
Resistor size depends on display
Ability to adjust drive strength to optimize tradeoff between power consumption and good drive of large
segments (high capacitive load)
•
•
External resistor ladder divider can be stabilized through capacitors to reduce ripple
Internal Charge Pump
Helps ensure a constant level of contrast despite decaying supply voltage conditions (battery-powered
applications)
•
•
•
Programmable voltage levels allow software-driven contrast control
Requires an external capacitor on the LCDCAP pins
Higher current consumption than simply using VCC for the LCD driver
10.2.2.3 Detailed Design Procedure
A major component in designing the LCD solution is determining the exact connections between the LCD_E
peripheral module and the display itself. Two basic design processes can be employed for this step, although
often a balanced co-design approach is recommended:
• PCB layout-driven design
• Software-driven design
In the PCB layout-driven design process, LCD_E offers configurable segment Sx and common COMx signals
which are connected to the respective MSP430 device pins so that the routing of the PCB can be optimized to
minimize signal crossings and to keep signals on one side of the PCB only, typically the top layer. For example,
using a multiplexed LCD, it is possible to arbitrarily connect the Sx and COMx signals between the LCD and the
MSP430 device as long as segment lines are swapped with segment lines and common lines are swapped with
common lines. It is also possible to not contiguously connect all segment lines but rather skip LCD_E module
segment connections to optimize layout or to allow access to other functions that may be multiplexed on a
particular device port pin. Employing a purely layout-driven design approach, however, can result in the LCD_E
module control bits that are responsible for turning on and off segments to appear scattered throughout the
memory map of the LCD controller (LCDMx registers). This approach potentially places a rather large burden on
the software design that may also result in increased energy consumption due to the computational overhead
required to work with the LCD.
The other extreme is a purely software-driven approach that starts with the idea that control bits for LCD
segments that are frequently turned on and off together should be co-located in memory in the same LCDMx
register or in adjacent registers. For example, in case of a 4-mux display that contains several 7-segment digits,
from a software perspective it can be very desirable to control all 7 segments of each digit though a single byte-
wide access to an LCDMx register. And consecutive segments are mapped to consecutive LCDMx registers.
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This allows use of simple look-up tables or software loops to output numbers on an LCD, reducing computational
overhead and optimizing the energy consumption of an application. Establishing of the most convenient memory
layout needs to be performed in conjunction with the specific LCD that is being used to understand its design
constraints in terms of which segment and which common signals are connected to, for example, a digit.
For design information regarding the LCD controller input voltage selection including internal and external
options, contrast control, and bias generation, see the LCD_E controller chapter in the MSP430FR4xx and
MSP430FR2xx Family User's Guide.
10.2.2.4 Layout Guidelines
LCD segment (Sx) and common (COMx) signal traces are continuously switching while the LCD is enabled and
should, therefore, be kept away from sensitive analog signals such as ADC inputs to prevent any noise coupling.
TI recommends keeping the LCD signal traces on one side of the PCB grouped together in a bus-like fashion. A
ground plane underneath the LCD traces and guard traces employed alongside the LCD traces can provide
shielding.
If the internal charge pump of the LCD module is used, the externally provided capacitor on the LCDCAP0 and
LCDCAP1 pins should be located as close as possible to the MCU. The capacitor should be connected to the
device using a short and direct trace.
For an example layout of connecting a 4-mux LCD with 27 segments to an MSP430FR4133 and using the
charge pump feature, see the MSP-EXP430FR4133 LaunchPad development kit.
10.2.3 Timer
10.2.3.1 Generate Accurate PWM Using Internal Oscillator
Generating an accurate PWM signal using the device internal oscillator is an important feature for many cost-
sensitive applications in which an external crystal is not desired. The MSP430FR4133 uses an on-chip 32-kHz
RC oscillator (REFO) combined with the 16-MHz digitally controlled oscillator (DCO) with frequency-locked loop
(FLL) to provide the clock source for the timer peripheral to generate the PWM. The REFO frequency may
change across different temperatures. To achieve improved PWM accuracy, application software may
periodically measure the device temperature and compute an appropriate timer capture/compare correction
value to offset for REFO temperature drift. For more information on how to implement this algorithm refer to How
to Achieve Higher Accuracy Timer with Internal Oscillator on MSP430 . 图 10-6 shows the absolute value of a
typical error percentage for a 44-kHz PWM signal over the temperature range.
The absolute value error percentages shown below can be interpreted as either positive or negative resulting in
a slightly faster or slower PWM frequency.
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图10-6. Calibrated 44-kHz Timer PWM Error Magnitude
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10.3 Typical Applications
表 10-2 lists reference designs that demonstrate use of the MSP430FR413x family of devices in different real-
world application scenarios. Consult these designs for additional guidance regarding schematic, layout, and
software implementation. For the most up-to-date list of available reference designs, visit TI reference designs.
表10-2. Reference Designs
DESIGN NAME
LINK
Thermostat Implementation With MSP430FR4xx
TIDM-FRAM-THERMOSTAT
Water Meter Implementation With MSP430FR4xx
TIDM-FRAM-WATERMETER
TIDM-REMOTE-CONTROLLER-FOR-AC
Remote Controller of Air Conditioner Using Low-Power Microcontroller
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11 Device and Documentation Support
11.1 Getting Started
For an introduction to the MSP430 family of devices and the tools and libraries that are available to help with
your development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview.
11.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS –Experimental device that is not necessarily representative of the final device's electrical specifications
MSP –Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. 图11-1 provides a legend for reading the complete device name.
MSP 430 FR
4
133
I
PM
R
Distribution Format
Processor Family
Platform
Packaging
Memory Type
Temperature Range
Series
Feature Set
Processor Family
Platform
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
430 = TI’s 16-Bit MSP430 Low-Power Microcontroller Platform
Memory Type
Series
FR = FRAM
4 = FRAM 4 series up to 16 MHz with LCD
Feature Set
First and Second Digits: ADC Channels / 16-bit Timers / I/Os Third Digit: FRAM (KB) / SRAM (KB)
13 = Up to 10 / 3 / Up to 60
3 = 16 / 2
2 = 8 / 1
1 = 4 / 0.5
Temperature Range
Packaging
I = –40°C to 85°C
http://www.ti.com/packaging
Distribution Format
T = Small reel
R = Large reel
No marking = Tube or tray
图11-1. Device Nomenclature
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11.3 Tools and Software
表 11-1 lists the debug features supported by the MSP430FR413x microcontrollers. See the Code Composer
Studio IDE for MSP430 MCUs User's Guide for details on the available features.
表11-1. Hardware Features
BREAK-
POINTS
(N)
RANGE
BREAK-
POINTS
LPMX.5
DEBUGGING
SUPPORT
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
CLOCK
CONTROL SEQUENCER
STATE
TRACE
BUFFER
MSP430Xv2
Yes
Yes
3
Yes
Yes
No
No
No
Design Kits and Evaluation Modules
MSP430FR4133 LaunchPad Development Kit
The MSP-EXP430FR4133 LaunchPad development kit is an easy-to-use Evaluation Module (EVM) for the
MSP430FR4133 microcontroller. It contains everything needed to start developing on the MSP430 ultra-low-
power (ULP) FRAM-based microcontroller (MCU) platform, including on-board emulation for programming,
debugging, and energy measurements.
MSP-TS430PM64D Target Development Board for MSP430FR2x/4x MCUs
The MSP-TS430PM64D is a stand-alone 64-pin ZIF socket target board used to program and debug the
MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.
MSP-FET430U64D Target Development Board (64-pin) and MSP-FET Programmer Bundle for MSP430FR2x/4x
MCUs
The MSP-FET430U64D is a bundle containing the MSP-FET emulator and MSP-TS430PM64D 64-pin ZIF
socket target board to program and debug the MSP430 MCU in-system through the JTAG interface or the Spy
Bi-Wire (2-wire JTAG) protocol.
Software
MSP430Ware™ Software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 MCU design resources, MSP430Ware software also includes a high-level API called MSP Driver
Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
MSP430FR413x, MSP430FR203x Code Examples
C code examples are available for every MSP device that configures each of the integrated peripherals for
various application needs.
FRAM Embedded Software Utilities for MSP Ultra-Low-Power Microcontrollers
The TI FRAM Utilities software is designed to grow as a collection of embedded software utilities that leverage
the ultra-low-power and virtually unlimited write endurance of FRAM. The utilities are available for MSP430FRxx
FRAM microcontrollers and provide example code to help start application development.
MSP430 Touch Pro GUI
The MSP430 Touch Pro Tool is a PC-based tool that can be used to verify capacitive touch button, slider, and
wheel designs. The tool receives and visualizes captouch sensor data to help the user quickly and easily
evaluate, diagnose, and tune button, slider, and wheel designs.
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MSP430 Touch Power Designer GUI
The MSP430 Capacitive Touch Power Designer enables the calculation of the estimated average current draw
for a given MSP430 capacitive touch system. By entering system parameters such as operating voltage,
frequency, number of buttons, and button gate time, the user can have a power estimate for a given capacitive
touch configuration on a given device family in minutes.
Digital Signal Processing (DSP) Library for MSP Microcontrollers
The Digital Signal Processing library is a set of highly optimized functions to perform many common signal
processing operations on fixed-point numbers for MSP430 and MSP432 microcontrollers. This function set is
typically used for applications where processing-intensive transforms are done in real-time for minimal energy
and with very high accuracy. This optimal use of the MSP intrinsic hardware for fixed-point math allows for
significant performance gains.
MSP Driver Library
The abstracted API of MSP Driver Library provides easy-to-use function calls that free you from directly
manipulating the bits and bytes of the MSP430 hardware. Thorough documentation is delivered through a
helpful API Guide, which includes details on each function call and the recognized parameters. Developers can
use Driver Library functions to write complete projects with minimal overhead.
MSP EnergyTrace Technology
EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and
displays the energy profile of the application and helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor
ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully use the unique ultra-
low-power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new microcontroller
developers, ULP Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and remarks to highlight areas
of your code that can be further optimized for lower power.
Fixed Point Math Library for MSP
The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 devices. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath
libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430
Continuing to innovate in the low-power and low-cost microcontroller space, TI provides MSPMATHLIB.
Leveraging the intelligent peripherals of our devices, this floating-point math library of scalar functions is up to 26
times faster than the standard MSP430 math functions. Mathlib is easy to integrate into your designs. This library
is free and is integrated in both Code Composer Studio IDE and IAR Embedded Workbench IDE.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio (CCS) integrated development environment (IDE) supports all MSP microcontroller
devices. CCS comprises a suite of embedded software utilities used to develop and debug embedded
applications. CCS includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features.
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Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) directly to the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – which lets users
quickly begin application development on MSP low-power MCUs. Creating MCU software usually requires
downloading the resulting binary program to the MSP device for validation and debugging.
MSP-GANG Production Programmer
The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight
identical MSP430 or MSP432 flash or FRAM devices at the same time. The MSP Gang Programmer connects to
a host PC using a standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
11.4 Documentation Support
The following documents describe the MSP430FR413x microcontrollers. Copies of these documents are
available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com. In the upper right corner, click the "Alert me" button. This registers you to receive a weekly
digest of product information that has changed (if any). For change details, check the revision history of any
revised document.
Errata
MSP430FR4133 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430FR4132 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430FR4131 Device Erratasheet
Describes the known exceptions to the functional specifications.
User's Guides
MSP430FR4xx and MSP430FR2xx Family User's Guide
Detailed description of all modules and peripherals available in this device family.
MSP430 FRAM Device Bootloader (BSL) User's Guide
The bootloader (BSL) on MSP430 MCUs lets users communicate with embedded memory in the MSP430 MCU
during the prototyping phase, final production, and in service. Both the programmable memory (FRAM memory)
and the data memory (RAM) can be modified as required.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module of the
MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,
it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).
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MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the
parallel port interface and the USB interface, are described.
Application Reports
MSP430 FRAM Technology –How To and Best Practices
FRAM is a nonvolatile memory technology that behaves similar to SRAM while enabling a whole host of new
applications, but also changing the way firmware should be designed. This application report outlines the how to
and best practices of using FRAM technology in MSP430 from an embedded software development perspective.
It discusses how to implement a memory layout according to application-specific code, constant, data space
requirements, and the use of FRAM to optimize application energy consumption.
MSP430 32-kHz Crystal Oscillators
Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the
correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages
and the need for designing cost-effective and ultra-low-power components. This application report addresses
three different ESD topics to help board designers and OEMs understand and design robust system-level
designs.
11.5 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
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www.ti.com.cn
11.6 Trademarks
LaunchPad™, MSP430Ware™, MSP430™, Code Composer Studio™, TI E2E™, and ULP Advisor™ are
trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
11.9 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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www.ti.com.cn
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430FR4131IG48
MSP430FR4131IG48R
MSP430FR4131IG56
MSP430FR4131IG56R
MSP430FR4131IPMR
MSP430FR4132IG48
MSP430FR4132IG48R
MSP430FR4132IG56
MSP430FR4132IG56R
MSP430FR4132IPMR
MSP430FR4133IG48
MSP430FR4133IG48R
MSP430FR4133IG56
MSP430FR4133IG56R
MSP430FR4133IPM
MSP430FR4133IPMR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
LQFP
DGG
DGG
DGG
DGG
PM
48
48
56
56
64
48
48
56
56
64
48
48
56
56
64
64
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
FR4131
2000 RoHS & Green
35 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
FR4131
FR4131
FR4131
FR4131
FR4132
FR4132
FR4132
FR4132
FR4132
FR4133
FR4133
FR4133
FR4133
FR4133
FR4133
2000 RoHS & Green
1000 RoHS & Green
TSSOP
TSSOP
TSSOP
TSSOP
LQFP
DGG
DGG
DGG
DGG
PM
40
2000 RoHS & Green
35 RoHS & Green
RoHS & Green
2000 RoHS & Green
1000 RoHS & Green
TSSOP
TSSOP
TSSOP
TSSOP
LQFP
DGG
DGG
DGG
DGG
PM
40
2000 RoHS & Green
35 RoHS & Green
2000 RoHS & Green
160 RoHS & Green
1000 RoHS & Green
RoHS & Green
LQFP
PM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2021
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430FR4131IG48R TSSOP
MSP430FR4131IPMR LQFP
DGG
PM
48
64
48
56
64
56
64
2000
1000
2000
2000
1000
2000
1000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
24.4
24.4
24.4
24.4
24.4
24.4
24.4
8.6
13.0
8.6
13.0
13.0
13.0
15.6
13.0
15.6
13.0
1.8
2.1
1.8
1.8
2.1
1.8
2.1
12.0
16.0
12.0
12.0
16.0
12.0
16.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
Q1
Q2
Q1
Q1
Q2
Q1
Q2
MSP430FR4132IG48R TSSOP
MSP430FR4132IG56R TSSOP
DGG
DGG
PM
8.6
MSP430FR4132IPMR
MSP430FR4133IG56R TSSOP
MSP430FR4133IPMR LQFP
LQFP
13.0
8.6
DGG
PM
13.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430FR4131IG48R
MSP430FR4131IPMR
MSP430FR4132IG48R
MSP430FR4132IG56R
MSP430FR4132IPMR
MSP430FR4133IG56R
MSP430FR4133IPMR
TSSOP
LQFP
DGG
PM
48
64
48
56
64
56
64
2000
1000
2000
2000
1000
2000
1000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
43.0
43.0
43.0
TSSOP
TSSOP
LQFP
DGG
DGG
PM
TSSOP
LQFP
DGG
PM
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
MSP430FR4131IG48
MSP430FR4131IG56
MSP430FR4132IG48
MSP430FR4132IG56
MSP430FR4133IG48
MSP430FR4133IG56
DGG
DGG
DGG
DGG
DGG
DGG
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
48
56
48
56
48
56
40
35
40
35
40
35
530
530
530
530
530
530
11.89
11.89
11.89
11.89
11.89
11.89
3600
3600
3600
3600
3600
3600
4.9
4.9
4.9
4.9
4.9
4.9
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
MSP430FR4133IPM
PM
LQFP
64
160
8 x 20
150
315 135.9 7620 15.2
13.1
13
Pack Materials-Page 4
PACKAGE OUTLINE
PM0064A
LQFP - 1.6 mm max height
SCALE 1.400
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
33
16
32
17
A
0.27
0.17
64X
60X 0.5
4X 7.5
0.08
C A B
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1.4)
1.6 MAX
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215162/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
49
64
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
33
16
17
32
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215162/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
64
49
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
16
33
17
32
(11.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4215162/A 03/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
29
0.27
0.17
6.2
6.0
56X
1.2 MAX
0.08
C A
B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
28
29
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DGG0048A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
3
5
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
46X 0.5
48
1
12.6
12.4
NOTE 3
2X
11.5
24
B
25
0.27
0.17
48X
6.2
6.0
1.2
1.0
0.08
C A B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.75
0.05
0.50
DETAIL A
TYPICAL
4214859/B 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
(R0.05)
TYP
SYMM
24
25
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214859/B 11/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
SYMM
(R0.05) TYP
24
25
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4214859/B 11/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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