MSP430FR2422IRHLR_技术文档

MSP430FR2422

ZHCSHB5D –JANUARY 2018 –REVISED JANUARY 2021

MSP430FR2422 混合信号微控制器

– 一个eUSCI_B 接口，支持SPI 和I²C

• 时钟系统(CS)

1 特性

• 嵌入式微控制器

– 片上32kHz RC 振荡器(REFO)

– 带有锁频环(FLL) 的片上16MHz 数控振荡器

(DCO)

– 16 位RISC 架构

– 支持的时钟频率最高可达16MHz

– 1.8V 至3.6V 的宽电源电压范围（最低电源电压

受限于SVS 电平，请参阅SVS 规格）

• 优化的超低功耗模式

• 室温下的精度为±1%（具有片上基准）

– 片上超低频10kHz 振荡器(VLO)

– 片上高频调制振荡器(MODOSC)

– 外部32kHz 晶振(LFXT)

– 可编程MCLK 预分频器（1 至128）

– 通过可编程预分频器（1、2、4 或8）从MCLK

获得的SMCLK

– 工作模式：120µA/MHz（典型值）

– 待机：采用32768Hz 晶振的LPM3.5 实时时钟

(RTC) 计数器：710nA（典型值）

– 关断(LPM4.5)：36nA，未使用SVS

• 低功耗铁电RAM (FRAM)

• 通用输入/输出和引脚功能

– 非易失性存储器容量高达7.5KB

– 内置错误修正码(ECC)

– 可配置的写保护

– 共计15 个I/O（采用VQFN-20 封装）

– 15 个中断引脚（P1 和P2）可以将MCU 从低

功耗模式下唤醒

– 对程序、常量和存储的统一存储

– 耐写次数达10¹⁵次

– 抗辐射和非磁性

• 开发工具和软件

– 开发工具

• 目标开发板MSP‑TS430RHL20

• 系列成员（另请参阅器件比较）

– MSP430FR2422：7.25KB 程序FRAM、256B

信息FRAM、2KB RAM

• 封装选项

– FRAM 与SRAM 之比高达4:1

• 高性能模拟

– 高达8 通道10 位模数转换器(ADC)

• 1.5V 的内部基准电压

• 采样保持200ksps

• 智能数字外设

– 20 引脚：VQFN (RHL)

– 16 引脚：TSSOP (PW)

– 两个16 位计时器，每个计时器有三个捕捉/比较

寄存器(Timer_A3)

2 应用

– 一个仅用作计数器的16 位RTC

– 16 位循环冗余校验(CRC)

• 增强型串行通信，支持引脚重映射功能（请参阅器

件比较）

• 工业传感器

• 电池组

• 便携式电器

• 电动牙刷

• 低功耗医疗、健康和健身器材

– 一个eUSCI_A 接口，支持UART、IrDA 和SPI

3 说明

MSP430FR2422 是MSP430^™超值系列微控制器(MCU) 产品组合的其中一个器件，该超值系列微控制器是 TI 成

本超低的 MCU 系列，适用于感应和测量应用。MSP430FR2422 MCU 可提供 8KB 非易失性存储器并配备8 通道

10 位 ADC。该架构、FRAM 和集成外设与多种低功耗模式相结合，针对在便携式和电池供电传感应用中延长电

池寿命进行了优化。采用16 引脚TSSOP 或20 引脚VQFN 封装。

TI 的 MSP430 超低功耗 FRAM 微控制器平台将独特的嵌入式 FRAM 和全面的超低功耗系统架构相结合，从而使

系统设计人员能够在降低能耗的同时提升性能。FRAM 技术兼有 RAM 的低功耗快速写入、灵活性、耐用性和闪

存非易失性等特性。

MSP430FR2422 MCU 由广泛的硬件和软件生态系统进行支持，提供参考设计和代码示例，协助用户快速开展设

计。开发套件包括 MSP-TS430RHL20 20 引脚目标开发板。TI 还提供免费的 MSP430Ware^™软件，该软件以

Code Composer Studio^™IDE 桌面和云版本组件的形式提供（位于 TI Resource Explorer 中）。E2E^™支持论坛

还为MSP430 MCU 提供广泛的在线配套资料、培训和在线支持。

有关完整的模块说明，请参阅《MSP430FR4xx 和MSP430FR2xx 系列器件用户指南》。

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLASEE5

MSP430FR2422

ZHCSHB5D –JANUARY 2018 –REVISED JANUARY 2021

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器件信息

封装

器件型号⁽¹⁾

MSP430FR2422IPW16

MSP430FR2422IRHL

封装尺寸⁽²⁾

5mm × 4.4mm

4.5mm × 3.5mm

TSSOP (16)

VQFN (20)

(1) 要获得最新的产品、封装和订购信息，请参阅节12 中的封装选项附录，或者访问德州仪器(TI) 网站

www.ti.com.cn。

(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参阅机械数据（节12 中）。

CAUTION

系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范，以防发生电气过载或对数据或代码存储器造

成干扰。如需更多信息，请参阅《MSP430 系统级ESD 注意事项》。

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4 功能方框图

图4-1 给出了功能方框图。

XIN XOUT

P1.x/P2.x

FRAM

RAM

2KB

MPY32

32-bit

Hardware Redundancy

Multiplier

CRC16

I/O Ports

P1 : 8 IOs

P2 : 7 IOs

Interrupt,

Wakeup,

DVCC

LFXT

Power

Management

Module

DVSS

16-bit

Cyclic

Clock

System

RST/NMI

7.25KB

+256B

Check

PA : 15 IOs

MAB

16-MHz CPU

inc.

16 Registers

MDB

EEM

RTC

Counter

eUSCI_A0

2 × TA

eUSCI_B0

(SPI, I²C)

ADC

BAKMEM

SYS

TCK

TMS

8 channels

Single-end

10 bit

32-bytes

Backup

Memory

16-bit

Real-Time

Clock

Timer_A3

3 CC

Registers

JTAG

SBW

TDI/TCLK

TDO

(UART,

IrDA, SPI)

Watchdog

200 ksps

SBWTCK

SBWTDIO

LPM3.5 Domain

图4-1. 功能方框图

• MCU 的主电源对DVCC 和DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为

4.7μF 至10μF 和0.1μF，精度为±5%。

• P1 和P2 特有引脚中断功能，可将MCU 从所有LPM 唤醒（包括LPM3.5 和LPM4）。

• 每个Timer_A3 具有3 个捕捉/比较寄存器，不过仅CCR1 和CCR2 从外部连接。CCR0 寄存器仅用于内部周

期时序和生成中断。

• 在LPM3.5 模式下，RTC 模块可在其他外设停止工作的情况下继续工作。

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Table of Contents

8.12 Timing and Switching Characteristics..................... 19

9 Detailed Description......................................................39

9.1 Overview...................................................................39

9.2 CPU.......................................................................... 39

9.3 Operating Modes...................................................... 39

9.4 Interrupt Vector Addresses....................................... 41

9.5 Bootloader (BSL)...................................................... 42

9.6 JTAG Standard Interface.......................................... 42

9.7 Spy-Bi-Wire Interface (SBW).................................... 43

9.8 FRAM........................................................................43

9.9 Memory Protection....................................................43

9.10 Peripherals..............................................................43

9.11 Input/Output Diagrams............................................52

9.12 Device Descriptors..................................................56

9.13 Memory...................................................................57

9.14 Identification............................................................65

10 Applications, Implementation, and Layout............... 66

10.1 Device Connection and Layout Fundamentals....... 66

10.2 Peripheral- and Interface-Specific Design

Information.................................................................. 69

11 Device and Documentation Support..........................71

11.1 Getting Started and Next Steps.............................. 71

11.2 Device Nomenclature..............................................71

11.3 Tools and Software..................................................72

11.4 Documentation Support.......................................... 74

11.5 支持资源..................................................................75

11.6 Trademarks............................................................. 75

11.7 静电放电警告...........................................................75

11.8 Export Control Notice..............................................75

11.9 术语表..................................................................... 75

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 功能方框图.........................................................................3

5 Revision History.............................................................. 5

6 Device Comparison.........................................................7

6.1 Related Products........................................................ 7

7 Terminal Configuration and Functions..........................8

7.1 Pin Diagrams.............................................................. 8

7.2 Pin Attributes...............................................................9

7.3 Signal Descriptions................................................... 11

7.4 Pin Multiplexing.........................................................13

7.5 Buffer Types..............................................................13

7.6 Connection of Unused Pins...................................... 13

8 Specifications................................................................ 14

8.1 Absolute Maximum Ratings...................................... 14

8.2 ESD Ratings............................................................. 14

8.3 Recommended Operating Conditions.......................14

8.4 Active Mode Supply Current Into V_CCExcluding

External Current.......................................................... 15

8.5 Active Mode Supply Current Per MHz...................... 15

8.6 Low-Power Mode (LPM0) Supply Currents Into

V_CCExcluding External Current.................................. 15

8.7 Low-Power Mode (LPM3, LPM4) Supply

Currents (Into V_CC) Excluding External Current.......... 16

8.8 Low-Power Mode (LPMx.5) Supply Currents

(Into V_CC) Excluding External Current.........................17

8.9 Typical Characteristics - Low-Power Mode

Supply Currents...........................................................18

8.10 Typical Characteristics –Current

Consumption Per Module............................................18

8.11 Thermal Resistance Characteristics....................... 19

Information.................................................................... 76

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5 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from revision C to revision D

Changes from December 11, 2019 to January 29, 2021

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• Added the TMS signal to pin 12 in 图7-2, 16-Pin PW Package (Top View) ......................................................8

• Corrected the assignments for TA0.2 and TA0.1 for RHL pins 16 and 17 and PW pins 12 and 13 in 表7-1, Pin

Attributes ............................................................................................................................................................9

Changes from revision B to revision C

Changes from August 20, 2019 to December 10, 2019

Page

• Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in 节

8.3, Recommended Operating Conditions .......................................................................................................14

• Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in 节

8.3, Recommended Operating Conditions .......................................................................................................14

• Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in 节8.3,

Recommended Operating Conditions ..............................................................................................................14

• Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to

节8.12.3.1, XT1 Crystal Oscillator (Low Frequency) ...................................................................................... 21

• Changed the note that begins "Requires external capacitors at both terminals..." in 节8.12.3.1, XT1 Crystal

Oscillator (Low Frequency) ..............................................................................................................................21

• Corrected the test conditions for the R_Iparameter in 节8.12.8.1, ADC, Power Supply and Input Range

Conditions ........................................................................................................................................................34

• Added the note that begins "t_Sample= ln(2ⁿ⁺¹) × τ..." in 节8.12.8.2, ADC, 10-Bit Timing Parameters ..........34

• Added "1.5-V reference factor" in 表9-18, Device Descriptors ....................................................................... 56

• Changed the CRC covered end address to 0x1AF5 in note (1) in 表9-18, Device Descriptors ..................... 56

Changes from revision A to revision B

Changes from November 8, 2018 to August 19, 2019

Page

• 更新了节1 特性................................................................................................................................................ 1

• Changed CapTIvate BSWP demonstration board to CapTIvate phone demonstration board in note (11) on 节

8.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into V_CC) Excluding External Current ...................... 16

• Changed CapTIvate BSWP demonstration board to CapTIvate phone demonstration board in note (19) on 节

8.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into V_CC) Excluding External Current ...................... 16

• Updated 节11.2, Device Nomenclature ...........................................................................................................71

Changes from initial release to revision A

Changes from January 12, 2018 to November 7, 2018

Page

• 更改了节1 特性中的列表项“1.8V 至3.6V 的宽电源电压范围...”...................................................................1

• Updated 节6.1, Related Products .....................................................................................................................7

• Changed HBM limit to ±1000 V and CDM limit to ±250 V in 节8.2, ESD Ratings .......................................... 14

• Changed the MIN value of the V_CCparameter from 2 V to 1.8 V in 节8.3, Recommended Operating

Conditions ........................................................................................................................................................14

• Changed the crystal in the footnote that begins "Characterized with a Seiko Crystal SC-32S crystal..." in 节

8.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into V_CC) Excluding External Current ...................... 16

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• Changed the crystal in the footnote that begins "Characterized with a Seiko Crystal SC-32S crystal..." in 节

8.8, Low-Power Mode (LPMx.5) Supply Currents (Into V_CC) Excluding External Current ...............................17

• Added note on V_SVSH-and V_SVSH+parameters to 节8.12.1.1, PMM, SVS and BOR ..................................... 19

• Changed the minimum V_CCfrom 2.0 V to 1.8 V in the test conditions for the f_REFO, df_REFO/ d_VCC, and f_DC

parameters and in note (2) in 节8.12.3.4, REFO ............................................................................................22

• Changed the minimum V_CCfrom 2.0 V to 1.8 V in the test conditions for the df_VLO/dV_CCparameter and in

note (2) in 节8.12.3.5, Internal Very-Low-Power Low-Frequency Oscillator (VLO) ........................................ 24

• Changed the minimum V_CCfrom 2.0 V to 1.8 V in the test conditions for the f_MODOSC/dV_CCparameter in 节

8.12.3.6, Module Oscillator (MODOSC) .......................................................................................................... 24

• Corrected bitfield from RTCCLK to RTCCKSEL in table note that starts "Controlled by ..." in 表9-8, Clock

Distribution .......................................................................................................................................................44

• Corrected bitfield from IRDSEL to IRDSSEL in 节9.10.8, Timers (Timer0_A3, Timer1_A3), in the description

that starts "The interconnection of Timer0_A3 and ..."..................................................................................... 49

• Corrected ADCINCHx column heading in 表9-13, ADC Channel Connections ..............................................50

• Added P1SELC information in 表9-28, Port P1, P2 Registers (Base Address: 0200h) ..................................58

• Added P2SELC information in 表9-28, Port P1, P2 Registers (Base Address: 0200h) ..................................58

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6 Device Comparison

表6-1 summarizes the features of the available family members.

表6-1. Device Comparison

PROGRAM FRAM +

SRAM

10-BIT ADC

CHANNELS

DEVICE⁽¹⁾

INFORMATION

FRAM (bytes)

TA0,TA1

eUSCI_A

eUSCI_B

GPIOs

PACKAGE⁽²⁾

(bytes)

20 RHL

(VQFN)

MSP430FR2422IRHL

MSP430FR2422IPW16

7424 + 256

2048

2, 3 × CCR⁽³⁾

1

8

5

15

11

16 PW

(TSSOP)

2048

(1) For the most current package and ordering information, see the Package Option Addendum in 节12, or see the TI website at

www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/

packaging.

(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM

outputs.

6.1 Related Products

For information about other devices in this family of products or related products, see the following links.

TI 16-bit and 32-bit microcontrollers

High-performance, low-power solutions to enable the autonomous future

Products for MSP430 ultra-low-power sensing and measurement microcontrollers

One platform. One ecosystem. Endless possibilities.

Companion Products for MSP430FR2422

Review products that are frequently purchased or used in conjunction with this product.

Reference Designs

Find reference designs leveraging the best in TI technology to solve your system-level challenges

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7 Terminal Configuration and Functions

7.1 Pin Diagrams

图7-1 shows the pinout of the 20-pin RHL package.

19 18 17 16 15 14 13 12

20

11

10

P2.4/TA1CLK/UCB0CLK/A6

P1.2/UCB0SIMO/UCB0SDA/SMCLK/A2/Veref-

P1.1/UCB0CLK/ACLK/A1/VREF+

MSP430FR2422IRHL

1

P2.5/UCB0SIMO/UCB0SDA/A7

2

3

4

5

6

7

8

9

图7-1. 20-Pin RHL Package (Top View)

图7-2 shows the pinout of the 16-pin PW package.

P1.1/UCB0CLK/ACLK/A1/VREF+

P1.0/UCB0STE/A0/Veref+

TEST/SBWTCK

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

P1.2/UCB0SIMO/UCB0SDA/SMCLK/A2/Veref-

P1.3/UCB0SOMI/UCB0SCL/MCLK/A3

DNC

P1.4/UCA0TXD/UCA0SIMO/TA0.1/TCK

P1.5/UCA0RXD/UCA0SOMI/TA0.2/TMS

P1.6/UCA0CLK/TA0CLK/TDI/TCLK

P1.7/UCA0STE/TDO

RST/NMI/SBWTDIO

DVCC

MSP430FR2422IPW16

DVSS

P2.1/UCA0RXD/UCA0SOMI/XIN

P2.0/UCA0TXD/UCA0SIMO/XOUT

P2.2/TA1.1/A4

图7-2. 16-Pin PW Package (Top View)

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7.2 Pin Attributes

表7-1 lists the attributes of all pins.

表7-1. Pin Attributes

PIN NUMBER

SIGNAL

TYPE⁽²⁾

RESET STATE

SIGNAL NAME^{(1) (4)}

BUFFER TYPE⁽³⁾

POWER SOURCE⁽⁵⁾

AFTER BOR⁽⁶⁾

RHL

PW16

P1.1 (RD)

UCB0CLK

ACLK

I/O

I

LVCMOS

Analog

DVCC

Power

DVCC

Power

DVCC

OFF

–

1

A1

–

VREF+

I

Analog

–

P1.0 (RD)

UCB0STE

A0

I/O

I

LVCMOS

Analog

OFF

–

2

Veref+

I

Analog

–

TEST (RD)

SBWTCK

RST (RD)

NMI

I

LVCMOS

Power

OFF

3

4

3

4

I

–

I

OFF

I

–

SBWTDIO

DVCC

I/O

P

5

6

5

6

N/A

OFF

DVSS

P

Power

P2.1 (RD)

UCA0RXD

UCA0SOMI

XIN

I/O

I

LVCMOS

Analog

–

7

I/O

I

–

P2.0 (RD)

UCA0TXD

UCA0SIMO

XOUT

I/O

O

OFF

–

8

9

8

I/O

O

–

P2.6 (RD)

UCB0SOMI

UCB0SCL

P2.5 (RD)

UCB0SIMO

UCB0SDA

A7

I/O

I

OFF

–

OFF

–

10

–

P2.4 (RD)

TA1CLK

UCB0CLK

A6

I/O

I

LVCMOS

Analog

OFF

–

11

12

–

I/O

I

–

P2.3 (RD)

TA1.2

I/O

I

LVCMOS

Analog

OFF

–

UCB0STE

A5

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表7-1. Pin Attributes (continued)

PIN NUMBER

RHL PW16

SIGNAL

TYPE⁽²⁾

RESET STATE

SIGNAL NAME^{(1) (4)}

BUFFER TYPE⁽³⁾

POWER SOURCE⁽⁵⁾

AFTER BOR⁽⁶⁾

P2.2 (RD)

TA1.1

I/O

I

LVCMOS

Analog

DVCC

OFF

13

9

–

A4

P1.7 (RD)

UCA0STE

TDO

I/O

O

LVCMOS

OFF

14

15

10

11

–

P1.6 (RD)

UCA0CLK

TA0CLK

TDI

I/O

I

OFF

–

I

–

TCLK

I

–

P1.5 (RD)

UCA0RXD

UCA0SOMI

TA0.2

I/O

I

OFF

–

16

12

I/O

I

–

TMS

–

P1.4 (RD)

UCA0TXD

UCA0SIMO

TA0.1

I/O

O

OFF

–

17

18

19

13

14

15

I/O

I

–

TCK

–

DNC

–

I/O

O

–

P1.3 (RD)

UCB0SOMI

UCB0SCL

MCLK

LVCMOS

Analog

DVCC

Power

OFF

–

A3

I

–

P1.2 (RD)

UCB0SIMO

UCB0SDA

SMCLK

A2

I/O

O

LVCMOS

Analog

OFF

–

20

16

I

Veref-

I

Analog

(1) Signals names with (RD) denote the reset default pin name.

(2) Signal Types: I = Input, O = Output, I/O = Input or Output

(3) Buffer Types: LVCMOS, Analog, or Power (see 表7-3)

(4) To determine the pin mux encodings for each pin, see 节9.11.

(5) The power source shown in this table is the I/O power source, which may differ from the module power source.

(6) Reset States:

OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled

N/A = Not applicable

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7.3 Signal Descriptions

表7-2 describes the signals for all device variants and package options.

表7-2. Signal Descriptions

PIN NUMBER

FUNCTION

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

RHL

2

PW

2

A0

A1

A2

A3

A4

A5

A6

A7

I

Analog input A0

1

I

Analog input A1

20

19

13

12

11

10

2

16

15

9

I

Analog input A2

I

Analog input A3

Analog input A4

ADC

I

Analog input A5

–

2

I

Analog input A6

I

Analog input A7

Veref+

Veref-

ACLK

MCLK

SMCLK

XIN

I

ADC positive reference

ADC negative reference

ACLK output

20

1

16

1

I

I/O

O

I

19

20

7

15

16

7

MCLK output

Clock

SMCLK output

Input terminal for crystal oscillator

Output terminal for crystal oscillator

Spy-Bi-Wire input clock

Spy-Bi-Wire data input/output

Test clock

XOUT

SBWTCK

SBWTDIO

TCK

8

O

I

3

4

I/O

I

17

15

14

3

13

11

10

TCLK

TDI

I

Test clock input

Debug

I

Test data input

TDO

O

I

Test data output

TEST

TMS

3

Test mode pin –selected digital I/O on JTAG pins

Test mode select

16

2

12

2

I

P1.0

I/O

General-purpose I/O

General-purpose I/O⁽⁴⁾

P1.1

1

P1.2

20

19

17

16

15

14

16

15

13

12

11

10

P1.3

P1.4

P1.5

P1.6

P1.7

GPIO

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

8

7

8

7

I/O

General-purpose I/O

13

12

11

10

9

–

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表7-2. Signal Descriptions (continued)

PIN NUMBER

FUNCTION

SIGNAL NAME

UCB0SCL⁽²⁾

DESCRIPTION

TYPE⁽¹⁾

RHL

19

PW

15

I/O

eUSCI_B0 I²C clock

eUSCI_B0 I²C data

UCB0SDA⁽²⁾

20

16

I²C

UCB0SCL⁽²⁾

UCB0SDA⁽²⁾

DVCC

9

10

5

I/O

P

eUSCI_B0 I²C clock

eUSCI_B0 I²C data

Power supply

–

5

Power

DVSS

6

P

Power ground

VREF+

1

P

Output of positive reference voltage with ground as reference

eUSCI_A0 SPI slave transmit enable

eUSCI_A0 SPI clock input/output

UCA0STE

14

15

16

17

7

10

11

12

13

7

I/O

UCA0CLK

UCA0SOMI^{(2) (3)}

UCA0SIMO^{(2) (3)}

UCA0SOMI^{(2) (3)}

UCA0SIMO^{(2) (3)}

eUSCI_A0 SPI slave out/master in

eUSCI_A0 SPI slave in/master out

eUSCI_A0 SPI slave out/master in

8

eUSCI_A0 SPI slave in/master out

UCB0STE⁽²⁾

UCB0CLK⁽²⁾

UCB0SOMI⁽²⁾

UCB0SIMO⁽²⁾

2

1

2

1

I/O

eUSCI_B0 slave transmit enable

eUSCI_B0 clock input/output

SPI

19

20

15

16

eUSCI_B0 SPI slave out/master in

eUSCI_B0 SPI slave in/master out

UCB0STE⁽²⁾

UCB0CLK⁽²⁾

UCB0SOMI⁽²⁾

UCB0SIMO⁽²⁾

NMI

12

11

9

I/O

I

eUSCI_B0 slave transmit enable

–

4

eUSCI_B0 clock input/output

eUSCI_B0 SPI slave out/master in

eUSCI_B0 SPI slave in/master out

Nonmaskable interrupt input

10

4

System

RST

4

I

Active-low reset input

TA0.1

17

16

15

13

12

11

I/O

I

Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs

Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs

Timer clock input TACLK for TA0

TA0.2

TA0CLK

Timer_A

TA1.1

13

12

11

16

17

9

I/O

I

Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs

Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs

Timer clock input TACLK for TA1

TA1.2

–

12

13

TA1CLK

UCA0RXD⁽²⁾

UCA0TXD⁽²⁾

I

eUSCI_A0 UART receive data

O

eUSCI_A0 UART transmit data

UART

UCA0RXD⁽²⁾

UCA0TXD⁽²⁾

Do not connect

7

8

7

8

I

eUSCI_A0 UART receive data

O

–

eUSCI_A0 UART transmit data

DNC

18

14

Do not connect

QFN package exposed thermal pad. TI recommends connecting to

QFN Pad

QFN thermal pad

Pad

–

V_SS

.

(1) Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power

(2) These signal assignments are controlled by the USCIARMP bit of the SYSCFG3 register or the USCIBRMP bit of the SYSCFG2

register. Only one group can be selected at one time.

(3) Signal assignments on these pins are controlled by the remap functionality and are selected by the USCIARMP bit in the SYSCFG3

register. Only one group can be selected at one time. The CLK and STE assignments are fixed and shared by both SPI function

groups.

(4) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to

prevent collisions.

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7.4 Pin Multiplexing

Pin multiplexing for this MCU is controlled by both register settings and operating modes (for example, if the

MCU is in test mode). For details of the settings for each pin and diagrams of the multiplexed ports, see 节9.11.

7.5 Buffer Types

表7-3 defines the pin buffer types that are listed in 表7-1

表7-3. Buffer Types

NOMINAL

OUTPUT DRIVE

STRENGTH

(mA)

BUFFER TYPE

(STANDARD)

NOMINAL

VOLTAGE

PU OR PD

STRENGTH

(µA)

OTHER

CHARACTERISTICS

HYSTERESIS

PU OR PD

LVCMOS

Analog

3.0 V

Y⁽¹⁾

N

Programmable

N/A

See 节8.12.4

See analog modules in 节8

for details.

N/A

SVS enables hysteresis on

DVCC.

Power (DVCC)

Power (AVCC)

3.0 V

N

N/A

(1) Only for input pins.

7.6 Connection of Unused Pins

表7-4 lists the correct termination of unused pins.

表7-4. Connection of Unused Pins

PIN⁽¹⁾

POTENTIAL

Open

COMMENT

Switched to port function, output direction (PxDIR.n = 1)

Px.0 to Px.7

RST/NMI

TEST

47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown⁽²⁾

DV_CC

Open

This pin always has an internal pull-down enabled.

(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection

guidelines.

(2) The pulldown capacitor should not exceed 1.1 nF when using MCUs with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like

FET interfaces or GANG programmers.

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Voltage applied at DVCC pin to V_SS

Voltage applied to any other pin⁽²⁾

4.1

V

–0.3

V_CC+ 0.3

(4.1 V Max)

V

–0.3

Diode current at any device pin

±2

85

mA

°C

Maximum junction temperature, T_J

(3)

Storage temperature, T_stg

125

°C

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS

.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

8.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS‑001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22‑C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as

±250 V may actually have higher performance.

8.3 Recommended Operating Conditions

MIN

NOM

MAX UNIT

V_CC

V_SS

T_A

Supply voltage applied at DVCC pin^{(1) (2) (3) (4)}

Supply voltage applied at DVSS pin

Operating free-air temperature

1.8

3.6

V

0

85

°C

µF

–40

4.7

T_J

Operating junction temperature

C_DVCC

Recommended capacitor at DVCC⁽⁵⁾

10

No FRAM wait states

(NWAITSx = 0)

0

8

f_SYSTEM

Processor frequency (maximum MCLK frequency)^{(4) (7)}

MHz

With FRAM wait states

(NWAITSx = 1)⁽⁶⁾

16⁽⁸⁾

f_ACLK

Maximum ACLK frequency

Maximum SMCLK frequency

40 kHz

f_SMCLK

16⁽⁸⁾MHz

(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range. Following

the data sheet recommendation for capacitor C_DVCClimits the slopes accordingly.

(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.

(3) TI recommends that power to the DVCC pin must not exceed the limits specified in Recommended Operating Conditions. Exceeding

the specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.

(4) The minimum supply voltage is defined by the SVS levels. See the SVS threshold parameters in 节8.12.1.1.

(5) A capacitor tolerance of ±20% or better is required. A low-ESR ceramic capacitor of 100 nF (minimum) should be placed as close as

possible (within a few millimeters) to the respective pin pair.

(6) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed

without wait states.

(7) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

(8) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to

comply with this operating condition.

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8.4 Active Mode Supply Current Into V_CCExcluding External Current

See ⁽¹⁾

FREQUENCY (f_MCLK= f_SMCLK

)

1 MHz

0 WAIT STATES

(NWAITSx = 0)

8 MHz

0 WAIT STATES

(NWAITSx = 0)

16 MHz

1 WAIT STATE

(NWAITSx = 1)

EXECUTION

MEMORY

TEST

CONDITION

PARAMETER

UNIT

TYP

454

471

191

MAX

TYP

2620

2700

573

MAX

TYP

2935

2980

950

MAX

3 V, 25°C

3 V, 85°C

3 V, 25°C

FRAM

0% cache hit ratio

I_{AM, FRAM}(0%)

µA

3250

1200

FRAM

100% cache hit

ratio

I_{AM, FRAM}(100%)

µA

3 V, 85°C

3 V, 25°C

199

216

592

772

974

(2)

I_{AM, RAM}

RAM

1300

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current. Characterized with program executing typical data

processing.

f_ACLK= 32768 Hz, f_MCLK= f_SMCLK= f_DCOat specified frequency

Program and data entirely reside in FRAM. All execution is from FRAM.

(2) Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.

8.5 Active Mode Supply Current Per MHz

V_CC= 3 V, T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TYP

UNIT

Active mode current consumption per MHz,

execution from FRAM, no wait states

[I_AM(75% cache hit rate) at 8 MHz –

I_AM(75% cache hit rate) at 1 MHz) / 7 MHz

dI_AM,FRAM/df

120

µA/MHz

8.6 Low-Power Mode (LPM0) Supply Currents Into V_CCExcluding External Current

V_CC= 3 V, T_A= 25°C (unless otherwise noted)^{(1) (2)}

FREQUENCY (f_SMCLK

)

PARAMETER

V_CC

1 MHz

TYP

8 MHz

16 MHz

TYP MAX

UNIT

MAX

TYP

292

300

MAX

2 V

3 V

145

155

395

I_LPM0

µA

394

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Current for watchdog timer clocked by SMCLK included.

f_ACLK= 32768 Hz, f_MCLK= 0 MHz, f_SMCLKat specified frequency.

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8.7 Low-Power Mode (LPM3, LPM4) Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾

25°C

85°C

–40°C

TYP MAX

PARAMETER

V_CC

UNIT

TYP

MAX

TYP

MAX

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

0.96

0.93

0.77

0.75

0.90

0.51

0.49

0.35

0.34

0.43

0.42

0.80

0.79

1.11

1.08

0.92

0.90

1.05

0.64

0.61

0.48

0.46

0.56

0.55

0.96

0.94

2.75

2.78

2.66

2.60

2.77

2.30

2.25

2.13

2.10

2.21

2.19

2.68

2.64

6.2

Low-power mode 3, 12.5-pF crystal, includes

SVS^{(2) (3) (4)}

I_LPM3,XT1

µA

6.0

I_LPM3,VLO

I_{LPM3, RTC}

I_{LPM4, SVS}

Low-power mode 3, VLO, excludes SVS⁽⁵⁾

Low-power mode 3, RTC, excludes SVS⁽⁹⁾

Low-power mode 4, includes SVS⁽⁶⁾

µA

I_LPM4

Low-power mode 4, excludes SVS⁽⁶⁾

µA

Low-power mode 4, RTC is soured from VLO,

excludes SVS⁽⁷⁾

I_LPM4,VLO

Low-power mode 4, RTC is soured from XT1,

excludes SVS⁽⁸⁾

I_LPM4,XT1

(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.

(2) Not applicable for MCUs with HF crystal oscillator only.

(3) Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.

(4) Low-power mode 3, 12.5-pF crystal, includes SVS test conditions:

Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),

f_XT1= 32768 Hz, f_ACLK= f_XT1, f_MCLK= f_SMCLK= 0 MHz

(5) Low-power mode 3, VLO, excludes SVS test conditions:

Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3)

f_XT1= 32768 Hz, f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(6) Low-power mode 4, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4), CPU and all clocks are disabled, WDT and RTC

disabled

(7) Low-power mode 4, VLO, excludes SVS test conditions:

Current for RTC clocked by VLO included. Current for brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4)

f_XT1= 0 Hz, f_MCLK= f_SMCLK= 0 MHz

(8) Low-power mode 4, XT1, excludes SVS test conditions:

Current for RTC clocked by XT1 included. Current for brownout included. SVS disabled (SVSHE = 0).

CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4)

f_XT1= 32768 Hz, f_MCLK= f_SMCLK= 0 MHz

(9) RTC periodically wakes up every second with external 32768-Hz input as source.

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8.8 Low-Power Mode (LPMx.5) Supply Currents (Into V_CC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

25°C

85°C

TYP

–40°C

TYP MAX

PARAMETER

V_CC

UNIT

TYP

MAX

Low-power mode 3.5, 12.5-pF crystal, includes

SVS^{(1) (2) (3)}

(also see 图8-3)

3 V

2 V

0.57

0.54

0.63

0.60

0.81

0.79

1.54

I_{LPM3.5, XT1}

µA

3 V

2 V

3 V

2 V

0.23

0.21

0.25

0.23

0.31

0.29

0.45

0.15

I_{LPM4.5, SVS}

Low-power mode 4.5, includes SVS⁽⁴⁾

Low-power mode 4.5, excludes SVS⁽⁵⁾

µA

0.027

0.022

0.036

0.031

0.080

0.073

I_LPM4.5

(1) Not applicable for MCUs with HF crystal oscillator only.

(2) Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.

(3) Low-power mode 3.5, 12.5-pF crystal, includes SVS test conditions:

Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),

f_XT1= 32768 Hz, f_ACLK= 0, f_MCLK= f_SMCLK= 0 MHz

(4) Low-power mode 4.5, includes SVS test conditions:

Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5)

f_XT1= 0 Hz, f_ACLK= f_MCLK= f_SMCLK= 0 MHz

(5) Low-power mode 4.5, excludes SVS test conditions:

Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.

PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5)

f_XT1= 0 Hz, f_ACLK= f_MCLK= f_SMCLK= 0 MHz

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8.9 Typical Characteristics - Low-Power Mode Supply Currents

V_CC= 3 V

RTC enabled

SVS disabled

V_CC= 3 V

RTC enabled

SVS disabled

图8-1. LPM3 Supply Current vs Temperature

图8-2. LPM4 Supply Current vs Temperature

V_CC= 3 V

SVS enabled

V_CC= 3 V

XT1 enabled

SVS enabled

图8-4. LPM4.5 Supply Current vs Temperature

图8-3. LPM3.5 Supply Current vs Temperature

8.10 Typical Characteristics –Current Consumption Per Module

MODULE

TEST CONDITIONS

REFERENCE CLOCK

MIN

TYP

5

MAX

UNIT

µA/MHz

nA

Timer_A

Module input clock

eUSCI_A

eUSCI_B

RTC

UART mode

Module input clock

32 kHz

7

SPI mode

5

SPI mode

5

I²C mode, 100 kbaud

5

85

8.5

CRC

From start to end of operation

MCLK

µA/MHz

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8.11 Thermal Resistance Characteristics

THERMAL METRIC⁽¹⁾

VALUE⁽²⁾

37.8

UNIT

VQFN 20 pin (RHL)

TSSOP 16 pin (PW16)

VQFN 20 pin (RHL)

TSSOP 16 pin (PW16)

VQFN 20 pin (RHL)

TSSOP 16 pin (PW16)

Junction-to-ambient thermal resistance, still air

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

Rθ_JA

Rθ_JC

Rθ_JB

101.7

34.1

°C/W

33.7

15.3

47.5

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (Rθ_JC) value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC

standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

8.12 Timing and Switching Characteristics

8.12.1 Power Supply Sequencing

节8.12.1.1 lists the characteristics of the SVS and BOR.

8.12.1.1 PMM, SVS and BOR

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

Safe BOR power-down level⁽¹⁾

Safe BOR reset delay⁽²⁾

TEST CONDITIONS

MIN

0.1

10

TYP

MAX UNIT

V_{BOR, safe}

t_{BOR, safe}

I_SVSH,AM

I_SVSH,LPM

V_SVSH-

V

ms

SVS_Hcurrent consumption, active mode

SVS_Hcurrent consumption, low-power modes

SVS_Hpower-down level⁽³⁾

V_CC= 3.6 V

1.5

µA

nA

V

240

1.80

1.88

80

1.71

1.76

1.87

1.99

V_SVSH+

SVS_Hpower-up level⁽³⁾

V

V_{SVSH_hys}SVS_Hhysteresis

mV

µs

t_{PD,SVSH, AM}SVS_Hpropagation delay, active mode

10

t_PD,SVSH,

SVS_Hpropagation delay, low-power modes

100

µs

LPM

(1) A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.

(2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches

V_SVSH+

.

(3) For additional information, see the Dynamic Voltage Scaling Power Solution for MSP430 Devices With Single-Channel LDO Reference

Design.

V

Power Cycle Reset

V_SVS+

SVS Reset

BOR Reset

V_SVS–

V_BOR

t_BOR

t

图8-5. Power Cycle, SVS, and BOR Reset Conditions

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8.12.2 Reset Timing

节8.12.2.1 lists the timing characteristics of wakeup from LPMs and reset.

8.12.2.1 Wake-up Times From Low-Power Modes and Reset

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

V_CC

3 V

MIN

TYP

MAX UNIT

Additional wake-up time to activate the FRAM in

AM if previously disabled by the FRAM controller or

from a LPM if immediate activation is selected for

wakeup⁽¹⁾

t_{WAKE-UP FRAM}

10

µs

200 +

ns

t_{WAKE-UP LPM0}

Wake-up time from LPM0 to active mode ⁽¹⁾

2.5 / f_DCO

t_{WAKE-UP LPM3}

t_{WAKE-UP LPM4}

Wake-up time from LPM3 to active mode ⁽²⁾

Wake-up time from LPM4 to active mode

3 V

10

µs

ms

t_{WAKE-UP LPM3.5}Wake-up time from LPM3.5 to active mode ⁽²⁾

350

1

SVSHE = 1

SVSHE = 0

t_{WAKE-UP LPM4.5}Wake-up time from LPM4.5 to active mode ⁽²⁾

3 V

Wake-up time from RST or BOR event to active

t_{WAKE-UP-RESET}

t_RESET

3 V

1

ms

µs

mode ⁽²⁾

Pulse duration required at RST/NMI pin to accept a

reset

2

(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first

externally observable MCLK clock edge.

(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first

instruction of the user program is executed.

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8.12.3 Clock Specifications

节8.12.3.1 lists the characteristics of the LF XT1.

8.12.3.1 XT1 Crystal Oscillator (Low Frequency)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

XT1 oscillator crystal, low

frequency

f_{XT1, LF}

LFXTBYPASS = 0

32768

Hz

Measured at MCLK,

f_LFXT= 32768 Hz

DC_{XT1, LF}

f_XT1,SW

DC_{XT1, SW}

OA_LFXT

C_L,eff

XT1 oscillator LF duty cycle

30%

70%

kHz

60%

kΩ

XT1 oscillator logic-level square-

wave input frequency

LFXTBYPASS = 1 ^{(3) (4)}

32.768

LFXT oscillator logic-level

square-wave input duty cycle

LFXTBYPASS = 1

40%

Oscillation allowance for

LF crystals ⁽⁵⁾

LFXTBYPASS = 0, LFXTDRIVE = {3},

f_LFXT= 32768 Hz, C_L,eff= 12.5 pF

200

1

Integrated effective load

capacitance⁽⁶⁾

See ⁽⁷⁾

pF

f_OSC= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

T_A= 25°C, C_L,eff= 12.5 pF

t_START,LFXTStart-up time ⁽⁹⁾

f_Fault,LFXT

Oscillator fault frequency ⁽¹⁰⁾

1000

ms

XTS = 0⁽⁸⁾

0

3500

Hz

(1) To improve EMI on the LFXT oscillator, observe the following guidelines:

•

Keep the trace between the device and the crystal as short as possible.

Design a good ground plane around the oscillator pins.

Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing.

(3) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DC_{LFXT, SW}

(4) Maximum frequency of operation of the entire device cannot be exceeded.

.

(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

•

For LFXTDRIVE = {0}, C_L,eff= 3.7 pF

For LFXTDRIVE = {1}, 6 pF ≤C_L,eff≤9 pF

For LFXTDRIVE = {2}, 6 pF ≤C_L,eff≤10 pF

For LFXTDRIVE = {3}, 6 pF ≤C_L,eff≤12 pF

(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers.

Recommended effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF.

The PCB adds additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective

load capacitance of the selected crystal is met.

(8) Measured with logic-level input frequency but also applies to operation with crystals.

(9) Includes start-up counter of 1024 clock cycles.

(10) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specifications might set the

flag. A static condition or stuck at fault condition sets the flag.

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8.12.3.2 DCO FLL, Frequency

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

3 V

MIN

–1.0%

–2.0%

TYP

MAX UNIT

1.0%

FLL lock frequency, 16 MHz, 25°C

FLL lock frequency, 16 MHz, –40°C to 85°C

Measured at MCLK, Internal

trimmed REFO as reference

2.0%

f_{DCO, FLL}

Measured at MCLK, XT1

crystal as reference

3 V

0.5%

60%

FLL lock frequency, 16 MHz, –40°C to 85°C

–0.5%

f_DUTY

Duty cycle

3 V

40%

50%

0.25%

0.022%

280

Jitter_cc

Jitter_long

t_{FLL, lock}

Cycle-to-cycle jitter, 16 MHz

Long term jitter, 16 MHz

FLL lock time, 16MHz

Measured at MCLK, XT1

crystal as reference

ms

节8.12.3.3 lists the characteristics of the DCO.

8.12.3.3 DCO Frequency

over recommended operating free-air temperature (unless otherwise noted) (see 图8-6)

PARAMETER

TEST CONDITIONS

V_CC

TYP

UNIT

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

7.1

11.8

17

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

f_{DCO, 16MHz}

f_{DCO, 12MHz}

f_{DCO, 8MHz}

f_{DCO, 4MHz}

DCO frequency, 16 MHz

3 V

MHz

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

DCORSEL = 101b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

27.7

5.5

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

9.1

DCO frequency, 12 MHz

DCO frequency, 8 MHz

DCO frequency, 4 MHz

MHz

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

13.1

21.5

3.7

DCORSEL = 100b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

6.3

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

9.0

DCORSEL = 011b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

14.9

1.9

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

3.2

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

4.6

DCORSEL = 010b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

7.8

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over recommended operating free-air temperature (unless otherwise noted) (see 图8-6)

PARAMETER

TEST CONDITIONS

V_CC

TYP

UNIT

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

0.96

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

1.6

2.3

f_{DCO, 2MHz}

DCO frequency, 2 MHz

3 V

MHz

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

DCORSEL = 001b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

4.0

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 0

0.5

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 000b, DCO = 511

0.85

1.2

f_{DCO, 1MHz}

DCO frequency, 1 MHz

3 V

MHz

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 0

DCORSEL = 000b, DISMOD = 1b, DCOFTRIMEN = 1b,

DCOFTRIM = 111b, DCO = 511

2.0

30

25

20

15

10

5

DCOFTRIM = 7

DCOFTRIM = 0

DCOFTRIM = 7

DCOFTRIM = 0

0

DCO

0

511

0

511

0

511

0

511

0

511

0

511

DCORSEL

0

1

2

3

4

5

V_CC= 3 V

T_A= –40°C to 85°C

图8-6. Typical DCO Frequency

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节8.12.3.4 lists the characteristics of the REFO.

8.12.3.4 REFO

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

3 V

MIN

TYP

15

MAX UNIT

I_REFO

REFO oscillator current consumption

REFO calibrated frequency

T_A= 25°C

µA

Hz

Measured at MCLK

–40°C to 85°C

3 V

32768

f_REFO

REFO absolute calibrated tolerance

REFO frequency temperature drift

1.8 V to 3.6 V

3 V

+3.5%

%/°C

–3.5%

df_REFO/d_T

Measured at MCLK⁽¹⁾

0.01

1

df_REFO

d_VCC

/

REFO frequency supply voltage drift

Measured at MCLK at 25°C⁽²⁾

1.8 V to 3.6 V

%/V

f_DC

REFO duty cycle

Measured at MCLK

40%

50%

50

60%

µs

t_START

REFO start-up time

40% to 60% duty cycle

(1) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C –(–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)

节8.12.3.5 lists the characteristics of the VLO.

8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VLO frequency

VLO frequency temperature drift

TEST CONDITIONS

V_CC

TYP UNIT

10 kHz

0.5 %/°C

f_VLO

Measured at MCLK

3 V

df_VLO/d_T

Measured at MCLK⁽¹⁾

Measured at MCLK⁽²⁾

Measured at MCLK

3 V

df_VLO/dV_CCVLO frequency supply voltage drift

f_VLO,DCDuty cycle

1.8 V to 3.6 V

3 V

4

%/V

50%

(1) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C –(–40°C))

(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)

Note

The VLO clock frequency is reduced by 15% (typical) when the device switches from active mode to

LPM3 or LPM4, because the reference changes. This lower frequency is not a violation of the VLO

specifications (see 节8.12.3.5).

节8.12.3.6 lists the characteristics of the MODOSC.

8.12.3.6 Module Oscillator (MODOSC)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

4.8

MAX UNIT

5.8 MHz

%/℃

f_MODOSC

MODOSC frequency

3 V

3.8

f_MODOSC/dT

MODOSC frequency temperature drift

3 V

0.102

1.02

50%

f_MODOSC/dV_CCMODOSC frequency supply voltage drift

f_MODOSC,DCDuty cycle

1.8 V to 3.6 V

3 V

%/V

40%

60%

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8.12.4 Digital I/Os

节8.12.4.1 lists the characteristics of the digital inputs.

8.12.4.1 Digital Inputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2 V

3 V

2 V

3 V

2 V

3 V

MIN

0.90

1.35

0.50

0.75

0.3

TYP

MAX UNIT

1.50

V

2.25

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

1.10

V

1.65

Negative-going input threshold voltage

0.8

V

1.2

Input voltage hysteresis (V_IT+–V_IT–

)

0.4

For pullup: V_IN= V_SS

For pulldown: V_IN= V_CC

R_Pull

Pullup or pulldown resistor

20

35

3

50

20

kΩ

pF

nA

C_I,dig

Input capacitance, digital only port pins

V_IN= V_SSor V_CC

Input capacitance, port pins with shared analog

functions

C_I,ana

I_lkg(Px.y)

5

High-impedance leakage current of GPIO pins See ^{(1) (2)}

Ports with interrupt capability

External interrupt timing (external trigger pulse (see block diagram and

2 V, 3 V

–20

t_(int)

50

ns

duration to set interrupt flag)⁽³⁾

terminal function

descriptions)

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pins, unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is

disabled.

(3) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t_(int)is met. It may be set by trigger signals

shorter than t_(int)

.

节8.12.4.2 lists the characteristics of the digital outputs.

8.12.4.2 Digital Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_(OHmax)= –3 mA⁽¹⁾

I_(OHmax)= –5 mA⁽¹⁾

I_(OLmax)= 3 mA⁽¹⁾

V_CC

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

MIN

1.4

2.4

0.0

16

TYP

MAX UNIT

2.0

V

3.0

V_OH

High-level output voltage

0.60

V

0.60

V_OL

Low-level output voltage

I_(OHmax)= 5 mA⁽¹⁾

f_{Port_CLK}

t_rise,dig

t_fall,dig

Clock output frequency

C_L= 20 pF⁽²⁾

C_L= 20 pF

MHz

ns

16

10

7

Port output rise time, digital only port pins

Port output fall time, digital only port pins

10

5

ns

(1) The maximum total current, I_(OHmax)and I_(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage

drop specified.

(2) The port can output frequencies at least up to the specified limit and might support higher frequencies.

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8.12.4.3 Typical Characteristics –Outputs at 3 V and 2 V

DVCC = 3 V

DVCC = 2 V

图8-7. Typical Low-Level Output Current vs Low-Level Output

图8-8. Typical Low-Level Output Current vs Low-Level Output

Voltage

DVCC = 3 V

DVCC = 2 V

图8-9. Typical High-Level Output Current vs High-Level Output

图8-10. Typical High-Level Output Current vs High-Level

Voltage

Output Voltage

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8.12.5 VREF+ Built-in Reference

节8.12.5.1 lists the characteristics of the VREF+.

8.12.5.1 VREF+

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

V_REF+

Positive built-in reference voltage

EXTREFEN = 1 with 1-mA load current

2 V, 3 V

1.15

1.19

1.23

V

Temperature coefficient of built-in

reference voltage

TC_REF+

30

µV/°C

8.12.6 Timer_A

节8.12.6.1 lists the characteristics of Timer_A.

8.12.6.1 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, ACLK

f_TA

Timer_A input clock frequency

External: TACLK

2 V, 3 V

16 MHz

Duty cycle = 50% ±10%

All capture inputs, minimum pulse

duration required for capture

t_TA,cap

Timer_A capture timing

2 V, 3 V

20

ns

t_TIMR

Timer Clock

CCR0-1

0h

1h

CCR0

CCR0-1

0h

CCR0

t_VALID,PWM

Timer

TAx.1

t_HD,PWM

图8-11. Timer PWM Mode

Capture

t_TIMR

Timer Clock

t_SU,CCIA

t_,HD,CCIA

TAx.CCIA

图8-12. Timer Capture Mode

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8.12.7 eUSCI

节8.12.7.1 lists the supported frequencies of the eUSCI in UART mode.

8.12.7.1 eUSCI (UART Mode) Clock Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX UNIT

Internal: SMCLK, MODCLK

External: UCLK

f_eUSCI

eUSCI input clock frequency

2 V, 3 V

16 MHz

Duty cycle = 50% ±10%

BITCLK clock frequency

(equals baud rate in Mbaud)

f_BITCLK

2 V, 3 V

5

MHz

节8.12.7.2 lists the characteristics of the eUSCI in UART mode.

8.12.7.2 eUSCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

TYP UNIT

UCGLITx = 0

12

UCGLITx = 1

UCGLITx = 2

UCGLITx = 3

40

ns

68

t_t

UART receive deglitch time ⁽¹⁾

2 V, 3 V

110

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

节8.12.7.3 lists the supported frequencies of the eUSCI in SPI master mode.

8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

MHz

Internal: SMCLK, MODCLK

Duty cycle = 50% ±10%

f_eUSCIeUSCI input clock frequency

8

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节8.12.7.4 lists the characteristics of the eUSCI in SPI master mode.

8.12.7.4 eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

MIN

MAX

UNIT

UCSTEM = 0, UCMODEx = 01 or 10

UCSTEM = 1, UCMODEx = 01 or 10

UCSTEM = 0, UCMODEx = 01 or 10

UCSTEM = 1, UCMODEx = 01 or 10

UCxCLK

cycles

t_STE,LEADSTE lead time, STE active to clock

1

UCxCLK

cycles

t_STE,LAGSTE lag time, last clock to STE inactive

1

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

48

37

0

t_SU,MI

SOMI input data setup time

SOMI input data hold time

ns

t_HD,MI

0

20

UCLK edge to SIMO valid,

C_L= 20 pF

t_VALID,MOSIMO output data valid time⁽²⁾

-6

-5

t_HD,MO

SIMO output data hold time⁽³⁾

C_L= 20 pF

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI= max(t_{VALID,MO(eUSCI)}+ t_SU,SI(Slave), t_SU,MI(eUSCI)+ t_{VALID,SO(Slave)}

)

For the slave parameters t_SU,SI(Slave)and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.

(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in 图8-13 and 图8-14.

(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in 图8-13

and 图8-14.

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UCMODEx = 01

STE

t_STE,LEAD

t_STE,LAG

UCMODEx = 10

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LOW/HIGH

t_SU,MI

t_HD,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

t_STE,ACC

t_STE,DIS

图8-13. SPI Master Mode, CKPH = 0

UCMODEx = 01

STE

UCMODEx = 10

t_STE,LEAD

t_STE,LAG

1/f_UCxCLK

CKPL = 0

CKPL = 1

UCLK

t_LOW/HIGH

t_HD,MI

t_SU,MI

SOMI

SIMO

t_HD,MO

t_VALID,MO

t_STE,DIS

t_STE,ACC

图8-14. SPI Master Mode, CKPH = 1

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节8.12.7.5 lists the characteristics of the eUSCI in SPI slave mode.

8.12.7.5 eUSCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

V_CC

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

2 V

3 V

MIN

MAX UNIT

55

t_STE,LEADSTE lead time, STE active to clock

ns

45

20

t_STE,LAG

t_STE,ACC

t_STE,DIS

t_SU,SI

STE lag time, Last clock to STE inactive

STE access time, STE active to SOMI data out

STE disable time, STE inactive to SOMI high impedance

SIMO input data setup time

ns

20

65

ns

40

ns

35

8

6

ns

12

t_HD,SI

SIMO input data hold time

68

ns

42

UCLK edge to SOMI valid,

C_L= 20 pF

t_VALID,SOSOMI output data valid time⁽²⁾

5

t_HD,SO

SOMI output data hold time ⁽³⁾

C_L= 20 pF

ns

(1) f_UCxCLK= 1/2t_LO/HIwith t_LO/HI≥max(t_{VALID,MO(Master)}+ t_SU,SI(eUSCI), t_{SU,MI(Master)}+ t_{VALID,SO(eUSCI)}

)

For the master parameters t_{SU,MI(Master)}and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in 图8-15 and 图8-16.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in 图8-15

and 图8-16.

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UCMODEx = 01

STE

t_STE,LEAD

t_STE,LAG

UCMODEx = 10

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_SU,SI

t_LOW/HIGH

t_HD,SI

SIMO

SOMI

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

图8-15. SPI Slave Mode, CKPH = 0

UCMODEx = 01

t_STE,LEAD

t_STE,LAG

STE

UCMODEx = 10

1/f_UCxCLK

CKPL = 0

UCLK

CKPL = 1

t_LOW/HIGH

t_HD,SI

t_SU,SI

SIMO

t_HD,SO

t_VALID,SO

t_STE,ACC

t_STE,DIS

SOMI

图8-16. SPI Slave Mode, CKPH = 1

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节8.12.7.6 lists the characteristics of the eUSCI in I²C mode.

8.12.7.6 eUSCI (I²C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图8-17)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

Internal: SMCLK, MODCLK

External: UCLK

f_eUSCI

eUSCI input clock frequency

16 MHz

Duty cycle = 50% ±10%

f_SCL

SCL clock frequency

2 V, 3 V

0

4.0

0.6

4.7

0.6

0

400 kHz

µs

f_SCL= 100 kHz

f_SCL> 100 kHz

f_SCL= 100 kHz

f_SCL> 100 kHz

t_HD,STA

Hold time (repeated) START

t_SU,STA

Setup time for a repeated START

2 V, 3 V

µs

t_HD,DAT

t_SU,DAT

Data hold time

Data setup time

2 V, 3 V

ns

250

4.0

0.6

50

f_SCL= 100 kHz

f_SCL> 100 kHz

UCGLITx = 0

UCGLITx = 1

UCGLITx = 2

UCGLITx = 3

UCCLTOx = 1

UCCLTOx = 2

UCCLTOx = 3

t_SU,STO

Setup time for STOP

2 V, 3 V

µs

600

25

300

ns

150

Pulse duration of spikes suppressed by

input filter

t_SP

2 V, 3 V

12.5

6.3

75

27

30

33

t_TIMEOUTClock low time-out

2 V, 3 V

ms

t_HD,STA

t_SU,STA

t_HD,STA

t_BUF

SDA

SCL

t_LOW

t_HIGH

t_SP

t_SU,DAT

t_SU,STO

t_HD,DAT

图8-17. I²C Mode Timing

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8.12.8 ADC

节8.12.8.1 lists the characteristics of the ADC power supply and input range conditions.

8.12.8.1 ADC, Power Supply and Input Range Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

2.0

0

TYP

MAX UNIT

DV_CC

V_(Ax)

ADC supply voltage

Analog input voltage range

3.6

V

All ADC pins

DV_CC

Operating supply current into

DVCC terminal, reference

current not included, repeat-

single-channel mode

2 V

3 V

185

207

f_ADCCLK= 5 MHz, ADCON = 1,

REFON = 0, SHT0 = 0, SHT1 = 0,

ADCDIV = 0, ADCCONSEQx = 10b

I_ADC

µA

Only one terminal Ax can be selected at one

time from the pad to the ADC capacitor array,

including wiring and pad

C_I

R_I

Input capacitance

2.2 V

2.5

3.5

36

pF

Input MUX ON resistance

DV_CC= 2 V, 0 V ≤V_Ax≤DV_CC

kΩ

节8.12.8.2 lists the ADC 10-bit timing parameters.

8.12.8.2 ADC, 10-Bit Timing Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP

MAX UNIT

For specified performance of ADC linearity

parameters

2 V to

3.6 V

f_ADCCLK

f_ADCOSC

0.45

5

5.5 MHz

Internal ADC oscillator

(MODOSC)

2 V to

3.6 V

ADCDIV = 0, f_ADCCLK= f_ADCOSC

3.8

4.8

5.8 MHz

REFON = 0, Internal oscillator,

10 ADCCLK cycles, 10-bit mode,

f_ADCOSC= 4.5 MHz to 5.5 MHz

2 V to

3.6 V

2.18

2.67

µs

t_CONVERT

Conversion time

External f_ADCCLKfrom ACLK, MCLK, or SMCLK,

ADCSSEL ≠0

2 V to

3.6 V

12 ×

1 / f_ADCCLK

The error in a conversion started after t_ADCONis

less than ±0.5 LSB.

Reference and input signal are already settled.

Turnon settling time of

the ADC

t_ADCON

100

ns

µs

R_S= 1000 Ω, R_I= 36000 Ω, C_I= 3.5 pF.

Approximately 8 Tau (t) are required for an error

of less than ±0.5 LSB.⁽¹⁾

t_Sample

Sampling time

3 V

2.0

(1) t_Sample= ln(2ⁿ⁺¹) × τ, where n = ADC resolution, τ= (R_I+ R_S) × C_I

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节8.12.8.3 lists the ADC 10-bit linearity parameters.

8.12.8.3 ADC, 10-Bit Linearity Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

–2

TYP

MAX UNIT

Integral linearity error (10-bit mode)

Integral linearity error (8-bit mode)

Differential linearity error (10-bit mode)

Differential linearity error (8-bit mode)

Offset error (10-bit mode)

2.4 V to 3.6 V

2.0 V to 3.6 V

2.4 V to 3.6 V

2.0 V to 3.6 V

2.4 V to 3.6 V

2.0 V to 3.6 V

2

E_I

Veref+ reference

LSB

2

–2

1

–1

E_D

E_O

LSB

1

–1

6.5

mV

6.5

–6.5

–2.0

–3.0%

–2.0

–3.0%

–2.0

–3.0%

–2.0

–3.0%

Offset error (8-bit mode)

Veref+ as reference

Internal 1.5-V reference

Veref+ as reference

Internal 1.5-V reference

Veref+ as reference

Internal 1.5-V reference

Veref+ as reference

Internal 1.5-V reference

2.0 LSB

3.0%

Gain error (10-bit mode)

2.4 V to 3.6 V

2.0 V to 3.6 V

2.4 V to 3.6 V

2.0 V to 3.6 V

E_G

2.0 LSB

3.0%

Gain error (8-bit mode)

2.0 LSB

3.0%

Total unadjusted error (10-bit mode)

E_T

2.0 LSB

3.0%

Total unadjusted error (8-bit mode)

See ⁽¹⁾

ADCON = 1, INCH = 0Ch,

T_A= 0℃

V_SENSOR

3 V

913

mV

TC_SENSORSee ⁽²⁾

ADCON = 1, INCH = 0Ch

3.35

mV/℃

ADCON = 1, INCH = 0Ch, Error

of conversion result ≤1 LSB,

AM and all LPMs above LPM3

3 V

30

t_SENSOR

Sample time required if channel 12 is

selected⁽³⁾

µs

(sample)

ADCON = 1, INCH = 0Ch, Error

of conversion result ≤1 LSB,

LPM3

100

(1) The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in

temperature sensor.

(2) The device descriptor structure contains calibration values for 30℃and 85℃for each available reference voltage level. The sensor

voltage can be computed as V_SENSE= TC_SENSOR× (Temperature, ℃) + V_SENSOR, where TC_SENSORand V_SENSORcan be computed

from the calibration values for higher accuracy.

(3) The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor on time, t_SENSOR(on)

.

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8.12.9 FRAM

节8.12.9.1 lists the characteristics of the FRAM.

8.12.9.1 FRAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

10¹⁵

100

40

TYP

MAX

UNIT

Read and write endurance

cycles

T_J= 25°C

t_Retention

Data retention duration

T_J= 70°C

T_J= 85°C

years

10

(1)

I_WRITE

I_ERASE

t_WRITE

Current to write into FRAM

Erase current

I_READ

nA

ns

N/A⁽²⁾

(3)

Write time

t_READ

(4)

NWAITSx = 0

NWAITSx = 1

1 / f_SYSTEM

2 / f_SYSTEM

t_READ

Read time

ns

(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read

current I_READis included in the active mode current consumption parameter I_AM,FRAM

.

(2) FRAM does not require a special erase sequence.

(3) Writing into FRAM is as fast as reading.

(4) The maximum read (and write) speed is specified by f_SYSTEMusing the appropriate wait state settings (NWAITSx).

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8.12.10 Debug and Emulation

节8.12.10.1 lists the characteristics of the 2-wire SBW interface.

8.12.10.1 JTAG, Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图8-18)

PARAMETER

V_CC

MIN

TYP

MAX UNIT

f_SBW

Spy-Bi-Wire input frequency

2 V, 3 V

0

8

MHz

µs

t_SBW,Low

Spy-Bi-Wire low clock pulse duration

0.028

15

SBWTDIO setup time (before falling edge of SBWTCK in TMS and

TDI slot, Spy-Bi-Wire)

t_{SU, SBWTDIO}

t_{HD, SBWTDIO}

t_{Valid, SBWTDIO}

t_{SBW, En}

2 V, 3 V

4

ns

µs

SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI

slot, Spy-Bi-Wire)

19

SBWTDIO data valid time (after falling edge of SBWTCK in TDO slot,

Spy-Bi-Wire)

31

Spy-Bi-Wire enable time (TEST high to acceptance of first clock

edge) ⁽¹⁾

110

t_SBW,Ret

R_internal

Spy-Bi-Wire return to normal operation time⁽²⁾

2 V, 3 V

15

20

100

50

µs

Internal pulldown resistance on TEST

35

kΩ

(1) Tools that access the Spy-Bi-Wire interface must wait for the t_SBW,Entime after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2) Maximum t_SBW,Rettime after pulling or releasing the TEST/SBWTCK pin low until the Spy-Bi-Wire pins revert from their Spy-Bi-Wire

function to their application function. This time applies only if the Spy-Bi-Wire mode is selected.

t_SBW,EN

t_SBW,Low

1/f_SBW

t_SBW,High

t_SBW,Ret

TEST/SBWTCK

t_EN,SBWTDIO

t_{Valid,SBWTDIO}

RST/NMI/SBWTDIO

t_SU,SBWTDIO

t_HD,SBWTDIO

图8-18. JTAG Spy-Bi-Wire Timing

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节8.12.10.2 lists the characteristics of the 4-wire JTAG interface.

8.12.10.2 JTAG, 4-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图8-19)

PARAMETER

V_CC

MIN

TYP

MAX UNIT

f_TCK

TCK input frequency⁽¹⁾

2 V, 3 V

0

10 MHz

t_TCK,Low

t_TCK,High

t_SU,TMS

t_HD,TMS

t_SU,TDI

t_HD,TDI

TCK low clock pulse duration

15

11

3

ns

TCK high clock pulse duration

TMS setup time (before rising edge of TCK)

TMS hold time (after rising edge of TCK)

TDI setup time (before rising edge of TCK)

TDI hold time (after rising edge of TCK)

13

5

t_Z-Valid,TDOTDO high impedance to valid output time (after falling edge of TCK)

t_Valid,TDOTDO to new valid output time (after falling edge of TCK)

t_Valid-Z,TDOTDO valid to high-impedance output time (after falling edge of TCK)

26

ns

µs

kΩ

26

t_JTAG,Ret

R_internal

Spy-Bi-Wire return to normal operation time

Internal pulldown resistance on TEST

15

20

100

50

2 V, 3 V

35

(1) f_TCKmay be restricted to meet the timing requirements of the module selected.

1/f_TCK

t_TCK,Low

t_TCK,High

TCK

TMS

t_SU,TMS

t_HD,TMS

TDI

(or TDO as TDI)

t_SU,TDI

t_HD,TDI

TDO

t_Z-Valid,TDO

t_Valid,TDO

t_Valid-Z,TDO

t_JTAG,Ret

TEST

图8-19. JTAG 4-Wire Timing

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9 Detailed Description

9.1 Overview

The MSP430FR2422 is an ultra-low-power MCU. The architecture, combined with extensive low-power modes,

is optimized to achieve extended battery life in, for example, portable measurement applications. The MCU

features two 16-bit timers, two eUSCIs that support UART, SPI, and I²C, a hardware multiplier, an RTC module,

and a high-performance 10-bit ADC.

9.2 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,

other than program-flow instructions, are performed as register operations in conjunction with seven addressing

modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register

operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register (SR),

and constant generator (CG), respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be handled with

all instructions.

9.3 Operating Modes

The MSP430 has one active mode and several software-selectable low-power modes of operation (see 表 9-1).

An interrupt event can wake the MCU from low-power mode LPM0, LPM3 or LPM4, service the request, and

restore the MCU back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5

and LPM4.5 disable the core supply to minimize power consumption.

Note

XT1CLK and VLOCLK can be active during LPM4 mode if requested by low-frequency peripherals,

such as RTC and WDT.

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表9-1. Operating Modes

AM

LPM0

CPU OFF

16 MHz

LPM3

STANDBY

40 kHz

LPM4

OFF

0

LPM3.5

ONLY RTC

40 kHz

LPM4.5

SHUTDOWN

0

ACTIVE

MODE

(FRAM ON)

Maximum system clock

16 MHz

1.2 µA with

RTC counter

only in LFXT

0.73 µA with

RTC counter

only in LFXT

0.49 µA

without SVS

16 nA without

SVS

Power consumption at 25°C, 3 V

126 µA/MHz

40 µA/MHz

Wake-up time

N/A

Instant

All

10 µs

All

10 µs

I/O

350 µs

I/O

RTC

I/O

Wake-up events

Partial Power Partial Power Partial Power

Regulator

Full Regulation Full Regulation

Power Down

Down

Optional

On

Down

Optional

On

Down

Optional

On

Power

SVS

On

Optional

On

Off

Brownout

MCLK

SMCLK

FLL

On

Active

Off

Optional

On

Optional

Off

DCO

Off

Clock⁽²⁾

MODCLK

REFO

Off

Optional

Off

ACLK

Off

XT1CLK

VLOCLK

CPU

Off

Optional

Off

FRAM

On

Off

Core

RAM

On

Off

Backup memory⁽¹⁾

Timer0_A3

Timer1_A3

WDT

On

Optional

Off

eUSCI_A0

eUSCI_B0

CRC

Off

Peripherals

Off

ADC

Optional

Off

RTC

Off

Optional

General-purpose digital

input/output

I/O

On

Optional

State Held

(1) Backup memory contains 32 bytes of register space in peripheral memory. See 表9-20 and 表9-35 for its memory allocation.

(2) The status shown for LPM4 applies to internal clocks only.

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9.4 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see 表 9-2).

The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

表9-2. Interrupt Sources, Flags, and Vectors

SYSTEM

INTERRUPT

WORD

ADDRESS

INTERRUPT SOURCE

INTERRUPT FLAG

PRIORITY

System Reset

Power up, Brownout, Supply supervisor

External reset RST

Watchdog time-out, Key violation

FRAM uncorrectable bit error detection

Software POR, BOR

SVSHIFG

PMMRSTIFG

WDTIFG

Reset

FFFEh

63, Highest

PMMPORIFG, PMMBORIFG

SYSRSTIV

FLLUNLOCKIFG

FLL unlock error

System NMI

Vacant memory access

JTAG mailbox

FRAM access time error

FRAM bit error detection

VMAIFG

JMBINIFG, JMBOUTIFG

CBDIFG, UBDIFG

Nonmaskable

FFFCh

FFFAh

62

61

User NMI

External NMI

Oscillator fault

NMIIFG

OFIFG

Timer0_A3

Timer1_A3

TA0CCR0 CCIFG0

Maskable

FFF8h

FFF6h

FFF4h

FFF2h

60

59

58

57

TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,

TA0IFG (TA0IV)

TA1CCR0 CCIFG0

TA1CCR1 CCIFG1, TA1CCR2 CCIFG2,

TA1IFG (TA1IV)

RTC

RTCIFG

WDTIFG

Maskable

FFF0h

FFEEh

56

55

Watchdog timer interval mode

UCTXCPTIFG, UCSTTIFG, UCRXIFG,

UCTXIFG (UART mode)

UCRXIFG, UCTXIFG (SPI mode)

(UCA0IV)

eUSCI_A0 receive or transmit

Maskable

FFECh

54

UCB0RXIFG, UCB0TXIFG (SPI mode)

UCALIFG, UCNACKIFG, UCSTTIFG,

UCSTPIFG, UCRXIFG0, UCTXIFG0,

UCRXIFG1, UCTXIFG1, UCRXIFG2,

UCTXIFG2, UCRXIFG3, UCTXIFG3,

UCCNTIFG, UCBIT9IFG (I²C mode)

(UCB0IV)

eUSCI_B0 receive or transmit

Maskable

FFEAh

FFE8h

53

52

ADCIFG0, ADCINIFG, ADCLOIFG,

ADCHIIFG, ADCTOVIFG, ADCOVIFG

(ADCIV)

ADC

P1

P2

P1IFG.0 to P1IFG.7 (P1IV)

P2IFG.0 to P2IFG.6 (P2IV)

Reserved

Maskable

FFE6h

FFE4h

51

50

Reserved

FFE0h–FF88h

表9-3. Signatures

SIGNATURE

BSL Signature2

BSL Signature1

JTAG Signature2

JTAG Signature1

WORD ADDRESS

0FF86h

0FF84h

0FF82h

0FF80h

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9.5 Bootloader (BSL)

The BSL lets users program the FRAM or RAM using either the UART serial interface or the I²C interface.

Access to the MCU memory through the BSL is protected by an user-defined password. Use of the BSL requires

four pins (see 表 9-4 and 表 9-5). The BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO

and TEST/SBWTCK pins. This device can support the blank device detection automatically to invoke the BSL

with bypass this special entry sequence for saving time and on board programmable. For the complete

description of the feature of the BSL, see the MSP430 FRAM Device Bootloader (BSL) User's Guide.

表9-4. UART BSL Pin Requirements and Functions

DEVICE SIGNAL

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.4

BSL FUNCTION

Entry sequence signal

Data transmit

P1.5

Data receive

DVCC

Power supply

DVSS

Ground supply

表9-5. I²C BSL Pin Requirements and Functions

DEVICE SIGNAL

RST/NMI/SBWTDIO

TEST/SBWTCK

P1.2

BSL FUNCTION

Entry sequence signal

Data transmit and receive

Clock

P1.3

DVCC

Power supply

DVSS

Ground supply

9.6 JTAG Standard Interface

The MSP low-power microcontrollers support the standard JTAG interface, which requires four signals for

sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin

enables the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with

MSP430 development tools and device programmers. 表 9-6 lists the JTAG pin requirements. For further details

on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide.

For details on using the JTAG interface, see MSP430 Programming With the JTAG Interface.

表9-6. JTAG Pin Requirements and Function

DEVICE SIGNAL

DIRECTION

JTAG FUNCTION

JTAG clock input

JTAG state control

JTAG data input, TCLK input

JTAG data output

Enable JTAG pins

External reset

P1.4/.../TCK

IN

P1.5/.../TMS

P1.6/.../TDI/TCLK

P1.7/.../TDO

TEST/SBWTCK

RST/NMI/SBWTDIO

DVCC

IN

OUT

IN

Power supply

–

DVSS

Ground supply

–

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9.7 Spy-Bi-Wire Interface (SBW)

The MSP low-power microcontrollers support the 2-wire SBW interface. SBW can be used to interface with MSP

development tools and device programmers. 表 9-7 lists the SBW interface pin requirements. For further details

on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide.

For details on using the SBW interface, see the MSP430 Programming With the JTAG Interface.

表9-7. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

TEST/SBWTCK

RST/NMI/SBWTDIO

DVCC

DIRECTION

SBW FUNCTION

Spy-Bi-Wire clock input

Spy-Bi-Wire data input and output

Power supply

IN

IN, OUT

–

DVSS

Ground supply

–

9.8 FRAM

The FRAM can be programmed using the JTAG port, SBW, the BSL, or in-system by the CPU. Features of the

FRAM include:

• Byte and word access capability

• Programmable wait state generation

• Error correction coding (ECC)

9.9 Memory Protection

The device features memory protection for user access authority and write protection, including options to:

• Secure the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing JTAG and

BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.

• Enable write protection to prevent unwanted write operation to FRAM contents by setting the control bits in

the System Configuration 0 register. For detailed information, see the SYS chapter in the MP430FR4xx and

MP430FR2xx Family User's Guide.

9.10 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be handled

by using all instructions in the memory map. For complete module description, see the MP430FR4xx and

MP430FR2xx Family User's Guide.

9.10.1 Power-Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also

includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR) is

implemented to provide the proper internal reset signal to the device during power on and power off. The SVS

circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is available on the

primary supply.

The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.

The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC channel

15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily represent as 方程

式1 by using ADC sampling 1.5-V reference without any external components support.

DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result

(1)

A 1.2-V reference voltage can be buffered, when EXTREFEN = 1 on PMMCTL2 register, and it can be output to

P1.1/../A1/VREF+ , meanwhile the ADC channel 1 can also be selected to monitor this voltage. For more

detailed information, see the MSP430FR4xx and MSP430FR2xx Family User's Guide.

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9.10.2 Clock System (CS) and Clock Distribution

The clock system includes a 32-kHz crystal oscillator (XT1), an internal very-low-power low-frequency oscillator

(VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator (DCO) that

may use frequency-locked loop (FLL) locking with internal or external 32-kHz reference clock, and an on-chip

asynchronous high-speed clock (MODOSC). The clock system is designed for cost-effective designs with

minimal external components. A fail-safe mechanism is included for XT1. The clock system module offers the

following clock signals.

• Main Clock (MCLK): The system clock used by the CPU and all relevant peripherals accessed by the bus. All

clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8, 16, 32, 64, or

128.

• Sub-Main Clock (SMCLK): The subsystem clock used by the peripheral modules. SMCLK derives from the

MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.

• Auxiliary Clock (ACLK): This clock is derived from the external XT1 clock or internal REFO clock up to

40 kHz.

All peripherals may have one or several clock sources depending on specific functionality. 表 9-8 lists the clock

distribution used in this device.

表9-8. Clock Distribution

CLOCK

SOURCE

SELECT

BITS

MCLK

SMCLK

ACLK

MODCLK

XT1CLK

VLOCLK

EXTERNAL PIN

Frequency

Range

DC to

16 MHz

DC to

16 MHz

DC to 40 kHz 5 MHz ±10% DC to 40 kHz 10 kHz ±50%

–

CPU

N/A

Default

–

00b

–

10b

–

FRAM

RAM

–

N/A

–

CRC

N/A

–

I/O

N/A

–

TA0

TASSEL

UCSSEL

WDTSSEL

ADCSSEL

RTCSS

10b

01b

01b⁽¹⁾

11b

00b (TA0CLK pin)

00b (TA1CLK pin)

00b (UCA0CLK pin)

00b (UCB0CLK pin)

TA1

10b

–

eUSCI_A0

eUSCI_B0

WDT

10b or 11b

00b

–

10b

–

ADC

10b or 11b

01b⁽¹⁾

–

RTC

11b

–

(1) Controlled by the RTCCKSEL bit in the SYSCFG2 register

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CPU

FRAM

SRAM

CRC

I/O

MCLK

Timer_A

A0

Timer_A

A1

eUSCI_A0

eUSCI_B0

WDT

RTC

ADC10

Clock System (CS)

SMCLK

ACLK

VLOCLK

MODCLK

Selected on SYSCFG2

XT1CLK

图9-1. Clock Distribution Block Diagram

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9.10.3 General-Purpose Input/Output Port (I/O)

Up to 15 I/O ports are implemented.

• P1 implements 8 bits, and P2 implements 7 bits.

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• Programmable pullup or pulldown on all ports.

• Edge-selectable interrupt and LPMx.5 wake-up input capability are available for P1 and P2.

• Read and write access to port-control registers is supported by all instructions.

• Ports can be accessed byte-wise or word-wise as a pair.

Note

Configuration of digital I/Os after BOR reset

To prevent any cross currents during start-up of the device, all port pins are high-impedance with

Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR reset, the

ports must be configured first and then the LOCKLPM5 bit must be cleared. For details, see the

Configuration After Reset section in the Digital I/O chapter of the MP430FR4xx and MP430FR2xx

Family User's Guide.

9.10.4 Watchdog Timer (WDT)

The primary function of the WDT module is to perform a controlled system restart after a software problem

occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed

in an application, the module can be configured as an interval timer and can generate interrupts at selected time

intervals. 表9-9 lists the system clocks that can be used to source the WDT.

表9-9. WDT Clocks

NORMAL OPERATION

WDTSSEL

(WATCHDOG AND INTERVAL TIMER

MODE)

00

01

10

11

SMCLK

ACLK

VLOCLK

Reserved

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9.10.5 System (SYS) Module

The SYS module handles many of the system functions within the device. These features include power-on reset

(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector

generators, bootloader entry mechanisms, and configuration management (device descriptors). The SYS

module also includes a data exchange mechanism through SBW called a JTAG mailbox mail box that can be

used in the application. 表9-10 summarizes the interrupts that are managed by the SYS module.

表9-10. System Module Interrupt Vector Registers

INTERRUPT VECTOR

ADDRESS

INTERRUPT EVENT

VALUE

PRIORITY

REGISTER

No interrupt pending

Brownout (BOR)

00h

02h

Highest

RSTIFG RST/NMI (BOR)

PMMSWBOR software BOR (BOR)

LPMx.5 wakeup (BOR)

Security violation (BOR)

Reserved

04h

06h

08h

0Ah

0Ch

SVSHIFG SVSH event (BOR)

Reserved

0Eh

10h

SYSRSTIV, System Reset

015Eh

Reserved

12h

PMMSWPOR software POR (POR)

WDTIFG watchdog time-out (PUC)

WDTPW password violation (PUC)

FRCTLPW password violation (PUC)

Uncorrectable FRAM bit error detection

Peripheral area fetch (PUC)

PMMPW PMM password violation (PUC)

FLL unlock (PUC)

14h

16h

18h

1Ah

1Ch

1Eh

20h

24h

Reserved

22h, 26h to 3Eh

00h

Lowest

Highest

No interrupt pending

SVS low-power reset entry

Uncorrectable FRAM bit error detection

Reserved

02h

04h

06h

Reserved

08h

Reserved

0Ah

Reserved

0Ch

SYSSNIV, System NMI

015Ch

Reserved

0Eh

Reserved

10h

VMAIFG vacant memory access

JMBINIFG JTAG mailbox input

JMBOUTIFG JTAG mailbox output

Correctable FRAM bit error detection

Reserved

12h

14h

16h

18h

1Ah to 1Eh

00h

Lowest

Highest

Lowest

No interrupt pending

NMIIFG NMI pin or SVS_Hevent

OFIFG oscillator fault

Reserved

02h

SYSUNIV, User NMI

015Ah

04h

06h to 1Eh

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9.10.6 Cyclic Redundancy Check (CRC)

The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data values

and can be used for data checking purposes. The CRC generation polynomial is compliant with CRC-16-CCITT

standard of x¹⁶+ x¹²+ x⁵+ 1.

9.10.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)

The eUSCI modules are used for serial data communications. The eUSCI_A module supports either UART or

SPI communications. The eUSCI_B module supports either SPI or I²C communications. Additionally, eUSCI_A

supports automatic baud-rate detection and IrDA. The eUSCI_A and eUSCI_B are connected either from P1 port

or P2 port, it can be selected from the USCIARMP of SYSCFG3 or USCIBRMP bit of SYSCFG2. 表9-11 lists the

pin configurations that are required for each eUSCI mode.

表9-11. eUSCI Pin Configurations

PIN (USCIARMP = 0)

UART

SPI

SIMO

SOMI

SCLK

STE

P1.4

TXD

P1.5

RXD

P1.6

–

P1.7

eUSCI_A0

PIN (USCIARMP = 1)

UART

TXD

RXD

SPI

P2.0

SIMO

SOMI

SCLK

STE

P2.1

P1.6

–

P1.7

–

PIN (USCIBRMP = 0)

I²C

SPI

P1.0

STE

–

P1.1

SCLK

SIMO

SOMI

SPI

P1.2

SDA

SCL

I²C

P1.3

eUSCI_B0

PIN (USCIBRMP = 1)

P2.3

P2.4

P2.5

P2.6

STE

–

SCLK

SIMO

SOMI

SDA

SCL

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9.10.8 Timers (Timer0_A3, Timer1_A3)

The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare registers

each. Each timer supports multiple captures or compares, PWM outputs, and interval timing (see 图 9-2). Each

timer has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions

and from each of the capture/compare registers. The CCR0 registers on both Timer0_A3 and Timer1_A3 are not

externally connected and can only be used for hardware period timing and interrupt generation. In Up mode,

they can be used to set the overflow value of the counter.

Timer_A0

Timer_A1

TA0CLK

ACLK

00

01

10

11

TA1CLK

ACLK

00

01

10

11

16-bit Counter

SMCLK

VLO

16-bit Counter

SMCLK

00

01

10

11

ACLK

VLO

TA0.0A

TA0.0B

00

01

10

11

CCR0

DVSS

DVCC

TA0.0A

TA0.0B

CCR0

DVSS

DVCC

P1.4

RTC

00

01

10

11

TA0.1A

TA0.1B

P1.4

P2.2

00

01

10

11

CCR1

DVSS

DVCC

TA0.1A

TA0.1B

P2.2

CCR1

DVSS

DVCC

To ADC Trigger

P1.5

00

01

10

11

TA0.2A

TA0.2B

P1.5

P2.3

00

01

10

11

CCR2

DVSS

DVCC

TA0.2A

TA0.2B

P2.3

CCR2

DVSS

DVCC

Coding

Carrier

Infrared

Logic (SYS)

P2.0/UCA0TXD/UCA0SIMO

UCA0TXD/UCA0SIMO

eUSCI_A0

Data

图9-2. Timer0_A3 and Timer1_A3 Signal Connections

The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of UCA0TXD/

UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated infrared command for

directly driving an external IR diode. The IR functions are fully controlled by SYS configuration registers 1

including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSSEL (data select), and IRDATA

(data) bits. For more information, see the SYS chapter in the MP430FR4xx and MP430FR2xx Family User's

Guide.

9.10.9 Hardware Multiplier (MPY)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations

with 32-, 24-, 16-, and 8-bit operands. The MPY module supports signed multiplication, unsigned multiplication,

signed multiply-and-accumulate, and unsigned multiply-and-accumulate operations.

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9.10.10 Backup Memory (BAKMEM)

The BAKMEM supports data retention during LPM3.5. This device provides up to 32 bytes that are retained

during LPM3.5.

9.10.11 Real-Time Clock (RTC)

The RTC is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. This module can

periodically wake up the CPU from LPM0, LPM3, or LPM3.5 based on timing from a low-power clock source

such as the XT1 and VLO clocks. RTC also can be sourced from ACLK controlled by RTCCLK in SYSCFG2. In

AM, RTC can be driven by SMCLK to generate high-frequency timing events and interrupts. The RTC overflow

events trigger:

• Timer0_B3 CCI1B

• ADC conversion trigger when ADCSHSx bits are set as 01b

表9-12. RTC Clock Source

RTCSS

CLOCK SOURCE

00

Reserved

01

SMCLK or ACLK is selected⁽¹⁾

XT1CLK

10

11

VLOCLK

(1) Controlled by the RTCCLK bit of the SYSCFG2 register

9.10.12 10-Bit Analog-to-Digital Converter (ADC)

The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The module

implements a 10-bit SAR core, sample select control, a reference generator, and a conversion result buffer. A

window comparator with lower and upper limits allows CPU-independent result monitoring with three window

comparator interrupt flags.

The ADC supports 10 external inputs and 4 internal inputs (see 表9-13).

表9-13. ADC Channel Connections

ADCINCH

ADC CHANNELS

EXTERNAL PIN

x

0

A0/Veref+

P1.0

P1.1

P1.2

P1.3

P2.2

P2.3

P2.4

P2.5

N/A

1

A1⁽¹⁾

2

A2/Veref-

3

A3

4

A4

5

A5

6

A6

7

A7

Not used

8

9

Not used

N/A

10

11

12

13

14

15

Not used

N/A

Not used

N/A

On-chip temperature sensor

Reference voltage (1.5 V)

DVSS

N/A

DVCC

N/A

(1) When A7 is used, the PMM 1.2-V reference voltage can be

output to this pin by setting the PMM control register. The 1.2-V

voltage can be measured by the A1 channel.

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The analog-to-digital conversion can be started by software or a hardware trigger. 表 9-14 lists the trigger

sources that are available.

表9-14. ADC Trigger Signal Connections

ADCSHSx

TRIGGER SOURCE

BINARY

DECIMAL

00

01

10

11

0

1

2

3

ADCSC bit (software trigger)

RTC event

TA1.1B

Reserved

9.10.13 Embedded Emulation Module (EEM)

The EEM supports real-time in-system debugging. The EEM on these devices has the following features:

• Three hardware triggers or breakpoints on memory access

• One hardware trigger or breakpoint on CPU register write access

• Up to four hardware triggers can be combined to form complex triggers or breakpoints

• One cycle counter

• Clock control on module level

• EEM version: S

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9.11 Input/Output Diagrams

9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger

图9-3 shows the port diagram. 表9-15 summarizes the selection of pin function.

A0 to A3

P1SEL.x = 11

P1REN.x

P1DIR.x

From Module1

From Module2

00

01

10

11

2 bit

DVSS

DVCC

0

1

00

01

P1OUT.x

From Module1

From Module2

DVSS

10

11

2 bit

P1SEL.x

EN

D

To module

P1IN.x

P1IE.x

Bus

Keeper

P1 Interrupt

D

S

Q

P1IFG.x

P1.0/UCB0STE/A0/Veref+

P1.1/UCB0CLK/ACLK/A1/VREF+

P1.2/UCB0SIMO/UCB0SDA/SMCLK/A2/Veref-

P1.3/UCB0SOMI/UCB0SCL/MCLK/A3

P1.4/UCA0TXD/UCA0SIMO/TA0.1/TCK

P1.5/UCA0RXD/UCA0SOMI/TA0.2/TMS

P1.6/UCA0CLK/TA0CLK/TDI/TCLK

P1.7/UCA0STE/TDO

Edge

Select

P1IES.x

From JTAG

To JTAG

图9-3. Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger

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表9-15. Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS AND SIGNALS⁽²⁾

PIN NAME (P1.x)

x

FUNCTION

ANALOG

P1SELx

P1DIR.x

JTAG

FUNCTION⁽¹⁾

P1.0 (I/O)

UCB0STE

I: 0; O: 1

X

00

01

0

P1.0/UCB0STE/A0/

Veref+

0

ADCPCTLx = 1 (x = 0) from

SYSCFG2

A0,Veref+

X

N/A

P1.1 (I/O)

UCB0CLK

ACLK

I: 0; O: 1

00

01

10

0

X

1

P1.1/UCB0CLK/ACLK/

A1/VREF+

1

2

3

ADCPCTLx = 1 (x = 1) from

SYSCFG2

A1,VREF+

P1.2 (I/O)

X

N/A

I: 0; O: 1

00

01

10

0

UCB0SIMO/UCB0SDA

SMCLK

X

1

P1.2/UCB0SIMO/

UCB0SDA/SMCLK/A2/

Veref-

ADCPCTLx = 1 (x = 2) from

SYSCFG2

A2, Veref-

X

N/A

P1.3 (I/O)

I: 0; O: 1

00

01

10

0

UCB0SOMI/UCB0SCL

MCLK

X

1

P1.3/UCB0SOMI/

UCB0SCL/MCLK/A3

ADCPCTLx = 1 (x = 3) from

SYSCFG2

A3

X

N/A

P1.4 (I/O)

I: 0; O: 1

00

01

0

Disabled

UCA0TXD/UCA0SIMO

TA0.CCI1A

TA0.1

X

P1.4/UCA0TXD/

UCA0SIMO/TA0.1/TCK

4

5

0

10

0

Disabled

1

JTAG TCK

P1.5 (I/O)

X

0

TCK

I: 0; O: 1

00

01

Disabled

UCA0RXD/UCA0SOMI

TA0.CCI2A

TA0.2

X

P1.5/UCA0RXD/

UCA0SOMI/TA0.2/TMS

0

10

0

Disabled

1

JTAG TMS

P1.6 (I/O)

X

00

01

10

X

0

X

0

X

TMS

I: 0; O: 1

Disabled

TDI/TCLK

Disabled

TDO

UCA0CLK

X

P1.6/UCA0CLK/

TA0CLK/TDI/TCLK

6

7

TA0CLK

0

JTAG TDI/TCLK

P1.7 (I/O)

X

I: 0; O: 1

00

01

X

P1.7/UCA0STE/TDO

UCA0STE

X

JTAG TDO

(1) Setting the bits disables both the output driver and input Schmitt trigger to prevent leakage when analog signals are applied.

(2) X = don't care

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9.11.2 Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger

图9-4 shows the port diagram. 表9-16 summarizes the selection of pin function.

A4 to A7

P2SEL.x = 11

P2REN.x

P2DIR.x

From Module1

From Module2

00

01

10

11

2 bit

DVSS

DVCC

0

1

00

01

P2OUT.x

From Module1

From Module2

DVSS

10

11

2 bit

P2SEL.x

EN

D

To module

P2IN.x

P2IE.x

Bus

Keeper

P2 Interrupt

D

S

Q

P2.0/UCA0TXD/UCA0SIMO/XOUT

P2.1/UCA0RXD/UCA0SOMI/XIN

P2.2/TA1.1/A4

P2.3/TA1.2/UCB0STE/A5

P2.4/TA1CLK/UCB0CLK/A6

P2.5/UCB0SIMO/UCB0SDA/A7

P2.6/UCB0SOMI/UCB0SCL

P2IFG.x

P2IES.x

Edge

Select

图9-4. Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger

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表9-16. Port P2 (P2.0 to P2.6) Pin Functions

CONTROL BITS AND SIGNALS⁽²⁾

PIN NAME (P2.x)

x

FUNCTION

P2DIR.x

P2SELx

00

ANALOG FUNCTION⁽¹⁾

P2.0 (I/O)

I: 0; O: 1

0

P2.0/UCA0TXD/

UCA0SIMO/XOUT

0

UCA0TXD/UCA0SIMO

XOUT

X

01

X

10

P2.1 (I/O)

I: 0; O: 1

00

P2.1/UCA0RXD/

UCA0SOMI/XIN

1

2

UCA0RXD/UCA0SOMI

XIN

X

01

X

10

P2.2 (I/O)

I: 0; O: 1

00

TA1.CCI1A

TA1.1

0

1

01

0

P2.2/TA1.1/A4

ADCPCTLx = 1 (x = 4)

from SYSCFG2⁽¹⁾

A4

X

P2.3 (I/O)

TA1.CCI2A

TA1.2

I: 0; O: 1

00

0

1

X

01

P2.3/TA1.2/

UCB0STE/A5

3

4

UCB0STE

10

X

ADCPCTLx = 1 (x = 5)

from SYSCFG2⁽¹⁾

A5

X

P2.4 (I/O)

TA1CLK

I: 0; O: 1

00

01

10

0

P2.4/TA1CLK/

UCB0CLK/A6

UCB0CLK

X

ADCPCTLx = 1 (x = 6)

from SYSCFG2⁽¹⁾

A6

X

P2.5 (I/O)

I: 0; O: 1

X

00

10

0

P2.5/UCB0SIMO/

UCB0SDA/A7

UCB0SIMO/UCB0SDA

5

6

ADCPCTLx = 1 (x = 7)

from SYSCFG2⁽¹⁾

A7

X

P2.6 (I/O)

I: 0; O: 1

X

00

10

0

P2.6/UCB0SOMI/

UCB0SCL

UCB0SOMI/UCB0SCL

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9.12 Device Descriptors

表 9-17 lists the Device IDs of the devices. 表 9-18 lists the contents of the device descriptor tag-length-value

(TLV) structure for the devices.

表9-17. Device IDs

DEVICE ID

DEVICE

1A05h

1A04h

MSP430FR2422

83h

11h

表9-18. Device Descriptors

MSP430FR2422

ADDRESS

DESCRIPTION

VALUE

06h

Info length

1A00h

1A01h

1A02h

1A03h

1A04h

1A05h

1A06h

1A07h

1A08h

1A09h

1A0Ah

1A0Bh

1A0Ch

1A0Dh

1A0Eh

1A0Fh

1A10h

1A11h

1A12h

1A13h

1A14h

1A15h

1A16h

1A17h

1A18h

1A19h

1A1Ah

1A1Bh

1A1Ch

1A1Dh

CRC length

06h

Per unit

CRC value⁽¹⁾

Information Block

Device ID

See 表9-17.

Hardware revision

Firmware revision

Die record tag

Per unit

08h

Die record length

0Ah

Per unit

Lot wafer ID

Die Record

Die X position

Die Y position

Test result

ADC calibration tag

ADC calibration length

ADC gain factor

ADC calibration

ADC offset

ADC 1.5-V reference, temperature 30°C

ADC 1.5-V reference, temperature 85°C

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表9-18. Device Descriptors (continued)

MSP430FR2422

DESCRIPTION

ADDRESS

1A1Eh

1A1Fh

1A20h

VALUE

12h

Calibration tag

Calibration length

04h

Per unit

Reference and DCO Calibration 1.5-V reference factor

1A21h

1A22h

DCO tap setting for 16 MHz, temperature 30°C⁽²⁾

1A23h

(1) The CRC value covers the check sum from 0x1A04h to 0x1AF5h by applying the CRC-CCITT-16 polynomial of x¹⁶+ x¹²+ x⁵+ 1.

(2) This value can be directly loaded into DCO bits in CSCTL0 registers to get accurate 16-MHz frequency at room temperature,

especially when the MCU exits from LPM3 and below. TI suggests using the predivider to decrease the frequency if the temperature

drift might result an overshoot beyond 16 MHz.

9.13 Memory

9.13.1 Memory Organization

表9-19 summarizes the memory organization of the devices.

表9-19. Memory Organization

ACCESS

MSP430FR2422

Memory (FRAM)

Main: interrupt vectors and signatures

Main: code memory

7.25KB

FFFFh to FF80h

FFFFh to E300h

Read/Write

(Optional Write Protect)⁽¹⁾

2KB

27FFh to 2000h

RAM

Read/Write

256B

18FFh to 1800h

Information Memory (FRAM)

Bootloader (BSL1) Memory (ROM)

Bootloader (BSL2) Memory (ROM)

Peripherals

(Optional Write Protect)⁽²⁾

2KB

17FFh to 1000h

Read only

Read/Write

1KB

FFFFFh to FFC00h

4KB

0FFFh to 0000h

(1) The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See the SYS chapter in the MP430FR4xx and

MP430FR2xx Family User's Guide for more details

(2) The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. See the SYS chapter in the MP430FR4xx

and MP430FR2xx Family User's Guide for more details

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9.13.2 Peripheral File Map

表9-20 lists the available peripherals and the register base address for each.

表9-20. Peripherals Summary

MODULE NAME

Special Functions (See 表9-21)

BASE ADDRESS

0100h

SIZE

0010h

0020h

0040h

0020h

0010h

0008h

0002h

0020h

0010h

0030h

0020h

0030h

0020h

0040h

0120h

PMM (See 表9-22)

0140h

SYS (See 表9-23)

0180h

CS (See 表9-24)

01A0h

01C0h

01CCh

0200h

FRAM (See 表9-25)

CRC (See 表9-26)

WDT (See 表9-27)

Port P1, P2 (See 表9-28)

RTC (See 表9-29)

0300h

0380h

Timer0_A3 (See 表9-30)

Timer1_A3 (See 表9-31)

MPY32 (See 表9-32)

eUSCI_A0 (See 表9-33)

eUSCI_B0 (See 表9-34)

Backup Memory (See 表9-35)

ADC (See 表9-36)

03C0h

04C0h

0500h

0540h

0660h

0700h

表9-21. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

SFR interrupt enable

SFR interrupt flag

SFRIE1

SFRIFG1

SFRRPCR

02h

SFR reset pin control

04h

表9-22. PMM Registers (Base Address: 0120h)

REGISTER DESCRIPTION

ACRONYM

PMMCTL0

PMMCTL1

PMMCTL2

PMMIFG

OFFSET

00h

PMM control 0

PMM control 1

PMM control 2

PMM interrupt flags

PM5 control 0

02h

04h

0Ah

PM5CTL0

10h

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表9-23. SYS Registers (Base Address: 0140h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

System control

SYSCTL

Bootloader configuration area

JTAG mailbox control

SYSBSLC

SYSJMBC

SYSJMBI0

SYSJMBI1

SYSJMBO0

SYSJMBO1

SYSBERRIV

SYSUNIV

SYSSNIV

02h

06h

JTAG mailbox input 0

08h

JTAG mailbox input 1

0Ah

0Ch

0Eh

18h

JTAG mailbox output 0

JTAG mailbox output 1

Bus error vector generator

User NMI vector generator

System NMI vector generator

Reset vector generator

System configuration 0

System configuration 1

System configuration 2

1Ah

1Ch

1Eh

20h

SYSRSTIV

SYSCFG0

SYSCFG1

SYSCFG2

22h

24h

表9-24. CS Registers (Base Address: 0180h)

REGISTER DESCRIPTION

ACRONYM

CSCTL0

CSCTL1

CSCTL2

CSCTL3

CSCTL4

CSCTL5

CSCTL6

CSCTL7

CSCTL8

OFFSET

00h

CS control 0

CS control 1

CS control 2

CS control 3

CS control 4

CS control 5

CS control 6

CS control 7

CS control 8

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

表9-25. FRAM Registers (Base Address: 01A0h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

FRAM control 0

General control 0

General control 1

FRCTL0

GCCTL0

GCCTL1

04h

06h

表9-26. CRC Registers (Base Address: 01C0h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

CRC data input

CRC16DI

CRC data input reverse byte

CRC initialization and result

CRC result reverse byte

CRCDIRB

CRCINIRES

CRCRESR

02h

04h

06h

表9-27. WDT Registers (Base Address: 01CCh)

REGISTER DESCRIPTION

ACRONYM

OFFSET

Watchdog timer control

WDTCTL

00h

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表9-28. Port P1, P2 Registers (Base Address: 0200h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

Port P1 input

P1IN

00h

02h

04h

06h

0Ah

0Ch

0Eh

18h

16h

1Ah

1Ch

01h

03h

05h

07h

0Bh

0Ch

17h

1Eh

19h

1Bh

1Dh

Port P1 output

Port P1 direction

P1OUT

P1DIR

P1REN

P1SEL0

P1SEL1

P1IV

Port P1 pulling enable

Port P1 selection 0

Port P1 selection 1

Port P1 interrupt vector word

Port P1 interrupt edge select

Port P1 complement selection

Port P1 interrupt enable

Port P1 interrupt flag

Port P2 input

P1IES

P1SELC

P1IE

P1IFG

P2IN

Port P2 output

P2OUT

P2DIR

P2REN

P2SEL0

P2SEL1

P2SELC

P2IV

Port P2 direction

Port P2 pulling enable

Port P2 selection 0

Port P2 selection 1

Port P2 complement selection

Port P2 interrupt vector word

Port P2 interrupt edge select

Port P2 interrupt enable

Port P2 interrupt flag

P2IES

P2IE

P2IFG

表9-29. RTC Registers (Base Address: 0300h)

REGISTER DESCRIPTION

ACRONYM

RTCCTL

RTCIV

OFFSET

00h

RTC control

RTC interrupt vector

RTC modulo

04h

RTCMOD

RTCCNT

08h

RTC counter

0Ch

60

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表9-30. Timer0_A3 Registers (Base Address: 0380h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

TA0 control

TA0CTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA0 counter

TA0CCTL0

TA0CCTL1

TA0CCTL2

TA0R

02h

04h

06h

10h

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA0 expansion 0

TA0CCR0

TA0CCR1

TA0CCR2

TA0EX0

12h

14h

16h

20h

TA0 interrupt vector

TA0IV

2Eh

表9-31. Timer1_A3 Registers (Base Address: 03C0h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

00h

TA1 control

TA1CTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

TA1 counter

TA1CCTL0

TA1CCTL1

TA1CCTL2

TA1R

02h

04h

06h

10h

Capture/compare 0

Capture/compare 1

Capture/compare 2

TA1 expansion 0

TA1CCR0

TA1CCR1

TA1CCR2

TA1EX0

12h

14h

16h

20h

TA1 interrupt vector

TA1IV

2Eh

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表9-32. MPY32 Registers (Base Address: 04C0h)

REGISTER DESCRIPTION

ACRONYM

OFFSET

MPY

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

20h

22h

24h

26h

28h

2Ah

2Ch

16-bit operand 1 –multiply

MPYS

16-bit operand 1 –signed multiply

16-bit operand 1 –multiply accumulate

16-bit operand 1 –signed multiply accumulate

16-bit operand 2

MAC

MACS

OP2

16 × 16 result low word

RESLO

RESHI

16 × 16 result high word

16 × 16 sum extension

SUMEXT

MPY32L

MPY32H

MPYS32L

MPYS32H

MAC32L

MAC32H

MACS32L

MACS32H

OP2L

32-bit operand 1 –multiply low word

32-bit operand 1 –multiply high word

32-bit operand 1 –signed multiply low word

32-bit operand 1 –signed multiply high word

32-bit operand 1 –multiply accumulate low word

32-bit operand 1 –multiply accumulate high word

32-bit operand 1 –signed multiply accumulate low word

32-bit operand 1 –signed multiply accumulate high word

32-bit operand 2 –low word

OP2H

32-bit operand 2 –high word

RES0

32 × 32 result 0 –least significant word

32 × 32 result 1

RES1

32 × 32 result 2

RES2

RES3

32 × 32 result 3 –most significant word

MPY32 control 0

MPY32CTL0

表9-33. eUSCI_A0 Registers (Base Address: 0500h)

REGISTER DESCRIPTION

ACRONYM

UCA0CTLW0

UCA0CTLW1

UCA0BR0

OFFSET

00h

eUSCI_A control word 0

eUSCI_A control word 1

eUSCI_A control rate 0

eUSCI_A control rate 1

eUSCI_A modulation control

eUSCI_A status

02h

06h

UCA0BR1

07h

UCA0MCTLW

UCA0STAT

UCA0RXBUF

UCA0TXBUF

UCA0ABCTL

lUCA0IRTCTL

IUCA0IRRCTL

UCA0IE

08h

0Ah

0Ch

0Eh

10h

eUSCI_A receive buffer

eUSCI_A transmit buffer

eUSCI_A LIN control

eUSCI_A IrDA transmit control

eUSCI_A IrDA receive control

eUSCI_A interrupt enable

eUSCI_A interrupt flags

eUSCI_A interrupt vector word

12h

13h

1Ah

1Ch

1Eh

UCA0IFG

UCA0IV

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表9-34. eUSCI_B0 Registers (Base Address: 0540h)

REGISTER DESCRIPTION

ACRONYM

UCB0CTLW0

UCB0CTLW1

UCB0BR0

OFFSET

00h

eUSCI_B control word 0

eUSCI_B control word 1

eUSCI_B bit rate 0

02h

06h

eUSCI_B bit rate 1

UCB0BR1

07h

eUSCI_B status word

UCB0STATW

UCB0TBCNT

UCB0RXBUF

UCB0TXBUF

UCB0I2COA0

UCB0I2COA1

UCB0I2COA2

UCB0I2COA3

UCB0ADDRX

UCB0ADDMASK

UCB0I2CSA

UCB0IE

08h

eUSCI_B byte counter threshold

eUSCI_B receive buffer

eUSCI_B transmit buffer

eUSCI_B I2C own address 0

eUSCI_B I2C own address 1

eUSCI_B I2C own address 2

eUSCI_B I2C own address 3

eUSCI_B receive address

eUSCI_B address mask

eUSCI_B I2C slave address

eUSCI_B interrupt enable

eUSCI_B interrupt flags

eUSCI_B interrupt vector word

0Ah

0Ch

0Eh

14h

16h

18h

1Ah

1Ch

1Eh

20h

2Ah

2Ch

2Eh

UCB0IFG

UCB0IV

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表9-35. Backup Memory Registers (Base Address: 0660h)

REGISTER DESCRIPTION

ACRONYM

BAKMEM0

BAKMEM1

BAKMEM2

BAKMEM3

BAKMEM4

BAKMEM5

BAKMEM6

BAKMEM7

BAKMEM8

BAKMEM9

BAKMEM10

BAKMEM11

BAKMEM12

BAKMEM13

BAKMEM14

BAKMEM15

OFFSET

Backup memory 0

Backup memory 1

Backup memory 2

Backup memory 3

Backup memory 4

Backup memory 5

Backup memory 6

Backup memory 7

Backup memory 8

Backup memory 9

Backup memory 10

Backup memory 11

Backup memory 12

Backup memory 13

Backup memory 14

Backup memory 15

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

表9-36. ADC Registers (Base Address: 0700h)

REGISTER DESCRIPTION

REGISTER

ADCCTL0

ADCCTL1

ADCCTL2

ADCLO

OFFSET

00h

ADC control 0

ADC control 1

02h

ADC control 2

04h

ADC window comparator low threshold

ADC window comparator high threshold

ADC memory control 0

ADC conversion memory

ADC interrupt enable

06h

ADCHI

08h

ADCMCTL0

ADCMEM0

ADCIE

0Ah

12h

1Ah

1Ch

1Eh

ADC interrupt flags

ADCIFG

ADC interrupt vector word

ADCIV

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9.14 Identification

9.14.1 Revision Identification

The device revision information is included as part of the top-side marking on the device package. The device-

specific errata sheet describes these markings.

The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on

this value, see the Hardware Revision entries in 节9.12.

9.14.2 Device Identification

The device type can be identified from the top-side marking on the device package. The device-specific errata

sheet describes these markings.

A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details

on this value, see the Device ID entries in 节9.12.

9.14.3 JTAG Identification

Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in detail in

MSP430 Programming With the JTAG Interface.

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10 Applications, Implementation, and Layout

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Device Connection and Layout Fundamentals

This section discusses the recommended guidelines when designing with the MSP430 devices. These

guidelines are to make sure that the device has proper connections for powering, programming, debugging, and

optimum analog performance.

10.1.1 Power Supply Decoupling and Bulk Capacitors

TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling capacitor to

the DVCC and DVSS pins. Higher-value capacitors may be used but can impact supply rail ramp-up time.

Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few

millimeters). Additionally, TI recommends separated grounds with a single-point connection for better noise

isolation from digital-to-analog circuits on the board and to achieve high analog accuracy.

DVCC

Digital

+

Power Supply

Decoupling

DVSS

10 µF

100 nF

图10-1. Power Supply Decoupling

10.1.2 External Oscillator

This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass

capacitors for the crystal oscillator pins are required.

It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the respective

oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT pin can be used

for other purposes. If the XIN and XOUT pins are not used, they must be terminated according to 节7.6.

图10-2 shows a typical connection diagram.

XIN

XOUT

C_L1

C_L2

图10-2. Typical Crystal Connection

See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal

oscillator with the MSP430 devices.

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10.1.3 JTAG

With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or MSP-

FET430UIF) can be used to program and debug code on the target board. In addition, the connections also

support the MSP-GANG production programmers, thus providing an easy way to program prototype boards, if

desired. 图 10-3 shows the connections between the 14-pin JTAG connector and the target device required to

support in-system programming and debugging for 4-wire JTAG communication. 图 10-4 shows the connections

for 2-wire JTAG mode (Spy-Bi-Wire).

The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are identical.

Both can supply V_CCto the target board (through pin 2). In addition, the MSP-FET and MSP-FET430UIF

interface modules and MSP-GANG have a V_CCsense feature that, if used, requires an alternate connection (pin

4 instead of pin 2). The V_CCsense feature detects the local V_CCpresent on the target board (that is, a battery or

other local power supply) and adjusts the output signals accordingly. 图 10-3 and 图 10-4 show a jumper block

that supports both scenarios of supplying V_CCto the target board. If this flexibility is not required, the desired V_CC

connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be connected at the same

time.

For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User's Guide.

V_CC

Important to connect

MSP430FRxxx

J1 (see Note A)

DVCC

J2 (see Note A)

R1

47 kW

JTAG

RST/NMI/SBWTDIO

VCC TOOL

TDO/TDI

TDI

TDO/TDI

TDI

2

1

VCC TARGET

4

3

TMS

6

5

7

TEST

TCK

8

TCK

GND

RST

10

12

14

9

11

13

TEST/SBWTCK

DVSS

C1

1 nF

(see Note B)

A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection

J2.

B. The upper limit for C1 is 1.1 nF when using current TI tools.

图10-3. Signal Connections for 4-Wire JTAG Communication

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V_CC

Important to connect

MSP430FRxxx

J1 (see Note A)

J2 (see Note A)

DVCC

R1

47 kΩ

(see Note B)

JTAG

VCC TOOL

TDO/TDI

2

1

3

5

7

9

RST/NMI/SBWTDIO

VCC TARGET

4

6

TCK

8

GND

10

12

14

11

13

TEST/SBWTCK

DVSS

C1

1 nF

(see Note B)

A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or

programming adapter.

B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and

any capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is

1.1 nF when using current TI tools.

图10-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)

10.1.4 Reset

The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function

Register (SFR), SFRRPCR.

In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing

specifications generates a BOR-type device reset.

Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge

sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI.

When an external NMI event occurs, the NMIIFG is set.

The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either pullup or

pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not. If the RST/NMI

pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-kΩpullup

resistor to the RST/NMI pin with a 10-nF pulldown capacitor. The pulldown capacitor should not exceed 1.1 nF

when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like

FET interfaces or GANG programmers.

See the MP430FR4xx and MP430FR2xx Family User's Guide for more information on the referenced control

registers and bits.

10.1.5 Unused Pins

For details on the connection of unused pins, see 节7.6.

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10.1.6 General Layout Recommendations

• Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430 32-kHz

Crystal Oscillators for recommended layout guidelines.

• Proper bypass capacitors on DVCC and reference pins, if used.

• Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching

signals such as PWM or JTAG signals away from the oscillator circuit.

• Proper ESD level protection should be considered to protect the device from unintended high-voltage

electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.

10.1.7 Do's and Don'ts

During power up, power down, and device operation, DVCC must not exceed the limits specified in 节 8.1.

Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and

FRAM.

10.2 Peripheral- and Interface-Specific Design Information

10.2.1 ADC Peripheral

10.2.1.1 Partial Schematic

图10-5 shows the recommended decoupling circuit when an external voltage reference is used.

DVSS

Using an external

VREF+/VEREF+

positive reference

+

100 nF

10 µF

Using an external

negative reference

VEREF-

+

10 µF

100 nF

图10-5. ADC Grounding and Noise Considerations

10.2.1.2 Design Requirements

As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be

followed to eliminate ground loops, unwanted parasitic effects, and noise.

Ground loops are formed when return current from the ADC flows through paths that are common with other

analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can

add to or subtract from the reference or input voltages of the ADC. The general guidelines in 节10.1.1 combined

with the connections shown in 图10-5 prevent this.

Quickly switching digital signals and noisy power supply lines can corrupt the conversion results, so keep the

ADC input trace shielded from those digital and power supply lines. Putting the MCU in low-power mode during

the ADC conversion improves the ADC performance in a noisy environment. If the device includes the analog

power pair inputs (AVCC and AVSS), TI recommends a noise-free design using separate analog and digital

ground planes with a single-point connection to achieve high accuracy.

图 10-5 shows the recommended decoupling circuit when an external voltage reference is used. The internal

reference module has a maximum drive current as described in the sections ADC Pin Enable and 1.2-V

Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide.

The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are

selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage

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enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters any low-frequency ripple.

A bypass capacitor of 100 nF filters out any high-frequency noise.

10.2.1.3 Layout Guidelines

Components that are shown in the partial schematic (see 图 10-5) should be placed as close as possible to the

respective device pins to avoid long traces, because they add additional parasitic capacitance, inductance, and

resistance on the signal.

Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM), because

the high-frequency switching can be coupled into the analog signal.

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11 Device and Documentation Support

11.1 Getting Started and Next Steps

For more information on the MSP low-power microcontrollers and the tools and libraries that are available to help

with your development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview.

11.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP

MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These

prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully

qualified production devices (MSP).

XMS –Experimental device that is not necessarily representative of the final device's electrical specifications

MSP –Fully qualified production device

XMS devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated

fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.

TI recommends that these devices not be used in any production system because their expected end-use failure

rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature

range, package type, and distribution format. 图11-1 provides a legend for reading the complete device name.

MSP 430 FR 2 422 I RHL T

Processor Family

MCU Platform

Device Type

Series

Distribution Format

Packaging

Temperature Range

Feature Set

Processor Family

MSP = Mixed-Signal Processor

XMS = Experimental Silicon

MCU Platform

Device Type

430 = MSP430 16-bit low-power platform

Memory Type

FR = FRAM

Series

2 = Up to 16 MHz without LCD

Feature Set

First and Second Digits:

ADC10 Channels / eUSCIs / 16-bit Timers / I/Os

42 = Up to 8 / 2 / 2 / Up to 15

Third Digit:

FRAM (KB) / SRAM (KB)

2 = 8 / 2

Temperature Range

Packaging

I = –40°C to 85°C

www.ti.com/packaging

Distribution Format

T = Small reel

R = Large reel

No Marking = Tube or tray

图11-1. Device Nomenclature

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11.3 Tools and Software

表 11-1 lists the debug features supported by these microcontrollers. See the Code Composer Studio IDE for

MSP430 MCUs User's Guide for details on the available features.

表11-1. Hardware Features

BREAK-

POINTS

(N)

RANGE

BREAK-

POINTS

LPMx.5

DEBUGGING

SUPPORT

MSP430

ARCHITECTURE

4-WIRE

JTAG

2-WIRE

JTAG

CLOCK

CONTROL

STATE

SEQUENCER

TRACE

BUFFER

EEM

VERSION

MSP430Xv2

Yes

3

Yes

No

S

Design Kits and Evaluation Modules

MSP-TS430RHL20 20-Pin Target Development Board for MSP430FR2x MCUs

The MSP-TS430RHL20 is a stand-alone ZIF socket target board used to program and debug the MSP430 in-

system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol. The development board supports

all MSP430FR252x and MSP430FR242x Flash parts in a 20-pin VQFN package (TI package code: RHL).

MSP-FET + MSP-TS430RHL20 FRAM Microcontroller Development Kit Bundle

The MSP-FET430RHL20-BNDL bundle combines two debugging tools that support the 20-pin RHL package for

the MSP430FR2422 microcontroller (for example, MSP430FR2422RHL). These two tools include MSP-

TS430RHL20 and MSP-FET.

Software

MSP430Ware^™Software

MSP430Ware software is a collection of code examples, data sheets, and other design resources for all

MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing

MSP430 design resources, MSP430Ware software also includes a high-level API called MSP430 Driver Library.

This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of

CCS or as a stand-alone package.

MSP430FR2422 Code Examples

C Code examples are available for every MSP device that configures each of the integrated peripherals for

various application needs.

MSP Driver Library

Driver Library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing easy-

to-use function calls. Thorough documentation is delivered through a helpful API Guide, which includes details

on each function call and the recognized parameters. Developers can use Driver Library functions to write

complete projects with minimal overhead.

MSP EnergyTrace^™Technology

EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and

displays the application’s energy profile and helps to optimize it for ultra-low-power consumption.

ULP (Ultra-Low Power) Advisor

ULP Advisor^™software is a tool for guiding developers to write more efficient code to fully utilize the unique

ultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new

microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every

last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks to

highlight areas of your code that can be further optimized for lower power.

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FRAM Embedded Software Utilities for MSP Ultra-Low-Power Microcontrollers

The FRAM Utilities is designed to grow as a collection of embedded software utilities that leverage the ultra-low-

power and virtually unlimited write endurance of FRAM. The utilities are available for MSP430FRxx FRAM

microcontrollers and provide example code to help start application development. Included utilities include

Compute Through Power Loss (CTPL). CTPL is utility API set that enables ease of use with LPMx.5 low-power

modes and a powerful shutdown mode that allows an application to save and restore critical system components

when a power loss is detected.

IEC60730 Software Package

The IEC60730 MSP430 software package was developed to be useful in assisting customers in complying with

IEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General

Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters,

power tools, e-bikes, and many others. The IEC60730 MSP430 software package can be embedded in customer

applications running on MSP430s to help simplify the customer’s certification efforts of functional safety-

compliant consumer devices to IEC 60730-1:2010 Class B.

Fixed Point Math Library for MSP

The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical

functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and

MSP432 devices. These routines are typically used in computationally intensive real-time applications where

optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath

libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably

lower than equivalent code written using floating-point math.

Floating Point Math Library for MSP430

Continuing to innovate in the low power and low cost microcontroller space, TI brings you MSPMATHLIB.

Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you

up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated

in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in depth look at the math library

and relevant benchmarks.

Development Tools

Code Composer Studio^™Integrated Development Environment for MSP Microcontrollers

Code Composer Studio is an integrated development environment (IDE) that supports all MSP microcontroller

devices. Code Composer Studio comprises a suite of embedded software utilities used to develop and debug

embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,

debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through

each step of the application development flow. Familiar utilities and interfaces allow users to get started faster

than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with

advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment

for embedded developers. When using CCS with an MSP MCU, a unique and powerful set of plugins and

embedded software utilities are made available to fully leverage the MSP microcontroller.

Command-Line Programmer

MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET

programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary

files (.txt or .hex) files directly to the MSP microcontroller without an IDE.

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MSP MCU Programmer and Debugger

The MSP-FET is a powerful emulation development tool – often called a debug probe – that lets users quickly

begin application development on MSP low-power microcontrollers (MCU). Creating MCU software usually

requires downloading the resulting binary program to the MSP device for validation and debugging. The MSP-

FET provides a debug communication pathway between a host computer and the target MSP. Furthermore, the

MSP-FET also provides a backchannel UART connection between the computer's USB interface and the MSP

UART. This affords the MSP programmer a convenient method for communicating serially between the MSP and

a terminal running on the computer.

MSP-GANG Production Programmer

The MSP Gang Programmer can program up to eight identical MSP430 or MSP432 flash or FRAM devices at

the same time. The MSP Gang Programmer connects to a host PC using a standard RS-232 or USB connection

and provides flexible programming options that allow the user to fully customize the process. The MSP Gang

Programmer is provided with an expansion board, called the Gang Splitter, that implements the interconnections

between the MSP Gang Programmer and multiple target devices.

11.4 Documentation Support

The following documents describe the MSP430FR2422 microcontrollers. Copies of these documents are

available on the Internet at www.ti.com.

Receiving Notification of Document Updates

To receive notification of documentation updates—including silicon errata—go to the product folder for your

device on ti.com (for example, MSP430FR2422). In the upper right corner, click the "Alert me" button. This

registers you to receive a weekly digest of product information that has changed (if any). For change details,

check the revision history of any revised document.

Errata

MSP430FR2422 Device Erratasheet

Describes the known exceptions to the functional specifications for all silicon revisions of this device.

User's Guides

MSP430FR4xx and MSP430FR2xx Family User's Guide

Detailed description of all modules and peripherals available in this device family.

MSP430 FRAM Device Bootloader (BSL) User's Guide

The BSL can program memory during MSP430 MCU project development and updates. The BSL can be

activated by a utility that sends commands using a serial protocol. The BSL enables the user to control the

activity of the MSP430 device and to exchange data using a personal computer or other device.

MSP430 Programming With the JTAG Interface

This document describes the functions that are required to erase, program, and verify the memory module of the

MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,

it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This

document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG

interface, which is also referred to as Spy-Bi-Wire (SBW).

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MSP430 Hardware Tools User's Guide

This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the

program development tool for the MSP430 ultra-low-power microcontroller.

Application Reports

MSP430 32-kHz Crystal Oscillators

Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal

oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the

correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout

are given. The document also contains detailed information on the possible oscillator tests to ensure stable

oscillator operation in mass production.

MSP430 System-Level ESD Considerations

System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages

and the need for designing cost-effective and ultra-low-power components. This application report addresses

different ESD topics to help board designers and OEMs understand and design robust system-level designs. A

few real-world system-level ESD protection design examples and their results are also discussed.

11.5 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.6 Trademarks

MSP430^™, MSP430Ware^™, Code Composer Studio^™, E2E^™, EnergyTrace^™, ULP Advisor^™, TI E2E^™are

trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

11.7 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.8 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as

defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled

product restricted by other applicable national regulations, received from disclosing party under nondisclosure

obligations (if any), or any direct product of such technology, to any destination to which such export or re-export

is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

11.9 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, see the left-hand navigation.

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PACKAGE OUTLINE

VQFN - 1 mm max height

RHL0020A

PLASTIC QUAD FLATPACK- NO LEAD

A

3.6

3.4

B

PIN 1 INDEX AREA

4.6

4.4

C

1 MAX

SEATING PLANE

0.08

C

2.05 0.1

2X 1.5

SYMM

0.5

0.3

20X

(0.2) TYP

10

11

14X 0.5

9

12

SYMM

2X

3.5

21

3.05 0.1

19

2

0.29

20X

0.19

0.1

0.05

20

4X (0.2)

2X (0.55)

1

PIN 1 ID

(OPTIONAL)

C

A B

C

4219071 / A 06/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RHL0020A

PLASTIC QUAD FLATPACK- NO LEAD

(3.3)

(2.05)

2X (1.5)

SYMM

1

20

2X (0.4)

20X (0.6)

19

2

20X (0.24)

14X (0.5)

SYMM

21

(3.05) (4.3)

6X (0.525)

2X (0.75)

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

9

12

(R0.05) TYP

(Ø0.2) VIA

TYP)

10

11

4X (0.2)

4X

(0.775)

2X (0.55)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 18X

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

0.07 MIN

ALL AROUND

EXPOSED METAL

METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219071 / A 06/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271)

.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to theri

locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RHL0020A

PLASTIC QUAD FLATPACK- NO LEAD

(3.3)

2X (1.5)

(0.55)

TYP

(0.56)

TYP

1

20

SOLDER MASK EDGE

TYP

20X (0.6)

2

19

20X (0.24)

14X (0.5)

SYMM

(1.05)

TYP

(4.3)

21

6X

(0.85)

(R0.05) TYP

METAL

TYP

9

12

2X

(0.775)

2X (0.25)

11

10

4X (0.2)

6X (0.92)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1mm THICK STENCIL

EXPOSED PAD

75% PRINTED COVERAGE BY AREA

SCALE: 20X

4219071 / A 06/2017

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations..

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	MSP430FR2422IRHLR
厂家：	TEXAS INSTRUMENTS
描述：	具有 8KB FRAM、2KB SRAM、10 位 ADC、UART/SPI/I2C 和计时器的 16MHz MCU \| RHL \| 20 \| -40 to 85 静态存储器外围集成电路
文件：	总86页 (文件大小：2172K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSP430FR2422IRHLR [TI]

相关型号：

MSP430FR2422IRHLT

MSP430FR2433

MSP430FR2433IRGER

MSP430FR2433IRGET

MSP430FR2433IYQWR

MSP430FR2433IYQWT

MSP430FR2475

MSP430FR2475TPT

MSP430FR2475TPTR

MSP430FR2475TRHAR

MSP430FR2475TRHAT

MSP430FR2475TRHBR