MSP430F6777AIPEUR [TI]

具有 7 个 Σ-Δ ADC、LCD、实时时钟、AES、256KB 闪存和 32KB RAM 的多相位计量 SoC | PEU | 128 | -40 to 85;
MSP430F6777AIPEUR
型号: MSP430F6777AIPEUR
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

具有 7 个 Σ-Δ ADC、LCD、实时时钟、AES、256KB 闪存和 32KB RAM 的多相位计量 SoC | PEU | 128 | -40 to 85

时钟 CD 闪存
文件: 总181页 (文件大小:2550K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Support &  
Community  
Product  
Folder  
Order  
Now  
Tools &  
Software  
Technical  
Documents  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
MSP430F677xA, MSP430F676xA, MSP430F674xA Polyphase Metering SoCs  
1 Device Overview  
1.1 Features  
1
• Accuracy < 0.1% Over 2000:1 Dynamic Range for  
Phase Current  
• Meets or Exceeds ANSI C12.20 and IEC 62053  
Standards  
• Support for Multiple Sensors Such as Current  
Transformers, Rogowski Coils, or Shunts  
• Highly Integrated Digital  
– Three-Channel Direct Memory Access (DMA)  
Controller  
– Integrated Hardware AES-128 Module for  
Encryption  
– 16-Bit Cyclic Redundancy Check (CRC) Module  
• Power Measurement for up to Three Phases Plus  
Neutral  
– Four 16-Bit Timers With Nine Total  
Capture/Compare Registers  
• Dedicated Pulse Output Pins for Active and  
Reactive Energy for Calibration  
• Six Enhanced Universal Serial Communication  
Interfaces (eUSCIs)  
• 4-Quadrant Measurement per Phase or  
Cumulative  
• Exact Phase-Angle Measurements  
• Digital Phase Correction for Current Transformers  
• Temperature-Compensated Energy Measurements  
– eUSCI_A0, eUSCI_A1, eUSCI_A2, and  
eUSCI_A3 Support UART, IrDA, and SPI  
– eUSCI_B0, eUSCI_B1 Support SPI and I2C  
• Ultra-Low Power Consumption  
– Multiple Low-Power Modes  
• 40-Hz to 70-Hz Line Frequency Range Using  
Single Calibration  
– Standby Mode (LPM3): 2.1 µA at 3 V,  
Wake up in Less Than 5 µs  
• Flexible Power Supply Options With Automatic  
Switching  
• Display Operates at Very Low Power During AC  
Mains Failure: 3 µA in LPM3  
• LCD Driver With Contrast Control for up to 320  
Segments  
• Password-Protected Real-Time Clock (RTC) With  
Tamper Detection, Crystal Offset Calibration, and  
Temperature Compensation  
– RTC Mode (LPM3.5): 0.34 µA at 3 V  
– Shutdown Mode (LPM4.5): 0.18 µA at 3 V  
• CPU  
– High-Performance 25-MHz CPU With 32-Bit  
Multiplier  
– Wide Input Supply Voltage Range:  
3.6 V Down to 1.8 V  
• Memory  
– Up to 512KB of Single-Cycle Flash  
– Up to 32KB of RAM With Single-Cycle Access  
• Package Options  
– 128-Pin LQFP (PEU) Package With 90 I/O Pins  
– 100-Pin LQFP (PZ) Package With 62 I/O Pins  
• Development Tools (Also See Tools and Software)  
• Integrated Security Modules to Support  
AntiTamper and Encryption  
• Multiple Communication Interfaces for Smart Meter  
Implementations  
• High-Performance Analog  
– Up to Seven Independent 24-Bit Sigma-Delta  
ADCs With Differential Inputs and Variable Gain  
– 10-Bit 200-ksps SAR ADC With Six External  
Channels and Two Internal Channels, Including  
Supply and Temperature Sensor Measurement  
– Energy Measurement Design Center for  
MSP430 MCUs with 24-Bit Sigma-Delta ADCs  
(MSP-EM-DESIGN-CENTER)  
– Three-Phase Electronic Watt-Hour EVM for  
Metering (EVM430-F6779)  
– Target Development Board  
(MSPTS430PEU128)  
1.2 Applications  
3-Phase Electronic Watt-Hour Meters  
Utility Metering  
Energy Monitoring  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
1.3 Description  
MSP430F67xxA polyphase metering SoCs are powerful highly integrated solutions that offer high  
accuracy and low system cost with few external components. The MSP430F67xxA microcontroller (MCU)  
family is part of the MSP430™ Metrology and Monitoring MCU portfolio targeting energy measurement  
and power monitoring applications including smart grid and building automation.  
MSP430F67xxA MCUs feature up to seven independent 24-bit sigma-delta ADCs that can provide better  
than 0.1% accuracy. MSP430F67xxA devices integrate a high-performance MSP430 CPU with a 32-bit  
multiplier to perform all metrology calculations. Family members include up to 512KB of flash, 32KB of  
RAM, and an LCD controller with support for up to 320 segments.  
The ultra-low power consumption of the MSP430F67xxA enables the system power supply to be  
minimized to reduce overall cost. Low standby power requires minimal energy storage, and critical data  
can be retained longer in case of a mains power failure.  
The MSP430F67xxA MCU family is supported by an extensive software and hardware ecosystem. The  
Texas Instruments Energy Measurement Design Center (EMDC) can simplify development and accelerate  
designs by quickly configuring the Energy Measurement software library, automatically generating code,  
performing calibration, and viewing results. MSP430F67xxA MCUs execute the Energy Measurement  
software library, which calculates all relevant energy and power results. Development kits include the  
EVM430-F6779 three-phase electricity meter evaluation module and the MSP-TS430PEU128 128-pin  
target development board. Industry standard development tools and hardware platforms are available to  
speed development of meters that meet all of the ANSI and IEC standards globally.  
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.  
Device Information(1)  
PART NUMBER  
MSP430F6779AIPEU  
MSP430F6779AIPZ  
PACKAGE  
LQFP (128)  
LQFP (100)  
BODY SIZE(2)  
20 mm × 14 mm  
14 mm × 14 mm  
(1) For the most current part, package, and ordering information, see the Package Option Addendum in  
Section 9, or see the TI website at www.ti.com.  
(2) The dimensions shown here are approximations. For the package dimensions with tolerances, see the  
Mechanical Data in Section 9.  
2
Device Overview  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
1.4 Application Diagram  
Figure 1-1 shows a typical application diagram.  
TOTAL  
kWh  
Load  
Sx, COMx  
Phase C  
VCC  
RST  
VSS  
Phase A  
MSP430F677xA  
R33  
Px.x  
LCDCAP  
Phase B  
Neutral  
+
Status LEDs  
ΣΔ Modulator  
CT  
CT  
CT  
CT  
IA  
IB  
IC  
+
Px.y  
ΣΔ Modulator  
Pulse LEDs  
+
ΣΔ Modulator  
XIN  
+
32768 Hz  
ΣΔ Modulator  
Ineutral  
XOUT  
USCIA0  
USCIA1  
USCIA2  
USCIA3  
USCIB0  
USCIB1  
VA  
AFE  
+
UART or SPI  
UART or SPI  
UART or SPI  
UART or SPI  
I2C or SPI  
ΣΔ Modulator  
VB  
+
ΣΔ Modulator  
VC  
VN  
+
ΣΔ Modulator  
I2C or SPI  
Vref  
Neutral  
Phase B  
Phase A  
Phase C  
Source From Utility  
Copyright © 2016, Texas Instruments Incorporated  
Figure 1-1. 3-Phase 4-Wire Star Connection Using MSP430F677xA  
Copyright © 2014–2018, Texas Instruments Incorporated  
Device Overview  
3
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table of Contents  
1
Device Overview ......................................... 1  
1.1 Features .............................................. 1  
1.2 Applications........................................... 1  
1.3 Description............................................ 2  
1.4 Application Diagram .................................. 3  
Revision History ......................................... 5  
Device Comparison ..................................... 6  
3.1 Related Products ..................................... 7  
Terminal Configuration and Functions.............. 8  
4.1 Pin Diagrams ......................................... 8  
4.2 Signal Descriptions.................................. 12  
4.3 Pin Multiplexing ..................................... 25  
4.4 Connection of Unused Pins ......................... 25  
Specifications ........................................... 26  
5.1 Absolute Maximum Ratings......................... 26  
5.2 ESD Ratings ........................................ 26  
5.3 Recommended Operating Conditions............... 26  
5.17 ADC10_A............................................ 60  
5.18 REF.................................................. 62  
5.19 Comparator_B....................................... 63  
5.20 Flash ................................................ 64  
5.21 Emulation and Debug ............................... 64  
Detailed Description ................................... 65  
6.1 Overview ............................................ 65  
6.2 Functional Block Diagrams.......................... 66  
6.3 CPU (Link to User's Guide) ......................... 67  
6.4 Instruction Set....................................... 68  
6.5 Operating Modes.................................... 69  
6.6 Interrupt Vector Addresses.......................... 70  
6.7 Special Function Registers (SFRs) ................. 71  
6.8 Bootloader (BSL).................................... 72  
6.9 JTAG Operation ..................................... 73  
6.10 Memory.............................................. 74  
6.11 Peripherals .......................................... 77  
6.12 Input/Output Diagrams............................. 103  
6.13 Device Descriptors (TLV) .......................... 158  
6.14 Identification........................................ 161  
Applications, Implementation, and Layout ...... 162  
Device and Documentation Support.............. 163  
8.1 Getting Started and Next Steps ................... 163  
8.2 Device Nomenclature.............................. 163  
8.3 Tools and Software ................................ 165  
8.4 Documentation Support............................ 167  
8.5 Related Links ...................................... 169  
8.6 Community Resources............................. 169  
8.7 Trademarks ........................................ 169  
8.8 Electrostatic Discharge Caution ................... 169  
8.9 Glossary............................................ 169  
2
3
6
4
5
5.4  
5.5  
5.6  
Active Mode Supply Current Into VCC Excluding  
External Current..................................... 28  
Low-Power Mode Supply Currents (Into VCC  
)
Excluding External Current.......................... 29  
Low-Power Mode With LCD Supply Currents (Into  
7
8
VCC) Excluding External Current.................... 30  
5.7 Thermal Resistance Characteristics ................ 31  
5.8 Timing and Switching Characteristics............... 32  
5.9 Digital I/Os........................................... 36  
5.10 Power-Management Module (PMM) ................ 40  
5.11 Auxiliary Supplies ................................... 42  
5.12 Timer_A ............................................. 45  
5.13 eUSCI ............................................... 45  
5.14 RTC Tamper Detect Pin ............................ 51  
5.15 LCD_C .............................................. 52  
5.16 SD24_B ............................................. 54  
9
Mechanical, Packaging, and Orderable  
Information............................................. 170  
4
Table of Contents  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
2 Revision History  
Changes from May 29, 2014 to September 28, 2018  
Page  
Updated Section 1.1, Features ..................................................................................................... 1  
Updated Section 1.3, Description .................................................................................................. 2  
Added Section 3.1, Related Products ............................................................................................. 7  
Corrected the port number (P4.2) on pin 61 in Figure 4-2, 100-Pin PZ Package (Top View) ............................ 10  
Added note to P1.3/ADC10CLK/A3 (pin 8) in Table 4-3, Terminal Functions – PEU Package........................... 12  
Added typical conditions statements at the beginning of Section 5, Specifications ........................................ 26  
Added SD24_B input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, and  
added SD24_B input pin limits in "Diode current at pins" parameter in Section 5.1, Absolute Maximum Ratings..... 26  
Added Section 5.2, ESD Ratings.................................................................................................. 26  
Added Section 5.7, Thermal Resistance Characteristics ...................................................................... 31  
Updated notes (1) and (2) and added note (3) in Table 5-1, Wake-up Times From Low-Power Modes and Reset .. 32  
Changed the TYP value of the CL,eff parameter with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF  
in Table 5-2, Crystal Oscillator, XT1, Low-Frequency Mode .................................................................. 33  
Corrected bit name in Test Conditions of RCHARGE parameter (changed CHCx to AUXCHCx) in Table 5-25,  
Auxiliary Supplies, Charge Limiting Resistor .................................................................................... 44  
Replaced fFrame parameter with fLCD, fFRAME,4mux, and fFRAME,8mux parameters in Table 5-37, LCD_C, Operating  
Conditions ............................................................................................................................ 52  
On the VID,FS parameter in Table 5-39, SD24_B Power Supply and Recommended Operating Conditions:  
Changed the MIN value from "VREF/GAIN" to "–VREF/GAIN"; Removed "Unipolar mode" test condition (mode is  
not supported) ....................................................................................................................... 54  
Removed ADC10DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Table 5-  
48, 10-Bit ADC, Switching Characteristics, because ADC10CLK is after division.......................................... 60  
Changed Test Conditions for all parameters in Table 5-49, 10-Bit ADC Linearity Parameters: Removed "VREF–";  
Changed from "(VeREF+ – VeREF–)min (VeREF+ – VeREF–)" to "1.4 V (VeREF+ – VeREF–)"; Changed from "CVREF+  
=
20 pF" to "CVeREF+ = 20 pF"; Added "CVeREF+ = 20 pF" to EI; Added "ADC10SREFx = 11b" to ET and EG .............. 61  
Changed from "VREF–/VeREF–" to "VeREF–" in Test Conditions for VeREF+, VeREF–, and (VeREF+ – VeREF–) parameters  
in Table 5-50, 10-Bit ADC, External Reference ................................................................................. 61  
Changed the MIN value of AVCC(min) with Test Conditions of "REFVSEL = {0} for 1.5 V" from 2.2 V to 1.8 V in  
Table 5-51, REF Built-In Reference .............................................................................................. 62  
Changed the MAX value of the tEN_CMP parameter with Test Conditions of "CBPWRMD = 10" from 50 µs to  
100 µs in Table 5-52, Comparator_B............................................................................................. 63  
Corrected the name of the RTC module (changed from RTC_CE to RTC_C) in Figure 6-1, Functional Block  
Diagram – PEU Package........................................................................................................... 66  
Corrected the name of the RTC module (changed from RTC_CE to RTC_C) in Figure 6-2, Functional Block  
Diagram – PZ Package............................................................................................................. 66  
Throughout document, changed all instances of "bootstrap loader" to "bootloader"....................................... 72  
Corrected spelling of NMIIFG in Table 6-13, System Module Interrupt Vector Registers ................................. 80  
Deleted mention of counter mode in Section 6.11.22, Real-Time Clock (RTC_C) (feature is not supported in this  
device) ................................................................................................................................ 85  
Replaced former section Development Tools Support with Section 8.3, Tools and Software .......................... 165  
Changed format and added content to Section 8.4, Documentation Support ............................................. 167  
Copyright © 2014–2018, Texas Instruments Incorporated  
Revision History  
5
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
3 Device Comparison  
Table 3-1 summarizes the available family members.  
Table 3-1. Device Comparison(1)(2)  
eUSCI  
CHANNEL  
A:  
UART, IrDA,  
SPI  
FLASH  
(KB)  
SRAM  
(KB)  
SD24_B  
CONVERTERS  
ADC10_A  
CHANNELS  
Timer_A(3)  
I/Os  
PACKAGE  
CHANNEL  
B:  
SPI, I2C  
DEVICE  
MSP430F6779AIPEU  
MSP430F6778AIPEU  
MSP430F6777AIPEU  
MSP430F6776AIPEU  
MSP430F6775AIPEU  
MSP430F6769AIPEU  
MSP430F6768AIPEU  
MSP430F6767AIPEU  
MSP430F6766AIPEU  
MSP430F6765AIPEU  
MSP430F6749AIPEU  
MSP430F6748AIPEU  
MSP430F6747AIPEU  
MSP430F6746AIPEU  
MSP430F6745AIPEU  
MSP430F6779AIPZ  
MSP430F6778AIPZ  
MSP430F6777AIPZ  
MSP430F6776AIPZ  
MSP430F6775AIPZ  
MSP430F6769AIPZ  
MSP430F6768AIPZ  
MSP430F6767AIPZ  
MSP430F6766AIPZ  
MSP430F6765AIPZ  
MSP430F6749AIPZ  
MSP430F6748AIPZ  
MSP430F6747AIPZ  
MSP430F6746AIPZ  
MSP430F6745AIPZ  
512  
512  
256  
256  
128  
512  
512  
256  
256  
128  
512  
512  
256  
256  
128  
512  
512  
256  
256  
128  
512  
512  
256  
256  
128  
512  
512  
256  
256  
128  
32  
16  
32  
16  
16  
32  
16  
32  
16  
16  
32  
16  
32  
16  
16  
32  
16  
32  
16  
16  
32  
16  
32  
16  
16  
32  
16  
32  
16  
16  
7
7
7
7
7
6
6
6
6
6
4
4
4
4
4
7
7
7
7
7
6
6
6
6
6
4
4
4
4
4
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
6 ext, 2 int  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
3, 2, 2, 2  
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
90  
90  
90  
90  
90  
90  
90  
90  
90  
90  
90  
90  
90  
90  
90  
62  
62  
62  
62  
62  
62  
62  
62  
62  
62  
62  
62  
62  
62  
62  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
128 PEU  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
100 PZ  
(1) For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at  
www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM  
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first  
instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.  
6
Device Comparison  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
3.1 Related Products  
For information about other devices in this family of products or related products, see the following links.  
Products for TI Microcontrollers TI's low-power and high-performance MCUs, with wired and wireless  
connectivity options, are optimized for a broad range of applications.  
Products for MSP430 Ultra-Low-Power Microcontrollers One platform. One ecosystem. Endless  
possibilities. Enabling the connected world with innovations in ultra-low-power  
microcontrollers with advanced peripherals for precise sensing and measurement.  
Companion Products for MSP430F6779A Review products that are frequently purchased or used with  
this product.  
Reference Designs for MSP430F6779A The TI Designs Reference Design Library is a robust reference  
design library that spans analog, embedded processor, and connectivity. Created by TI  
experts to help you jump start your system design, all TI Designs include schematic or block  
diagrams, BOMs, and design files to speed your time to market.  
Copyright © 2014–2018, Texas Instruments Incorporated  
Device Comparison  
7
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
4 Terminal Configuration and Functions  
4.1 Pin Diagrams  
Figure 4-1 shows the pinout for the 128-pin PEU package. Table 4-1 summarizes the differences in the  
pinout among the device variants.  
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103  
XIN  
XOUT  
1
102  
101  
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
RST/NMI/SBWTDIO  
PJ.3/TCK  
2
AUXVCC3  
3
PJ.2/TMS  
RTCCAP1  
4
PJ.1/TDI/TCLK  
PJ.0/TDO  
RTCCAP0  
5
P1.5/SMCLK/CB0/A5  
P1.4/MCLK/CB1/A4  
P1.3/ADC10CLK/A3  
P1.2/ACLK/A2  
6
TEST/SBWTCK  
P2.3/PM_TA1.0  
P2.2/PM_TA0.2  
P2.1/PM_TA0.1/BSL_RX  
P2.0/PM_TA0.0/BSL_TX  
P11.5/TACLK/RTCCLK  
P11.4/CBOUT  
P11.3/TA2.1  
P11.2/TA1.1  
P11.1/TA3.1/CB3  
P11.0/S0  
7
8
9
P1.1/TA2.1/VeREF+/A1  
P1.0/TA1.1/VeREF-/A0  
P2.4/PM_TA2.0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
P2.5/PM_UCB0SOMI/PM_UCB0SCL  
P2.6/PM_UCB0SIMO/PM_UCB0SDA  
P2.7/PM_UCB0CLK  
P3.0/PM_UCA0RXD/PM_UCA0SOMI  
P3.1/PM_UCA0TXD/PM_UCA0SIMO  
P3.2/PM_UCA0CLK  
P3.3/PM_UCA1CLK  
P3.4/PM_UCA1RXD/PM_UCA1SOMI  
P3.5/PM_UCA1TXD/PM_UCA1SIMO  
COM0  
P10.7/S1  
P10.6/S2  
P10.5/S3  
P10.4/S4  
P10.3/S5  
P10.2/S6  
COM1  
P10.1/S7  
P1.6/COM2  
P10.0/S8  
P1.7/COM3  
P9.7/S9  
P5.0/COM4  
P9.6/S10  
P5.1/COM5  
P9.5/S11  
P5.2/COM6  
P9.4/S12  
P5.3/COM7  
P9.3/S13  
LCDCAP/R33  
P9.2/S14  
P5.4/SDCLK/R23  
P9.1/S15  
P5.5/SD0DIO/LCDREF/R13  
P5.6/SD1DIO/R03  
P9.0/S16  
DVSS2  
P5.7/SD2DIO/CB2  
VDSYS2  
P6.0/SD3DIO  
P8.7/S17  
P3.6/PM_UCA2RXD/PM_UCA2SOMI  
P3.7/PM_UCA2TXD/PM_UCA2SIMO  
P4.0/PM_UCA2CLK  
P8.6/S18  
P8.5/S19  
P8.4/S20  
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64  
A. The secondary digital functions on Ports P2, P3, and P4 are fully mappable. This pinout shows only the default  
mapping. See Section 6.11.6 for details.  
B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper  
device operation.  
C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.  
Figure 4-1. 128-Pin PEU Package (Top View)  
8
Terminal Configuration and Functions  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-1. Pinout Differences for PEU Package, F677xA, F676xA, and F674xA  
PIN NAME  
PIN  
NUMBER  
MSP430F677xAIPEU  
P6.1/SD4DIO/S39  
P6.2/SD5DIO/S38  
P6.3/SD6DIO/S37  
VREF  
MSP430F676xAIPEU  
P6.1/SD4DIO/S39  
P6.2/SD5DIO/S38  
P6.3/S37  
VREF  
MSP430F674xAIPEU  
46  
P6.1/S39  
P6.2/S38  
P6.3/S37  
VREF  
NC  
47  
48  
113  
114  
115  
116  
117  
118  
119  
SD4P0  
SD4P0  
SD4N0  
SD4N0  
NC  
SD5P0  
SD5P0  
NC  
SD5N0  
SD5NO  
NC  
SD6P0  
NC  
NC  
SD6N0  
NC  
NC  
Copyright © 2014–2018, Texas Instruments Incorporated  
Terminal Configuration and Functions  
9
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Figure 4-2 shows the pinout for the 100-pin PZ package. Table 4-2 summarizes the differences in the  
pinout among the device variants.  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76  
SD0P0  
SD0N0  
SD1P0  
SD1N0  
SD2P0  
SD2N0  
SD3P0  
SD3N0  
VASYS2  
AVSS2  
VREF  
1
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
VDSYS2  
2
P5.7/SD6DIO/S17  
3
P5.6/SD5DIO/S18  
4
P5.5/SD4DIO/S19  
5
P5.4/SD3DIO/S20  
6
P5.3/SD2DIO/S21  
7
P5.2/SD1DIO/S22  
8
P5.1/SD0DIO/S23  
9
P5.0/SDCLK/S24  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
P4.7/PM_TA3.0/S25  
P4.6/PM_UCB1CLK/S26  
SD4P0  
SD4N0  
SD5P0  
SD5N0  
SD6P0  
SD6N0  
AVSS1  
AVCC  
P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27  
P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28  
P4.3/PM_UCA3CLK/S29  
P4.2/PM_UCA3TXD/PM_UCA3SIMO/S30  
P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31  
P4.0/PM_UCA2CLK/S32  
P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33  
P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34  
P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35  
P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36  
P3.3/PM_UCA1CLK/S37  
VASYS1  
AUXVCC2  
AUXVCC1  
VDSYS1  
DVCC  
P3.2/PM_UCA0CLK/S38  
P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39  
P3.0/PM_UCA0RXD/PM_UCA0SOMI  
DVSS1  
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
A. The secondary digital functions on Ports P2, P3, and P4 are fully mappable. This pinout shows only the default  
mapping. See Section 6.11.6 for details.  
B. The pair of pins VDSYS1 and VDSYS2, VASYS1 and VASYS2 must be connected externally on board for proper  
device operation.  
C. CAUTION: The LCDCAP/R33 pin must be connected to DVSS if it is not used.  
Figure 4-2. 100-Pin PZ Package (Top View)  
10  
Terminal Configuration and Functions  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-2. Pinout Differences for PZ Package, F677xA, F676xA, and F674xA  
PIN NAME  
PIN  
NUMBER  
MSP430F677xAIPZ  
VREF  
MSP430F676xAIPZ  
VREF  
MSP430F674xAIPZ  
11  
12  
13  
14  
15  
16  
17  
72  
73  
74  
VREF  
NC  
SD4P0  
SD4P0  
SD4N0  
SD4N0  
NC  
SD5P0  
SD5P0  
NC  
SD5N0  
SD5NO  
NC  
SD6P0  
NC  
NC  
SD6N0  
NC  
NC  
P5.5/SD4DIO/S19  
P5.6/SD5DIO/S18  
P5.7/SD6DIO/S17  
P5.5/SD4DIO/S19  
P5.6/SD5DIO/S18  
P5.7/S17  
P5.5/S19  
P5.6/S18  
P5.7/S17  
Copyright © 2014–2018, Texas Instruments Incorporated  
Terminal Configuration and Functions  
11  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
4.2 Signal Descriptions  
Table 4-3 describes the signals for devices in the PEU package. See Table 4-4 for the signals in the PZ  
package.  
Table 4-3. Terminal Functions – PEU Package  
TERMINAL  
NO. I/O(1)  
PEU  
DESCRIPTION  
NAME  
XIN  
1
2
3
4
5
I/O Input terminal for crystal oscillator  
I/O Output terminal for crystal oscillator  
XOUT  
AUXVCC3  
RTCCAP1  
RTCCAP0  
Auxiliary power supply AUXVCC3 for backup subsystem  
External time capture pin 1 for RTC_C  
External time capture pin 0 for RTC_C  
General-purpose digital I/O with port interrupt  
SMCLK clock output  
I
I
P1.5/SMCLK/CB0/A5  
P1.4/MCLK/CB1/A4  
6
7
I/O  
I/O  
Comparator_B input CB0  
Analog input A5 for 10-bit ADC  
General-purpose digital I/O with port interrupt  
MCLK clock output  
Comparator_B input CB1  
Analog input A4 for 10-bit ADC  
General-purpose digital I/O with port interrupt  
P1.3/ADC10CLK/A3(2)  
P1.2/ACLK/A2  
8
9
I/O ADC10_A clock output  
Analog input A3 for 10-bit ADC  
General-purpose digital I/O with port interrupt  
I/O ACLK clock output  
Analog input A2 for 10-bit ADC  
General-purpose digital I/O with port interrupt  
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output  
P1.1/TA2.1/VeREF+/A1  
10  
11  
I/O  
Positive terminal for the ADC reference voltage for an external applied reference voltage  
Analog input A1 for 10-bit ADC  
General-purpose digital I/O with port interrupt  
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output  
P1.0/TA1.1/VeREF-/A0  
P2.4/PM_TA2.0  
I/O  
Negative terminal for the ADC reference voltage for an external applied reference voltage  
Analog input A0 for 10-bit ADC  
General-purpose digital I/O with port interrupt and mappable secondary function  
12  
13  
I/O  
Default mapping: Timer TA2 capture CCR0: CCI0A input, compare: Out0 output  
General-purpose digital I/O with port interrupt and mappable secondary function  
I/O Default mapping: eUSCI_B0 SPI slave out master in  
Default mapping: eUSCI_B0 I2C clock  
P2.5/PM_UCB0SOMI/  
PM_UCB0SCL  
General-purpose digital I/O with port interrupt and mappable secondary function  
I/O Default mapping: eUSCI_B0 SPI slave in master out  
Default mapping: eUSCI_B0 I2C data  
P2.6/PM_UCB0SIMO/  
PM_UCB0SDA  
14  
15  
General-purpose digital I/O with port interrupt and mappable secondary function  
P2.7/PM_UCB0CLK  
I/O  
Default mapping: eUSCI_B0 clock input/output  
(1) I = input, O = output  
(2) Before enabling the analog function (A3), pull this pin low by setting the port function to output low or to input with the internal pulldown  
resistor enabled.  
12  
Terminal Configuration and Functions  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-3. Terminal Functions – PEU Package (continued)  
TERMINAL  
NAME  
NO. I/O(1)  
PEU  
DESCRIPTION  
General-purpose digital I/O with mappable secondary function  
P3.0/PM_UCA0RXD/  
PM_UCA0SOMI  
16  
17  
I/O Default mapping: eUSCI_A0 UART receive data  
Default mapping: eUSCI_A0 SPI slave out master in  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A0 UART transmit data  
Default mapping: eUSCI_A0 SPI slave in master out  
P3.1/PM_UCA0TXD/  
PM_UCA0SIMO  
General-purpose digital I/O with mappable secondary function  
P3.2/PM_UCA0CLK  
P3.3/PM_UCA1CLK  
18  
19  
I/O  
Default mapping: eUSCI_A0 clock input/output  
General-purpose digital I/O with mappable secondary function  
I/O  
Default mapping: eUSCI_A1 clock input/output  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A1 UART receive data  
Default mapping: eUSCI_A1 SPI slave out master in  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A1 UART transmit data  
Default mapping: eUSCI_A1 SPI slave in master out  
P3.4/PM_UCA1RXD/  
PM_UCA1SOMI  
20  
21  
P3.5/PM_UCA1TXD/  
PM_UCA1SIMO  
COM0  
COM1  
22  
23  
O
O
LCD common output COM0 for LCD backplane  
LCD common output COM1 for LCD backplane  
General-purpose digital I/O with port interrupt  
LCD common output COM2 for LCD backplane  
General-purpose digital I/O with port interrupt  
LCD common output COM3 for LCD backplane  
General-purpose digital I/O  
P1.6/COM2  
P1.7/COM3  
P5.0/COM4  
P5.1/COM5  
P5.2/COM6  
P5.3/COM7  
24  
25  
26  
27  
28  
29  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
LCD common output COM4 for LCD backplane  
General-purpose digital I/O  
LCD common output COM5 for LCD backplane  
General-purpose digital I/O  
LCD common output COM6 for LCD backplane  
General-purpose digital I/O  
LCD common output COM7 for LCD backplane  
LCD capacitor connection  
LCDCAP/R33  
30  
31  
I/O Input/output port of most positive analog LCD voltage (V1)  
CAUTION: This pin must be connected to DVSS if not used.  
General-purpose digital I/O  
P5.4/SDCLK/R23  
I/O SD24_B bit-stream clock input/output  
Input/Output port of second most positive analog LCD voltage (V2)  
General-purpose digital I/O  
SD24_B converter 0 bit-stream data input/output  
P5.5/SD0DIO/  
LCDREF/R13  
32  
33  
I/O  
External reference voltage input for regulated LCD voltage  
Input/output port of third most positive analog LCD voltage (V3 or V4)  
General-purpose digital I/O  
P5.6/SD1DIO/R03  
I/O SD24_B converter 1 bit-stream data input/output  
Input/output port of lowest analog LCD voltage (V5)  
Copyright © 2014–2018, Texas Instruments Incorporated  
Terminal Configuration and Functions  
13  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-3. Terminal Functions – PEU Package (continued)  
TERMINAL  
NO. I/O(1)  
PEU  
DESCRIPTION  
NAME  
P5.7/SD2DIO/CB2  
P6.0/SD3DIO  
General-purpose digital I/O  
34  
35  
36  
I/O SD24_B converter 2 bit-stream data input/output  
Comparator_B input CB2  
General-purpose digital I/O  
I/O  
SD24_B converter 3 bit-stream data input/output  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A2 UART receive data  
Default mapping: eUSCI_A2 SPI slave out master in  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A2 UART transmit data  
Default mapping: eUSCI_A2 SPI slave in master out  
P3.6/PM_UCA2RXD/  
PM_UCA2SOMI  
P3.7/PM_UCA2TXD/  
PM_UCA2SIMO  
37  
38  
39  
General-purpose digital I/O with mappable secondary function  
P4.0/PM_UCA2CLK  
I/O  
Default mapping: eUSCI_A2 clock input/output  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A3 UART receive data  
Default mapping: eUSCI_A3 SPI slave out master in  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A3 UART transmit data  
Default mapping: eUSCI_A3 SPI slave in master out  
P4.1/PM_UCA3RXD/  
PM_UCA3SOMI  
P4.2/PM_UCA3TXD/  
PM_UCA3SIMO  
40  
41  
42  
General-purpose digital I/O with mappable secondary function  
P4.3/PM_UCA3CLK  
I/O  
Default mapping: eUSCI_A3 clock input/output  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_B1 SPI slave out, master in  
Default mapping: eUSCI_B1 I2C clock  
P4.4/PM_UCB1SOMI/  
PM_UCB1SCL  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_B1 SPI slave in, master out  
Default mapping: eUSCI_B1 I2C data  
P4.5/PM_UCB1SIMO/  
PM_UCB1SDA  
43  
General-purpose digital I/O with mappable secondary function  
P4.6/PM_UCB1CLK  
P4.7/PM_TA3.0  
44  
45  
I/O  
Default mapping: eUSCI_B1 clock input/output  
General-purpose digital I/O with mappable secondary function  
I/O  
Default mapping: Timer TA3 capture CCR0: CCI0A input, compare: Out0 output  
General-purpose digital I/O  
P6.1/SD4DIO/S39  
P6.2/SD5DIO/S38  
P6.3/SD6DIO/S37  
46  
47  
48  
I/O SD24_B converter 4 bit-stream data input/output (not available in F674xA devices)  
LCD segment output S39  
General-purpose digital I/O  
I/O SD24_B converter 5 bit-stream data input/output (not available in F674xA devices)  
LCD segment output S38  
General-purpose digital I/O  
I/O SD24_B converter 6 bit-stream data input/output (not available in F676xA, F674xA devices)  
LCD segment output S37  
General-purpose digital I/O  
I/O  
P6.4/S36  
P6.5/S35  
49  
50  
LCD segment output S36  
General-purpose digital I/O  
I/O  
LCD segment output S35  
14  
Terminal Configuration and Functions  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-3. Terminal Functions – PEU Package (continued)  
TERMINAL  
NAME  
NO. I/O(1)  
PEU  
DESCRIPTION  
General-purpose digital I/O  
LCD segment output S34  
General-purpose digital I/O  
LCD segment output S33  
General-purpose digital I/O  
LCD segment output S32  
General-purpose digital I/O  
LCD segment output S31  
General-purpose digital I/O  
LCD segment output S30  
General-purpose digital I/O  
LCD segment output S29  
General-purpose digital I/O  
LCD segment output S28  
General-purpose digital I/O  
LCD segment output S27  
General-purpose digital I/O  
LCD segment output S26  
General-purpose digital I/O  
LCD segment output S25  
General-purpose digital I/O  
LCD segment output S24  
General-purpose digital I/O  
LCD segment output S23  
General-purpose digital I/O  
LCD segment output S22  
General-purpose digital I/O  
LCD segment output S21  
General-purpose digital I/O  
LCD segment output S20  
General-purpose digital I/O  
LCD segment output S19  
General-purpose digital I/O  
LCD segment output S18  
General-purpose digital I/O  
LCD segment output S17  
Digital power supply for I/Os  
Digital ground supply  
P6.6/S34  
P6.7/S33  
P7.0/S32  
P7.1/S31  
P7.2/S30  
P7.3/S29  
P7.4/S28  
P7.5/S27  
P7.6/S26  
P7.7/S25  
P8.0/S24  
P8.1/S23  
P8.2/S22  
P8.3/S21  
P8.4/S20  
P8.5/S19  
P8.6/S18  
P8.7/S17  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
VDSYS2(3)  
DVSS2  
69  
70  
General-purpose digital I/O  
LCD segment output S16  
General-purpose digital I/O  
LCD segment output S15  
General-purpose digital I/O  
LCD segment output S14  
P9.0/S16  
P9.1/S15  
P9.2/S14  
71  
72  
73  
I/O  
I/O  
I/O  
(3) The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.  
Terminal Configuration and Functions  
Copyright © 2014–2018, Texas Instruments Incorporated  
15  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-3. Terminal Functions – PEU Package (continued)  
TERMINAL  
NO. I/O(1)  
PEU  
DESCRIPTION  
NAME  
General-purpose digital I/O  
LCD segment output S13  
General-purpose digital I/O  
LCD segment output S12  
General-purpose digital I/O  
LCD segment output S11  
General-purpose digital I/O  
LCD segment output S10  
General-purpose digital I/O  
LCD segment output S9  
General-purpose digital I/O  
LCD segment output S8  
General-purpose digital I/O  
LCD segment output S7  
General-purpose digital I/O  
LCD segment output S6  
General-purpose digital I/O  
LCD segment output S5  
General-purpose digital I/O  
LCD segment output S4  
General-purpose digital I/O  
LCD segment output S3  
General-purpose digital I/O  
LCD segment output S2  
General-purpose digital I/O  
LCD segment output S1  
General-purpose digital I/O  
LCD segment output S0  
General-purpose digital I/O  
P9.3/S13  
P9.4/S12  
P9.5/S11  
P9.6/S10  
P9.7/S9  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
P10.0/S8  
P10.1/S7  
P10.2/S6  
P10.3/S5  
P10.4/S4  
P10.5/S3  
P10.6/S2  
P10.7/S1  
P11.0/S0  
P11.1/TA3.1/CB3  
88  
I/O Timer TA3 capture CCR1: CCI1A input, compare: Out1 output  
Comparator_B input CB3  
General-purpose digital I/O  
P11.2/TA1.1  
P11.3/TA2.1  
P11.4/CBOUT  
89  
90  
91  
I/O  
Timer TA1 capture CCR1: CCI1A input, compare: Out1 output  
General-purpose digital I/O  
I/O  
Timer TA2 capture CCR1: CCI1A input, compare: Out1 output  
General-purpose digital I/O  
I/O  
Comparator_B output  
General-purpose digital I/O  
P11.5/TACLK/RTCCLK  
P2.0/PM_TA0.0/BSL_TX  
92  
93  
I/O Timer clock input TACLK for TA0, TA1, TA2, TA3  
RTCCLK clock output  
General-purpose digital I/O with port interrupt and mappable secondary function  
I/O Default mapping: Timer TA0 capture CCR0: CCI0A input, compare: Out0 output  
Bootloader: Data transmit  
16  
Terminal Configuration and Functions  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-3. Terminal Functions – PEU Package (continued)  
TERMINAL  
NAME  
NO. I/O(1)  
PEU  
DESCRIPTION  
General-purpose digital I/O with port interrupt and mappable secondary function  
P2.1/PM_TA0.1/BSL_RX  
94  
I/O Default mapping: Timer TA0 capture CCR1: CCI1A input, compare: Out1 output  
Bootloader: Data receive  
General-purpose digital I/O with port interrupt and mappable secondary function  
P2.2/PM_TA0.2  
P2.3/PM_TA1.0  
TEST/SBWTCK  
PJ.0/TDO  
95  
96  
97  
98  
I/O  
Default mapping: Timer TA0 capture CCR2: CCI2A input, compare: Out2 output  
General-purpose digital I/O port interrupt and with mappable secondary function  
I/O  
Default mapping: Timer TA1 capture CCR0: CCI0A input, compare: Out0 output  
Test mode pin – select digital I/O on JTAG pins  
I
Spy-Bi-Wire input clock  
General-purpose digital I/O  
I/O  
Test data output  
General-purpose digital I/O  
I/O Test data input  
PJ.1/TDI/TCLK  
99  
Test clock input  
General-purpose digital I/O  
PJ.2/TMS  
PJ.3/TCK  
100  
101  
I/O  
Test mode select  
General-purpose digital I/O  
I/O  
Test clock  
Reset input, active-low(4)  
I/O Nonmaskable interrupt input  
Spy-By-Wire data input/output  
RST/NMI/SBWTDIO  
102  
SD0P0  
SD0N0  
SD1P0  
SD1N0  
SD2P0  
SD2N0  
SD3P0  
SD3N0  
103  
104  
105  
106  
107  
108  
109  
110  
I
I
I
I
I
I
I
I
SD24_B positive analog input for converter 0(5)  
SD24_B negative analog input for converter 0(5)  
SD24_B positive analog input for converter 1(5)  
SD24_B negative analog input for converter 1(5)  
SD24_B positive analog input for converter 2(5)  
SD24_B negative analog input for converter 2(5)  
SD24_B positive analog input for converter 3(5)  
SD24_B negative analog input for converter 3(4)  
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended  
VASYS2  
111  
capacitor value of CVSYS  
.
AVSS2  
VREF  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
Analog ground supply  
I
I
I
I
I
I
I
SD24_B external reference voltage  
SD4P0  
SD4N0  
SD5P0  
SD5N0  
SD6P0  
SD6N0  
AVSS1  
AVCC  
SD24_B positive analog input for converter 4(5) (not available on F674xA devices)  
SD24_B negative analog input for converter 4(5) (not available on F674xA devices)  
SD24_B positive analog input for converter 5(5) (not available on F674xA devices)  
SD24_B negative analog input for converter 5(5) (not available on F674xA devices)  
SD24_B positive analog input for converter 6(5) (not available on F676xA, F674xA devices)  
SD24_B negative analog input for converter 6(5) (not available on F676xA, F674xA devices)  
Analog ground supply  
Analog power supply  
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended  
VASYS1  
122  
123  
capacitor value of CVSYS  
.
AUXVCC2  
Auxiliary power supply AUXVCC2  
(4) When this pin is configured as reset, the internal pullup resistor is enabled by default.  
(5) TI recommends shorting unused analog input pairs and connecting them to analog ground.  
Copyright © 2014–2018, Texas Instruments Incorporated  
Terminal Configuration and Functions  
17  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-3. Terminal Functions – PEU Package (continued)  
TERMINAL  
NO. I/O(1)  
PEU  
DESCRIPTION  
NAME  
AUXVCC1  
VDSYS1(3)  
124  
Auxiliary power supply AUXVCC1  
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended  
125  
capacitor value of CVSYS  
Digital power supply  
Digital ground supply  
.
DVCC  
126  
127  
128  
DVSS1  
VCORE(6)  
Regulated core power supply (internal use only, no external current loading)  
(6) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended  
capacitor value, CVCORE  
.
18  
Terminal Configuration and Functions  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-4 describes the signals for devices in the PZ package. See Table 4-3 for the signals in the PEU  
package.  
Table 4-4. Terminal Functions – PZ Package  
TERMINAL  
NO. I/O(1)  
PZ  
DESCRIPTION  
SD24_B positive analog input for converter 0(2)  
SD24_B negative analog input for converter 0(2)  
SD24_B positive analog input for converter 1(2)  
SD24_B negative analog input for converter 1(2)  
SD24_B positive analog input for converter 2(2)  
SD24_B negative analog input for converter 2(2)  
SD24_B positive analog input for converter 3(2)  
NAME  
SD0P0  
SD0N0  
SD1P0  
SD1N0  
SD2P0  
SD2N0  
SD3P0  
SD3N0  
1
2
3
4
5
6
7
8
I
I
I
I
I
I
I
I
SD24_B negative analog input for converter 3(2)  
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended  
VASYS2  
9
capacitor value of CVSYS  
.
AVSS2  
VREF  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Analog ground supply  
I
I
I
I
I
I
I
SD24_B external reference voltage  
SD4P0  
SD4N0  
SD5P0  
SD5N0  
SD6P0  
SD6N0  
AVSS1  
AVCC  
SD24_B positive analog input for converter 4(2) (not available on F674x devices)  
SD24_B negative analog input for converter 4(2) (not available on F674xA devices)  
SD24_B positive analog input for converter 5(2) (not available on F674xA devices)  
SD24_B negative analog input for converter 5(2) (not available on F674xA devices)  
SD24_B positive analog input for converter 6(2) (not available on F676xA, F674xA devices)  
SD24_B negative analog input for converter 6(2) (not available on F676xA, F674xA devices)  
Analog ground supply  
Analog power supply  
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect recommended  
capacitor value of CVSYS  
VASYS1  
20  
AUXVCC2  
AUXVCC1  
21  
22  
Auxiliary power supply AUXVCC2  
Auxiliary power supply AUXVCC1  
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect recommended  
(3)  
VDSYS1  
23  
capacitor value of CVSYS  
Digital power supply  
Digital ground supply  
.
DVCC  
DVSS1  
VCORE  
XIN  
24  
25  
26  
27  
28  
29  
30  
31  
(4)  
Regulated core power supply (internal use only, no external current loading)  
I/O Input terminal for crystal oscillator  
XOUT  
I/O Output terminal for crystal oscillator  
AUXVCC3  
RTCCAP1  
RTCCAP0  
Auxiliary power supply AUXVCC3 for backup subsystem  
I
I
External time capture pin 1 for RTC_C  
External time capture pin 0 for RTC_C  
General-purpose digital I/O with port interrupt  
SMCLK clock output  
P1.5/SMCLK/CB0/A5  
32  
I/O  
Comparator_B input CB0  
Analog input A5 for 10-bit ADC  
(1) I = input, O = output  
(2) TI recommends shorting unused analog input pairs and connecting them to analog ground.  
(3) The pins VDSYS1 and VDSYS2 must be connected externally on board for proper device operation.  
(4) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended  
capacitor value, CVCORE  
.
Copyright © 2014–2018, Texas Instruments Incorporated  
Terminal Configuration and Functions  
19  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-4. Terminal Functions – PZ Package (continued)  
TERMINAL  
NO. I/O(1)  
PZ  
DESCRIPTION  
NAME  
General-purpose digital I/O with port interrupt  
MCLK clock output  
P1.4/MCLK/CB1/A4  
33  
I/O  
Comparator_B input CB1  
Analog input A4 for 10-bit ADC  
General-purpose digital I/O with port interrupt  
P1.3/ADC10CLK/A3  
P1.2/ACLK/A2  
34  
35  
I/O ADC10_A clock output  
Analog input A3 for 10-bit ADC  
General-purpose digital I/O with port interrupt  
I/O ACLK clock output  
Analog input A2 for 10-bit ADC  
General-purpose digital I/O with port interrupt  
Timer TA2 CCR1 capture: CCI1A input, compare: Out1 output  
I/O Comparator_B Output  
P1.1/TA2.1/CBOUT/  
VeREF+/A1  
36  
Positive terminal for the ADC reference voltage for an external applied reference voltage  
Analog input A1 for 10-bit ADC  
General-purpose digital I/O with port interrupt  
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output  
Negative terminal for the ADC reference voltage for an external applied reference voltage  
Analog input A0 for 10-bit ADC  
P1.0/TA1.1/VeREF-/A0  
37  
I/O  
COM0  
COM1  
38  
39  
I/O LCD common output COM0 for LCD backplane  
I/O LCD common output COM1 for LCD backplane  
General-purpose digital I/O with port interrupt  
I/O  
P1.6/COM2  
P1.7/COM3  
40  
41  
LCD common output COM2 for LCD backplane  
General-purpose digital I/O with port interrupt  
I/O  
LCD common output COM3 for LCD backplane  
General-purpose digital I/O with port interrupt and mappable secondary function  
Default Mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output  
P2.0/PM_TA0.0/  
BSL_TX/COM4  
42  
43  
I/O  
Bootloader: Data transmit  
LCD common output COM4 for LCD backplane  
General-purpose digital I/O with port interrupt and mappable secondary function  
Default Mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output  
P2.1/PM_TA0.1/  
BSL_RX/COM5  
I/O  
Bootloader: Data receive  
LCD common output COM5 for LCD backplane  
General-purpose digital I/O with port interrupt and mappable secondary function  
I/O Default Mapping: Timer TA0 CCR0 capture: CCI2A input, compare: Out2 output  
LCD common output COM6 for LCD backplane  
P2.2/PM_TA0.2/COM6  
P2.3/PM_TA1.0/COM7  
LCDCAP/R33  
44  
45  
46  
47  
General-purpose digital I/O with port interrupt and mappable secondary function  
I/O Default Mapping: Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output  
LCD common output COM7 for LCD backplane  
LCD capacitor connection  
I/O Input/output port of most positive analog LCD voltage (V1)  
CAUTION: This pin must be connected to DVSS if not used.  
General-purpose digital I/O with port interrupt and mappable secondary function  
I/O Default Mapping: Timer TA2 CCR0 capture: CCI0A input, compare: Out0 output  
Input/output port of second most positive analog LCD voltage (V2)  
P2.4/PM_TA2.0/R23  
20  
Terminal Configuration and Functions  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-4. Terminal Functions – PZ Package (continued)  
TERMINAL  
NAME  
NO. I/O(1)  
PZ  
DESCRIPTION  
General-purpose digital I/O with port interrupt and mappable secondary function  
Default mapping: eUSCI_B0 SPI slave out, master in  
I/O Default mapping: eUSCI_B0 I2C clock  
P2.5/PM_UCB0SOMI/  
PM_UCB0SCL/LCDREF/  
R13  
48  
49  
External reference voltage input for regulated LCD voltage  
Input/output port of third most positive analog LCD voltage (V3 or V4)  
General-purpose digital I/O with port interrupt and mappable secondary function  
Default mapping: eUSCI_B0 SPI slave in, master out  
Default mapping: eUSCI_B0 I2C data  
P2.6/PM_UCB0SIMO/  
PM_UCB0SDA/R03  
I/O  
Input/output port of lowest analog LCD voltage (V5)  
General-purpose digital I/O with port interrupt and mappable secondary function  
I/O Default mapping: eUSCI_B0 clock input/output  
Comparator_B input CB2  
P2.7/PM_UCB0CLK/CB2  
50  
51  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A0 UART receive data  
Default mapping: eUSCI_A0 SPI slave out, master in  
General-purpose digital I/O with mappable secondary function  
P3.0/PM_UCA0RXD/  
PM_UCA0SOMI  
Default mapping: eUSCI_A0 UART transmit data  
P3.1/PM_UCA0TXD/  
PM_UCA0SIMO/S39  
52  
I/O  
Default mapping: eUSCI_A0 SPI slave in, master out  
LCD segment output S39  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A0 clock input/output  
LCD segment output S38  
P3.2/PM_UCA0CLK/S38  
P3.3/PM_UCA1CLK/S37  
53  
54  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A1 clock input/output  
LCD segment output S37  
General-purpose digital I/O with mappable secondary function  
Default mapping: eUSCI_A1 UART receive data  
I/O  
P3.4/PM_UCA1RXD/  
PM_UCA1SOMI/S36  
55  
56  
57  
Default mapping: eUSCI_A1 SPI slave out, master in  
LCD segment output S36  
General-purpose digital I/O with mappable secondary function  
Default mapping: eUSCI_A1 UART transmit data  
P3.5/PM_UCA1TXD/  
PM_UCA1SIMO/S35  
I/O  
Default mapping: eUSCI_A1 SPI slave in, master out  
LCD segment output S35  
General-purpose digital I/O with mappable secondary function  
Default mapping: eUSCI_A2 UART receive data  
I/O  
P3.6/PM_UCA2RXD/  
PM_UCA2SOMI/S34  
Default mapping: eUSCI_A2 SPI slave out, master in  
LCD segment output S34  
General-purpose digital I/O with mappable secondary function  
Default mapping: eUSCI_A2 UART transmit data  
P3.7/PM_UCA2TXD/  
PM_UCA2SIMO/S33  
58  
59  
I/O  
Default mapping: eUSCI_A2 SPI slave in, master out  
LCD segment output S33  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_A2 clock input/output  
LCD segment output S32  
P4.0/PM_UCA2CLK/S32  
Copyright © 2014–2018, Texas Instruments Incorporated  
Terminal Configuration and Functions  
21  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-4. Terminal Functions – PZ Package (continued)  
TERMINAL  
NO. I/O(1)  
PZ  
DESCRIPTION  
NAME  
General-purpose digital I/O with mappable secondary function  
Default mapping: eUSCI_A3 UART receive data  
Default mapping: eUSCI_A3 SPI slave out, master in  
LCD segment output S31  
P4.1/PM_UCA3RXD/  
PM_UCA3SOMI/S31  
60  
I/O  
I/O  
General-purpose digital I/O with mappable secondary function  
Default mapping: eUSCI_A3 UART transmit data  
Default mapping: eUSCI_A3 SPI slave in, master out  
LCD segment output S30  
P4.2/PM_UCA3TXD/  
PM_UCA3SIMO/S30  
61  
62  
63  
General-purpose digital I/O with mappable secondary function  
P4.3/PM_UCA3CLK/S29  
I/O Default mapping: eUSCI_A3 clock input/output  
LCD segment output S29  
General-purpose digital I/O with mappable secondary function  
Default mapping: eUSCI_B1 SPI slave out, master in  
Default mapping: eUSCI_B1 I2C clock  
P4.4/PM_UCB1SOMI/  
PM_UCB1SCL/S28  
I/O  
LCD segment output S28  
General-purpose digital I/O with mappable secondary function  
Default mapping: eUSCI_B1 SPI slave in, master out  
Default mapping: eUSCI_B1 I2C data  
P4.5/PM_UCB1SIMO/  
PM_UCB1SDA/S27  
64  
I/O  
LCD segment output S27  
General-purpose digital I/O with mappable secondary function  
I/O Default mapping: eUSCI_B1 clock input/output  
LCD segment output S26  
P4.6/PM_UCB1CLK/S26  
P4.7/PM_TA3.0/S25  
P5.0/SDCLK/S24  
65  
66  
67  
68  
69  
70  
71  
General-purpose digital I/O with mappable secondary function  
I/O Default Mapping: Timer TA3 CCR0 capture: CCI0A input, compare: Out0 output  
LCD segment output S25  
General-purpose digital I/O  
I/O SD24_B bit-stream clock input/output  
LCD segment output S24  
General-purpose digital I/O  
P5.1/PM_SD0DIO/S23  
P5.2/PM_SD1DIO/S22  
P5.3/PM_SD2DIO/S21  
P5.4/PM_SD3DIO/S20  
I/O Default mapping: SD24_B converter 0 bit-stream data input/output  
LCD segment output S23  
General-purpose digital I/O  
I/O Default mapping: SD24_B converter 1 bit-stream data input/output  
LCD segment output S22  
General-purpose digital I/O  
I/O Default mapping: SD24_B converter 2 bit-stream data input/output  
LCD segment output S21  
General-purpose digital I/O  
I/O Default mapping: SD24_B converter 3 bit-stream data input/output  
LCD segment output S20  
General-purpose digital I/O  
Default mapping: SD24_B converter 4 bit-stream data input/output (not available on F674xA  
devices)  
P5.5/PM_SD4DIO/S19  
72  
I/O  
LCD segment output S19  
22  
Terminal Configuration and Functions  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-4. Terminal Functions – PZ Package (continued)  
TERMINAL  
NAME  
NO. I/O(1)  
PZ  
DESCRIPTION  
General-purpose digital I/O  
Default mapping: SD24_B converter 5 bit-stream data input/output (not available on F674xA  
devices)  
P5.6/PM_SD5DIO/S18  
73  
74  
I/O  
I/O  
LCD segment output S18  
General-purpose digital I/O  
Default mapping: SD24_B converter 6 bit-stream data input/output (not available on F676xA or  
F674xA devices)  
P5.7/PM_SD6DIO/S17  
LCD segment output S17  
Digital power supply for I/Os  
Digital ground supply  
VDSYS2(3)  
DVSS2  
75  
76  
General-purpose digital I/O  
LCD segment output S16  
General-purpose digital I/O  
LCD segment output S15  
General-purpose digital I/O  
LCD segment output S14  
General-purpose digital I/O  
LCD segment output S13  
General-purpose digital I/O  
LCD segment output S12  
General-purpose digital I/O  
LCD segment output S11  
General-purpose digital I/O  
LCD segment output S10  
General-purpose digital I/O  
LCD segment output S9  
General-purpose digital I/O  
LCD segment output S8  
General-purpose digital I/O  
LCD segment output S7  
General-purpose digital I/O  
LCD segment output S6  
General-purpose digital I/O  
LCD segment output S5  
General-purpose digital I/O  
LCD segment output S4  
General-purpose digital I/O  
LCD segment output S3  
General-purpose digital I/O  
LCD segment output S2  
General-purpose digital I/O  
LCD segment output S1  
General-purpose digital I/O  
LCD segment output S0  
P6.0/S16  
P6.1/S15  
P6.2/S14  
P6.3/S13  
P6.4/S12  
P6.5/S11  
P6.6/S10  
P6.7/S9  
P7.0/S8  
P7.1/S7  
P7.2/S6  
P7.3/S5  
P7.4/S4  
P7.5/S3  
P7.6/S2  
P7.7/S1  
P8.0/S0  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
Copyright © 2014–2018, Texas Instruments Incorporated  
Terminal Configuration and Functions  
23  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 4-4. Terminal Functions – PZ Package (continued)  
TERMINAL  
NO. I/O(1)  
PZ  
DESCRIPTION  
NAME  
General-purpose digital I/O  
Timer clock input TACLK for TA0, TA1, TA2, TA3  
RTCCLK clock output  
P8.1/TACLK/RTCCLK/CB3  
94  
I/O  
Comparator_B input CB3  
Test mode pin – select digital I/O on JTAG pins  
Spy-By-Wire input clock  
TEST/SBWTCK  
PJ.0/TDO  
95  
96  
97  
98  
99  
I
General-purpose digital I/O  
Test data output  
I/O  
I/O  
I/O  
I/O  
General-purpose digital I/O  
Test data input or Test clock input  
General-purpose digital I/O  
Test mode select  
PJ.1/TDI/TCLK  
PJ.2/TMS  
General-purpose digital I/O  
Test clock  
PJ.3/TCK  
Reset input active low(5)  
RST/NMI/SBWTDIO  
100  
I/O Nonmaskable interrupt input  
Spy-By-Wire data input/output  
(5) When this pin is configured as reset, the internal pullup resistor is enabled by default.  
24  
Terminal Configuration and Functions  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
4.3 Pin Multiplexing  
Pin multiplexing for these devices is controlled by both register settings and operating modes (for  
example, if the device is in test mode). For details of the settings for each pin and schematics of the  
multiplexed ports, see Section 6.12.  
4.4 Connection of Unused Pins  
Table 4-5 lists the correct termination of unused pins.  
Table 4-5. Connection of Unused Pins(1)  
PIN  
POTENTIAL  
DVCC  
COMMENT  
AVCC  
AVSS  
DVSS  
Switched to port function, output direction (PxDIR.n = 1). Px.y represents port x and bit y  
of port x (for example, P1.0, P1.1, P2.2, PJ.0, PJ.1)  
Px.y  
XIN  
Open  
DVSS  
Open  
For dedicated XIN pins only. XIN pins with shared GPIO functions should be  
programmed to GPIO and follow Px.y recommendations.  
For dedicated XOUT pins only. XOUT pins with shared GPIO functions should be  
programmed to GPIO and follow Px.y recommendations.  
XOUT  
LCDCAP  
RST/NMI  
DVSS  
DVCC or VCC  
47-kpullup or internal pullup selected with 10-nF (2.2 nF) pulldown(2)  
PJ.0/TDO  
PJ.1/TDI  
PJ.2/TMS  
PJ.3/TCK  
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used,  
these should be switched to port function, output direction (PJDIR.n = 1). When used as  
JTAG pins, these pins should remain open.  
Open  
Open  
TEST  
This pin always has an internal pulldown enabled.  
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.y unused pin connection  
guidelines.  
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG  
mode with TI tools such as FET interfaces or GANG programmers.  
Copyright © 2014–2018, Texas Instruments Incorporated  
Terminal Configuration and Functions  
25  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5 Specifications  
All graphs in this section are for typical conditions, unless otherwise noted.  
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.  
5.1 Absolute Maximum Ratings  
over operating free-air temperature range (unless otherwise noted)(1)  
MIN  
MAX  
UNIT  
Voltage applied at DVCC to DVSS  
Voltage applied to pins(2)  
–0.3  
4.1  
V
All pins except VCORE(3), SD24_B input pins (SDxN0, SDxP0)(4)  
AUXVCC1, AUXVCC2, and AUXVCC3(5)  
,
–0.3  
VCC + 0.3  
V
All pins except SD24_B input pins (SDxN0, SDxP0)  
±2  
2
Diode current at pins  
mA  
SD0N0, SD0P0, SD1N0, SD1P0, SD2N0, SD2P0, SD3N0, SD3P0,  
SD4N0, SD4P0, SD5N0, SD5P0, SD6N0, SD6P0(6)  
Maximum junction temperature, TJ  
95  
°C  
°C  
(7)  
Storage temperature, Tstg  
–55  
105  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating  
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltages referenced to VSS = VDVSS = VAVSS  
.
(3) VCORE is for internal device use only. No external DC loading or voltage should be applied.  
(4) See Table 5-39 for SD24_B specifications.  
(5) See Table 5-18 for AUX specifications.  
(6) A protection diode is connected to VCC for the SD24_B input pins. No protection diode is connected to VSS  
.
(7) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow  
temperatures not higher than classified on the device label on the shipping boxes or reels.  
5.2 ESD Ratings  
VALUE  
±1000  
±250  
UNIT  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)  
V(ESD)  
Electrostatic discharge  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as  
±1000 V may actually have higher performance.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V  
may actually have higher performance.  
5.3 Recommended Operating Conditions  
MIN NOM  
MAX UNIT  
PMMCOREVx = 0  
1.8  
2.0  
2.2  
2.4  
0
3.6  
PMMCOREVx = 0, 1  
PMMCOREVx = 0, 1,3 2  
PMMCOREVx = 0, 1, 2, 3  
3.6  
V
Supply voltage during program execution and flash  
VCC  
(1)(2)  
programming (VAVCC = VDVCC = VCC  
)
3.6  
3.6  
V
VSS  
TA  
Supply voltage VAVSS = VDVSS = VSS  
Operating free-air temperature  
I version  
I version  
–40  
–40  
470  
85  
85  
°C  
°C  
nF  
TJ  
Operating junction temperature  
Recommended capacitor at VCORE  
CVCORE  
CDVCC  
CVCORE  
/
Capacitor ratio of DVCC to VCORE  
10  
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can be  
tolerated during power up and operation.  
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Table 5-14 threshold parameters for  
the exact values and further details.  
26  
Specifications  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Recommended Operating Conditions (continued)  
MIN NOM  
MAX UNIT  
PMMCOREVx = 0,  
1.8 V VCC 3.6 V  
(default condition)  
0
8.0  
PMMCOREVx = 1,  
2 V VCC 3.6 V  
Processor frequency (maximum MCLK frequency)(3) (4)  
(see Figure 5-1)  
0
0
0
12.0  
MHz  
fSYSTEM  
PMMCOREVx = 2,  
2.2 V VCC 3.6 V  
20.0  
25.0  
PMMCOREVx = 3,  
2.4 V VCC 3.6 V  
Maximum load current that can be drawn from DVCC for core and IO  
(ILOAD = ICORE + IIO  
ILOAD, DVCCD  
ILOAD, AUX1D  
ILOAD, AUX2D  
ILOAD, AVCCA  
ILOAD, AUX1A  
20  
20  
20  
10  
5
mA  
mA  
mA  
mA  
mA  
)
Maximum load current that can be drawn from AUXVCC1 for core and IO  
(ILOAD = ICORE + IIO  
)
Maximum load current that can be drawn from AUXVCC2 for core and IO  
(ILOAD = ICORE + IIO  
)
Maximum load current that can be drawn from AVCC for analog modules  
(ILOAD = IModules  
)
Maximum load current that can be drawn from AUXVCC1 for analog modules  
(ILOAD = IModules  
)
Maximum load current that can be drawn from AUXVCC2 for analog modules  
(ILOAD = IModules  
ILOAD, AUX2A  
PINT  
5
mA  
W
)
Internal power dissipation  
VCC x I(DVCC)  
(VCC – VIOH) x IIOH  
VIOL x IIOL  
+
PIO  
I/O power dissipation of the I/O pins powered by DVCC  
Maximum allowed power dissipation, PMAX > PIO + PINT  
W
PMAX  
(TJ – TA) / θJA  
W
(3) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the  
specified maximum frequency.  
(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.  
25  
3
20  
2, 3  
2
12  
8
1, 2  
1, 2, 3  
1
0
0, 1  
0, 1, 2  
0, 1, 2, 3  
0
1.8  
2.0  
2.2  
2.4  
3.6  
Supply Voltage - V  
The numbers within the fields denote the supported PMMCOREVx settings.  
Figure 5-1. Maximum System Frequency  
Copyright © 2014–2018, Texas Instruments Incorporated  
Specifications  
27  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5.4 Active Mode Supply Current Into VCC Excluding External Current  
over recommended operating free-air temperature (unless otherwise noted)(1)(2)(3)  
FREQUENCY (fDCO = fMCLK = fSMCLK  
)
EXECUTION  
MEMORY  
PMMCOREV  
x
PARAMETER  
VCC  
1 MHz  
8 MHz  
12 MHz  
20 MHz  
TYP  
25 MHz  
TYP MAX  
UNIT  
TYP MAX  
TYP MAX  
TYP MAX  
MAX  
0
1
2
3
0
1
2
3
0.32  
0.35  
0.39  
0.41  
0.19  
0.21  
0.23  
0.24  
0.50  
2.08  
2.35  
2.68  
2.83  
1.04  
1.20  
1.38  
1.47  
2.84  
3.50  
3.99  
4.22  
4.76  
(4)  
IAM, Flash  
Flash  
RAM  
3 V  
mA  
mA  
6.61  
6.98  
8.3  
8.67  
11.75  
1.77  
2.04  
2.18  
(5)  
IAM, RAM  
3 V  
3.35  
3.58  
4.44  
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.  
(2) The currents are characterized with a Micro Crystal MS1 V-T1K crystal with a load capacitance of 12.5 pF. The internal and external  
load capacitance are chosen to closely match the required 12.5 pF.  
(3) Characterized with program executing typical data processing.  
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.  
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.  
(4) Active mode supply current when program executes in flash at a nominal supply voltage of 3.0 V.  
(5) Active mode supply current when program executes in RAM at a nominal supply voltage of 3.0 V.  
28  
Specifications  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)  
TEMPERATURE (TA)  
PARAMETER  
VCC  
PMMCOREVx  
–40°C  
TYP  
25°C  
TYP  
85°C  
TYP  
UNIT  
MAX  
MAX  
105  
18  
MAX  
130  
30  
2.2 V  
3 V  
0
3
0
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
70  
81  
75  
87  
86  
100  
12.5  
13.8  
7.8  
8.3  
8.6  
8.6  
8.5  
9.0  
9.3  
9.3  
7.5  
7.9  
8.2  
8.2  
7.4  
7.8  
7.9  
8.0  
1.4  
1.8  
1.2  
ILPM0,1MHz  
Low-power mode 0(3) (4)  
Low-power mode 2(5) (4)  
µA  
µA  
2.2 V  
3 V  
5.9  
6.7  
1.50  
1.65  
1.80  
1.84  
2.0  
2.1  
2.3  
2.3  
1.3  
1.3  
1.4  
1.4  
1.2  
1.2  
1.3  
1.3  
0.7  
1.0  
0.6  
6.5  
7.3  
2.0  
2.2  
2.4  
2.4  
2.5  
2.7  
2.9  
2.9  
1.7  
1.8  
1.9  
1.9  
1.6  
1.7  
1.7  
1.7  
0.9  
1.2  
0.7  
ILPM2  
Low-power mode 3, crystal  
mode(6) (4)  
ILPM3,XT1LF  
ILPM3,XT1LF  
ILPM3,VLO  
ILPM4  
2.2 V  
3 V  
µA  
µA  
µA  
µA  
Low-power mode 3, crystal  
mode(6) (4)  
25  
25.0  
23.0  
Low-power mode 3,  
VLO mode(7) (4)  
3 V  
Low-power mode 4(8) (4)  
3 V  
2.2 V  
3 V  
Low-power mode 3.5, RTC  
active on AUXVCC3(9)  
ILPM3.5  
ILPM4.5  
µA  
µA  
1.5  
1.0  
3.0  
2.0  
Low-power mode 4.5(10)  
3 V  
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.  
(2) The currents are characterized with a Micro Crystal MS1 V-T1K crystal with a load capacitance of 12.5 pF. The internal and external  
load capacitance are chosen to closely match the required 12.5 pF.  
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).  
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz  
(4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)  
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.  
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).  
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting  
= 1-MHz operation, DCO bias generator enabled.  
(6) Current for watchdog timer and RTC clocked by low-frequency clock included. ACLK = low frequency crystal operation (XTS = 0,  
XT1DRIVEx = 0).  
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz  
(7) Current for watchdog timer and RTC clocked by low-frequency clock included. ACLK = VLO.  
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz  
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz  
(9) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC active on AUXVCC3 supply  
(10) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, PMMREGOFF = 1  
Copyright © 2014–2018, Texas Instruments Incorporated  
Specifications  
29  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)  
TEMPERATURE (TA)  
PARAMETER  
VCC  
PMMCOREVx  
–40°C  
TYP  
25°C  
TYP  
85°C  
TYP MAX  
UNIT  
MAX  
MAX  
6.0  
0
1
2
3
0
1
2
3
0
1
2
0
1
2
3
2.5  
2.6  
2.8  
2.8  
2.9  
3.1  
3.2  
3.3  
2.2  
2.3  
2.5  
2.6  
2.8  
2.9  
3.0  
3.1  
3.3  
3.5  
3.5  
3.5  
3.7  
4.0  
4.0  
2.8  
3.0  
3.2  
3.2  
3.4  
3.6  
3.7  
9.1  
9.5  
ILPM3  
LCD,  
ext. bias  
Low-power mode 3 (LPM3)  
current, LCD 4-mux mode,  
external biasing(3) (4)  
3 V  
µA  
9.9  
10.0  
9.7  
25.0  
25.0  
Low-power mode 3 (LPM3)  
current, LCD 4-mux mode,  
internal biasing, charge  
pump disabled(3) (5)  
ILPM3  
LCD,  
int. bias  
10.1  
10.5  
10.5  
8.8  
3 V  
2.2 V  
3 V  
µA  
µA  
µA  
5.5  
9.1  
Low-power mode 3 (LPM3)  
current, LCD 4-mux mode,  
internal biasing, charge  
pump enabled(3) (6)  
9.5  
ILPM3  
LCD,CP  
9.3  
9.7  
10.1  
10.2  
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.  
(2) The currents are characterized with a Micro Crystal MS1 V-T1K crystal with a load capacitance of 12.5 pF. The internal and external  
load capacitance are chosen to closely match the required 12.5 pF.  
(3) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).  
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz  
Current for brownout and high-side supervisor (SVSH) in normal mode included. Low-side supervisor (SVSL) and low-side monitor  
(SVML) disabled. High-side monitor (SVMH) disabled. RAM retention enabled.  
(4) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump  
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)  
Current through external resistors not included (voltage levels are supplied by test equipment).  
Even segments (S0, S2, ...) = 0, and odd segments (S1, S3, ...) = 1. No LCD panel load.  
(5) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump  
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)  
Even segments (S0, S2, ...) = 0, and odd segments (S1, S3, ...) = 1. No LCD panel load.  
(6) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump  
enabled), VLCDx = 1000 (VLCD = 3 V typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)  
Even segments (S0, S2, ...) = 0, and odd segments (S1, S3, ...) = 1. No LCD panel load.  
30  
Specifications  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5.7 Thermal Resistance Characteristics  
THERMAL METRIC(1) (2)  
VALUE  
44.4  
42.9  
10.5  
9.3  
UNIT  
LQFP 128 (PEU)  
LQFP 100 (PZ)  
LQFP 128 (PEU)  
LQFP 100 (PZ)  
LQFP 128 (PEU)  
LQFP 100 (PZ)  
LQFP 128 (PEU)  
LQFP 100 (PZ)  
LQFP 128 (PEU)  
LQFP 100 (PZ)  
LQFP 128 (PEU)  
LQFP 100 (PZ)  
RθJA  
Junction-to-ambient thermal resistance, still air  
°C/W  
RθJC(TOP)  
RθJC(BOTTOM)  
RθJB  
Junction-to-case (top) thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
N/A(3)  
Junction-to-case (bottom) thermal resistance  
Junction-to-board thermal resistance  
N/A  
23.1  
20.6  
0.4  
ΨJT  
Junction-to-package-top thermal characterization parameter  
Junction-to-board thermal characterization parameter  
0.3  
22.8  
20.3  
ΨJB  
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.  
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a  
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these  
EIA/JEDEC standards:  
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)  
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages  
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements  
(3) N/A = not applicable  
Copyright © 2014–2018, Texas Instruments Incorporated  
Specifications  
31  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5.8 Timing and Switching Characteristics  
5.8.1 Reset Timing  
Table 5-1 lists the device wake-up times.  
Table 5-1. Wake-up Times From Low-Power Modes and Reset  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
Wake-up time from LPM2,  
LPM3, or LPM4 to active  
mode(1)  
PMMCOREV = SVSMLRRL = n  
(where n = 0, 1, 2, or 3),  
SVSLFP = 1  
f
MCLK 4.0 MHz  
5
tWAKE-UP-FAST  
µs  
fMCLK < 4.0 MHz  
10  
Wake-up time from LPM2,  
LPM3, or LPM4 to active  
mode(2)(3)  
PMMCOREV = SVSMLRRL = n  
(where n = 0, 1, 2, or 3),  
SVSLFP = 0  
tWAKE-UP-SLOW  
150  
165  
µs  
Wake-up time from LPM4.5  
to active mode(4)  
tWAKE-UP-LPM4.5  
tWAKE-UP-RESET  
2
2
3
3
ms  
ms  
Wake-up time from RST or  
BOR event to active mode(4)  
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance  
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in full performance  
mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in  
the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.  
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the performance  
mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in normal mode (low  
current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode Selection section in the  
Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx Family User's Guide.  
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by the  
performance mode settings as for LPM2, LPM3, and LPM4.  
(4) This value represents the time from the wake-up event to the reset vector execution.  
32  
Specifications  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5.8.2 Clock Specifications  
Table 5-2 lists the characteristics of the crystal oscillator in low-frequency mode.  
Table 5-2. Crystal Oscillator, XT1, Low-Frequency Mode(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
MAX UNIT  
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,  
XT1DRIVEx = 1, TA = 25°C  
0.075  
Differential XT1 oscillator  
crystal current consumption  
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,  
ΔIDVCC.LF  
3 V  
0.170  
0.290  
32768  
µA  
from lowest drive setting, LF XT1DRIVEx = 2, TA = 25°C  
mode  
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,  
XT1DRIVEx = 3, TA = 25°C  
XT1 oscillator crystal  
frequency, LF mode  
fXT1,LF0  
XTS = 0, XT1BYPASS = 0  
Hz  
XT1 oscillator logic-level  
(3)  
fXT1,LF,SW  
square-wave input frequency, XTS = 0, XT1BYPASS = 1(2)  
LF mode  
10 32.768  
50 kHz  
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,  
fXT1,LF = 32768 Hz, CL,eff = 6 pF  
210  
300  
Oscillation allowance for  
LF crystals(4)  
OALF  
kΩ  
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,  
fXT1,LF = 32768 Hz, CL,eff = 12 pF  
XTS = 0, XCAPx = 0(6)  
XTS = 0, XCAPx = 1  
XTS = 0, XCAPx = 2  
XTS = 0, XCAPx = 3  
1
5.5  
Integrated effective load  
capacitance, LF mode(5)  
CL,eff  
pF  
8.5  
12.0  
XTS = 0, Measured at ACLK,  
fXT1,LF = 32768 Hz  
Duty cycle, LF mode  
30%  
10  
70%  
Oscillator fault frequency,  
LF mode(7)  
fFault,LF  
XTS = 0(8)  
10000  
Hz  
ms  
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,  
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF  
1000  
500  
tSTART,LF  
Start-up time, LF mode  
3 V  
fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,  
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF  
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.  
Keep the trace between the device and the crystal as short as possible.  
Design a good ground plane around the oscillator pins.  
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.  
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.  
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.  
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.  
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in  
the Schmitt-trigger Inputs section of this data sheet.  
(3) Maximum frequency of operation of the entire device cannot be exceeded.  
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the  
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following  
guidelines, but should be evaluated based on the actual crystal selected for the application:  
For XT1DRIVEx = 0, CL,eff 6 pF.  
For XT1DRIVEx = 1, 6 pF CL,eff 9 pF.  
For XT1DRIVEx = 2, 6 pF CL,eff 10 pF.  
For XT1DRIVEx = 3, CL,eff 6 pF.  
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).  
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the  
effective load capacitance should always match the specification of the used crystal.  
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.  
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.  
Frequencies in between might set the flag.  
(8) Measured with logic-level input frequency but also applies to operation with crystals.  
Copyright © 2014–2018, Texas Instruments Incorporated  
Specifications  
33  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 5-3 lists the characteristics of the VLO.  
Table 5-3. Internal Very-Low-Power Low-Frequency Oscillator (VLO)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
VLO frequency  
VLO frequency temperature drift  
TEST CONDITIONS  
Measured at ACLK  
VCC  
MIN  
TYP  
9.6  
0.5  
4
MAX UNIT  
15 kHz  
%/°C  
fVLO  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
6
dfVLO/dT  
Measured at ACLK  
Measured at ACLK  
Measured at ACLK  
dfVLO/dVCC VLO frequency supply voltage drift  
Duty cycle  
%/V  
40%  
50%  
60%  
Table 5-4 lists the characteristics of the REFO.  
Table 5-4. Internal Reference, Low-Frequency Oscillator (REFO)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
TYP  
3
MAX UNIT  
µA  
IREFO  
REFO oscillator current consumption TA = 25°C  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
3 V  
REFO frequency calibrated  
Measured at ACLK  
32768  
Hz  
fREFO  
Full temperature range  
TA = 25°C  
–3.5%  
–1.5%  
+3.5%  
+1.5%  
%/°C  
%/V  
REFO absolute tolerance calibrated  
dfREFO/dT  
REFO frequency temperature drift  
REFO frequency supply voltage drift  
Duty cycle  
Measured at ACLK  
Measured at ACLK  
Measured at ACLK  
40%/60% duty cycle  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
1.8 V to 3.6 V  
0.01  
1.0  
dfREFO/dVCC  
40%  
50%  
25  
60%  
tSTART  
REFO start-up time  
µs  
34  
Specifications  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 5-5 lists the frequency characteristics of the DCO.  
Table 5-5. DCO Frequency  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-2)  
PARAMETER  
TEST CONDITIONS  
DCORSELx = 0, DCOx = 0, MODx = 0  
DCORSELx = 0, DCOx = 31, MODx = 0  
DCORSELx = 1, DCOx = 0, MODx = 0  
DCORSELx = 1, DCOx = 31, MODx = 0  
DCORSELx = 2, DCOx = 0, MODx = 0  
DCORSELx = 2, DCOx = 31, MODx = 0  
DCORSELx = 3, DCOx = 0, MODx = 0  
DCORSELx = 3, DCOx = 31, MODx = 0  
DCORSELx = 4, DCOx = 0, MODx = 0  
DCORSELx = 4, DCOx = 31, MODx = 0  
DCORSELx = 5, DCOx = 0, MODx = 0  
DCORSELx = 5, DCOx = 31, MODx = 0  
DCORSELx = 6, DCOx = 0, MODx = 0  
DCORSELx = 6, DCOx = 31, MODx = 0  
DCORSELx = 7, DCOx = 0, MODx = 0  
DCORSELx = 7, DCOx = 31, MODx = 0  
MIN  
0.07  
0.70  
0.15  
1.47  
0.32  
3.17  
0.64  
6.07  
1.3  
TYP  
MAX UNIT  
0.20 MHz  
1.70 MHz  
0.36 MHz  
3.45 MHz  
0.75 MHz  
7.38 MHz  
1.51 MHz  
14.0 MHz  
3.2 MHz  
fDCO(0,0)  
fDCO(0,31)  
fDCO(1,0)  
fDCO(1,31)  
fDCO(2,0)  
fDCO(2,31)  
fDCO(3,0)  
fDCO(3,31)  
fDCO(4,0)  
fDCO(4,31)  
fDCO(5,0)  
fDCO(5,31)  
fDCO(6,0)  
fDCO(6,31)  
fDCO(7,0)  
fDCO(7,31)  
DCO frequency (0, 0)(1)  
DCO frequency (0, 31)(1)  
DCO frequency (1, 0)(1)  
DCO frequency (1, 31)(1)  
DCO frequency (2, 0)(1)  
DCO frequency (2, 31)(1)  
DCO frequency (3, 0)(1)  
DCO frequency (3, 31)(1)  
DCO frequency (4, 0)(1)  
DCO frequency (4, 31)(1)  
DCO frequency (5, 0)(1)  
DCO frequency (5, 31)(1)  
DCO frequency (6, 0)(1)  
DCO frequency (6, 31)(1)  
DCO frequency (7, 0)(1)  
DCO frequency (7, 31)(1)  
12.3  
2.5  
28.2 MHz  
6.0 MHz  
23.7  
4.6  
54.1 MHz  
10.7 MHz  
88.0 MHz  
19.6 MHz  
135 MHz  
39.0  
8.5  
60  
Frequency step between range  
DCORSEL and DCORSEL + 1  
SDCORSEL  
SDCO  
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)  
1.2  
2.3 ratio  
Frequency step between tap  
DCO and DCO + 1  
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)  
Measured at SMCLK  
1.02  
40%  
1.12 ratio  
Duty cycle  
50%  
0.1  
60%  
%/°C  
%/V  
dfDCO/dT  
DCO frequency temperature drift fDCO = 1 MHz  
DCO frequency voltage drift fDCO = 1 MHz  
dfDCO/dVCORE  
1.9  
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the  
range of fDCO(n, 0),MAX fDCO fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,  
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap  
31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual  
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the  
selected range is at its minimum or maximum tap setting.  
100  
VCC = 3.0 V  
TA = 25°C  
10  
DCOx = 31  
1
DCOx = 0  
0.1  
0
1
2
3
4
5
6
7
DCORSEL  
Figure 5-2. Typical DCO Frequency  
Copyright © 2014–2018, Texas Instruments Incorporated  
Specifications  
35  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5.9 Digital I/Os  
Table 5-6 lists the input characteristics of the Schmitt-trigger GPIOs.  
Table 5-6. Schmitt-Trigger Inputs – General-Purpose I/O  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
1.8 V  
3 V  
MIN  
0.80  
1.50  
0.45  
0.75  
0.3  
TYP  
MAX UNIT  
1.40  
V
VIT+  
VIT–  
Vhys  
Positive-going input threshold voltage  
2.10  
1.8 V  
3 V  
1.00  
V
Negative-going input threshold voltage  
1.65  
1.8 V  
3 V  
0.85  
V
Input voltage hysteresis (VIT+ – VIT–  
)
0.4  
1.0  
For pullup: VIN = VSS  
For pulldown: VIN = VCC  
,
RPull  
CI  
Pullup or pulldown resistor  
Input capacitance  
20  
35  
5
50  
kΩ  
VIN = VSS or VCC  
pF  
Table 5-7 lists the input characteristics of the GPIOs.  
Table 5-7. Inputs – Ports P1 and P2(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
MAX UNIT  
Port P1, P2: P1.x to P2.x, External trigger pulse duration  
to set interrupt flag  
t(int)  
External interrupt timing(2)  
2.2 V, 3 V  
20  
ns  
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.  
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals  
shorter than t(int)  
.
Table 5-8 lists the leakage characteristics of the GPIOs.  
Table 5-8. Leakage Current – General-Purpose I/O  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN  
MAX UNIT  
+50 nA  
(1)(2)  
Ilkg(Px.y)  
High-impedance leakage current  
1.8 V, 3 V  
–50  
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.  
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is  
disabled.  
36  
Specifications  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
 
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 5-9 lists the output characteristics of the GPIOs in full drive strength mode.  
Table 5-9. Outputs – General-Purpose I/O (Full Drive Strength)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Section 5.9.2)  
PARAMETER  
TEST CONDITIONS  
I(OHmax) = –3 mA(1)  
VCC  
MIN  
1.55  
1.20  
2.75  
2.40  
0.00  
0.00  
0.00  
0.00  
MAX UNIT  
1.80  
1.8 V  
I(OHmax) = –10 mA(1)  
I(OHmax) = –5 mA(1)  
I(OHmax) = –15 mA(1)  
I(OLmax) = 3 mA(2)  
I(OLmax) = 10 mA(3)  
I(OLmax) = 5 mA(2)  
I(OLmax) = 15 mA(3)  
1.80  
V
VOH  
High-level output voltage  
3.00  
3 V  
1.8 V  
3 V  
3.00  
0.25  
0.60  
V
VOL  
Low-level output voltage  
0.25  
0.60  
(1) The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.  
See Section 5.3 for more details.  
(2) The maximum total current, I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.  
(3) The maximum total current, I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.  
Table 5-10 lists the output characteristics of the GPIOs in reduced drive strength mode.  
Table 5-10. Outputs – General-Purpose I/O (Reduced Drive Strength)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see  
Section 5.9.1)  
PARAMETER  
TEST CONDITIONS  
I(OHmax) = –1 mA(2)  
VCC  
MIN  
1.55  
1.20  
2.75  
2.40  
0.00  
0.00  
0.00  
0.00  
MAX UNIT  
1.80  
1.8 V  
I(OHmax) = –3 mA(2)  
I(OHmax) = –2 mA(2)  
I(OHmax) = –6 mA(2)  
I(OLmax) = 1 mA(3)  
I(OLmax) = 3 mA(4)  
I(OLmax) = 2 mA(3)  
I(OLmax) = 6 mA(4)  
1.80  
V
VOH  
High-level output voltage  
3.00  
3 V  
1.8 V  
3 V  
3.00  
0.25  
0.60  
V
VOL  
Low-level output voltage  
0.25  
0.60  
(1) Selecting reduced drive strength may reduce EMI.  
(2) The maximum total current, I(OHmax), for all outputs combined should not exceed ±20 mA to hold the maximum voltage drop specified.  
See Section 5.3 for more details.  
(3) The maximum total current, I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.  
(4) The maximum total current, I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.  
Table 5-11 lists the output frequency of the GPIOs.  
Table 5-11. Output Frequency – General-Purpose I/O  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
MAX UNIT  
VCC = 1.8 V,  
PMMCOREVx = 0  
16  
(1) (2)  
fPx.y  
Port output frequency (with load)  
See  
MHz  
25  
VCC = 3 V,  
PMMCOREVx = 3  
VCC = 1.8 V,  
PMMCOREVx = 0  
ACLK  
16  
SMCLK  
MCLK  
fPort_CLK  
Clock output frequency  
MHz  
25  
VCC = 3 V,  
PMMCOREVx = 3  
CL = 20 pF(2)  
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full  
drive strength, R1 = 550 . For reduced drive strength, R1 = 1.6 k. CL = 20 pF is connected to the output to VSS  
.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.  
Copyright © 2014–2018, Texas Instruments Incorporated  
Specifications  
37  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
 
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5.9.1 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
20  
8
7
6
5
4
3
2
1
0
18  
16  
14  
12  
10  
8
TA = 25°C  
TA = 25°C  
TA = 85°C  
TA = 85°C  
6
4
2
0
0
0.5  
1
1.5  
2
2.5  
3
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
1.8  
VOL – Low-Level Output Voltage – V  
VOL – Low-Level Output Voltage – V  
VCC = 3 V  
Reduced drive strength  
VCC = 1.8 V  
Reduced drive strength  
Figure 5-3. Typical Low-Level Output Current vs  
Low-Level Output Voltage  
Figure 5-4. Typical Low-Level Output Current vs  
Low-Level Output Voltage  
0
-5  
0
-1  
-2  
-3  
-4  
-5  
-6  
-7  
-8  
-10  
-15  
-20  
-25  
TA = 85°C  
TA = 25°C  
TA = 85°C  
TA = 25°C  
0
0.5  
1
1.5  
2
2.5  
3
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
1.8  
VOH – High-Level Output Voltage – V  
VOH – High-Level Output Voltage – V  
VCC = 3 V  
Reduced drive strength  
VCC = 1.8 V  
Reduced drive strength  
Figure 5-5. Typical High-Level Output Current vs  
High-Level Output Voltage  
Figure 5-6. Typical High-Level Output Current vs  
High-Level Output Voltage  
38  
Specifications  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5.9.2 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
60  
50  
40  
30  
20  
10  
0
25  
20  
15  
10  
5
TA = 25°C  
TA = 25°C  
TA = 85°C  
TA = 85°C  
0
0
0.5  
1
1.5  
2
2.5  
3
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
1.8  
VOL – Low-Level Output Voltage – V  
VOL – Low-Level Output Voltage – V  
VCC = 3 V  
Full drive strength  
VCC = 1.8 V  
Full drive strength  
Figure 5-7. Typical Low-Level Output Current vs  
Low-Level Output Voltage  
Figure 5-8. Typical Low-Level Output Current vs  
Low-Level Output Voltage  
0
-10  
-20  
-30  
-40  
-50  
-60  
0
-5  
-10  
-15  
-20  
-25  
TA = 85°C  
TA = 25°C  
TA = 85°C  
TA = 25°C  
0
0.5  
1
1.5  
2
2.5  
3
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
1.8  
VOH – High-Level Output Voltage – V  
VOH – High-Level Output Voltage – V  
VCC = 3 V  
Full drive strength  
VCC = 1.8 V  
Full drive strength  
Figure 5-9. Typical High-Level Output Current vs  
High-Level Output Voltage  
Figure 5-10. Typical High-Level Output Current vs  
High-Level Output Voltage  
Copyright © 2014–2018, Texas Instruments Incorporated  
Specifications  
39  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
5.10 Power-Management Module (PMM)  
Table 5-12 lists the characteristics of the BOR.  
Table 5-12. PMM, Brownout Reset (BOR)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
| dDVCC/dt | < 3 V/s  
| dDVCC/dt | < 3 V/s  
MIN  
TYP  
MAX UNIT  
V(DVCC_BOR_IT–)  
V(DVCC_BOR_IT+)  
V(DVCC_BOR_hys)  
tRESET  
BORH on voltage, DVCC falling level  
BORH off voltage, DVCC rising level  
BORH hysteresis  
1.45  
1.50  
250  
V
V
0.80  
50  
2
1.20  
mV  
µs  
Pulse duration required at RST/NMI pin to accept a reset  
Table 5-13 lists the core voltage characteristics of the PMM.  
Table 5-13. PMM, Core Voltage  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
2.4 V DVCC 3.6 V  
2.2 V DVCC 3.6 V  
2 V DVCC 3.6 V  
1.8 V DVCC 3.6 V  
2.4 V DVCC 3.6 V  
2.2 V DVCC 3.6 V  
2 V DVCC 3.6 V  
1.8 V DVCC 3.6 V  
MIN  
TYP  
1.91  
1.81  
1.61  
1.41  
1.94  
1.92  
1.73  
1.52  
MAX UNIT  
VCORE3(AM)  
VCORE2(AM)  
VCORE1(AM)  
VCORE0(AM)  
VCORE3(LPM)  
VCORE2(LPM)  
VCORE1(LPM)  
VCORE0(LPM)  
Core voltage, active mode, PMMCOREV = 3  
Core voltage, active mode, PMMCOREV = 2  
Core voltage, active mode, PMMCOREV = 1  
Core voltage, active mode, PMMCOREV = 0  
Core voltage, low-current mode, PMMCOREV = 3  
Core voltage, low-current mode, PMMCOREV = 2  
Core voltage, low-current mode, PMMCOREV = 1  
Core voltage, low-current mode, PMMCOREV = 0  
V
V
V
V
V
V
V
V
Table 5-14 lists the characteristics of the high-side SVS.  
Table 5-14. PMM, SVS High Side  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
SVSHE = 0, DVCC = 3.6 V  
MIN  
TYP  
0
MAX UNIT  
nA  
I(SVSH)  
SVS current consumption  
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0  
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1  
SVSHE = 1, SVSHRVL = 0  
200  
1.5  
µA  
1.60  
1.77  
1.93  
2.09  
1.65  
1.85  
2.05  
2.15  
2.30  
2.57  
2.90  
2.90  
1.65  
1.84  
2.00  
2.16  
1.75  
1.95  
2.15  
2.25  
2.40  
2.70  
3.05  
3.05  
2.5  
1.75  
SVSHE = 1, SVSHRVL = 1  
1.95  
V
V(SVSH_IT–)  
SVSH on voltage level  
SVSHE = 1, SVSHRVL = 2  
2.12  
SVSHE = 1, SVSHRVL = 3  
2.29  
1.85  
2.05  
2.25  
SVSHE = 1, SVSMHRRL = 0  
SVSHE = 1, SVSMHRRL = 1  
SVSHE = 1, SVSMHRRL = 2  
SVSHE = 1, SVSMHRRL = 3  
2.35  
V
V(SVSH_IT+)  
SVSH off voltage level  
SVSHE = 1, SVSMHRRL = 4  
2.55  
SVSHE = 1, SVSMHRRL = 5  
2.83  
3.20  
3.20  
SVSHE = 1, SVSMHRRL = 6  
SVSHE = 1, SVSMHRRL = 7  
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1  
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0  
SVSHE = 0 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1  
SVSHE = 0 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0  
tpd(SVSH)  
SVSH propagation delay  
µs  
µs  
20  
12.5  
100  
t(SVSH)  
SVSH on or off delay time  
DVCC rise time  
dVDVCC/dt  
0
1000  
V/s  
40  
Specifications  
Copyright © 2014–2018, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
 
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A  
MSP430F6769A, MSP430F6768A, MSP430F6767A, MSP430F6766A, MSP430F6765A  
MSP430F6749A, MSP430F6748A, MSP430F6747A, MSP430F6746A, MSP430F6745A  
SLAS982A MAY 2014REVISED SEPTEMBER 2018  
www.ti.com  
Table 5-15 lists the characteristics of the high-side SVM.  
Table 5-15. PMM, SVM High Side  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
SVMHE = 0, DVCC = 3.6 V  
MIN  
TYP  
0
MAX UNIT  
nA  
I(SVMH)  
SVMH current consumption  
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0  
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1  
SVMHE = 1, SVSMHRRL = 0  
200  
1.5  
µA  
1.83  
1.63  
1.83  
2.03  
2.13  
2.28  
2.55  
2.88  
2.88  
1.73  
1.93  
2.13  
2.23  
2.40  
2.70  
3.02  
3.02  
3.77  
2.5  
SVMHE = 1, SVSMHRRL = 1  
2.03  
SVMHE = 1, SVSMHRRL = 2  
2.23  
SVMHE = 1, SVSMHRRL = 3  
2.33  
V(SVMH)  
SVMH on or off voltage level(1)  
SVMHE = 1, SVSMHRRL = 4  
2.53  
2.81  
3.18  
3.18  
V
SVMHE = 1, SVSMHRRL = 5  
SVMHE = 1, SVSMHRRL = 6  
SVMHE = 1, SVSMHRRL = 7  
SVMHE = 1, SVMHOVPE = 1  
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1  
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0  
tpd(SVMH) SVMH propagation delay  
µs  
µs  
20  
SVMHE = 0 1, dVDVCC/dt = 10 mV/µs,  
SVMHFP = 1  
12.5  
100  
t(SVMH)  
SVMH on or off delay time  
SVMHE = 0 1, dVDVCC/dt = 1 mV/µs,  
SVMHFP = 0  
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage  
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use.  
Table 5-16 lists the characteristics of the low-side SVS.  
Table 5-16. PMM, SVS Low Side  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
SVSLE = 0, PMMCOREV = 2  
MIN  
TYP  
0
MAX UNIT  
nA  
µA  
µs  
I(SVSL)  
SVSL current consumption  
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0  
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1  
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1  
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0  
200  
1.5  
2.5  
20  
tpd(SVSL)  
SVSL propagation delay  
SVSL on or off delay time  
SVSLE = 0 1, dVCORE/dt = 10 mV/µs,  
SVSLFP = 1  
12.5  
100  
t(SVSL)  
µs  
SVSLE = 0 1, dVCORE/dt = 1 mV/µs,  
SVSLFP = 0  
Copyright © 2014–2018, Texas Instruments Incorporated  
Specifications  
41  
Submit Documentation Feedback  
Product Folder Links: MSP430F6779A MSP430F6778A MSP430F6777A MSP430F6776A MSP430F6775A  
MSP430F6769A MSP430F6768A MSP430F6767A MSP430F6766A MSP430F6765A MSP430F6749A  
MSP430F6748A MSP430F6747A MSP430F6746A MSP430F6745A  
 
 
MSP430F6779A, MSP430F6778A, MSP430F6777A, MSP430F6776A, MSP430F6775A