MSP430F5438A-ET [TI]
MSP430F5438A-ET Mixed-Signal Controller;
| 型号： | MSP430F5438A-ET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MSP430F5438A-ET Mixed-Signal Controller |
| 文件： | 总118页 (文件大小：3098K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A, MSP430F5419A,
MSP430F5418A
SLAS655G – JANUARY 2010 – REVISED SEPTEMBER 2020
MSP430F543xA, MSP430F541xA Mixed-Signal Microcontrollers
– High-frequency crystals up to 32 MHz
16-bit timer TA0, Timer_A with five capture/
compare registers
16-bit timer TA1, Timer_A with three capture/
compare registers
16-bit timer TB0, Timer_B with seven capture/
compare shadow registers
Up to four universal serial communication
interfaces (USCIs)
– USCI_A0, USCI_A1, USCI_A2, and USCI_A3
each support:
1 Features
•
•
•
•
•
Low supply voltage range:
3.6 V down to 1.8 V
•
Ultra-low power consumption
– Active mode (AM):
all system clocks active
230 µA/MHz at 8 MHz, 3.0 V, flash program
execution (typical)
110 µA/MHz at 8 MHz, 3.0 V, RAM program
execution (typical)
– Standby mode (LPM3):
•
Enhanced UART supports automatic baud-
rate detection
real-time clock (RTC) with crystal, watchdog,
and supply supervisor operational, full RAM
retention, fast wakeup:
1.7 µA at 2.2 V, 2.1 µA at 3.0 V (typical)
low-power oscillator (VLO), general-purpose
counter, watchdog, and supply supervisor
operational, full RAM retention, fast wakeup:
1.2 µA at 3.0 V (typical)
•
•
IrDA encoder and decoder
Synchronous SPI
– USCI_B0, USCI_B1, USCI_B2, and USCI_B3
each support:
•
•
I2C
Synchronous SPI
– Off mode (LPM4):
•
12-bit analog-to-digital converter (ADC)
– Internal reference
– Sample-and-hold
full RAM retention, supply supervisor
operational, fast wakeup:
1.2 µA at 3.0 V (typical)
– Autoscan feature
– Shutdown mode (LPM4.5):
0.1 µA at 3.0 V (typical)
Wake up from standby mode in 3.5 µs (typical)
16-bit RISC architecture
– 14 external channels, 2 internal channels
Hardware multiplier supports 32-bit operations
Serial onboard programming, no external
programming voltage needed
3-channel internal DMA
Basic timer with RTC feature
Device Comparison summarizes the available
family members
•
•
•
•
– Extended memory
•
•
•
– Up to 25-MHz system clock
Flexible power-management system
– Fully integrated LDO with programmable
regulated core supply voltage
– Supply voltage supervision, monitoring, and
brownout
•
•
2 Applications
•
•
•
•
•
•
Analog and Digital Sensor Systems
Digital Motor Controls
Remote Controls
Thermostats
Digital Timers
Unified clock system
– FLL control loop for frequency stabilization
– Low-power low-frequency internal clock source
(VLO)
– Low-frequency trimmed internal reference
source (REFO)
Hand-Held Meters
– 32-kHz crystals
3 Description
The TI MSP family of ultra-low-power microcontrollers consists of several devices featuring different sets of
peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is
optimized to achieve extended battery life in portable measurement applications. The device features a powerful
16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A, MSP430F5419A, MSP430F5418A
SLAS655G – JANUARY 2010 – REVISED SEPTEMBER 2020
www.ti.com
digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in 3.5 µs
(typical).
The MSP430F543xA and MSP430F541xA series are microcontroller configurations with three 16-bit timers, a
high-performance 12-bit ADC, up to four USCIs, a hardware multiplier, DMA, an RTC module with alarm
capabilities, and up to 87 I/O pins.
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.
Device Information
PART NUMBER(1)
MSP430F5438AIPZ
PACKAGE
BODY SIZE(2)
14 mm × 14 mm
12 mm × 12 mm
7 mm × 7 mm
7 mm × 7 mm
LQFP (100)
MSP430F5437AIPN
MSP430F5438AIZCA
MSP430F5438AIZQW(3)
LQFP (80)
nFBGA (113)
MicroStar Junior™ BGA (113)
(1) For the most current part, package, and ordering information, see the Package Option Addendum
in Section 11, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 11.
(3) All orderable part numbers in the ZQW (MicroStar Junior BGA) package have been changed to a
status of Last Time Buy. Visit the Product life cycle page for details on this status.
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MSP430F5418A
SLAS655G – JANUARY 2010 – REVISED SEPTEMBER 2020
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4 Functional Block Diagrams
Figure 4-1 and Figure 4-2 show the functional block diagrams.
PA
PB
PC
PD
PE
PF
P11.x
XIN XOUT
DVCC DVSS AVCC AVSS
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x P10.x
XT2IN
I/O Ports
Power
Management
ACLK
SMCLK
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
2×8 I/Os
I/O Ports
P9, P10
2×8 I/Os
I/O Ports
P11
1×3 I/Os
Unified
Clock
System
P1, P2
2×8 I/Os
Interrupt
Capability
256KB
192KB
128KB
SYS
16KB
RAM
XT2OUT
Watchdog
LDO
SVM, SVS
Brownout
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
PE
1×16 I/Os
PF
1×3 I/Os
Flash
PA
1×16 I/Os
MCLK
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(L: 8+2)
ADC12_A
USCI0,1,2,3
12 bit
200 ksps
TA0
TA1
TB0
USCI_Ax:
UART,
IrDA, SPI
JTAG,
SBW
Interface
RTC_A
MPY32
CRC16
REF
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
16 channels
(14 ext, 2 int)
Autoscan
UCSI_Bx:
SPI, I2C
Copyright © 2016, Texas Instruments Incorporated
Figure 4-1. Functional Block Diagram – MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ,
MSP430F5438AIZCAW, MSP430F5436AIZCA, MSP430F5419AIZCA, MSP430F5438AIZQW,
MSP430F5436AIZQW, MSP430F5419AIZQW
PA
PB
PC
PD
XIN XOUT
DVCC DVSS AVCC AVSS
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
XT2IN
Power
Management
I/O Ports
ACLK
SMCLK
I/O Ports
P3, P4
2×8 I/Os
I/O Ports
P5, P6
2×8 I/Os
I/O Ports
P7, P8
2×8 I/Os
Unified
Clock
System
P1, P2
2×8 I/Os
Interrupt
Capability
256KB
192KB
128KB
SYS
16KB
RAM
XT2OUT
LDO
SVM, SVS
Brownout
Watchdog
PB
1×16 I/Os
PC
1×16 I/Os
PD
1×16 I/Os
PA
1×16 I/Os
MCLK
Flash
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(L: 8+2)
ADC12_A
USCI0,1
12 bit
200 ksps
TA0
TA1
TB0
UCSI_Ax:
UART,
IrDA, SPI
JTAG,
SBW
Interface
RTC_A
REF
MPY32
CRC16
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
16 channels
(14 ext, 2 int)
Autoscan
USCI_Bx:
SPI, I2C
Copyright © 2016, Texas Instruments Incorporated
Functional Block Diagram – MSP430F5437AIPN, MSP430F5435AIPN, MSP430F5418AIPN
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MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A, MSP430F5419A, MSP430F5418A
SLAS655G – JANUARY 2010 – REVISED SEPTEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Functional Block Diagrams............................................ 3
5 Revision History.............................................................. 5
6 Device Comparison.........................................................6
6.1 Related Products........................................................ 6
7 Terminal Configuration and Functions..........................7
7.1 Pin Diagrams.............................................................. 7
7.2 Signal Descriptions................................................... 10
8 Specifications................................................................ 15
8.1 Absolute Maximum Ratings...................................... 15
8.2 ESD Ratings............................................................. 15
8.3 Recommended Operating Conditions.......................15
8.4 Active Mode Supply Current Into VCC Excluding
8.28 Timer_A...................................................................30
8.29 Timer_B...................................................................30
8.30 USCI (UART Mode) Clock Frequency.................... 30
8.31 USCI (UART Mode)................................................ 30
8.32 USCI (SPI Master Mode) Clock Frequency............ 31
8.33 USCI (SPI Master Mode)........................................ 31
8.34 USCI (SPI Slave Mode).......................................... 33
8.35 USCI (I2C Mode).....................................................35
8.36 12-Bit ADC, Power Supply and Input Range
Conditions................................................................... 36
8.37 12-Bit ADC, Timing Parameters..............................36
8.38 12-Bit ADC, Linearity Parameters Using an
External Reference Voltage or AVCC as
Reference Voltage.......................................................37
8.39 12-Bit ADC, Linearity Parameters Using the
External Current.......................................................... 16
Internal Reference Voltage..........................................37
8.40 12-Bit ADC, Temperature Sensor and Built-In
8.5 Low-Power Mode Supply Currents (Into VCC
)
Excluding External Current..........................................17
8.6 Thermal Resistance Characteristics......................... 18
8.7 Schmitt-Trigger Inputs – General-Purpose I/O..........18
8.8 Inputs – Ports P1 and P2..........................................18
8.9 Leakage Current – General-Purpose I/O..................18
8.10 Outputs – General-Purpose I/O (Full Drive
Strength)......................................................................19
8.11 Outputs – General-Purpose I/O (Reduced Drive
Strength)......................................................................19
8.12 Output Frequency – General-Purpose I/O..............19
8.13 Typical Characteristics – Outputs, Reduced
VMID ............................................................................38
8.41 REF, External Reference........................................ 39
8.42 REF, Built-In Reference.......................................... 40
8.43 Flash Memory......................................................... 41
8.44 JTAG and Spy-Bi-Wire Interface.............................41
9 Detailed Description......................................................42
9.1 CPU ......................................................................... 42
9.2 Operating Modes...................................................... 43
9.3 Interrupt Vector Addresses....................................... 44
9.4 Memory Organization................................................45
9.5 Bootloader (BSL)...................................................... 45
9.6 JTAG Operation........................................................ 46
9.7 Flash Memory .......................................................... 47
9.8 RAM .........................................................................47
9.9 Peripherals................................................................47
9.10 Input/Output Diagrams............................................68
9.11 Device Descriptors..................................................94
10 Device and Documentation Support..........................97
10.1 Getting Started........................................................97
10.2 Device Nomenclature..............................................97
10.3 Tools and Software................................................. 99
10.4 Documentation Support........................................ 101
10.5 Related Links........................................................ 102
10.6 Support Resources............................................... 103
10.7 Trademarks...........................................................103
10.8 Electrostatic Discharge Caution............................103
10.9 Export Control Notice............................................103
10.10 Glossary..............................................................103
11 Mechanical, Packaging, and Orderable
Drive Strength (PxDS.y = 0)........................................20
8.14 Typical Characteristics – Outputs, Full Drive
Strength (PxDS.y = 1)................................................. 21
8.15 Crystal Oscillator, XT1, Low-Frequency Mode........22
8.16 Crystal Oscillator, XT1, High-Frequency Mode.......23
8.17 Crystal Oscillator, XT2............................................ 24
8.18 Internal Very-Low-Power Low-Frequency
Oscillator (VLO)...........................................................25
8.19 Internal Reference, Low-Frequency Oscillator
(REFO)........................................................................25
8.20 DCO Frequency......................................................26
8.21 PMM, Brownout Reset (BOR).................................27
8.22 PMM, Core Voltage.................................................27
8.23 PMM, SVS High Side..............................................28
8.24 PMM, SVM High Side............................................. 28
8.25 PMM, SVS Low Side...............................................29
8.26 PMM, SVM Low Side..............................................29
8.27 Wake-up Times From Low-Power Modes and
Reset...........................................................................29
Information.................................................................. 104
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MSP430F5418A
SLAS655G – JANUARY 2010 – REVISED SEPTEMBER 2020
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5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from September 26, 2018 to September 11, 2020
Page
•
•
•
•
Updated the numbering for sections, tables, figures, and cross-references throughout the document..............1
Added nFBGA package (ZCA) information throughout document......................................................................1
Added note about status change for all orderable part numbers in the ZQW package in Device Information .. 1
Changed the MAX value of the IERASE and IMERASE, IBANK parameters in Section 8.43, Flash Memory ......... 41
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6 Device Comparison
Table 6-1 summarizes the available family members.
Table 6-1. Device Characteristics
USCI
FLASH
(KB)(2)
SRAM
(KB)
ADC12_A
(Ch)
DEVICE(1)
Timer_A(3)
Timer_B(4)
I/O
PACKAGE
CHANNEL A:
CHANNEL B:
SPI, I2C
UART, IrDA, SPI
100 PZ,
113 ZCA,
113 ZQW
MSP430F5438A
MSP430F5437A
MSP430F5436A
MSP430F5435A
MSP430F5419A
MSP430F5418A
256
256
192
192
128
128
16
16
16
16
16
16
5, 3
5, 3
5, 3
5, 3
5, 3
5, 3
7
7
7
7
7
7
4
2
4
2
4
2
4
2
4
2
4
2
14 ext, 2 int
14 ext, 2 int
14 ext, 2 int
14 ext, 2 int
14 ext, 2 int
14 ext, 2 int
87
67
87
67
87
67
80 PN
100 PZ,
113 ZCA,
113 ZQW
80 PN
100 PZ,
113 ZCA,
113 ZQW
80 PN
(1) For the most current part, package, and ordering information, see the Package Option Addendum in Section 11, or see the TI website
at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators.
6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers
TI's low-power and high-performance MCUs, with wired and wireless connectivity options, are optimized for a
broad range of applications.
Products for MSP430 Ultra-Low-Power Microcontrollers
One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-low-
power microcontrollers with advanced peripherals for precise sensing and measurement.
Companion Products for MSP430F5438A
Review products that are frequently purchased or used with this product.
Reference Designs for MSP430F5438A
Find reference designs that leverage the best in TI technology to solve your system-level challenges.
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MSP430F5418A
SLAS655G – JANUARY 2010 – REVISED SEPTEMBER 2020
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7 Terminal Configuration and Functions
7.1 Pin Diagrams
Figure 7-1 shows the pinout of the 100-pin PZ package for the MSP430F5438A, MSP430F5436A, and
MSP430F5419A devices.
P6.4/A4
P6.5/A5
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7
2
P9.6
P6.6/A6
3
P9.5/UCA2RXDUCA2SOMI
P9.4/UCA2TXD/UCA2SIMO
P9.3/UCB2CLK/UCA2STE
P9.2/UCB2SOMI/UCB2SCL
P9.1/UCB2SIMO/UCB2SDA
P9.0/UCB2STE/UCA2CLK
P8.7
P6.7/A7
4
P7.4/A12
5
P7.5/A13
6
P7.6/A14
7
P7.7/A15
8
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P8.6/TA1.1
AVCC
AVSS
P8.5/TA1.0
DVCC2
DVSS2
P7.0/XIN
VCORE
P7.1/XOUT
DVSS1
P8.4/TA0.4
P8.3/TA0.3
DVCC1
P8.2/TA0.2
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P8.1/TA0.1
P8.0/TA0.0
P7.3/TA1.2
P7.2/TB0OUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
P2.0/TA1CLK/MCLK
Figure 7-1. 100-Pin PZ Package (Top View) – MSP430F5438AIPZ, MSP430F5436AIPZ, MSP430F5419AIPZ
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Figure 7-2 shows the pinout of the 80-pin PN package for the MSP430F5437A, MSP430F5435A, and
MSP430F5418A devices.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P6.4/A4
P6.5/A5
60 P8.0/TA0.0
1
59 P7.3/TA1.2
2
P6.6/A6
58 P7.2/TB0OUTH/SVMOUT
57 P5.7/UCA1RXD/UCA1SOMI
56 P5.6/UCA1TXD/UCA1SIMO
55 P5.5/UCB1CLK/UCA1STE
54 P5.4/UCB1SOMI/UCB1SCL
53 P4.7/TB0CLK/SMCLK
52 P4.6/TB0.6
3
P6.7/A7
4
P7.4/A12
5
P7.5/A13
6
P7.6/A14
7
P7.7/A15
8
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF−/VeREF−
AVCC
9
51 DVCC2
10
11
12
13
14
15
16
17
18
19
20
50 DVSS2
AVSS
49 VCORE
P7.0/XIN
48 P4.5/TB0.5
P7.1/XOUT
DVSS1
47 P4.4/TB0.4
46 P4.3/TB0.3
DVCC1
45 P4.2/TB0.2
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
44 P4.1/TB0.1
P4.0/TB0.0
43
42 P3.7/UCB1SIMO/UCB1SDA
41 P3.6/UCB1STE/UCA1CLK
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 7-2. 80-Pin PN Package (Top View) – MSP430F5437AIPN, MSP430F5435AIPN, MSP430F5418AIPN
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Figure 7-3 shows the pinout of the 113-pin ZCA or ZQW package for the MSP430F5438A, MSP430F5436A, and
MSP430F5419A devices.
P6.4
A1
P6.2
A2
RST
A3
PJ.1
A4
P5.3
A5
P5.2 P11.2 P11.0 P10.6 P10.4 P10.1 P9.7
A6
A7
A8
A9
A10
A11
A12
P6.6
B1
P6.3
B2
P6.1
B3
PJ.3
B4
PJ.0 DVSS4 DVCC4 P10.7 P10.5 P10.3 P9.6
P9.5
B12
B5
B6
B7
B8
B9
B10
B11
P7.5
C1
P6.7
C2
P9.4
C11
P9.2
C12
C3
P5.0
D1
P7.6
D2
P6.0
D4
PJ.2 TEST P11.1 P10.2 P10.0
P9.0
D11
P8.7
D12
D5
E5
F5
G5
H5
D6
D7
D8
E8
F8
G8
H8
D9
P5.1 AVCC
E1 E2
P6.5
E4
P9.3
E9
P8.6 DVCC2
E11 E12
E6
E7
P7.0 AVSS
F1 F2
P7.4
F4
P9.1
F9
P8.5 DVSS2
F11 F12
P7.1 DVSS1
G1 G2
P7.7
G4
P8.3
G9
P8.4 VCORE
G11
G12
P1.0 DVCC1
P1.1
H4
P8.0
H9
P8.1
H11
P8.2
H12
H1
H2
H6
H7
P1.3
J1
P1.4
J2
P1.2
J4
P2.7
J5
P3.2
J6
P3.5
J7
P4.0
J8
P5.5
J9
P7.2
J11
P7.3
J12
P1.5
K1
P1.6
K2
P5.6
K11
P5.7
K12
P1.7
L1
P2.1
L2
P2.3
L3
P2.5
L4
P3.0
L5
P3.3
L6
P3.4
L7
P3.7
L8
P4.2
L9
P4.3
L10
P4.5
L11
P5.4
L12
P2.0
M1
P2.2
M2
P2.4
M3
P2.6
M4
P3.1 DVSS3 DVCC3 P3.6
M7
M5 M6 M8
P4.1
M9
P4.4
M10
P4.6
M11
P4.7
M12
Figure 7-3. 113-Pin ZCA or ZQW Package (Top View) – MSP430F5438AIZCA, MSP430F5436AIZCA,
MSP430F5419AIZCA, MSP430F5438AIZQW, MSP430F5436AIZQW, MSP430F5419AIZQW
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7.2 Signal Descriptions
Section 7.2 describes the signals for all device variants and package options.
Table 7-1. Signal Descriptions
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZCA,
ZQW
PZ
1
PN
1
General-purpose digital I/O
Analog input A4 for the ADC
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
A1
E4
B1
C2
F4
C1
D2
G4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O
Analog input A5 for the ADC
2
2
General-purpose digital I/O
Analog input A6 for the ADC
3
3
General-purpose digital I/O
Analog input A7 for the ADC
4
4
General-purpose digital I/O
Analog input A12 for the ADC
5
5
General-purpose digital I/O
Analog input A13 for the ADC
6
6
General-purpose digital I/O
Analog input A14 for the ADC
7
7
General-purpose digital I/O
Analog input A15 for the ADC
8
8
General-purpose digital I/O
Analog input A8 for the ADC
Output of reference voltage to the ADC
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF-/VeREF-
9
9
D1
E1
I/O
I/O
Input for an external reference voltage to the ADC
General-purpose digital I/O
Analog input A9 for the ADC
Negative terminal for the ADC reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage
10
10
AVCC
AVSS
11
12
11
12
E2
F2
Analog power supply
Analog ground supply
General-purpose digital I/O
Input terminal for crystal oscillator XT1
P7.0/XIN
13
14
13
14
F1
I/O
I/O
General-purpose digital I/O
Output terminal of crystal oscillator XT1
P7.1/XOUT
G1
DVSS1
DVCC1
15
16
15
16
G2
H2
Digital ground supply
Digital power supply
General-purpose digital I/O with port interrupt
P1.0/TA0CLK/ACLK
P1.1/TA0.0
17
18
19
17
18
19
H1
H4
J4
I/O TA0 clock signal TACLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
General-purpose digital I/O with port interrupt
I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
P1.2/TA0.1
General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
20
21
22
20
21
22
J1
J2
K1
I/O
General-purpose digital I/O with port interrupt
I/O
TA0 CCR3 capture: CCI3A input compare: Out3 output
General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
I/O
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZCA,
ZQW
PZ
PN
General-purpose digital I/O with port interrupt
SMCLK output
P1.6/SMCLK
P1.7
23
24
23
24
K2
L1
I/O
I/O General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
I/O TA1 clock signal TA1CLK input
MCLK output
P2.0/TA1CLK/MCLK
25
25
M1
General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
26
27
28
26
27
28
L2
M2
L3
I/O
General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
I/O
General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
I/O
General-purpose digital I/O with port interrupt
RTCCLK output
P2.4/RTCCLK
P2.5
29
30
31
29
32
33
M3
L4
I/O
I/O General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
I/O
P2.6/ACLK
M4
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
I/O Conversion clock output for the ADC
DMA external trigger input
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
32
33
34
35
J5
L5
General-purpose digital I/O
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
I/O
Clock signal output – USCI_A0 SPI master mode
General-purpose digital I/O
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
34
35
36
37
M5
J6
I/O Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
General-purpose digital I/O
I/O Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode
P3.3/UCB0CLK/UCA0STE
36
38
L6
I/O
Slave transmit enable – USCI_A0 SPI mode
DVSS3
DVCC3
37
38
30
31
M6
M7
Digital ground supply
Digital power supply
General-purpose digital I/O
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
39
40
39
40
L7
J7
I/O Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
General-purpose digital I/O
I/O Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
General-purpose digital I/O
Slave transmit enable – USCI_B1 SPI mode
Clock signal input – USCI_A1 SPI slave mode
P3.6/UCB1STE/UCA1CLK
41
41
M8
I/O
Clock signal output – USCI_A1 SPI master mode
General-purpose digital I/O
P3.7/UCB1SIMO/UCB1SDA
P4.0/TB0.0
42
43
42
43
L8
J8
I/O Slave in, master out – USCI_B1 SPI mode
I2C data – USCI_B1 I2C mode
General-purpose digital I/O
I/O
TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZCA,
ZQW
PZ
44
45
46
47
48
49
PN
44
45
46
47
48
52
General-purpose digital I/O
TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output
P4.1/TB0.1
P4.2/TB0.2
P4.3/TB0.3
P4.4/TB0.4
P4.5/TB0.5
P4.6/TB0.6
M9
L9
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O
TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O
TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output
L10
M10
L11
M11
General-purpose digital I/O
TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output
General-purpose digital I/O
TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output
General-purpose digital I/O
TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output
General-purpose digital I/O
P4.7/TB0CLK/SMCLK
50
51
53
54
M12
L12
I/O TB0 clock input
SMCLK output
General-purpose digital I/O
P5.4/UCB1SOMI/UCB1SCL
I/O Slave out, master in – USCI_B1 SPI mode
I2C clock – USCI_B1 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B1 SPI slave mode
Clock signal output – USCI_B1 SPI master mode
P5.5/UCB1CLK/UCA1STE
52
55
J9
I/O
Slave transmit enable – USCI_A1 SPI mode
General-purpose digital I/O
P5.6/UCA1TXD/UCA1SIMO
P5.7/UCA1RXD/UCA1SOMI
P7.2/TB0OUTH/SVMOUT
53
54
55
56
57
58
K11
K12
J11
I/O Transmit data – USCI_A1 UART mode
Slave in, master out – USCI_A1 SPI mode
General-purpose digital I/O
I/O Receive data – USCI_A1 UART mode
Slave out, master in – USCI_A1 SPI mode
General-purpose digital I/O
I/O Switch all PWM outputs to high impedance – Timer TB0
SVM output
General-purpose digital I/O
TA1 CCR2 capture: CCI2B input, compare: Out2 output
P7.3/TA1.2
P8.0/TA0.0
P8.1/TA0.1
P8.2/TA0.2
P8.3/TA0.3
P8.4/TA0.4
VCORE(3)
56
57
58
59
60
61
62
59
60
61
62
63
64
49
J12
H9
I/O
General-purpose digital I/O
TA0 CCR0 capture: CCI0B input, compare: Out0 output
I/O
General-purpose digital I/O
TA0 CCR1 capture: CCI1B input, compare: Out1 output
H11
H12
G9
I/O
General-purpose digital I/O
TA0 CCR2 capture: CCI2B input, compare: Out2 output
I/O
General-purpose digital I/O
TA0 CCR3 capture: CCI3B input, compare: Out3 output
I/O
General-purpose digital I/O
TA0 CCR4 capture: CCI4B input, compare: Out4 output
G11
G12
I/O
Regulated core power supply output (internal use only, no external current
loading)
DVSS2
DVCC2
63
64
50
51
F12
E12
Digital ground supply
Digital power supply
General-purpose digital I/O
TA1 CCR0 capture: CCI0B input, compare: Out0 output
P8.5/TA1.0
65
65
F11
I/O
I/O
General-purpose digital I/O
TA1 CCR1 capture: CCI1B input, compare: Out1 output
P8.6/TA1.1
P8.7
66
67
66
E11
D12
N/A
I/O General-purpose digital I/O
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZCA,
ZQW
PZ
PN
General-purpose digital I/O
Slave transmit enable – USCI_B2 SPI mode
Clock signal input – USCI_A2 SPI slave mode
Clock signal output – USCI_A2 SPI master mode
P9.0/UCB2STE/UCA2CLK
68
N/A
D11
I/O
General-purpose digital I/O
P9.1/UCB2SIMO/UCB2SDA
P9.2/UCB2SOMI/UCB2SCL
69
70
N/A
N/A
F9
I/O Slave in, master out – USCI_B2 SPI mode
I2C data – USCI_B2 I2C mode
General-purpose digital I/O
C12
I/O Slave out, master in – USCI_B2 SPI mode
I2C clock – USCI_B2 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B2 SPI slave mode
Clock signal output – USCI_B2 SPI master mode
P9.3/UCB2CLK/UCA2STE
71
N/A
E9
I/O
Slave transmit enable – USCI_A2 SPI mode
General-purpose digital I/O
P9.4/UCA2TXD/UCA2SIMO
P9.5/UCA2RXD/UCA2SOMI
72
73
N/A
N/A
C11
B12
I/O Transmit data – USCI_A2 UART mode
Slave in, master out – USCI_A2 SPI mode
General-purpose digital I/O
I/O Receive data – USCI_A2 UART mode
Slave out, master in – USCI_A2 SPI mode
P9.6
P9.7
74
75
N/A
N/A
B11
A12
I/O General-purpose digital I/O
I/O General-purpose digital I/O
General-purpose digital I/O
Slave transmit enable – USCI_B3 SPI mode
Clock signal input – USCI_A3 SPI slave mode
P10.0/UCB3STE/UCA3CLK
76
N/A
D9
I/O
Clock signal output – USCI_A3 SPI master mode
General-purpose digital I/O
P10.1/UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
77
78
N/A
N/A
A11
D8
I/O Slave in, master out – USCI_B3 SPI mode
I2C data – USCI_B3 I2C mode
General-purpose digital I/O
I/O Slave out, master in – USCI_B3 SPI mode
I2C clock – USCI_B3 I2C mode
General-purpose digital I/O
Clock signal input – USCI_B3 SPI slave mode
Clock signal output – USCI_B3 SPI master mode
P10.3/UCB3CLK/UCA3STE
79
N/A
B10
I/O
Slave transmit enable – USCI_A3 SPI mode
General-purpose digital I/O
P10.4/UCA3TXD/UCA3SIMO
P10.5/UCA3RXD/UCA3SOMI
80
81
N/A
N/A
A10
B9
I/O Transmit data – USCI_A3 UART mode
Slave in, master out – USCI_A3 SPI mode
General-purpose digital I/O
I/O Receive data – USCI_A3 UART mode
Slave out, master in – USCI_A3 SPI mode
P10.6
P10.7
82
83
N/A
N/A
A9
B8
I/O General-purpose digital I/O
I/O General-purpose digital I/O
General-purpose digital I/O
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P11.0/ACLK
P11.1/MCLK
P11.2/SMCLK
84
85
86
N/A
N/A
N/A
A8
D7
A7
I/O
General-purpose digital I/O
MCLK output
I/O
General-purpose digital I/O
SMCLK output
I/O
DVCC4
DVSS4
87
88
67
68
B7
B6
Digital power supply
Digital ground supply
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Table 7-1. Signal Descriptions (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
ZCA,
ZQW
PZ
89
90
91
92
93
94
95
PN
69
70
71
72
73
74
75
General-purpose digital I/O
Input terminal for crystal oscillator XT2
P5.2/XT2IN
A6
A5
D6
B5
A4
D5
B4
I/O
I/O
I
General-purpose digital I/O
Output terminal of crystal oscillator XT2
P5.3/XT2OUT
TEST/SBWTCK(4)
PJ.0/TDO(5)
Test mode pin – Selects four wire JTAG operation.
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
General-purpose digital I/O
JTAG test data output port
I/O
I/O
I/O
I/O
General-purpose digital I/O
JTAG test data input or test clock input
PJ.1/TDI/TCLK(5)
PJ.2/TMS(5)
General-purpose digital I/O
JTAG test mode select
General-purpose digital I/O
JTAG test clock
PJ.3/TCK(5)
Reset input active low(6)
I/O Nonmaskable interrupt input
RST/NMI/SBWTDIO(4)
96
76
A3
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated.
General-purpose digital I/O
Analog input A0 for the ADC
P6.0/A0
P6.1/A1
P6.2/A2
97
98
99
77
78
79
D4
B3
A2
I/O
I/O
I/O
I/O
General-purpose digital I/O
Analog input A1 for the ADC
General-purpose digital I/O
Analog input A2 for the ADC
General-purpose digital I/O
Analog input A3 for the ADC
P6.3/A3
100
N/A
80
B2
(2)
Reserved
N/A
(1) I = input, O = output, N/A = not available on this package offering
(2) C3, E5, E6, E7, E8, F5, F8, G5, G8, H5, H6, H7, H8 are reserved and should be connected to ground.
(3) VCORE is for internal use only. No external current loading is possible. VCORE should be connected to only the recommended
capacitor value, CVCORE
.
(4) See Section 9.5 and Section 9.6 for use with BSL and JTAG functions, respectively.
(5) See Section 9.6 for use with JTAG function.
(6) When this pin is configured as reset, the internal pullup resistor is enabled by default.
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8 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
MAX
UNIT
V
(1)
Voltage applied at VCC to VSS
4.1
Voltage applied to any pin (excluding VCORE)(2)
–0.3 VCC + 0.3
±2
V
Diode current at any device pin
mA
°C
(3)
Storage temperature, Tstg
–55
105
95
Maximum junction temperature, TJ
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
8.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.
8.3 Recommended Operating Conditions
MIN
NOM
MAX UNIT
Supply voltage during program execution and flash programming
VCC
1.8
3.6
V
(1) (2)
(AVCC = DVCC1/2/3/4 = DVCC
)
VSS
TA
Supply voltage (AVSS = DVSS1/2/3/4 = DVSS
Operating free-air temperature
)
0
V
–40
–40
85
85
°C
°C
nF
TJ
Operating junction temperature
CVCORE
Recommended capacitor at VCORE(3)
470
CDVCC
CVCORE
/
Capacitor ratio of DVCC to VCORE
10
PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V
PMMCOREVx = 1, 2.0 V ≤ VCC ≤ 3.6 V
PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V
PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V
0
0
0
0
8
12
20
25
Processor frequency (maximum MCLK
frequency)(4) (5) (see Figure 8-1)
fSYSTEM
MHz
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 8.23 threshold parameters for
the exact values and further details.
(3) A capacitor tolerance of ±20% or better is required.
(4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
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25
3
20
2, 3
2
12
8
1, 2
1, 2, 3
1
0
0, 1
0, 1, 2
0, 1, 2, 3
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.
Figure 8-1. Frequency vs Supply Voltage
8.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK
8 MHz 12 MHz 20 MHz
TYP MAX TYP MAX
)
EXECUTION
MEMORY
PARAMETER
VCC
PMMCOREVx
1 MHz
25 MHz
UNIT
TYP
MAX
TYP
MAX
TYP
8.90
4.50
MAX
9.60
4.90
0
1
2
3
0
1
2
3
0.29
0.32
0.33
0.35
0.17
0.18
0.19
0.20
0.33
1.84
2.08
2.24
2.36
0.88
1.00
1.13
1.20
2.08
3.10
3.50
3.70
IAM, Flash
Flash
3.0 V
mA
mA
6.37
6.75
0.19
0.99
1.47
1.68
1.78
IAM, RAM
RAM
3.0 V
2.82
3.00
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32768 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
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8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
–40°C
25°C
60°C
85°C
PARAMETER
VCC
PMMCOREVx
UNIT
TYP
MAX
93
TYP
MAX
93
TYP
MAX
93
TYP
MAX
93
2.2 V
3.0 V
2.2 V
3.0 V
0
3
0
3
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
69
73
69
73
69
73
69
73
ILPM0,1MHz
Low-power mode 0(3) (9)
Low-power mode 2(4) (9)
µA
100
15.5
17.5
100
15.5
17.5
100
15.5
17.5
100
15.5
17.5
11
11
11
11
ILPM2
µA
11.7
1.4
1.5
1.5
1.8
1.8
1.9
2.0
1.0
1.0
1.1
1.2
1.1
1.2
1.3
1.3
0.10
11.7
1.7
1.8
2.0
2.1
2.3
2.4
2.3
1.2
1.3
1.4
1.4
1.2
1.2
1.3
1.3
0.10
11.7
2.6
2.9
3.3
2.8
3.1
3.5
3.9
2.0
2.3
2.8
3.0
1.9
2.2
2.6
2.9
0.20
11.7
6.6
2.2 V
9.9
10.1
7.1
Low-power mode 3, crystal
mode(5) (9)
ILPM3,XT1LF
2.4
13.6
µA
µA
10.5
10.6
11.8
5.8
3.0 V
2.6
14.8
12.9
1.42
6.0
Low-power mode 3,
VLO mode(6) (9)
ILPM3,VLO
3.0 V
6.2
1.62
1.35
6.2
13.9
12.9
5.7
5.9
ILPM4
Low-power mode 4(7) (9)
Low-power mode 4.5(8)
3.0 V
3.0 V
µA
µA
6.1
1.52
0.13
6.2
13.9
1.14
ILPM4.5
0.50
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz,
DCO setting = 1 MHz operation, DCO bias generator enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(7) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(8) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) Current for brownout, high side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)
disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
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UNIT
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8.6 Thermal Resistance Characteristics
THERMAL METRIC
VALUE
50.1
57.9
60
LQFP (PZ)
Low-K board (JESD51-3)
High-K board (JESD51-7)
LQFP (PN)
BGA (ZQW)
LQFP (PZ)
LQFP (PN)
BGA (ZQW)
LQFP (PZ)
LQFP (PN)
BGA (ZQW)
RθJA Junction-to-ambient thermal resistance, still air
°C/W
°C/W
40.8
37.9
42
8.9
RθJC Junction-to-case thermal resistance
10.3
8
8.7 Schmitt-Trigger Inputs – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
0.80
1.50
0.45
0.75
0.3
TYP
MAX UNIT
1.40
V
2.10
VIT+
VIT–
Vhys
Positive-going input threshold voltage
1.8 V
3 V
1.00
V
1.65
Negative-going input threshold voltage
1.8 V
3 V
0.85
V
1.0
Input voltage hysteresis (VIT+ – VIT–
)
0.4
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI
Pullup or pulldown resistor(2)
Input capacitance
20
35
5
50
kΩ
pF
VIN = VSS or VCC
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to the RST pin when the pullup or pulldown resistor is enabled.
8.8 Inputs – Ports P1 and P2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
MIN
MAX UNIT
Port P1, P2: P1.x to P2.x, external trigger pulse
duration to set interrupt flag
t(int)
External interrupt timing(2)
2.2 V, 3 V
20
ns
(1) Some devices may contain additional ports with interrupts. See the block diagram (see Section 4) and signal descriptions (see Section
7.2).
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
8.9 Leakage Current – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See (1) (2)
VCC
MIN
MAX UNIT
Ilkg(Px.y)
High-impedance leakage current
1.8 V, 3 V
±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
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8.10 Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –10 mA(2)
I(OHmax) = –5 mA(1)
I(OHmax) = –15 mA(2)
I(OLmax) = 3 mA(1)
I(OLmax) = 10 mA(2)
I(OLmax) = 5 mA(1)
I(OLmax) = 15 mA(2)
VCC
VOH
High-level output voltage
V
VCC
3 V
1.8 V
3 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(1)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(1)
I(OLmax) = 3 mA(2)
I(OLmax) = 2 mA(1)
I(OLmax) = 6 mA(2)
VCC
VOH
High-level output voltage
V
VCC
3.0 V
1.8 V
3.0 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
(3) Selecting reduced drive strength may reduce EMI.
8.12 Output Frequency – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
VCC = 1.8 V,
PMMCOREVx = 0
16
Port output frequency
(with load)
fPx.y
P1.6/SMCLK (1) (2)
MHz
25
VCC = 3 V,
PMMCOREVx = 3
VCC = 1.8 V,
PMMCOREVx = 0
P1.0/TA0CLK/ACLK
P1.6/SMCLK
16
fPort_CLK
Clock output frequency
MHz
25
P2.0/TA1CLK/MCLK
VCC = 3 V,
PMMCOREVx = 3
CL = 20 pF(2)
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS
.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
25.0
20.0
15.0
10.0
5.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
TA = 25°C
TA = 85°C
VCC = 3.0 V
Px.y
VCC = 1.8 V
Px.y
TA = 25°C
TA = 85°C
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
Figure 8-3. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 8-2. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
0.0
VCC = 3.0 V
Px.y
VCC = 1.8 V
Px.y
−1.0
−5.0
−2.0
−3.0
−4.0
−10.0
TA = 85°C
−5.0
−15.0
TA = 85°C
−6.0
TA = 25°C
−20.0
TA = 25°C
−7.0
−8.0
−25.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
Figure 8-4. Typical High-Level Output Current vs
High-Level Output Voltage
Figure 8-5. Typical High-Level Output Current vs
High-Level Output Voltage
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8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
60.0
24
20
16
12
8
TA = 25°C
TA = 85°C
VCC = 1.8 V
Px.y
VCC = 3.0 V
Px.y
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
TA = 25°C
TA = 85°C
4
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
Figure 8-6. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 8-7. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
0
VCC = 1.8 V
Px.y
VCC = 3.0 V
−5.0
Px.y
−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−4
−8
−12
−45.0
TA = 85°C
−16
TA = 85°C
−50.0
−55.0
TA = 25°C
−60.0
TA = 25°C
−20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
Figure 8-8. Typical High-Level Output Current vs
High-Level Output Voltage
Figure 8-9. Typical High-Level Output Current vs
High-Level Output Voltage
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8.15 Crystal Oscillator, XT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
0.075
Differential XT1 oscillator crystal current fOSC = 32768 Hz, XTS = 0,
ΔIDVCC.LF
consumption from lowest drive setting,
LF mode
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
3.0 V
0.170
0.290
µA
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
XT1 oscillator crystal frequency,
LF mode
fXT1,LF0
XTS = 0, XT1BYPASS = 0
32768
32.768
Hz
XT1 oscillator logic-level square-wave
input frequency, LF mode
fXT1,LF,SW
XTS = 0, XT1BYPASS = 1(2) (3)
10
50
kHz
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
210
300
OALF
Oscillation allowance for LF crystals(4)
kΩ
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0(6)
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
Integrated effective load capacitance, LF
mode(5)
CL,eff
pF
8.5
12.0
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
30%
10
70%
fFault,LF
Oscillator fault frequency, LF mode(7)
XTS = 0(8)
10000
Hz
ms
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
1000
500
tSTART,LF
Start-up time, LF mode
3.0 V
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
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8.16 Crystal Oscillator, XT1, High-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C
200
fOSC = 12 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
260
325
450
IDVCC.HF
XT1 oscillator crystal current, HF mode
3.0 V
µA
fOSC = 20 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
fOSC = 32 MHz,
XTS = 1, XOSCOFF = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
XT1 oscillator crystal frequency,
HF mode 0
XTS = 1,
fXT1,HF0
fXT1,HF1
fXT1,HF2
fXT1,HF3
fXT1,HF,SW
4
8
8
16
24
32
32
MHz
MHz
MHz
MHz
MHz
XT1BYPASS = 0, XT1DRIVEx = 0(2)
XT1 oscillator crystal frequency,
HF mode 1
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1(2)
XT1 oscillator crystal frequency,
HF mode 2
XTS = 1,
16
24
0.7
XT1BYPASS = 0, XT1DRIVEx = 2(2)
XT1 oscillator crystal frequency,
HF mode 3
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3(2)
XT1 oscillator logic-level square-wave
XTS = 1,
input frequency, HF mode, bypass mode XT1BYPASS = 1(3) (2)
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,HF = 6 MHz, CL,eff = 15 pF
450
320
200
200
0.5
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,HF = 12 MHz, CL,eff = 15 pF
OAHF
Oscillation allowance for HF crystals(4)
Ω
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2,
fXT1,HF = 20 MHz, CL,eff = 15 pF
XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 3,
fXT1,HF = 32 MHz, CL,eff = 15 pF
fOSC = 6 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
tSTART,HF
Start-up time, HF mode
3.0 V
ms
fOSC = 20 MHz, XTS = 1,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
0.3
Integrated effective load capacitance,
HF mode(5) (6)
CL,eff
XTS = 1
1
pF
XTS = 1, Measured at ACLK,
fXT1,HF2 = 20 MHz
Duty cycle, HF mode
40%
30
50%
60%
300
fFault,HF
Oscillator fault frequency, HF mode(7)
XTS = 1(8)
kHz
(1) To improve EMI on the XT1 oscillator the following guidelines should be observed.
•
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
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(3) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance
of up to 18 pF can be supported.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
8.17 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C
200
fOSC = 12 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 1,
TA = 25°C
260
325
450
XT2 oscillator crystal current
consumption
IDVCC.XT2
3.0 V
µA
fOSC = 20 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C
fOSC = 32 MHz, XT2OFF = 0,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C
XT2 oscillator crystal frequency,
mode 0
fXT2,HF0
fXT2,HF1
fXT2,HF2
fXT2,HF3
fXT2,HF,SW
XT2DRIVEx = 0, XT2BYPASS = 0(3)
XT2DRIVEx = 1, XT2BYPASS = 0(3)
XT2DRIVEx = 2, XT2BYPASS = 0(3)
XT2DRIVEx = 3, XT2BYPASS = 0(3)
XT2BYPASS = 1(4) (3)
4
8
8
MHz
XT2 oscillator crystal frequency,
mode 1
16 MHz
24 MHz
32 MHz
32 MHz
XT2 oscillator crystal frequency,
mode 2
16
24
0.7
XT2 oscillator crystal frequency,
mode 3
XT2 oscillator logic-level square-
wave input frequency, bypass mode
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
450
320
200
200
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
Oscillation allowance for
HF crystals(5)
OAHF
Ω
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
fOSC = 6 MHz,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
0.5
0.3
tSTART,HF
Start-up time
3.0 V
ms
pF
fOSC = 20 MHz,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
Integrated effective load
CL,eff
1
capacitance, HF mode(6) (1)
Duty cycle
Measured at ACLK, fXT2,HF2 = 20 MHz
XT2BYPASS = 1(8)
40%
30
50%
60%
300 kHz
fFault,HF
Oscillator fault frequency(7)
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance
of up to 18 pF can be supported.
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(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.
•
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
8.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
MIN
TYP
9.4
0.5
4
MAX UNIT
14 kHz
%/°C
fVLO
Measured at ACLK
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
6
dfVLO/dT
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
%/V
40%
50%
60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
8.19 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
IREFO
REFO oscillator current consumption TA = 25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
3 V
3
µA
REFO frequency calibrated
Measured at ACLK
32768
Hz
fREFO
Full temperature range
TA = 25°C
±3.5%
±1.5%
%/°C
%/V
REFO absolute tolerance calibrated
dfREFO/dT
REFO frequency temperature drift
Measured at ACLK(1)
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
0.01
1.0
dfREFO/dVCC
REFO frequency supply voltage drift Measured at ACLK(2)
Duty cycle
Measured at ACLK
40%/60% duty cycle
40%
50%
25
60%
tSTART
REFO start-up time
µs
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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8.20 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
MIN
0.07
0.70
0.15
1.47
0.32
3.17
0.64
6.07
1.3
TYP
MAX UNIT
0.20 MHz
1.70 MHz
0.36 MHz
3.45 MHz
0.75 MHz
7.38 MHz
1.51 MHz
14.0 MHz
3.2 MHz
fDCO(0,0)
fDCO(0,31)
fDCO(1,0)
fDCO(1,31)
fDCO(2,0)
fDCO(2,31)
fDCO(3,0)
fDCO(3,31)
fDCO(4,0)
fDCO(4,31)
fDCO(5,0)
fDCO(5,31)
fDCO(6,0)
fDCO(6,31)
fDCO(7,0)
fDCO(7,31)
DCO frequency (0, 0)(1)
DCO frequency (0, 31)(1)
DCO frequency (1, 0)(1)
DCO frequency (1, 31)(1)
DCO frequency (2, 0)(1)
DCO frequency (2, 31)(1)
DCO frequency (3, 0)(1)
DCO frequency (3, 31)(1)
DCO frequency (4, 0)(1)
DCO frequency (4, 31)(1)
DCO frequency (5, 0)(1)
DCO frequency (5, 31)(1)
DCO frequency (6, 0)(1)
DCO frequency (6, 31)(1)
DCO frequency (7, 0)(1)
DCO frequency (7, 31)(1)
12.3
2.5
28.2 MHz
6.0 MHz
23.7
4.6
54.1 MHz
10.7 MHz
88.0 MHz
19.6 MHz
135 MHz
39.0
8.5
60
Frequency step between range
DCORSEL and DCORSEL + 1
SDCORSEL
SDCO
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3 ratio
Frequency step between tap DCO
and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
Measured at SMCLK
1.02
40%
1.12 ratio
Duty cycle
50%
0.1
60%
%/°C
%/V
dfDCO/dT
DCO frequency temperature drift(2) fDCO = 1 MHz
DCO frequency voltage drift(3)
fDCO = 1 MHz
dfDCO/dVCC
1.9
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(3) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
100
VCC = 3.0 V
TA = 25°C
10
DCOx = 31
1
DCOx = 0
0.1
0
1
2
3
4
5
6
7
DCORSEL
Figure 8-10. Typical DCO Frequency
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8.21 PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s
MIN
TYP
MAX UNIT
V(DVCC_BOR_IT–)
V(DVCC_BOR_IT+)
V(DVCC_BOR_hys)
BORH on voltage, DVCC falling level
BORH off voltage, DVCC rising level
BORH hysteresis
1.45
1.50
V
V
0.80
50
1.30
250 mV
µs
Pulse duration required at RST/NMI pin to
accept a reset
tRESET
2
8.22 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Core voltage, active mode,
PMMCOREV = 3
VCORE3(AM)
VCORE2(AM)
VCORE1(AM)
VCORE0(AM)
VCORE3(LPM)
VCORE2(LPM)
VCORE1(LPM)
VCORE0(LPM)
2.4 V ≤ DVCC ≤ 3.6 V
1.90
V
Core voltage, active mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
2.4 V ≤ DVCC ≤ 3.6 V
2.2 V ≤ DVCC ≤ 3.6 V
2.0 V ≤ DVCC ≤ 3.6 V
1.8 V ≤ DVCC ≤ 3.6 V
1.80
1.60
1.40
1.94
1.84
1.64
1.44
V
V
V
V
V
V
V
Core voltage, active mode,
PMMCOREV = 1
Core voltage, active mode,
PMMCOREV = 0
Core voltage, low-current mode,
PMMCOREV = 3
Core voltage, low-current mode,
PMMCOREV = 2
Core voltage, low-current mode,
PMMCOREV = 1
Core voltage, low-current mode,
PMMCOREV = 0
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8.23 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SVSHE = 0, DVCC = 3.6 V
0
nA
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
SVSHE = 1, SVSHRVL = 0
200
1.5
1.68
1.88
2.08
2.18
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
2.5
µA
1.57
1.79
1.98
2.10
1.62
1.88
2.07
2.20
2.32
2.52
2.90
2.90
1.78
1.98
2.21
2.31
1.85
2.07
2.28
2.42
2.55
2.88
3.23
3.23
SVSHE = 1, SVSHRVL = 1
V(SVSH_IT–)
SVSH on voltage level(1)
V
SVSHE = 1, SVSHRVL = 2
SVSHE = 1, SVSHRVL = 3
SVSHE = 1, SVSMHRRL = 0
SVSHE = 1, SVSMHRRL = 1
SVSHE = 1, SVSMHRRL = 2
SVSHE = 1, SVSMHRRL = 3
V(SVSH_IT+)
SVSH off voltage level(1)
V
SVSHE = 1, SVSMHRRL = 4
SVSHE = 1, SVSMHRRL = 5
SVSHE = 1, SVSMHRRL = 6
SVSHE = 1, SVSMHRRL = 7
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
SVSHE = 0 → 1, SVSHFP = 1
SVSHE = 0 → 1, SVSHFP = 0
tpd(SVSH)
SVSH propagation delay
µs
µs
20
12.5
100
t(SVSH)
SVSH on or off delay time
DVCC rise time
dVDVCC/dt
0
1000 V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use.
8.24 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SVMHE = 0, DVCC = 3.6 V
0
nA
µA
I(SVMH)
SVMH current consumption
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
200
1.5
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
3.75
2.5
1.62
1.88
2.07
2.20
2.32
2.52
2.90
2.90
1.85
2.07
2.28
2.42
2.55
2.88
3.23
3.23
SVMHE = 1, SVSMHRRL = 1
SVMHE = 1, SVSMHRRL = 2
SVMHE = 1, SVSMHRRL = 3
V(SVMH)
SVMH on or off voltage level(1)
SVMHE = 1, SVSMHRRL = 4
V
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
SVMHE = 0 → 1, SVMHFP = 1
SVMHE = 0 → 1, SVMHFP = 0
tpd(SVMH)
SVMH propagation delay
SVMH on or off delay time
µs
µs
20
12.5
100
t(SVMH)
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use.
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8.25 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SVSLE = 0, PMMCOREV = 2
0
nA
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
1.5
2.5
µA
µs
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
tpd(SVSL)
SVSL propagation delay
SVSL on or off delay time
20
12.5
100
t(SVSL)
µs
8.26 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SVMLE = 0, PMMCOREV = 2
0
nA
I(SVML)
SVML current consumption
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
200
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
1.5
2.5
µA
µs
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
tpd(SVML)
SVML propagation delay
SVML on or off delay time
20
12.5
100
t(SVML)
µs
8.27 Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
fMCLK ≥ 4.0 MHz
3.5
7.5
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-FAST
µs
9
1.0 MHz < fMCLK
< 4.0 MHz
4.5
Wake-up time from LPM2,
LPM3 or LPM4 to active
mode(2) (3)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-SLOW
150
165
µs
Wake-up time from LPM4.5 to
active mode(4)
tWAKE-UP-LPM5
tWAKE-UP-RESET
2
2
3
3
ms
ms
Wake-up time from RST or
BOR event to active mode(4)
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in
full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx
Family User's Guide.
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in
normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx
Family User's Guide.
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by
the performance mode settings as for LPM2, LPM3, and LPM4.
(4) This value represents the time from the wake-up event to the reset vector execution.
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8.28 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
fTA
Timer_A input clock frequency
External: TACLK,
1.8 V, 3.0 V
25 MHz
Duty cycle = 50% ±10%
All capture inputs,
Minimum pulse duration required for capture
tTA,cap
Timer_A capture timing
1.8 V, 3.0 V
20
ns
8.29 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
fTB
Timer_B input clock frequency
External: TBCLK,
1.8 V, 3.0 V
25 MHz
Duty cycle = 50% ±10%
All capture inputs, minimum pulse duration
required for capture
tTB,cap Timer_B capture timing
1.8 V, 3.0 V
20
ns
8.30 USCI (UART Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
Internal: SMCLK or ACLK,
External: UCLK,
Duty cycle = 50% ±10%
MIN
MAX UNIT
fUSCI
USCI input clock frequency
fSYSTEM MHz
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
1
MHz
8.31 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
2.2 V
3 V
MIN
MAX UNIT
50
600
ns
600
tτ
UART receive deglitch time(1)
50
(1) Pulses on the UART receive input (UCxRX) that are shorter than the UART receive deglitch time are suppressed. To make sure that
pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.
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8.32 USCI (SPI Master Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
Internal: SMCLK or ACLK,
Duty cycle = 50% ±10%
MIN
MAX UNIT
fUSCI
USCI input clock frequency
fSYSTEM MHz
8.33 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-11 and Figure 8-12)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
SMCLK or ACLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
PMMCOREV = 0
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
55
38
30
25
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time(2)
SIMO output data hold time(3)
ns
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
0
tHD,MI
ns
0
0
20
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
18
ns
16
tVALID,MO
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
15
–10
–8
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
tHD,MO
ns
–10
–8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-11 and Figure 8-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure
8-11 and Figure 8-12.
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 8-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 8-12. SPI Master Mode, CKPH = 1
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8.34 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-13 and Figure 8-14)
PARAMETER
TEST CONDITIONS
VCC
MIN
11
8
MAX UNIT
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
PMMCOREV = 0
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE low to clock
ns
7
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
6
3
3
STE lag time, Last clock to STE high
ns
3
3
66
50
ns
36
STE access time, STE low to SOMI data out
30
30
23
ns
16
STE disable time, STE high to SOMI high
impedance
13
5
5
2
2
5
5
5
5
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
SOMI output data hold time(3)
ns
tHD,SI
ns
76
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0
60
ns
44
tVALID,SO
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3
40
18
12
10
8
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
tHD,SO
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-13 and Figure 8-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure
8-13 and Figure 8-14.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tSU,SI
tLO/HI
tLO/HI
tHD,SI
SIMO
SOMI
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 8-13. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
SOMI
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 8-14. SPI Slave Mode, CKPH = 1
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8.35 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 8-15)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2.2 V, 3 V
2.2 V, 3 V
0
4.0
0.6
4.7
0.6
0
400
kHz
µs
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2.2 V, 3 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V, 3 V
2.2 V, 3 V
ns
ns
250
4.0
0.6
50
fSCL ≤ 100 kHz
fSCL > 100 kHz
tSU,STO
Setup time for STOP
2.2 V, 3 V
µs
ns
2.2 V
3 V
600
600
tSP
Pulse duration of spikes suppressed by input filter
50
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 8-15. I2C Mode Timing
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8.36 12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
0
TYP
MAX UNIT
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
Analog supply voltage
Analog input voltage range(2)
3.6
V
V(Ax)
All ADC12 analog input pins Ax
fADC12CLK = 5.0 MHz(4)
AVCC
155
V
2.2 V
3 V
125
150
Operating supply current into
AVCC terminal(3)
IADC12_A
µA
220
Only one terminal Ax can be selected at one
time
CI
RI
Input capacitance
2.2 V
20
25
pF
Ω
Input MUX ON-resistance
0 V ≤ VAx ≤ AVCC
10
200
1900
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See Section 8.41 and Section 8.42.
(3) The internal reference supply current is not included in current consumption parameter IADC12_A
(4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0.
.
8.37 12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC12 linearity
parameters using an external reference voltage
or AVCC as reference(1)
0.45
4.8
5.0
ADC conversion
clock
fADC12CLK
For specified performance of ADC12 linearity
parameters using the internal reference(2)
2.2 V, 3 V
MHz
4.0
0.45
0.45
4.2
2.4
2.4
4.8
For specified performance of ADC12 linearity
parameters using the internal reference(3)
2.7
Internal ADC12
oscillator(4)
fADC12OSC
tCONVERT
tSample
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
2.2 V, 3 V
5.4 MHz
REFON = 0, Internal oscillator,
ADC12OSC used for ADC conversion clock
2.4
3.1
µs
Conversion time
Sampling time
External fADC12CLK from ACLK, MCLK, or
SMCLK, ADC12SSEL ≠ 0
13 ×
1 / fADC12CLK
RS = 400 Ω, RI = 1000 Ω, CI = 20 pF,
2.2 V, 3 V
1000
ns
(5)
τ = (RS + RI) × CI
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(5) Approximately 10 Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
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8.38 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as
Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Integral linearity error(1)
Differential linearity error(1)
Offset error(3)
TEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V(2)
VCC
MIN
TYP
MAX UNIT
±2.0
LSB
±1.7
EI
2.2 V, 3 V
1.6 V < dVREF(2)
(2)
ED
EO
EG
ET
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
±1.0 LSB
dVREF ≤ 2.2 V(2)
±1.0
±1.0
±1.0
±1.4
±1.4
±2.0
LSB
±2.0
dVREF > 2.2 V(2)
Gain error(3)
±2.0 LSB
(2)
dVREF ≤ 2.2 V(2)
dVREF > 2.2 V(2)
±3.5
LSB
±3.5
Total unadjusted error
(1) Parameters are derived using the histogram method.
(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ – VR–, VR+ < AVCC, VR–
>
AVSS. Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω, and two decoupling
capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current. See also the MSP430x5xx and
MSP430x6xx Family User's Guide.
(3) Parameters are derived using a best fit curve.
8.39 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
VCC
MIN
TYP
MAX UNIT
ADC12SR = 0, REFOUT = 1
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 4.0 MHz
fADC12CLK ≤ 2.7 MHz
fADC12CLK ≤ 4.0 MHz
±1.7
LSB
±2.5
Integral linearity
error(2)
EI
2.2 V, 3 V
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
ADC12SR = 0, REFOUT = 0
ADC12SR = 0, REFOUT = 1
–1.0
–1.0
–1.0
+1.5
Differential
ED
2.2 V, 3 V
+1.0 LSB
+2.5
linearity error(2)
±2.0
±2.0
±1.0
±4.0
LSB
±4.0
EO
EG
Offset error(3)
Gain error(3)
2.2 V, 3 V
2.2 V, 3 V
±2.5 LSB
±1.5%(4) VREF
±5 LSB
Total
±2
ET
unadjusted
error
2.2 V, 3 V
ADC12SR = 0, REFOUT = 0
fADC12CLK ≤ 2.7 MHz
±1.5%(4) VREF
(1) The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+ – VR–
.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.
(4) The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this
mode the reference voltage used by the ADC12_A is not available on a pin.
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8.40 12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
TYP
680
680
2.25
2.25
MAX UNIT
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
VSENSOR
See (2)
mV
2.2 V
3 V
TCSENSOR
ADC12ON = 1, INCH = 0Ah
mV/°C
2.2 V
3 V
100
100
Sample time required if
channel 10 is selected(3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
tSENSOR(sample)
µs
AVCC divider at channel 11,
VAVCC factor
ADC12ON = 1, INCH = 0Bh
ADC12ON = 1, INCH = 0Bh
0.48
0.5
0.52 VAVCC
VMID
2.2 V
3 V
1.06
1.44
1.1
1.5
1.14
V
1.56
AVCC divider at channel 11
Sample time required if
channel 11 is selected(4)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
tVMID(sample)
2.2 V, 3 V
1000
ns
(1) The temperature sensor is provided by the REF module. See the REF module parametric IREF+ regarding the current consumption of
the temperature sensor.
(2) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor. The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference
voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and
VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430x5xx and MSP430x6xx Family User's
Guide.
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor on time, tSENSOR(on)
.
(4) The on time (tVMID(on)) is included in the sampling time (tVMID(sample)); no additional on time is needed.
1000
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10
0 10 20 30 40 50 60 70 80
Ambient Temperature (°C)
Figure 8-16. Typical Temperature Sensor Voltage
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8.41 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Positive external reference
voltage input
(2)
VeREF+
VeREF+ > VREF–/VeREF–
1.4
AVCC
1.2
V
V
V
Negative external reference
voltage input
(3)
VREF–/VeREF–
VeREF+ > VREF–/VeREF–
0
(VeREF+
VREF–/VeREF–
–
Differential external reference
voltage input
(4)
VeREF+ > VREF–/VeREF–
1.4 V ≤ VeREF+ ≤ VAVCC
1.4
AVCC
)
,
VeREF– = 0 V, fADC12CLK = 5 MHz,
ADC12SHTx = 1h,
Conversion rate 200 ksps
2.2 V, 3 V
2.2 V, 3 V
–26
26
1
IVeREF+,
IVREF–/VeREF–
Static input current
µA
µF
1.4 V ≤ VeREF+ ≤ VAVCC
,
VeREF– = 0 V, fADC12CLK = 5 MHz,
ADC12SHTx = 8h,
Conversion rate 20 ksps
–1
10
Capacitance at VREF+ or VREF-
terminals
CVREF+/-
See (5)
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is
also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide.
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8.42 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
REFVSEL = {2} for 2.5 V,
REFON = REFOUT = 1, IVREF+= 0 A
3 V
2.50 ±1.5%
1.98 ±1.5%
1.49 ±1.5%
Positive built-in reference
voltage output
REFVSEL = {1} for 2.0 V,
REFON = REFOUT = 1, IVREF+= 0 A
VREF+
3 V
V
V
REFVSEL = {0} for 1.5 V,
REFON = REFOUT = 1, IVREF+= 0 A
2.2 V, 3 V
REFVSEL = {0} for 1.5 V
REFVSEL = {1} for 2.0 V
REFVSEL = {2} for 2.5 V
2.2
2.3
2.8
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
ADC12SR = 1, REFON = 1, REFOUT = 0,
REFBURST = 0
3 V
3 V
3 V
3 V
70
0.45
210
100
0.75
310
1.7
µA
mA
µA
ADC12SR = 1, REFON = 1, REFOUT = 1,
REFBURST = 0
Operating supply current into
AVCC terminal(2) (3)
IREF+
ADC12SR = 0, REFON = 1, REFOUT = 0,
REFBURST = 0
ADC12SR = 0, REFON = 1, REFOUT = 1,
REFBURST = 0
0.95
mA
REFVSEL = {0, 1, 2}
Load-current regulation,
VREF+ terminal(4)
IVREF+ = +10 µA or –1000 µA
AVCC = AVCC (min) for each reference level,
REFVSEL = {0, 1, 2}, REFON = REFOUT = 1
IL(VREF+)
2500 µV/mA
Capacitance at VREF+
terminals
CVREF+
REFON = REFOUT = 1
20
100
50
pF
IVREF+ = 0 A,
REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
Temperature coefficient of
built-in reference(5)
ppm/
°C
TCREF+
30
AVCC = AVCC (min) to AVCC(max), TA = 25°C,
REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
Power supply rejection ratio
(DC)
PSRR_DC
PSRR_AC
120
300 µV/V
mV/V
AVCC = AVCC (min) to AVCC(max), TA = 25°C,
Power supply rejection ratio f = 1 kHz, ΔVpp = 100 mV,
6.4
75
75
(AC)
REFVSEL = {0, 1, 2}, REFON = 1,
REFOUT = 0 or 1
AVCC = AVCC (min) to AVCC(max)
,
REFVSEL = {0, 1, 2}, REFOUT = 0,
REFON = 0 → 1
Settling time of reference
voltage(6)
tSETTLE
µs
AVCC = AVCC (min) to AVCC(max)
,
CVREF = CVREF(max),
REFVSEL = {0, 1, 2}, REFOUT = 1,
REFON = 0 → 1
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers,
one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal and is
used as the reference for the conversion and uses the larger buffer. When REFOUT = 0, the reference is only used as the reference
for the conversion and uses the smaller buffer.
(2) The internal reference current is supplied from the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
(3) The temperature sensor is provided by the REF module. Its current is supplied from the AVCC terminal and is equivalent to IREF+ with
REFON = 1 and REFOUT = 0.
(4) Contribution only due to the reference and buffer including package. This does not include resistance due to the PCB traces or other
application factors.
(5) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(6) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.
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8.43 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
MAX UNIT
DVCC(PGM/ERASE) Program and erase supply voltage
1.8
3.6
5
V
mA
IPGM
Average supply current from DVCC during program
3
6
6
IERASE
Average supply current from DVCC during erase
Average supply current from DVCC during mass erase or bank erase
Cumulative program time(1)
15
15
16
mA
IMERASE, IBANK
tCPT
mA
ms
Program and erase endurance
104
100
64
105
cycles
years
µs
tRetention
tWord
Data retention duration
25°C
Word or byte program time(2)
85
65
tBlock, 0
Block program time for first byte or word(2)
49
µs
Block program time for each additional byte or word, except for last byte
or word(2)
tBlock, 1–(N–1)
37
49
µs
tBlock, N
tErase
Block program time for last byte or word(2)
55
23
73
32
µs
Erase time for segment, mass erase, and bank erase when available(2)
ms
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
fMCLK,MGR
0
1
MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
(2) These values are hardwired into the state machine of the flash controller.
8.44 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0
20 MHz
tSBW,Low
tSBW, En
tSBW,Rst
Spy-Bi-Wire low clock pulse duration
0.025
15
1
µs
µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1)
Spy-Bi-Wire return to normal operation time
15
0
100
5
µs
2.2 V
3 V
MHz
fTCK
TCK input frequency, 4-wire JTAG(2)
Internal pulldown resistance on TEST
0
10 MHz
80 kΩ
Rinternal
2.2 V, 3 V
45
60
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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9 Detailed Description
9.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are
general-purpose registers (see Figure 9-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed with
all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Program Counter
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Figure 9-1. Integrated CPU Registers
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9.2 Operating Modes
These microcontrollers have one active mode and six software-selectable low-power modes of operation. An
interrupt event can wake up the device from any of the low-power modes, service the request, and restore back
to the low-power mode on return from the interrupt program.
Software can configure the following operating modes:
•
Active mode (AM)
– All clocks are active
•
Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active
– MCLK is disabled
– FLL loop control remains active
Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active
– MCLK is disabled
Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
•
•
•
•
Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
•
Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wake-up input from RST or digital I/O
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9.3 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table
9-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 9-1. Interrupt Sources, Flags, and Vectors
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
PRIORITY
System Reset
Power up
External reset
WDTIFG, KEYV (SYSRSTIV)(1) (3)
Reset
0FFFEh
63, highest
Watchdog time-out, password violation
Flash memory password violation
PMM password violation
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG,
VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
62
61
(1)
User NMI
NMI
Oscillator fault
NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(1) (3)
TBCCR0 CCIFG0 (2)
Flash memory access violation
TB0
TB0
Maskable
Maskable
0FFF8h
0FFF6h
60
59
TBCCR1 CCIFG1 to TBCCR6 CCIFG6,
TBIFG (TBIV)(1) (2)
Watchdog timer interval timer mode
USCI_A0 receive and transmit
USCI_B0 receive and transmit
ADC12_A
WDTIFG
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
58
57
56
55
54
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (2)
UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (2)
ADC12IFG0 to ADC12IFG15 (ADC12IV)(1) (2)
TA0CCR0 CCIFG0(2)
TA0
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1) (2)
TA0
Maskable
0FFEAh
53
USCI_A2 receive and transmit
UCA2RXIFG, UCA2TXIFG (UCA2IV)(1) (2)
UCB2RXIFG, UCB2TXIFG (UCB2IV)(1) (2)
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (2)
TA1CCR0 CCIFG0(2)
Maskable
Maskable
Maskable
Maskable
0FFE8h
0FFE6h
0FFE4h
0FFE2h
52
51
50
49
USCI_B2 receive and transmit
DMA
TA1
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1) (2)
TA1
Maskable
0FFE0h
48
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV)(1) (2)
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (2)
UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (2)
UCA3RXIFG, UCA3TXIFG (UCA3IV)(1) (2)
UCB3RXIFG, UCB3TXIFG (UCB3IV)(1) (2)
P2IFG.0 to P2IFG.7 (P2IV)(1) (2)
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFDEh
0FFDCh
0FFDAh
0FFD8h
0FFD6h
0FFD4h
47
46
45
44
43
42
USCI_A1 receive and transmit
USCI_B1 receive and transmit
USCI_A3 receive and transmit
USCI_B3 receive and transmit
I/O Port P2
RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG,
RT1PSIFG (RTCIV)(1) (2)
RTC_A
Maskable
0FFD2h
41
0FFD0h
⋮
40
Reserved
Reserved(4)
⋮
0FF80h
0, lowest
(1) Multiple source flags
(2) Interrupt flags are in the module.
(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To
maintain compatibility with other devices, TI recommends reserving these locations.
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9.4 Memory Organization
Table 9-2 summarizes the memory map for all devices.
Table 9-2. Memory Organization
MSP430F5419A
MSP430F5418A
MSP430F5436A
MSP430F5435A
MSP430F5438A
MSP430F5437A
Memory (flash)
Main: interrupt vector
Main: code memory
Total Size
Flash
128KB
00FFFFh to 00FF80h
025BFFh to 005C00h
192KB
00FFFFh to 00FF80h
035BFFh to 005C00h
256KB
00FFFFh to 00FF80h
045BFFh to 005C00h
Flash
23KB
035BFFh to 030000h
64KB
03FFFFh to 030000h
Bank D
Bank C
Bank B
N/A
23KB
025BFFh to 020000h
64KB
02FFFFh to 020000h
64KB
02FFFFh to 020000h
Main: code memory
64KB
01FFFFh to 010000h
64KB
01FFFFh to 010000h
64KB
01FFFFh to 010000h
64KB
045BFFh to 040000h
00FFFFh to 005C00h
41KB
00FFFFh to 005C00h
41KB
00FFFFh to 005C00h
Bank A
Size
16 KB
16KB
16KB
4KB
4KB
4KB
Sector 3
005BFFh to 004C00h
005BFFh to 004C00h
005BFFh to 004C00h
4KB
4KB
4KB
Sector 2
Sector 1
Sector 0
Info A
RAM
004BFFh to 003C00h
004BFFh to 003C00h
004BFFh to 003C00h
4KB
4KB
4KB
003BFFh to 002C00h
003BFFh to 002C00h
003BFFh to 002C00h
4KB
4KB
4KB
002BFFh to 001C00h
002BFFh to 001C00h
002BFFh to 001C00h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
0019FFh to 001980h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
128 B
00197Fh to 001900h
Info B
Information memory
(flash)
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
128 B
0018FFh to 001880h
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
Size
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
128 B
00187Fh to 001800h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0017FFh to 001600h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
512 B
0015FFh to 001400h
Bootloader (BSL)
memory (flash)
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0013FFh to 001200h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
512 B
0011FFh to 001000h
4KB
4KB
4KB
Peripherals
000FFFh to 000000h
000FFFh to 000000h
000FFFh to 000000h
9.5 Bootloader (BSL)
The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the
device memory through the BSL is protected by an user-defined password. Table 9-3 lists the BSL pin
requirements. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK
pins. For complete description of the features of the BSL and its implementation, see MSP430 Memory
Programming With the Bootloader (BSL).
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Table 9-3. BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.1
P1.2
VCC
VSS
Data receive
Power supply
Ground supply
9.6 JTAG Operation
9.6.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. Table 9-4 lists the JTAG pin requirements. For further details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For
complete description of the features of the JTAG interface and its implementation, see MSP430 Memory
Programming With the JTAG Interface.
Table 9-4. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
PJ.3/TCK
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
IN
Power supply
VSS
Ground supply
9.6.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 microcontrollers support the 2-wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table
9-5 lists the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide. For the description of the Spy-Bi-Wire
interface and its implementation, see the MSP430 Memory Programming With the JTAG Interface.
Table 9-5. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
IN
IN, OUT
VSS
Ground supply
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9.7 Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
•
•
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually. Segments A to D are also called information memory.
Segment A can be locked separately.
9.8 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all
data are lost. Features of the RAM include:
•
•
•
•
RAM has n sectors. The size of a sector can be found in Section 9.4.
Each sector 0 to n can be complete disabled; however, data retention is lost.
Each sector 0 to n automatically enters low-power retention mode when possible.
For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
9.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled
using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's
Guide.
9.9.1 Digital I/O
Up to ten 8-bit I/O ports are implemented: For 100- and 113-pin options, P1 through P10 are complete, and P11
contains three individual I/O ports. For 80-pin options, P1 through P7 are complete, P8 contains seven individual
I/O ports, and P9 through P11 do not exist. Port PJ contains four individual I/O ports, common to all devices.
•
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Drive strength on all ports is programmable.
Edge-selectable interrupt and LPM4.5 wake-up input capability is available for all bits of ports P1 and P2.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P11) or word-wise in pairs (PA through PF).
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9.9.2 Oscillator and System Clock
The clock system is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz
watch crystal oscillator (XT1 LF mode), an internal very-low-power low-frequency oscillator (VLO), an internal
trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-
frequency crystal oscillator (XT1 HF mode or XT2). The UCS module is designed to meet the requirements of
both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL)
hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple
of the selected FLL reference frequency. The internal DCO provides a fast turnon clock source and stabilizes in
less than 5 µs. The UCS module provides the following clock signals:
•
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal, a high-frequency crystal, the internal low-
frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally controlled
oscillator (DCO).
•
•
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
9.9.3 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power on and power off. The SVS
and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
9.9.4 Hardware Multiplier (MPY)
The multiplication operation is supported by a dedicated peripheral module. The module performs operations
with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed
and unsigned multiply-and-accumulate operations.
9.9.5 Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-
time clock (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be
cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode
integrates an internal calendar which compensates for months with less than 31 days and includes leap year
correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
9.9.6 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
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9.9.7 System Module (SYS)
The SYS module handles many of the system functions within the device. These functions include power on
reset and power up clear handling, NMI source selection and management, reset interrupt vector generators,
bootloader entry mechanisms, and configuration management (device descriptors). SYS also includes a data
exchange mechanism through JTAG called a JTAG mailbox that can be used in the application. Table 9-6
summarizes the SYS module interrupt vector registers.
Table 9-6. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
ADDRESS
INTERRUPT EVENT
No interrupt pending
Brownout (BOR)
RST/NMI (POR)
PMMSWBOR (BOR)
Wake up from LPMx.5
Security violation (BOR)
SVSL (POR)
VALUE
00h
PRIORITY
02h
Highest
04h
06h
08h
0Ah
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
PMMSWPOR (POR)
WDT time-out (PUC)
WDT password violation (PUC)
KEYV flash password violation (PUC)
Reserved
10h
SYSRSTIV, System Reset
019Eh
12h
14h
16h
18h
1Ah
1Ch
Peripheral area fetch (PUC)
PMM password violation (PUC)
Reserved
1Eh
20h
22h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVMLIFG
02h
SVMHIFG
04h
SVSMLDLYIFG
SVSMHDLYIFG
VMAIFG
06h
08h
SYSSNIV, System NMI
019Ch
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
SVMHVLRIFG
12h
Reserved
14h to 1Eh
00h
Lowest
Highest
No interrupt pending
NMIIFG
02h
OFIFG
04h
SYSUNIV, User NMI
019Ah
ACCVIFG
06h
Reserved
08h
Reserved
0Ah to 1Eh
Lowest
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9.9.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM.
Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces
system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move
data to or from a peripheral. Table 9-7 lists the available DMA triggers.
Table 9-7. DMA Trigger Assignments
CHANNEL
TRIGGER(1)
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
2
3
4
5
6
7
8
Reserved
Reserved
Reserved
9
Reserved
Reserved
Reserved
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC12IFGx
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC12IFGx
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC12IFGx
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MPY ready
DMA2IFG
MPY ready
DMA0IFG
MPY ready
DMA1IFG
DMAE0
DMAE0
DMAE0
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not
cause any DMA trigger event when selected.
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9.9.9 Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocols such
as UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI module contains two
portions, A and B.
The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I2C.
The MSP430F5438A, MSP430F5436A, and MSP430F5419A include four complete USCI modules (n = 0 to 3).
The MSP430F5437A, MSP430F5435A, and MSP430F5418A include two complete USCI modules (n = 0 or 1).
9.9.10 TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 9-8). TA0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers. Table 9-8 lists the available signal connections.
Table 9-8. TA0 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
PZ, ZCA,
PN
PZ, ZCA, ZQW
PN
ZQW
17, H1-P1.0
17-P1.0
TA0CLK
ACLK
TACLK
ACLK
Timer
CCR0
N/A
TA0
N/A
SMCLK
TA0CLK
TA0.0
SMCLK
TACLK
CCI0A
CCI0B
17, H1-P1.0
18, H4-P1.1
57, H9-P8.0
17-P1.0
18-P1.1
60-P8.0
18, H4-P1.1
57, H9-P8.0
18-P1.1
60-P8.0
TA0.0
TA0.0
ADC12 (internal)
ADC12SHSx = {1} ADC12SHSx = {1}
ADC12 (internal)
DVSS
GND
DVCC
TA0.1
TA0.1
DVSS
DVCC
TA0.2
TA0.2
DVSS
DVCC
TA0.3
TA0.3
DVSS
DVCC
TA0.4
TA0.4
DVSS
DVCC
VCC
CCI1A
CCI1B
GND
19, J4-P1.2
19-P1.2
61-P8.1
19, J4-P1.2
19-P1.2
61-P8.1
58, H11-P8.1
58, H11-P8.1
CCR1
CCR2
CCR3
CCR4
TA1
TA2
TA3
TA4
TA0.1
TA0.2
TA0.3
TA0.4
VCC
20, J1-P1.3
20-P1.3
62-P8.2
CCI2A
CCI2B
GND
20, J1-P1.3
20-P1.3
62-P8.2
59, H12-P8.2
59, H12-P8.2
VCC
21, J2-P1.4
60, G9-P8.3
21-P1.4
63-P8.3
CCI3A
CCI3B
GND
21, J2-P1.4
60, G9-P8.3
21-P1.4
63-P8.3
VCC
22, K1-P1.5
22-P1.5
64-P8.4
CCI4A
CCI4B
GND
22, K1-P1.5
22-P1.5
64-P8.4
61, G11-P8.4
61, G11-P8.4
VCC
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9.9.11 TA1
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 9-9). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers. Table 9-9 lists the available signal connections.
Table 9-9. TA1 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
PZ, ZCA,
PN
PZ, ZCA,
PN
ZQW
ZQW
25, M1-P2.0
25-P2.0
TA1CLK
ACLK
SMCLK
TA1CLK
TA1.0
TA1.0
DVSS
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
CCR2
N/A
TA0
TA1
TA2
N/A
25, M1-P2.0
26, L2-P2.1
65, F11-P8.5
25-P2.0
26-P2.1
65-P8.5
26, L2-P2.1
26-P2.1
65-P8.5
65, F11-P8.5
TA1.0
TA1.1
TA1.2
DVCC
VCC
27, M2-P2.2
66, E11-P8.6
27-P2.2
66-P8.6
TA1.1
TA1.1
DVSS
CCI1A
CCI1B
GND
27, M2-P2.2
66, E11-P8.6
27-P2.2
66-P8.6
DVCC
VCC
28, L3-P2.3
56, J12-P7.3
28-P2.3
59-P7.3
TA1.2
TA1.2
DVSS
CCI2A
CCI2B
GND
28, L3-P2.3
56, J12-P7.3
28-P2.3
59-P7.3
DVCC
VCC
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9.9.12 TB0
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 can support multiple
capture/compares, PWM outputs, and interval timing (see Table 9-10). TB0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers. Table 9-10 lists the available signal connections.
Table 9-10. TB0 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
MODULE
BLOCK
PZ, ZCA,
PN
PZ, ZCA, ZQW
PN
ZQW
50, M12-P4.7
53-P4.7
TB0CLK
ACLK
TBCLK
ACLK
Timer
CCR0
N/A
N/A
SMCLK
TB0CLK
TB0.0
SMCLK
TBCLK
CCI0A
50, M12-P4.7
43, J8-P4.0
53-P4.7
43-P4.0
43, J8-P4.0
43-P4.0
ADC12 (internal)
ADC12SHSx = {2} ADC12SHSx = {2}
ADC12 (internal)
43, J8-P4.0
43-P4.0
TB0.0
CCI0B
TB0
TB0.0
DVSS
DVCC
TB0.1
GND
VCC
44, M9-P4.1
44, M9-P4.1
44-P4.1
44-P4.1
CCI1A
44, M9-P4.1
44-P4.1
ADC12 (internal)
ADC12SHSx = {3} ADC12SHSx = {3}
ADC12 (internal)
TB0.1
CCI1B
CCR1
TB1
TB0.1
DVSS
DVCC
TB0.2
TB0.2
DVSS
DVCC
TB0.3
TB0.3
DVSS
DVCC
TB0.4
TB0.4
DVSS
DVCC
TB0.5
TB0.5
DVSS
DVCC
TB0.6
GND
VCC
45, L9-P4.2
45, L9-P4.2
45-P4.2
45-P4.2
CCI2A
CCI2B
GND
45, L9-P4.2
46, L10-P4.3
47, M10-P4.4
48, L11-P4.5
49, M11-P4.6
45-P4.2
46-P4.3
47-P4.4
48-P4.5
52-P4.6
CCR2
CCR3
CCR4
CCR5
TB2
TB3
TB4
TB5
TB0.2
TB0.3
TB0.4
TB0.5
VCC
46, L10-P4.3
46, L10-P4.3
46-P4.3
46-P4.3
CCI3A
CCI3B
GND
VCC
47, M10-P4.4
47, M10-P4.4
47-P4.4
47-P4.4
CCI4A
CCI4B
GND
VCC
48, L11-P4.5
48, L11-P4.5
48-P4.5
48-P4.5
CCI5A
CCI5B
GND
VCC
49, M11-P4.6
52-P4.6
CCI6A
ACLK
(internal)
CCI6B
CCR6
TB6
TB0.6
DVSS
DVCC
GND
VCC
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9.9.13 ADC12_A
The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-
and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU
intervention.
9.9.14 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
9.9.15 Reference (REF) Module Voltage Reference
The REF is responsible for generation of all critical reference voltages that can be used by the various analog
peripherals in the device.
9.9.16 Embedded Emulation Module (EEM) (L Version)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:
•
•
•
•
•
•
•
Eight hardware triggers or breakpoints on memory access
Two hardware trigger or breakpoint on CPU register write access
Up to 10 hardware triggers that can be combined to form complex triggers or breakpoints
Two cycle counters
Sequencer
State storage
Clock control on module level
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9.9.17 Peripheral File Map
Table 9-11 lists the base address of the registers for each peripheral.
Table 9-11. Peripherals
OFFSET ADDRESS
RANGE
MODULE NAME
BASE ADDRESS
Special Functions (see Table 9-12)
PMM (see Table 9-13)
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
0200h
0220h
0240h
0260h
0280h
02A0h
0320h
0340h
0380h
03C0h
04A0h
04C0h
0500h
0510h
0520h
0530h
05C0h
05E0h
0600h
0620h
0640h
0660h
0680h
06A0h
0700h
000h to 01Fh
000h to 010h
000h to 00Fh
000h to 007h
000h to 001h
000h to 001h
000h to 01Fh
000h to 01Fh
000h to 001h
000h to 01Fh
000h to 00Bh
000h to 00Bh
000h to 00Bh
000h to 00Bh
000h to 00Ah
000h to 01Fh
000h to 02Eh
000h to 02Eh
000h to 02Eh
000h to 01Bh
000h to 02Fh
000h to 00Fh
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 03Eh
Flash Control (see Table 9-14)
CRC16 (see Table 9-15)
RAM Control (see Table 9-16)
Watchdog (see Table 9-17)
UCS (see Table 9-18)
SYS (see Table 9-19)
Shared Reference (see Table 9-20)
Port P1, P2 (see Table 9-21)
Port P3, P4 (see Table 9-22)
Port P5, P6 (see Table 9-23)
Port P7, P8 (see Table 9-24)
Port P9, P10 (see Table 9-25)
Port P11 (see Table 9-26)
Port PJ (see Table 9-27)
TA0 (see Table 9-28)
TA1 (see Table 9-29)
TB0 (see Table 9-30)
Real Timer Clock (RTC_A) (see Table 9-31)
32-Bit Hardware Multiplier (see Table 9-32)
DMA General Control (see Table 9-33)
DMA Channel 0 (see Table 9-33)
DMA Channel 1 (see Table 9-33)
DMA Channel 2 (see Table 9-33)
USCI_A0 (see Table 9-34)
USCI_B0 (see Table 9-35)
USCI_A1 (see Table 9-36)
USCI_B1 (see Table 9-37)
USCI_A2 (see Table 9-38)
USCI_B2 (see Table 9-39)
USCI_A3 (see Table 9-40)
USCI_B3 (see Table 9-41)
ADC12_A (see Table 9-42)
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Table 9-12. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFR interrupt flag
SFRIE1
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
Table 9-13. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
00h
02h
04h
06h
0Ch
0Eh
10h
PMM control 1
PMMCTL1
SVSMHCTL
SVSMLCTL
PMMIFG
SVS high-side control
SVS low-side control
PMM interrupt flags
PMM interrupt enable
PMM power mode 5 control
PMMIE
PM5CTL0
Table 9-14. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
Flash control 1
Flash control 3
Flash control 4
FCTL1
FCTL3
FCTL4
00h
04h
06h
Table 9-15. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC data input
CRC16DI
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
Table 9-16. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
OFFSET
RAM control 0
RCCTL0
00h
00h
Table 9-17. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
Watchdog timer control
WDTCTL
Table 9-18. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
UCS control 0
UCS control 1
UCS control 2
UCS control 3
UCS control 4
UCS control 5
UCS control 6
UCS control 7
UCS control 8
UCSCTL0
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
UCSCTL1
UCSCTL2
UCSCTL3
UCSCTL4
UCSCTL5
UCSCTL6
UCSCTL7
UCSCTL8
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Table 9-19. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Bootloader configuration area
JTAG mailbox control
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSSNIV
SYSRSTIV
Table 9-20. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
Shared reference control
REFCTL
00h
Table 9-21. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
Port P1 input
P1IN
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
Port P1 output
P1OUT
P1DIR
P1REN
P1DS
P1SEL
P1IV
Port P1 direction
Port P1 resistor enable
Port P1 drive strength
Port P1 selection
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2DS
P2SEL
P2IV
Port P2 direction
Port P2 resistor enable
Port P2 drive strength
Port P2 selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
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Table 9-22. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P3 output
P3OUT
P3DIR
P3REN
P3DS
Port P3 direction
Port P3 resistor enable
Port P3 drive strength
Port P3 selection
Port P4 input
P3SEL
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4DS
Port P4 direction
Port P4 resistor enable
Port P4 drive strength
Port P4 selection
P4SEL
Table 9-23. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P5 output
P5OUT
P5DIR
P5REN
P5DS
Port P5 direction
Port P5 resistor enable
Port P5 drive strength
Port P5 selection
Port P6 input
P5SEL
P6IN
Port P6 output
P6OUT
P6DIR
P6REN
P6DS
Port P6 direction
Port P6 resistor enable
Port P6 drive strength
Port P6 selection
P6SEL
Table 9-24. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P7 output
P7OUT
P7DIR
P7REN
P7DS
Port P7 direction
Port P7 resistor enable
Port P7 drive strength
Port P7 selection
Port P8 input
P7SEL
P8IN
Port P8 output
P8OUT
P8DIR
P8REN
P8DS
Port P8 direction
Port P8 resistor enable
Port P8 drive strength
Port P8 selection
P8SEL
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Table 9-25. Port P9, P10 Registers (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P9 input
P9IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P9 output
P9OUT
P9DIR
P9REN
P9DS
Port P9 direction
Port P9 resistor enable
Port P9 drive strength
Port P9 selection
Port P10 input
P9SEL
P10IN
Port P10 output
P10OUT
P10DIR
P10REN
P10DS
Port P10 direction
Port P10 resistor enable
Port P10 drive strength
Port P10 selection
P10SEL
Table 9-26. Port P11 Registers (Base Address: 02A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P11 input
P11IN
00h
02h
04h
06h
08h
0Ah
Port P11 output
P11OUT
P11DIR
P11REN
P11DS
Port P11 direction
Port P11 resistor enable
Port P11 drive strength
Port P11 selection
P11SEL
Table 9-27. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
08h
Port PJ output
PJOUT
PJDIR
PJREN
PJDS
Port PJ direction
Port PJ resistor enable
Port PJ drive strength
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Table 9-28. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
02h
04h
06h
08h
0Ah
10h
12h
14h
16h
18h
1Ah
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0CCTL3
TA0CCTL4
TA0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0CCR3
TA0CCR4
TA0EX0
TA0 interrupt vector
TA0IV
Table 9-29. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1 interrupt vector
TA1IV
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Table 9-30. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
TB0 counter
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0CCTL3
TB0CCTL4
TB0CCTL5
TB0CCTL6
TB0R
Capture/compare 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0CCR3
TB0CCR4
TB0CCR5
TB0CCR6
TB0EX0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Capture/compare 5
Capture/compare 6
TB0 expansion 0
TB0 interrupt vector
TB0IV
Table 9-31. Real Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
01h
02h
03h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
RTC control 1
RTCCTL1
RTC control 2
RTCCTL2
RTC control 3
RTCCTL3
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTC prescaler 1
RTCPS1
RTC interrupt vector word
RTC seconds/counter 1
RTC minutes/counter 2
RTC hours/counter 3
RTC day of week/counter 4
RTC days
RTCIV
RTCSEC/RTCNT1
RTCMIN/RTCNT2
RTCHOUR/RTCNT3
RTCDOW/RTCNT4
RTCDAY
RTC month
RTCMON
RTC year low
RTCYEARL
RTCYEARH
RTCAMIN
RTC year high
RTC alarm minutes
RTC alarm hours
RTC alarm day of week
RTC alarm days
RTCAHOUR
RTCADOW
RTCADAY
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Table 9-32. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
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Table 9-33. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Eh
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA module control 0
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
Table 9-34. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA0CTL1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA0CTL0
UCA0BR0
USCI baud rate 0
USCI baud rate 1
UCA0BR1
USCI modulation control
USCI status
UCA0MCTL
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA0IFG
UCA0IV
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Table 9-35. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
UCB0CTL1
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB0CTL0
UCB0BR0
UCB0BR1
UCB0STAT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA
UCB0I2CSA
UCB0IE
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB0IFG
USCI interrupt vector word
UCB0IV
Table 9-36. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA1CTL1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA1CTL0
UCA1BR0
USCI baud rate 0
USCI baud rate 1
UCA1BR1
USCI modulation control
USCI status
UCA1MCTL
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA1IFG
UCA1IV
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Table 9-37. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
UCB1CTL1
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB1CTL0
UCB1BR0
UCB1BR1
UCB1STAT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA
UCB1I2CSA
UCB1IE
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB1IFG
USCI interrupt vector word
UCB1IV
Table 9-38. USCI_A2 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA2CTL1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA2CTL0
UCA2BR0
USCI baud rate 0
USCI baud rate 1
UCA2BR1
USCI modulation control
USCI status
UCA2MCTL
UCA2STAT
UCA2RXBUF
UCA2TXBUF
UCA2ABCTL
UCA2IRTCTL
UCA2IRRCTL
UCA2IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA2IFG
UCA2IV
Table 9-39. USCI_B2 Registers (Base Address: 0660h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
UCB2CTL1
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB2CTL0
UCB2BR0
UCB2BR1
UCB2STAT
UCB2RXBUF
UCB2TXBUF
UCB2I2COA
UCB2I2CSA
UCB2IE
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB2IFG
USCI interrupt vector word
UCB2IV
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Table 9-40. USCI_A3 Registers (Base Address: 0680h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA3CTL1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA3CTL0
UCA3BR0
USCI baud rate 0
USCI baud rate 1
UCA3BR1
USCI modulation control
USCI status
UCA3MCTL
UCA3STAT
UCA3RXBUF
UCA3TXBUF
UCA3ABCTL
UCA3IRTCTL
UCA3IRRCTL
UCA3IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA3IFG
UCA3IV
Table 9-41. USCI_B3 Registers (Base Address: 06A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
UCB3CTL1
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB3CTL0
UCB3BR0
UCB3BR1
UCB3STAT
UCB3RXBUF
UCB3TXBUF
UCB3I2COA
UCB3I2CSA
UCB3IE
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB3IFG
USCI interrupt vector word
UCB3IV
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Table 9-42. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Control 0
ADC12CTL0
00h
02h
04h
0Ah
0Ch
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
36h
38h
3Ah
3Ch
3Eh
Control 1
ADC12CTL1
Control 2
ADC12CTL2
Interrupt flag
ADC12IFG
Interrupt enable
ADC12IE
Interrupt vector word
ADC memory control 0
ADC memory control 1
ADC memory control 2
ADC memory control 3
ADC memory control 4
ADC memory control 5
ADC memory control 6
ADC memory control 7
ADC memory control 8
ADC memory control 9
ADC memory control 10
ADC memory control 11
ADC memory control 12
ADC memory control 13
ADC memory control 14
ADC memory control 15
Conversion memory 0
Conversion memory 1
Conversion memory 2
Conversion memory 3
Conversion memory 4
Conversion memory 5
Conversion memory 6
Conversion memory 7
Conversion memory 8
Conversion memory 9
Conversion memory 10
Conversion memory 11
Conversion memory 12
Conversion memory 13
Conversion memory 14
Conversion memory 15
ADC12IV
ADC12MCTL0
ADC12MCTL1
ADC12MCTL2
ADC12MCTL3
ADC12MCTL4
ADC12MCTL5
ADC12MCTL6
ADC12MCTL7
ADC12MCTL8
ADC12MCTL9
ADC12MCTL10
ADC12MCTL11
ADC12MCTL12
ADC12MCTL13
ADC12MCTL14
ADC12MCTL15
ADC12MEM0
ADC12MEM1
ADC12MEM2
ADC12MEM3
ADC12MEM4
ADC12MEM5
ADC12MEM6
ADC12MEM7
ADC12MEM8
ADC12MEM9
ADC12MEM10
ADC12MEM11
ADC12MEM12
ADC12MEM13
ADC12MEM14
ADC12MEM15
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9.10 Input/Output Diagrams
9.10.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Figure 9-2 shows the port diagram. Table 9-43 summarizes the selection of the pin functions.
Pad Logic
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Q
P1IFG.x
Set
P1SEL.x
P1IES.x
Interrupt
Edge
Select
Figure 9-2. Port P1 (P1.0 to P1.7) Diagram
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Table 9-43. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS OR SIGNALS
FUNCTION
PIN NAME (P1.x)
x
P1DIR.x
P1SEL.x
P1.0 (I/O)
TA0.TA0CLK
ACLK
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
P1.0/TA0CLK/ACLK
P1.1/TA0.0
0
0
1
P1.1 (I/O)
TA0.CCI0A
TA0.0
I: 0; O: 1
1
2
3
4
5
0
1
P1.2 (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
P1.2/TA0.1
0
1
P1.3 (I/O)
TA0.CCI2A
TA0.2
I: 0; O: 1
P1.3/TA0.2
0
1
P1.4 (I/O)
TA0.CCI3A
TA0.3
I: 0; O: 1
P1.4/TA0.3
0
1
P1.5 (I/O)
TA0.CCI4A
TA0.4
I: 0; O: 1
P1.5/TA0.4
0
1
P1.6 (I/O)
SMCLK
I: 0; O: 1
1
P1.6/SMCLK
P1.7
6
7
P1.7 (I/O)
I: 0; O: 1
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9.10.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
Figure 9-3 shows the port diagram. Table 9-44 summarizes the selection of the pin functions.
Pad Logic
P2REN.x
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
P2OUT.x
0
1
Module X OUT
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
P2.5
P2.6/ACLK
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
EN
D
P2.7/ADC12CLK/DMAE0
Module X IN
P2IRQ.x
P2IE.x
EN
Q
P2IFG.x
Set
P2SEL.x
P2IES.x
Interrupt
Edge
Select
Figure 9-3. Port P2 (P2.0 to P2.7) Diagram
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Table 9-44. Port P2 (P2.0 to P2.7) Pin Functions
CONTROL BITS OR SIGNALS
FUNCTION
PIN NAME (P2.x)
x
P2DIR.x
P2SEL.x
P2.0 (I/O)
TA1CLK
MCLK
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
0
1
0
1
1
P2.0/TA1CLK/MCLK
P2.1/TA1.0
0
0
1
P2.1 (I/O)
TA1.CCI0A
TA1.0
I: 0; O: 1
1
2
3
0
1
P2.2 (I/O)
TA1.CCI1A
TA1.1
I: 0; O: 1
P2.2/TA1.1
0
1
P2.3 (I/O)
TA1.CCI2A
TA1.2
I: 0; O: 1
P2.3/TA1.2
0
1
P2.4 (I/O)
RTCCLK
P2.5 (I/O)
P2.6 (I/O)
ACLK
I: 0; O: 1
P2.4/RTCCLK
P2.5
4
5
6
1
I: 0; O: 1
I: 0; O: 1
P2.6/ACLK
1
P2.7 (I/O)
DMAE0
I: 0; O: 1
P2.7/ADC12CLK/DMAE0
7
0
1
ADC12CLK
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9.10.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
Figure 9-4 shows the port diagram. Table 9-45 summarizes the selection of the pin functions.
Pad Logic
P3REN.x
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
P3OUT.x
0
1
Module X OUT
P3.0/UB0STE/UCA0CLK
P3DS.x
0: Low drive
1: High drive
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/USC0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
P3.7/UCB1SIMO/UCB1SDA
P3SEL.x
P3IN.x
EN
D
Module X IN
Figure 9-4. Port P3 (P3.0 to P3.7) Diagram
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Table 9-45. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
FUNCTION
PIN NAME (P3.x)
x
0
1
2
3
4
5
6
7
P3DIR.x
P3SEL.x
P3.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/UCB1STE/UCA1CLK
UCB0STE/UCA0CLK(2) (4)
X
P3.1 (I/O)
I: 0; O: 1
UCB0SIMO/UCB0SDA(2) (3)
P3.2 (I/O)
X
I: 0; O: 1
UCB0SOMI/UCB0SCL(2) (3)
X
P3.3 (I/O)
I: 0; O: 1
UCB0CLK/UCA0STE(2) (5)
P3.4 (I/O)
X
I: 0; O: 1
UCA0TXD/UCA0SIMO(2)
X
P3.5 (I/O)
I: 0; O: 1
UCA0RXD/UCA0SOMI(2)
P3.6 (I/O)
X
I: 0; O: 1
X
UCB1STE/UCA1CLK(2) (6)
P3.7 (I/O)
I: 0; O: 1
X
P3.7/UCB1SIMO/UCB1SDA
(1) X = Don't care
UCB1SIMO/UCB1SDA(2) (3)
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(5) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(6) UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output, USCI_B1 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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9.10.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
Figure 9-5 shows the port diagram. Table 9-46 summarizes the selection of the pin functions.
Pad Logic
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
P4OUT.x
0
1
Module X OUT
P4.0/TB0.0
P4.1/TB0.1
P4.2/TB0.2
P4.3/TB0.3
P4.4/TB0.4
P4.5/TB0.5
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
P4.6/TB0.6
P4.7/TB0CLK/SMCLK
EN
D
Module X IN
Figure 9-5. Port P4 (P4.0 to P4.7) Diagram
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Table 9-46. Port P4 (P4.0 to P4.7) Pin Functions
CONTROL BITS OR SIGNALS
FUNCTION
PIN NAME (P4.x)
x
P4DIR.x
P4SEL.x
4.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
P4.0/TB0.0
0
TB0.CCI0A and TB0.CCI0B
TB0.0(1)
0
1
4.1 (I/O)
I: 0; O: 1
P4.1/TB0.1
1
2
3
4
5
6
7
TB0.CCI1A and TB0.CCI1B
TB0.1(1)
0
1
4.2 (I/O)
I: 0; O: 1
P4.2/TB0.2
TB0.CCI2A and TB0.CCI2B
TB0.2(1)
0
1
4.3 (I/O)
I: 0; O: 1
P4.3/TB0.3
TB0.CCI3A and TB0.CCI3B
TB0.3(1)
0
1
4.4 (I/O)
I: 0; O: 1
P4.4/TB0.5
TB0.CCI4A and TB0.CCI4B
TB0.4(1)
0
1
4.5 (I/O)
I: 0; O: 1
P4.5/TB0.5
TB0.CCI5A and TB0.CCI5B
TB0.5(1)
0
1
4.6 (I/O)
I: 0; O: 1
P4.6/TB0.6
TB0.CCI6A and TB0.CCI6B
TB0.6(1)
0
1
4.7 (I/O)
I: 0; O: 1
P4.7/TB0CLK/SMCLK
TB0CLK
0
1
SMCLK
(1) Setting TBOUTH causes all Timer_B configured outputs to be set to high impedance.
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9.10.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
Figure 9-6 shows the port diagram. Table 9-47 summarizes the selection of the pin functions.
Pad Logic
To ADC12
INCHx = y
To/From
ADC12 Reference
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
P5OUT.x
0
1
Module X OUT
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF–/VeREF–
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
D
Module X IN
Figure 9-6. Port P5 (P5.0 and P5.1) Diagram
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Table 9-47. Port P5 (P5.0 and P5.1) Pin Functions
CONTROL BITS OR SIGNALS(1)
FUNCTION
PIN NAME (P5.x)
x
P5DIR.x
P5SEL.x
REFOUT
P5.0 (I/O)(2)
A8/VeREF+(3)
A8/VREF+(4)
P5.1 (I/O)(2)
A9/VeREF–(5)
A9/VREF–(6)
I: 0; O: 1
0
1
1
0
1
1
X
0
1
X
0
1
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF–/VeREF–
0
X
X
I: 0; O: 1
1
X
X
(1) X = Don't care
(2) Default condition
(3) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A. Channel A8, when
selected with the INCHx bits, is connected to the VREF+/VeREF+ pin.
(4) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The ADC12_A, VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected
to the VREF+/VeREF+ pin.
(5) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A. Channel A9, when selected
with the INCHx bits, is connected to the VREF-/VeREF- pin.
(6) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The ADC12_A, VREF– reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected
to the VREF-/VeREF- pin.
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9.10.6 Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
Figure 9-7 and Figure 9-8 show the port diagrams. Table 9-48 summarizes the selection of the pin functions.
Pad Logic
To XT2
P5REN.2
DVSS
DVCC
0
1
1
P5DIR.2
0
1
P5OUT.2
0
1
Module X OUT
P5.2/XT2IN
P5DS.2
0: Low drive
1: High drive
P5SEL.2
P5IN.2
Bus
Keeper
EN
D
Module X IN
Figure 9-7. Port P5 (P5.2) Diagram
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Pad Logic
To XT2
P5REN.3
DVSS
DVCC
0
1
1
P5DIR.3
0
1
P5OUT.3
0
1
Module X OUT
P5SEL.2
P5.3/XT2OUT
P5DS.3
0: Low drive
1: High drive
XT2BYPASS
P5SEL.3
P5IN.3
Bus
Keeper
EN
D
Module X IN
Figure 9-8. Port P5 (P5.3) Diagram
Table 9-48. Port P5 (P5.2 and P5.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.2
P5SEL.3
XT2BYPASS
P5.2 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
0
X
0
1
X
0
1
P5.2/XT2IN
2
XT2IN crystal mode(2)
XT2IN bypass mode(2)
P5.3 (I/O)
X
X
I: 0; O: 1
P5.3/XT2OUT
3
XT2OUT crystal mode(3)
P5.3 (I/O)(3)
X
X
X
0
(1) X = Don't care
(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
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9.10.7 Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
Figure 9-9 shows the port diagram. Table 9-49 summarizes the selection of the pin functions.
Pad Logic
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
Direction
0: Input
1: Output
P5OUT.x
0
1
Module X OUT
P5.4/UCB1SOMI/UCB1SCL
P5.5/UCB1CLK/UCA1STE
P5.6/UCA1TXD/UCA1SIMO
P5.7/UCA1RXD/UCA1SOMI
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
EN
D
Module X IN
Figure 9-9. Port P5 (P5.4 to P5.7) Diagram
Table 9-49. Port P5 (P5.4 to P5.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
I: 0; O: 1
X
P5SEL.x
P5.4 (I/O)
0
1
0
1
0
1
0
1
P5.4/UCB1SOMI/UCB1SCL
P5.5/UCB1CLK/UCA1STE
P5.6/UCA1TXD/UCA1SIMO
4
5
6
7
UCB1SOMI/UCB1SCL(2) (3)
P5.5 (I/O)
I: 0; O: 1
X
UCB1CLK/UCA1STE(2) (4)
P5.6 (I/O)
I: 0; O: 1
X
UCA1TXD/UCA1SIMO(2)
P5.7 (I/O)
I: 0; O: 1
X
P5.7/UCA1RXD/UCA1SOMI
(1) X = Don't care
UCA1RXD/UCA1SOMI(2)
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCB1CLK function takes precedence over UCA1STE function. If the pin is required as UCB1CLK input or output, USCI_A1 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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9.10.8 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
Figure 9-10 shows the port diagram. Table 9-50 summarizes the selection of the pin functions.
Pad Logic
To ADC12
INCHx = y
P6REN.x
DVSS
DVCC
0
1
1
P6DIR.x
0
1
P6OUT.x
0
1
Module X OUT
P6.0/A0
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
EN
D
Module X IN
Figure 9-10. Port P6 (P6.0 to P6.7) Diagram
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Table 9-50. Port P6 (P6.0 to P6.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
0
1
2
3
4
5
6
7
FUNCTION
P6DIR.x
P6SEL.x
INCHx
P6.0 (I/O)
A0(2) (3)
I: 0; O: 1
0
X
0
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
P6.0/A0
X
P6.1 (I/O)
A1(2) (3)
I: 0; O: 1
P6.1/A1
P6.2/A2
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
X
X
0
P6.2 (I/O)
A2(2) (3)
I: 0; O: 1
X
X
0
P6.3 (I/O)
A3(2) (3)
I: 0; O: 1
X
X
0
P6.4 (I/O)
A4(2) (3)
I: 0; O: 1
X
X
0
P6.5 (I/O)
A5(1) (2) (3)
P6.6 (I/O)
A6(2) (3)
I: 0; O: 1
X
I: 0; O: 1
X
X
0
X
0
P6.7 (I/O)
A7(2) (3)
I: 0; O: 1
X
P6.7/A7
X
(1) X = Don't care
(2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(3) The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
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9.10.9 Port P7 (P7.0 and P7.1) Input/Output With Schmitt Trigger
Figure 9-11 and Figure 9-12 show the port diagrams. Table 9-51 summarizes the selection of the pin functions.
Pad Logic
To XT1
P7REN.0
DVSS
DVCC
0
1
1
P7DIR.0
0
1
P7OUT.0
0
1
Module X OUT
P7.0/XIN
P7DS.0
0: Low drive
1: High drive
P7SEL.0
P7IN.0
Bus
Keeper
EN
D
Module X IN
Figure 9-11. Port P7 (P7.0) Diagram
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Pad Logic
To XT1
P7REN.1
DVSS
DVCC
0
1
1
P7DIR.1
0
1
P7OUT.1
0
1
Module X OUT
P7SEL.0
P7.1/XOUT
P7DS.1
0: Low drive
1: High drive
XT1BYPASS
P7SEL.1
P7IN.1
Bus
Keeper
EN
D
Module X IN
Figure 9-12. Port P7 (P7.1) Diagram
Table 9-51. Port P7 (P7.0 and P7.1) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL.0
P7SEL.1
XT1BYPASS
P7.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
0
X
0
1
X
0
1
P7.0/XIN
0
XIN crystal mode(2)
XIN bypass mode(2)
P7.1 (I/O)
X
X
I: 0; O: 1
P7.1/XOUT
1
XOUT crystal mode(3)
P7.1 (I/O)(3)
X
X
X
0
(1) X = Don't care
(2) Setting P7SEL.0 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P7.0 is configured for crystal
mode or bypass mode.
(3) Setting P7SEL.0 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.1 can be used as
general-purpose I/O.
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9.10.10 Port P7 (P7.2 and P7.3) Input/Output With Schmitt Trigger
Figure 9-13 shows the port diagram. Table 9-52 summarizes the selection of the pin functions.
Pad Logic
P7REN.x
DVSS
DVCC
0
1
1
P7DIR.x
0
1
Direction
0: Input
1: Output
P7OUT.x
0
1
Module X OUT
P7.2/TB0OUTH/SVMOUT
P7.3/TA1.2
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
EN
D
Module X IN
Figure 9-13. Port P7 (P7.2 and P7.3) Diagram
Table 9-52. Port P7 (P7.2 and P7.3) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL.x
P7.2 (I/O)
TB0OUTH
SVMOUT
P7.3 (I/O)
TA1.CCI2B
TA1.2
I: 0; O: 1
0
1
1
0
1
1
P7.2/TB0OUTH/SVMOUT
2
0
1
I: 0; O: 1
P7.3/TA1.2
3
0
1
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9.10.11 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
Figure 9-14 shows the port diagram. Table 9-53 summarizes the selection of the pin functions.
Pad Logic
To ADC12
INCHx = y
P7REN.x
DVSS
DVCC
0
1
1
P7DIR.x
0
1
P7OUT.x
0
1
Module X OUT
P7.4/A12
P7DS.x
0: Low drive
1: High drive
P7.5/A13
P7.6/A14
P7.7/A15
P7SEL.x
P7IN.x
Bus
Keeper
EN
D
Module X IN
Figure 9-14. Port P7 (P7.4 to P7.7) Diagram
Table 9-53. Port P7 (P7.4 to P7.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
x
4
5
6
7
FUNCTION
P7DIR.x
P7SEL.x
INCHx
P7.4 (I/O)
I: 0; O: 1
0
X
0
X
12
X
P7.4/A12
P7.5/A13
P7.6/A14
A12(2) (3)
P7.5 (I/O)
A13(2) (3)
P7.6 (I/O)
A14(2) (3)
P7.7 (I/O)
A15(2) (3)
X
I: 0; O: 1
X
I: 0; O: 1
X
X
0
13
X
X
0
14
X
I: 0; O: 1
X
P7.7/A15
X
15
(1) X = Don't care
(2) Setting the P7SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(3) The ADC12_A channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
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9.10.12 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
Figure 9-15 shows the port diagram. Table 9-54 summarizes the selection of the pin functions.
Pad Logic
P8REN.x
0
1
DVSS
DVCC
1
P8DIR.x
0
1
Direction
0: Input
1: Output
0
1
P8OUT.x
Module X OUT
P8.0/TA0.0
P8.1/TA0.1
P8.2/TA0.2
P8.3/TA0.3
P8.4/TA0.4
P8.5/TA1.0
P8.6/TA1.1
P8.7
P8DS.x
0: Low drive
1: High drive
P8SEL.x
P8IN.x
EN
D
Module X IN
Figure 9-15. Port P8 (P8.0 to P8.7) Diagram
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Table 9-54. Port P8 (P8.0 to P8.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P8.x)
x
FUNCTION
P8DIR.x
P8SEL.x
P8.0 (I/O)
TA0.CCI0B
TA0.0
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
P8.0/TA0.0
0
0
1
P8.1 (I/O)
TA0.CCI1B
TA0.1
I: 0; O: 1
P8.1/TA0.1
P8.2/TA0.2
P8.3/TA0.3
P8.4/TA0.4
P8.5/TA1.0
1
2
3
4
5
0
1
P8.2 (I/O)
TA0.CCI2B
TA0.2
I: 0; O: 1
0
1
P8.3 (I/O)
TA0.CCI3B
TA0.3
I: 0; O: 1
0
1
P8.4 (I/O)
TA0.CCI4B
TA0.4
I: 0; O: 1
0
1
P8.5 (I/O)
TA1.CCI0B
TA1.0
I: 0; O: 1
0
1
P8.6 (I/O)
TA1.CCI1B
TA1.1
I: 0; O: 1
P8.6/TA1.1
P8.7
6
7
0
1
P8.7 (I/O)
I: 0; O: 1
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9.10.13 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
Figure 9-16 shows the port diagram. Table 9-55 summarizes the selection of the pin functions.
Pad Logic
P9REN.x
DVSS
DVCC
0
1
1
P9DIR.x
0
1
Direction
0: Input
1: Output
P9OUT.x
0
1
Module X OUT
P9.0/UCB2STE/UCA2CLK
P9.1/UCB2SIMO/UCB2SDA
P9.2/UCB2SOMI/UCB2SCL
P9.3/UCB2CLK/UCA2STE
P9.4/UCA2TXD/UCA2SIMO
P9.5/UCA2RXD/UCA2SOMI
P9.6
P9DS.x
0: Low drive
1: High drive
P9SEL.x
P9IN.x
EN
D
P9.7
Module X IN
Figure 9-16. Port P9 (P9.0 to P9.7) Diagram
Table 9-55. Port P9 (P9.0 to P9.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P9.x)
x
FUNCTION
P9DIR.x
I: 0; O: 1
X
P9SEL.x
P9.0 (I/O)
0
1
0
1
0
1
0
1
0
1
0
1
0
0
P9.0/UCB2STE/UCA2CLK
P9.1/UCB2SIMO/UCB2SDA
P9.2/UCB2SOMI/UCB2SCL
P9.3/UCB2CLK/UCA2STE
P9.4/UCA2TXD/UCA2SIMO
P9.5/UCA2RXD/UCA2SOMI
0
1
2
3
4
5
UCB2STE/UCA2CLK(2) (4)
P9.1 (I/O)
I: 0; O: 1
X
UCB2SIMO/UCB2SDA(2) (3)
P9.2 (I/O)
I: 0; O: 1
X
UCB2SOMI/UCB2SCL(2) (3)
P9.3 (I/O)
I: 0; O: 1
X
UCB2CLK/UCA2STE(2) (5)
P9.4 (I/O)
I: 0; O: 1
X
UCA2TXD/UCA2SIMO(2)
P9.5 (I/O)
I: 0; O: 1
X
UCA2RXD/UCA2SOMI(2)
P9.6 (I/O)
P9.6
P9.7
6
7
I: 0; O: 1
I: 0; O: 1
P9.7 (I/O)
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCA2CLK function takes precedence over UCB2STE function. If the pin is required as UCA2CLK input or output, USCI_B2 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(5) UCB2CLK function takes precedence over UCA2STE function. If the pin is required as UCB2CLK input or output, USCI_A2 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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9.10.14 Port P10 (P10.0 to P10.7) Input/Output With Schmitt Trigger
Figure 9-17 shows the port diagram. Table 9-56 summarizes the selection of the pin functions.
Pad Logic
P10REN.x
DVSS
DVCC
0
1
1
P10DIR.x
0
1
Direction
0: Input
1: Output
P10OUT.x
0
1
Module X OUT
P10.0/UCB3STE/UCA3CLK
P10.1/UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
P10.3/UCB3CLK/UCA3STE
P10.4/UCA3TXD/UCA3SIMO
P10.5/UCA3RXD/UCA3SOMI
P10.6
P10DS.x
0: Low drive
1: High drive
P10SEL.x
P10IN.x
EN
D
P10.7
Module X IN
Figure 9-17. Port P10 (P10.0 to P10.7) Diagram
Table 9-56. Port P10 (P10.0 to P10.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P10.x)
P10.0/UCB3STE/UCA3CLK
P10.1/UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
P10.3/UCB3CLK/UCA3STE
P10.4/UCA3TXD/UCA3SIMO
P10.5/UCA3RXD/UCA3SOMI
P10.6
x
0
1
2
3
4
5
6
7
FUNCTION
P10DIR.x
P10SEL.x
P10.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UCB3STE/UCA3CLK(2) (4)
P10.1 (I/O)
X
I: 0; O: 1
UCB3SIMO/UCB3SDA(2) (3)
P10.2 (I/O)
X
I: 0; O: 1
UCB3SOMI/UCB3SCL(2) (3)
P10.3 (I/O)
X
I: 0; O: 1
UCB3CLK/UCA3STE(2) (5)
P10.4 (I/O)
X
I: 0; O: 1
UCA3TXD/UCA3SIMO(2)
P10.5 (I/O)
X
I: 0; O: 1
UCA3RXD/UCA3SOMI(2)
P10.6 (I/O)
X
I: 0; O: 1
Reserved(6)
X
I: 0; O: 1
x
P10.7 (I/O)
P10.7
Reserved(6)
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI_B3 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(5) UCB3CLK function takes precedence over UCA3STE function. If the pin is required as UCB3CLK input or output, USCI_A3 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(6) The secondary function on these pins are reserved for factory test purposes. Application should keep the P10SEL.x of these ports
cleared to prevent potential conflicts with the application.
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9.10.15 Port P11 (P11.0 to P11.2) Input/Output With Schmitt Trigger
Figure 9-18 shows the port diagram. Table 9-57 summarizes the selection of the pin functions.
Pad Logic
P11REN.x
0
1
DVSS
DVCC
1
P11DIR.x
0
1
Direction
0: Input
1: Output
P11OUT.x
0
1
Module X OUT
P11.0/ACLK
P11.1/MCLK
P11.2/SMCLK
P11DS.x
0: Low drive
1: High drive
P11SEL.x
P11IN.x
EN
D
Module X IN
Figure 9-18. Port P11 (P11.0 to P11.2) Diagram
Table 9-57. Port P11 (P11.0 to P11.2) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P11.x)
x
0
1
2
FUNCTION
P11DIR.x
P11SEL.x
P11.0 (I/O)
ACLK
I: 0; O: 1
0
1
0
1
0
1
P11.0/ACLK
P11.1/MCLK
P11.2/SMCLK
1
P11.1 (I/O)
MCLK
I: 0; O: 1
1
I: 0; O: 1
1
P11.2 (I/O)
SMCLK
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9.10.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 9-19 shows the port diagram. Table 9-58 summarizes the selection of the pin functions.
Pad Logic
PJREN.0
0
1
DVSS
DVCC
1
PJDIR.0
DVCC
0
1
PJOUT.0
0
1
From JTAG
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
Figure 9-19. Port PJ (PJ.0) Diagram
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9.10.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or
Output
Figure 9-20 shows the port diagram. Table 9-58 summarizes the selection of the pin functions.
Pad Logic
PJREN.x
0
1
DVSS
DVCC
1
PJDIR.x
DVSS
0
1
PJOUT.x
0
1
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJDS.x
0: Low drive
1: High drive
From JTAG
PJIN.x
EN
D
To JTAG
Figure 9-20. Port PJ (PJ.1 to PJ.3) Diagram
Table 9-58. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS
OR SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
I: 0; O: 1
X
PJ.0 (I/O)(2)
PJ.0/TDO
0
1
2
3
TDO(3)
PJ.1 (I/O)(2)
TDI/TCLK(3) (4)
PJ.2 (I/O)(2)
TMS(3) (4)
I: 0; O: 1
X
PJ.1/TDI/TCLK
PJ.2/TMS
I: 0; O: 1
X
PJ.3 (I/O)(2)
TCK(3) (4)
I: 0; O: 1
X
PJ.3/TCK
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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9.11 Device Descriptors
Table 9-59 shows the contents of the device descriptor tag-length-value (TLV) structure for each device type.
Table 9-59. Device Descriptors
VALUE
SIZE
(bytes)
DESCRIPTION(1)
Info length
ADDRESS
F5438A
06h
F5437A
06h
F5436A
06h
F5435A
06h
F5419A
06h
F5418A
06h
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
1
1
2
1
1
1
1
1
1
4
2
2
2
1
1
2
2
CRC length
CRC value
06h
06h
06h
06h
06h
06h
Per unit
05h
Per unit
04h
Per unit
03h
Per unit
02h
Per unit
01h
Per unit
00h
Info Block
Device ID
Device ID
80h
80h
80h
80h
80h
80h
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Per unit
Per unit
Per unit
Per unit
11h
Die Record
Die X position
Die Y position
Test results
ADC12 calibration tag
ADC12 calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
ADC12
Calibration
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
REF calibration tag
REF calibration length
REF 1.5-V reference
01A26h
01A27h
01A28h
01A2Ah
01A2Ch
01A2Eh
01A2Fh
1
1
2
2
2
1
1
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
12h
06h
REF Calibration
Per unit
Per unit
Per unit
02h
Per unit
Per unit
Per unit
02h
Per unit
Per unit
Per unit
02h
Per unit
Per unit
Per unit
02h
Per unit
Per unit
Per unit
02h
Per unit
Per unit
Per unit
02h
REF 2.0-V reference
REF 2.5-V reference
Peripheral descriptor tag
Peripheral descriptor length
61h
059h
62h
5Ah
61h
59h
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
08h
8Ah
Memory 1
Memory 2
Memory 3
Memory 4
2
2
2
2
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Ch
86h
0Eh
30h
0Eh
30h
0Eh
30h
0Eh
30h
0Eh
30h
0Eh
30h
Peripheral
Descriptor
2Eh
98h
2Eh
98h
2Eh
97h
2Eh
97h
2Eh
96h
2Eh
96h
Memory 5
Delimiter
0/1
1
N/A
00h
21h
N/A
00h
1Dh
94h
00h
21h
94h
00h
1Dh
N/A
00h
21h
N/A
00h
1Dh
Peripheral count
1
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
00h
23h
MSP430CPUXV2
2
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Table 9-59. Device Descriptors (continued)
VALUE
SIZE
DESCRIPTION(1)
ADDRESS
(bytes)
F5438A
F5437A
F5436A
F5435A
F5419A
F5418A
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
00h
0Fh
SBW
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
00h
05h
EEM-8
TI BSL
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
FCh
00h
1Fh
00h
1Fh
00h
1Fh
00h
1Fh
00h
1Fh
00h
1Fh
Package
SFR
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
10h
41h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
02h
30h
PMM
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
02h
38h
FCTL
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
01h
3Ch
CRC16 straight
CRC16 bit reversed
RAMCTL
WDT_A
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
3Dh
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
44h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
00h
40h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
01h
48h
UCS
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
02h
42h
SYS
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
03h
A0h
REF
05h
51h
05h
51h
05h
51h
05h
51h
05h
51h
05h
51h
Port 1 and 2
Port 3 and 4
Port 5 and 6
Port 7 and 8
Port 9 and 10
Port 11 and 12
JTAG
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
52h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
53h
02h
54h
02h
54h
02h
54h
02h
54h
02h
54h
02h
54h
02h
55h
02h
55h
02h
55h
N/A
N/A
N/A
N/A
N/A
N/A
02h
56h
02h
56h
02h
56h
08h
5Fh
0Ch
5Fh
08h
5Fh
0Ch
5Fh
08h
5Fh
0Ch
5Fh
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
02h
62h
TA0
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
04h
61h
TA1
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
04h
67h
TB0
Peripheral
Descriptor
(continued)
0Eh
68h
0Eh
68h
0Eh
68h
0Eh
68h
0Eh
68h
0Eh
68h
RTC
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
02h
85h
MPY32
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
04h
47h
DMA-3
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
0Ch
90h
USCI_A and USCI_B
USCI_A and USCI_B
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
04h
90h
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Table 9-59. Device Descriptors (continued)
VALUE
SIZE
(bytes)
DESCRIPTION(1)
ADDRESS
F5438A
F5437A
F5436A
F5435A
F5419A
F5418A
04h
90h
04h
90h
04h
90h
USCI_A and USCI_B
2
N/A
N/A
N/A
04h
90h
04h
90h
04h
90h
USCI_A and USCI_B
ADC12_A
2
2
N/A
N/A
N/A
08h
D1h
10h
D1h
08h
D1h
10h
D1h
08h
D1h
10h
D1h
TB0.CCIFG0
TB0.CCIFG1..6
WDTIFG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
64h
65h
40h
90h
91h
D0h
60h
61h
94h
95h
46h
62h
63h
50h
92h
93h
96h
97h
51h
68h
00h
64h
65h
40h
90h
91h
D0h
60h
61h
01h
01h
46h
62h
63h
50h
92h
93h
01h
01h
51h
68h
00h
64h
65h
40h
90h
91h
D0h
60h
61h
94h
95h
46h
62h
63h
50h
92h
93h
96h
97h
51h
68h
00h
64h
65h
40h
90h
91h
D0h
60h
61h
01h
01h
46h
62h
63h
50h
92h
93h
01h
01h
51h
68h
00h
64h
65h
40h
90h
91h
D0h
60h
61h
94h
95h
46h
62h
63h
50h
92h
93h
96h
97h
51h
68h
00h
64h
65h
40h
90h
91h
D0h
60h
61h
01h
01h
46h
62h
63h
50h
92h
93h
01h
01h
51h
68h
00h
USCI_A0
USCI_B0
ADC12_A
TA0.CCIFG0
TA0.CCIFG1..4
USCI_A2
USCI_B2
DMA
Interrupts
TA1.CCIFG0
TA1.CCIFG1..2
P1
USCI_A1
USCI_B1
USCI_A3
USCI_B3
P2
RTC_A
Delimiter
(1) N/A = Not applicable
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10 Device and Documentation Support
10.1 Getting Started
For an introduction to the MSP430™ family of devices and the tools and libraries that are available to help with
your development, visit the MSP430 ultra-low-power sensing & measurement MCUs overview.
10.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. Figure 10-1 provides a legend for reading the complete device
name.
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MSP 430 F 5 438 A I PM T -EP
Processor Family
MCU Platform
Device Type
Series
Feature Set
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: Revision
Processor Family
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
MCU Platform
Device Type
430 = MSP430 low-power microcontroller platform
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash
L = No nonvolatile memory
Specialized Application
AFE = Analog front end
BQ = Contactless power
CG = ROM medical
FE = Flash energy meter
FG = Flash medical
FW = Flash electronic flow meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD driver
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD driver
0 = Low-voltage series
Feature Set
Various levels of integration within a series
Updated version of the base part number
Optional: Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)
-HT = Extreme temperature parts (–55°C to 150°C)
-Q1 = Automotive Q100 qualified
Figure 10-1. Device Nomenclature
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10.3 Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are
available from TI and various third parties. See them all at MSP430 Ultra-Low-Power MCUs – Tools & software.
Table 10-1 lists the debug features of the MSP430F543xA and MSP430F541xA MCUs. See the Code Composer
Studio IDE for MSP430 User's Guide for details on the available features.
Table 10-1. Hardware Debug Features
BREAK-
POINTS
(N)
RANGE
BREAK-
POINTS
LPMx.5
DEBUGGING
SUPPORT
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
CLOCK
CONTROL SEQUENCER
STATE
TRACE
BUFFER
MSP430Xv2
Yes
Yes
8
Yes
Yes
Yes
Yes
No
Design Kits and Evaluation Modules
MSP-TS430PZ5x100 - 100-pin Target Development Board for MSP430F5x MCUs
The MSP-TS430PZ5X100 is a stand-alone ZIF socket target board used to program and debug the MSP430
MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.
100-pin Target Development Board and MSP-FET Programmer Bundle for MSP430F5x MCUs
The MSP-FET430U5x100 is a powerful flash emulation tool (FET) that includes the hardware and software
required to quickly begin application development on the MSP430 MCU. It includes a ZIF socket target board
(MSP-TS430PZ5x100) and a USB debugging interface (MSP-FET) used to program and debug the MSP430 in-
system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased
and programmed in seconds with only a few keystrokes, and since the MSP430 flash is ultra-low power, no
external power supply is required.
MSP430F5438 Experimenter Board
The MSP430F5438 Experimenter Board (MSP-EXP430F5438) is a microcontroller development for highly
integrated, high performance MSP430F5438 MCUs. It features a 100-pin socket which supports the
MSP430F5438A and other devices with similar pinout. The socket allows for quick upgrades to newer devices or
quick applications changes. It is compatible with many TI low-power RF wireless development kits such as the
CC2520EMK. The Experimenter Board helps designers quickly learn and develop using the F5xx MCUs, which
provide low power, more memory and leading integration for applications such as energy harvesting, wireless
sensing and automatic metering infrastructure (AMI).
Software
MSP430Ware™ Software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware software also includes a high-level API called MSP Driver Library. This
library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of
Code Composer Studio™ IDE or as a stand-alone package.
MSP430F543xA, MSP430F541xA Code Examples
C Code examples are available for every MSP device that configures each of the integrated peripherals for
various application needs.
MSP Driver Library
Driver Library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing easy-
to-use function calls. Thorough documentation is delivered through a helpful API Guide, which includes details
on each function call and the recognized parameters. Developers can use Driver Library functions to write
complete projects with minimal overhead.
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MSP EnergyTrace™ Technology
EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and
displays the application's energy profile and helps to optimize it for ultra-low-power consumption.
ULP (Ultra-Low Power) Advisor
ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully utilize the unique
ultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new
microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every
last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks to
highlight areas of your code that can be further optimized for lower power.
IEC60730 Software Package
The IEC60730 MSP430 software package was developed to be useful in assisting customers in complying with
IEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General
Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters,
power tools, e-bikes, and many others. The IEC60730 MSP430 software package can be embedded in customer
applications running on MSP430s to help simplify the customer’s certification efforts of functional safety-
compliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP
The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 devices. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath
libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430
Continuing to innovate in the low power and low cost microcontroller space, TI brings you MSPMATHLIB.
Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you
up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated
in both Code Composer Studio and IAR IDEs. Read the user’s guide for an in depth look at the math library and
relevant benchmarks.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports all MSP microcontroller
devices. Code Composer Studio comprises a suite of embedded software utilities used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar utilities and interfaces allow users to get started faster
than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with
advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment
for embedded developers. When using CCS with an MSP MCU, a unique and powerful set of plugins and
embedded software utilities are made available to fully leverage the MSP microcontroller.
Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) files directly to the MSP microcontroller without an IDE.
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MSP430F5418A
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MSP430F5418A
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MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – which allows users to
quickly begin application development on MSP low-power microcontrollers (MCU). Creating MCU software
usually requires downloading the resulting binary program to the MSP device for validation and debugging. The
MSP-FET provides a debug communication pathway between a host computer and the target MSP.
Furthermore, the MSP-FET also provides a Backchannel UART connection between the computer's USB
interface and the MSP UART. This affords the MSP programmer a convenient method for communicating serially
between the MSP and a terminal running on the computer. It also supports loading programs (often called
firmware) to the MSP target using the BSL (bootloader) through the UART and I2C communication protocols.
MSP-GANG Production Programmer
The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight
identical MSP430 or MSP432 Flash or FRAM devices at the same time. The MSP Gang Programmer connects
to a host PC using a standard RS-232 or USB connection and provides flexible programming options that allow
the user to fully customize the process. The MSP Gang Programmer is provided with an expansion board, called
the Gang Splitter, that implements the interconnections between the MSP Gang Programmer and multiple target
devices. Eight cables are provided that connect the expansion board to eight target devices (through JTAG or
Spy-Bi-Wire connectors). The programming can be done with a PC or as a stand-alone device. A PC-side
graphical user interface is also available and is DLL-based.
10.4 Documentation Support
The following documents describe the MSP430F543xA and MSP430F541xA MCUs. Copies of these documents
are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com (for links to the product folders, see Section 10.5). In the upper right corner, click the "Alert me"
button. This registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
Errata
MSP430F5438A Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F5437A Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F5436A Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F5435A Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F5419A Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
MSP430F5418A Device Erratasheet
Describes the known exceptions to the functional specifications for all silicon revisions of this device.
Copyright © 2020 Texas Instruments Incorporated
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MSP430F5418A
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SLAS655G – JANUARY 2010 – REVISED SEPTEMBER 2020
www.ti.com
User's Guides
MSP430F5xx and MSP430F6xx Family User's Guide
Detailed information on the modules and peripherals available in this device family.
MSP430 Flash Device Bootloader (BSL) User's Guide
The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller
during the prototyping phase, final production, and in service. Both the programmable memory (flash memory)
and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap
loader programs found in some digital signal processors (DSPs) that automatically load program code (and data)
from external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module of the
MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,
it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the
parallel port interface and the USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators
Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the
correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages
and the need for designing cost-effective and ultra-low-power components. This application report addresses
three different ESD topics to help board designers and OEMs understand and design robust system-level
designs.
10.5 Related Links
Table 10-2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 10-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
MSP430F5438A
MSP430F5437A
MSP430F5436A
MSP430F5435A
MSP430F5419A
MSP430F5418A
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
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MSP430F5418A
MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A, MSP430F5419A,
MSP430F5418A
SLAS655G – JANUARY 2010 – REVISED SEPTEMBER 2020
www.ti.com
10.6 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.7 Trademarks
MicroStar Junior™, MSP430™, MSP430Ware™, Code Composer Studio™, EnergyTrace™, ULP Advisor™, TI
E2E™ are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
10.8 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.9 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
10.10 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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SLAS655G – JANUARY 2010 – REVISED SEPTEMBER 2020
www.ti.com
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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MSP430F5418A
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
119
1000
90
(1)
(2)
(3)
(4/5)
(6)
MSP430F5418AIPN
MSP430F5418AIPNR
MSP430F5419AIPZ
MSP430F5419AIPZR
ACTIVE
LQFP
LQFP
LQFP
LQFP
PN
80
80
Green (RoHS
& no Sb/Br)
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
M430F5418A
ACTIVE
ACTIVE
ACTIVE
PN
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
M430F5418A
M430F5419A
M430F5419A
PZ
100
100
Green (RoHS
& no Sb/Br)
PZ
1000
Green (RoHS
& no Sb/Br)
MSP430F5419AIZCAR
MSP430F5419AIZCAT
MSP430F5419AIZQWR
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
ZCA
ZCA
ZQW
113
113
113
2500
250
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
F5419A
TBD
F5419A
BGA
MICROSTAR
JUNIOR
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
M430F5419A
MSP430F5419AIZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430F5419A
MSP430F5435AIPN
MSP430F5435AIPNR
MSP430F5436AIPZ
MSP430F5436AIPZR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
PN
PN
PZ
PZ
80
80
119
1000
90
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
M430F5435A
M430F5435A
M430F5436A
M430F5436A
Green (RoHS
& no Sb/Br)
100
100
Green (RoHS
& no Sb/Br)
1000
Green (RoHS
& no Sb/Br)
MSP430F5436AIZCAR
MSP430F5436AIZCAT
MSP430F5436AIZQWR
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
ZCA
ZCA
ZQW
113
113
113
2500
250
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
F5436A
TBD
F5436A
BGA
MICROSTAR
JUNIOR
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
M430F5436A
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F5436AIZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
M430F5436A
MSP430F5437AIPN
MSP430F5437AIPNR
MSP430F5438AIPZ
MSP430F5438AIPZR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
PN
PN
PZ
PZ
80
80
119
1000
90
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
M430F5437A
M430F5437A
M430F5438A
M430F5438A
Green (RoHS
& no Sb/Br)
100
100
Green (RoHS
& no Sb/Br)
1000
Green (RoHS
& no Sb/Br)
MSP430F5438AIZCAR
MSP430F5438AIZCAT
MSP430F5438AIZQWR
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
ZCA
ZCA
ZQW
113
113
113
2500
250
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
F5438A
TBD
F5438A
BGA
MICROSTAR
JUNIOR
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
M430F5438A
MSP430F5438AIZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
M430F5438A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2020
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF MSP430F5438A :
Enhanced Product: MSP430F5438A-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F5418AIPNR
MSP430F5419AIPZR
LQFP
LQFP
PN
PZ
80
1000
1000
2500
330.0
330.0
330.0
24.4
24.4
16.4
15.0
17.0
7.3
15.0
17.0
7.3
2.1
2.1
1.5
20.0
20.0
12.0
24.0
24.0
16.0
Q2
Q2
Q1
100
113
MSP430F5419AIZQWR BGA MI
ZQW
CROSTA
R JUNI
OR
MSP430F5419AIZQWT BGA MI
ZQW
113
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
CROSTA
R JUNI
OR
MSP430F5435AIPNR
MSP430F5436AIPZR
LQFP
LQFP
PN
PZ
80
1000
1000
2500
330.0
330.0
330.0
24.4
24.4
16.4
15.0
17.0
7.3
15.0
17.0
7.3
2.1
2.1
1.5
20.0
20.0
12.0
24.0
24.0
16.0
Q2
Q2
Q1
100
113
MSP430F5436AIZQWR BGA MI
ZQW
CROSTA
R JUNI
OR
MSP430F5436AIZQWT BGA MI
ZQW
PN
113
80
250
180.0
330.0
16.4
24.4
7.3
7.3
1.5
2.1
12.0
20.0
16.0
24.0
Q1
Q2
CROSTA
R JUNI
OR
MSP430F5437AIPNR
LQFP
1000
15.0
15.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F5438AIPZR
LQFP
PZ
100
113
1000
2500
330.0
330.0
24.4
16.4
17.0
7.3
17.0
7.3
2.1
1.5
20.0
12.0
24.0
16.0
Q2
Q1
MSP430F5438AIZQWR BGA MI
ZQW
CROSTA
R JUNI
OR
MSP430F5438AIZQWT BGA MI
ZQW
113
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
CROSTA
R JUNI
OR
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F5418AIPNR
MSP430F5419AIPZR
LQFP
LQFP
PN
PZ
80
1000
1000
2500
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
100
113
MSP430F5419AIZQWR BGA MICROSTAR
JUNIOR
ZQW
MSP430F5419AIZQWT BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
MSP430F5435AIPNR
MSP430F5436AIPZR
LQFP
LQFP
PN
PZ
80
1000
1000
2500
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
100
113
MSP430F5436AIZQWR BGA MICROSTAR
JUNIOR
ZQW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2020
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F5436AIZQWT BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
MSP430F5437AIPNR
MSP430F5438AIPZR
LQFP
LQFP
PN
PZ
80
1000
1000
2500
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
100
113
MSP430F5438AIZQWR BGA MICROSTAR
JUNIOR
ZQW
MSP430F5438AIZQWT BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
Pack Materials-Page 3
PACKAGE OUTLINE
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZCA0113A
A
7.1
6.9
B
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.08 C
0.25
0.15
BALL TYP
5.5
TYP
(0.75) TYP
SYMM
M
L
K
J
(0.75) TYP
H
G
F
E
D
C
SYMM
5.5
TYP
0.35
0.25
113X Ø
B
A
0.15
0.05
C
C
A B
1
2
3
4
5
6
7
8
9 10 11 12
0.5 TYP
0.5 TYP
4225149/A 08/2019
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZCA0113A
(0.5) TYP
(0.5) TYP
1
2
3
4
5
6
7
8
9
10 11 12
A
B
C
D
E
F
113X (Ø0.25)
SYMM
G
H
J
K
L
M
SYMM
LAND PATTERN EXAMPLE
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED
METAL
(Ø 0.25)
METAL
(Ø 0.25)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225149/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZCA0113A
(0.5) TYP
(0.5) TYP
1
2
3
4
5
6
7
8
9
10 11 12
A
B
C
D
E
F
(R0.05)
SYMM
G
H
J
METAL TYP
113X ( 0.25)
K
L
M
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 10X
4225149/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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