MSP430F5252 [TI]
具有 128KB 闪存、16KB SRAM、比较器、DMA、UART/SPI/I2C 和 1.8V 双电源 I/O 的 25MHz MCU;型号: | MSP430F5252 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 128KB 闪存、16KB SRAM、比较器、DMA、UART/SPI/I2C 和 1.8V 双电源 I/O 的 25MHz MCU 静态存储器 比较器 闪存 |
文件: | 总112页 (文件大小:3972K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
ZHCSER2D –MAY 2013 –REVISED OCTOBER 2020
MSP430F525x 混合信号微控制器
• 单一时钟系统
1 特性
– 针对频率稳定的锁相环(FLL) 控制环路
– 低功耗低频内部时钟源(VLO)
– 低频修整内部基准源(REFO)
– 32kHz 手表晶振(XT1)
• 双电源电压器件
– 主电源(AVCC、DVCC)
• 由外部电源供电:
– 高达32MHz 的高频晶体(XT2)
• 配有五个捕捉/比较寄存器的16 位计时器TA0,
Timer_A
从3.6V 低至1.8V
• 多达18 个通用I/O,支持多达8 个外部中断
– 低压接口电源(DVIO)
• 配有三个捕捉/比较寄存器的16 位计时器TA1,
Timer_A
• 配有三个捕捉/比较寄存器的16 位计时器TA2,
Timer_A
• 由单独的外部电源供电:1.62 V 至1.98 V
• 多达35 个通用I/O,支持多达16 个外部中
断
• 串行通信
• 具有七个捕捉/比较影子寄存器的16 位计时器
TB0,Timer_B
• 四个通用串行通信接口
• 超低功耗
– 工作模式(AM):
所有系统时钟均工作
– USCI_A0、A1、A2 和A3 均支持:
在8MHz、3.0V 且闪存程序执行时为
290µA/MHz(典型值)
在8MHz、3.0V 且RAM 程序执行时为
• 具有自动波特率检测功能的增强型通用异步
收发器(UART)
• 红外数据通讯(IrDA) 编码器和解码器
• 同步SPI
150µA/MHz(典型值)
– 待机模式(LPM3):
– USCI_B0、B1、B2 和B3 均支持:
含晶体的实时时钟(RTC)、看门狗、电源监控器
可用,完全RAM 保持,快速唤醒:
2.2V 时为2.1µA,3.0V 时为2.3µA(典型值)
低功耗振荡器(VLO)、通用计数器、看门狗、电
源监控器可用,完全RAM 保持,快速唤醒:
3.0V 时为1.6µA(典型值)
• I2C
• 同步串行外设接口(SPI)
• 带内部基准、采样保持功能的10 位模数转换器
(ADC)
• 比较器
• 硬件乘法器支持32 位运算
• 串行板上编程,无需外部编程电压
• 3 通道内部DMA
• 具有RTC 功能的基本定时器
• 器件比较汇总了可用的产品系列成员和封装
– 关闭模式(LPM4):
完全RAM 保持、电源监控器可用、快速唤醒:
3.0V 时为1.3µA(典型值)
– 关断模式(LPM4.5):
3.0V 时为0.18µA(典型值)
• 在3.5μs(典型值)内从待机模式唤醒
• 16 位RISC 架构,扩展存储器,高达25MHz 的系
统时钟
2 应用
• “常开型”系统控制器
• 电源管理集线器
• Bluetooth® 控制器
• 模拟和数字传感器融合系统
• 数据记录器
• 灵活的电源管理系统
– 具有可编程稳压内核电源电压的完全集成LDO
– 电源电压监控、监视和欠压保护
• 通用应用
3 说明
使用一款“始终开启”的超低功耗系统控制器,可为手机和平板电脑等便携式设备显著降低功耗。当高耗电的应
用处理器和触摸屏控制器关闭时,这些控制器可充当传感器集线器并监视用户激励信号(例如,读取惯性传感器
或触摸传感器)和重要的系统参数(例如,电池健康状况和温度)。之后,微控制器会根据用户输入或者在出现
故障需要CPU 干预时“唤醒”系统。
MSP430F525x 系列是 1.8V 双电源 I/O 产品系列中最新推出的产品(以前仅提供 MSP430F522x),专为“常开
型”系统控制器应用而设计。凭借 1.8V I/O,无需进行外部电平转换即可无缝连接至应用处理器和其他器件,同
时MCU 的主电源可处于更高的电压轨上。
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLAS903
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
ZHCSER2D –MAY 2013 –REVISED OCTOBER 2020
www.ti.com.cn
与 MSP430F522x 相比,MSP430F525x 的 RAM 容量翻了两番 (32KB),串行接口数量也翻了一倍(四个
USCI_A 和四个 USCI_B)。MSP430F525x 还采用 4 个 16 位计时器、1 个高性能 10 位 ADC、1 个硬件乘法
器、DMA、1 个比较器和 1 个具有警报功能的 RTC 模块。MSP430F525x 在工作模式下(从闪存运行)的电流消
耗为 290 µA/MHz(典型值),在待机模式 (LPM3) 下的电流消耗为 1.6µA(典型值)。MSP430F525x 可在
3.5µs(典型值)内切换至工作模式,因此非常适合“常开型”低功耗应用。
MSP430F525x 的主要优势如下:
• 高达32KB 的RAM,支持复杂的传感器集线器算法以及键盘控制和电源管理等高级聚合。
• 四个USCI_A 和四个USCI_B 模块,支持八个专用硬件串行接口(例如,四个I2C 和四个SPI)并行工作,从
而快速而稳定地与传感器或外设进行通信。
• 多达35 个可在1.8V 电压轨中使用的I/O。
有关完整的模块说明,请参阅 MSP430F5xx 和 MSP430F6xx 系列用户指南。有关设计指南,请参阅使用
MSP430F522x 和MSP430F521x 器件进行设计。
器件信息
器件型号(1)
MSP430F5259IRGC
MSP430F5252IZXH
MSP430F5252IZQE(3)
封装尺寸(2)
9mm x 9mm
5mm × 5mm
5mm × 5mm
封装
VQFN (64)
nFBGA (80)
MicroStar Junior™ BGA (80)
(1) 如需获得所有可用器件的最新部件、封装和订购信息,请参阅封装选项附录(节11)或浏览TI 网站
www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸,请参阅机械数据(节11 中)。
(3) 采用ZQE (MicroStar Junior BGA) 封装的所有可订购器件型号均已更改为“最后可采购期限”状
态。有关此状态的详细信息,请访问产品生命周期页面。
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MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
ZHCSER2D –MAY 2013 –REVISED OCTOBER 2020
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4 Functional Block Diagram
图4-1 shows the functional block diagram.
DVCC AVCC
DVSS AVSS
PB
PC
PD
PJ
PA
XIN XOUT
DVIO VCORE
RSTDVCC RST/NMI BSLEN
P1.x P2.x P3.x P4.x P5.x P6.x
P7.x PJ.x
P6(1)
1×8 I/Os
P1(1)(2)
1×8 I/Os
P3
P4 P5
1×8 I/Os 1×6 I/Os
P7
1×6 I/Os
XT2IN
P2(1)(2)
SYS
4x
ACLK
Power
Management
1×8 I/Os1×5 I/Os
Unified
Clock
System
USCI_Ax:
UART,
IrDA, SPI
PA(1)(2)
1×16 I/Os
128KB
Flash
32KB
16KB
PB
1×13 I/Os
PC
1×14 I/Os
PD PJ
1×6 I/Os 1×4 I/Os
Watchdog
XT2OUT
SMCLK
Port Map
Control
(P4)
I/O Ports
LDO
SVM, SVS
Brownout
4x
USCI_Bx:
SPI, I2C
RAM
MCLK
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
ADC10_A
TA0
TA1
TA2
TB0
10 Bit
200 ksps
12 Channels
(10 ext, 2 int)
JTAG,
SBW
Interface
COMP_B
RTC_A
MPY32
CRC16
REF
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
8 Channels
I/O are supplied by DVIO
(1) Interrupt capability
(2) Wakeup capability
Copyright © 2016, Texas Instruments Incorporated
图4-1. Functional Block Diagram
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MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
ZHCSER2D –MAY 2013 –REVISED OCTOBER 2020
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Table of Contents
8.21 Crystal Oscillator, XT1, Low-Frequency Mode........27
8.22 Crystal Oscillator, XT2............................................ 28
8.23 Internal Very-Low-Power Low-Frequency
Oscillator (VLO)...........................................................29
8.24 Internal Reference, Low-Frequency Oscillator
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison.........................................................7
6.1 Related Products........................................................ 7
7 Terminal Configuration and Functions..........................8
7.1 Pin Diagrams.............................................................. 8
7.2 Signal Descriptions................................................... 10
8 Specifications................................................................ 15
8.1 Absolute Maximum Ratings...................................... 15
8.2 ESD Ratings............................................................. 15
8.3 Recommended Operating Conditions.......................15
8.4 Active Mode Supply Current Into VCC Excluding
(REFO)........................................................................29
8.25 DCO Frequency......................................................30
8.26 PMM, Brownout Reset (BOR).................................31
8.27 PMM, Core Voltage.................................................31
8.28 PMM, SVS High Side..............................................31
8.29 PMM, SVM High Side............................................. 32
8.30 PMM, SVS Low Side...............................................32
8.31 PMM, SVM Low Side..............................................33
8.32 Wake-up Times From Low-Power Modes and
Reset...........................................................................33
8.33 Timer_A...................................................................34
8.34 Timer_B...................................................................34
8.35 USCI (UART Mode) Clock Frequency.................... 35
8.36 USCI (UART Mode)................................................ 35
8.37 USCI (SPI Master Mode) Clock Frequency............ 35
8.38 USCI (SPI Master Mode)........................................ 35
8.39 USCI (SPI Slave Mode).......................................... 37
8.40 USCI (I2C Mode).....................................................39
8.41 10-Bit ADC, Power Supply and Input Range
Conditions................................................................... 40
8.42 10-Bit ADC, Timing Parameters..............................40
8.43 10-Bit ADC, Linearity Parameters...........................41
8.44 REF, External Reference........................................ 41
8.45 REF, Built-In Reference.......................................... 42
8.46 Comparator_B.........................................................43
8.47 Flash Memory......................................................... 44
8.48 JTAG and Spy-Bi-Wire Interface.............................44
8.49 DVIO BSL Entry......................................................45
9 Detailed Description......................................................46
9.1 CPU.......................................................................... 46
9.2 Operating Modes...................................................... 47
9.3 Interrupt Vector Addresses....................................... 48
9.4 Memory Organization................................................49
9.5 Bootloader (BSL)...................................................... 50
9.6 JTAG Operation........................................................ 52
9.7 Flash Memory........................................................... 54
9.8 RAM..........................................................................54
9.9 Peripherals................................................................55
9.10 Input/Output Diagrams............................................78
9.11 Device Descriptors..................................................94
10 Device and Documentation Support..........................96
10.1 Getting Started and Next Steps.............................. 96
10.2 Device Nomenclature..............................................96
10.3 Tools and Software................................................. 98
10.4 Documentation Support........................................ 100
10.5 Related Links........................................................ 102
10.6 支持资源................................................................102
10.7 Trademarks...........................................................102
10.8 静电放电警告........................................................ 102
10.9 Export Control Notice............................................102
10.10 术语表................................................................. 102
11 Mechanical, Packaging, and Orderable
External Current.......................................................... 18
8.5 Low-Power Mode Supply Currents (Into VCC
)
Excluding External Current..........................................19
8.6 Thermal Resistance Characteristics......................... 20
8.7 Schmitt-Trigger Inputs –General-Purpose I/O
DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0
to PJ.3, RSTDVCC).....................................................21
8.8 Schmitt-Trigger Inputs –General-Purpose I/O
DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to
P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)..21
8.9 Inputs –Interrupts DVCC Domain Port P6
(P6.0 to P6.7).............................................................. 21
8.10 Inputs –Interrupts DVIO Domain Ports P1 and
P2 (P1.0 to P1.7, P2.0 to P2.7)...................................21
8.11 Leakage Current –General-Purpose I/O
DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0
to PJ.3)........................................................................22
8.12 Leakage Current –General-Purpose I/O DVIO
Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4,
P4.0 to P4.7, P7.0 to P7.5)..........................................22
8.13 Outputs –General-Purpose I/O DVCC
Domain (Full Drive Strength) (P5.0 to P5.5, P6.0
to P6.7, PJ.0 to PJ.3).................................................. 22
8.14 Outputs –General-Purpose I/O DVCC
Domain (Reduced Drive Strength) (P5.0 to P5.5,
P6.0 to P6.7, PJ.0 to PJ.3)..........................................23
8.15 Outputs –General-Purpose I/O DVIO Domain
(Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7,
P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)....................23
8.16 Outputs –General-Purpose I/O DVIO Domain
(Reduced Drive Strength) (P1.0 to P1.7, P2.0 to
P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5).......... 23
8.17 Output Frequency –General-Purpose I/O
DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0
to PJ.3)........................................................................24
8.18 Output Frequency –General-Purpose I/O
DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to
P3.4, P4.0 to P4.7, P7.0 to P7.5)................................ 24
8.19 Typical Characteristics –Outputs, Reduced
Drive Strength (PxDS.y = 0)........................................25
8.20 Typical Characteristics –Outputs, Full Drive
Strength (PxDS.y = 1)................................................. 26
Information.................................................................. 103
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MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
ZHCSER2D –MAY 2013 –REVISED OCTOBER 2020
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5 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from revision C to revision D
Changes from September 28, 2018 to October 20, 2020
Page
• 更新了整个文档中的章节、表格、图和交叉参考的编号..................................................................................... 1
• 通篇添加了nFBGA 封装(ZXH) 信息..................................................................................................................1
• 器件信息中添加了有关采用ZQE 封装的所有可订购器件型号的状态变化说明...................................................1
• Corrected the description of the P2.3/UCB3SOMI/UCB3SCL signals in 表7-1, Terminal Functions ..............10
• Changed the MAX value of the IERASE and IMERASE, IBANK parameters in 节8.47, Flash Memory ..................44
Changes from revision B to revision C
Changes from November 26, 2015 to September 27, 2018
Page
• Added 节6.1, Related Products ........................................................................................................................ 7
• Added color to P1.0 (pin H2) and DVSS (pin F9) to indicate supply from DVIO in 图7-2, 80-Pin ZXH or ZQE
Package (Top View) ...........................................................................................................................................8
• Added typical conditions statements at the beginning of 节8, Specifications .................................................15
• Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in 节8.26, PMM, Brownout
Reset (BOR) .................................................................................................................................................... 31
• Updated notes (1) and (2) and added note (3) in 节8.32, Wake-up Times From Low-Power Modes and Reset
..........................................................................................................................................................................33
• Removed ADC10DIV from the formula for the TYP value in the second row of the tCONVERT parameter in 节
8.42, 10-Bit ADC, Timing Parameters, because ADC10CLK is after division.................................................. 40
• Added second row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs in 节
8.46, Comparator_B ........................................................................................................................................ 43
• Renamed FCTL4.MGR0 and MGR1 bits in the fMCLK,MGR parameter in 节8.47, Flash Memory, to be
consistent with header files ..............................................................................................................................44
• Added links to the custom BSL430 package download in 节9.5, Bootloader (BSL) .......................................50
• Replaced former section Development Tools Support with 节10.3, Tools and Software ................................98
• Updated list of related documentation in 节10.4, Documentation Support ...................................................100
Changes from revision A to revision B
Changes from July 31, 2013 to November 25, 2015
Page
• 通篇更改了格式和结构,包括添加了章节编号....................................................................................................1
• 添加了器件信息表..............................................................................................................................................1
• Moved 节4, Functional Block Diagram ............................................................................................................. 3
• Added 16KB RAM option in 图4-1, Functional Block Diagram ......................................................................... 3
• Added 节6, Device Comparison, and moved 表6-1 to it...................................................................................7
• Added 节7, Terminal Configuration and Functions, and moved pinout drawings and terminal functions table
to it .....................................................................................................................................................................8
• Added indication of terminals powered by DVIO in RGC pinout ........................................................................8
• Added indication of terminals powered by DVIO in ZQE pinout......................................................................... 8
• Removed preview YFF pinout............................................................................................................................ 8
• Added SUPPLY column and removed YFF column in 表7-1, Terminal Functions ..........................................10
• Added 节8.2, ESD Ratings ............................................................................................................................. 15
• Added note on CVCORE .................................................................................................................................... 15
• Added 节8.6, Thermal Resistance Characteristics .........................................................................................20
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• Moved note on RPull from 节8.7 to 节8.8 ........................................................................................................21
• Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF in 节8.21,
Crystal Oscillator, XT1, Low-Frequency Mode ................................................................................................ 27
• Corrected Test Conditions (removed VREF–) for all parameters in 节8.43 ..................................................... 41
• Updated Test Conditions for all parameters in 节8.43, 10-Bit ADC, Linearity Parameters: changed from
"CVREF+ = 20 pF" to "CVeREF+ = 20 pF"; changed from "(VeREF+ –VeREF–)min ≤(VeREF+ –VeREF–)" to
"1.4 V ≤(VeREF+ –VeREF–)".......................................................................................................................... 41
• Added "CVeREF+ = 20 pF" to EI Test Conditions................................................................................................41
• Added "ADC10SREFx = 11b" to Test Conditions for EG and ET ......................................................................41
• Corrected Test Conditions (removed VREF–) for VeREF+, VeREF–, and (VeREF+ –VeREF–) parameters in 节
8.44, REF, External Reference ........................................................................................................................ 41
• Changed MIN value of AVCC(min) with Test Conditions of "REFVSEL = {0} for 1.5 V" from 2.2 V to 1.8 V in 节
8.45, REF, Built-In Reference .......................................................................................................................... 42
• Corrected spelling of MRG bits in fMCLK,MRG parameter symbol and description............................................. 44
• Throughout document, changed all instances of "bootstrap loader" to "bootloader"........................................50
• Added note to clarify that all JTAG pins are on DVCC......................................................................................52
• Added note to indicate that all SBW pins are on DVCC................................................................................... 53
• Corrected spelling of NMIIFG in 表9-10, System Module Interrupt Vector Registers .....................................58
• Removed YFF package information from 表9-12, TA0 Signal Connections ...................................................60
• Removed YFF package information from 表9-13, TA1 Signal Connections ...................................................61
• Removed YFF package information from 表9-14, TA2 Signal Connections ...................................................62
• Removed YFF package information from 表9-15, TB0 Signal Connections ...................................................63
• Changed 图9-8, Port P5 (P5.3) Diagram (added P5SEL.2 and XT2BYPASS inputs with AND and OR gates)
..........................................................................................................................................................................85
• Changed P5SEL.3 column from X to 0 for "P5.3 (I/O)" rows............................................................................85
• Changed 图9-10, Port P5 (P5.5) Diagram (added P5SEL.5 input and OR gate)............................................ 87
• Changed P5SEL.5 column from X to 0 for "P5.5 (I/O)" rows............................................................................87
• Added 节10 and moved Development Tools Support, Device and Development Tool Nomenclature,
Trademarks, and Electrostatic Discharge Caution sections to it.......................................................................96
• Added 节11, Mechanical, Packaging, and Orderable Information ................................................................103
Changes from initial release to revision A
REVISION
CHANGES
Updated PRODUCT PREVIEW release.
Added 节2.
SLAS903A
July 2013
Changed 节3.
Added Development Tools Support and 节10.2.
SLAS903
July 2013
PRODUCT PREVIEW release
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6 Device Comparison
表6-1 summarizes the available family members.
表6-1. Device Comparison
USCI
ADC10
_A
(Ch)
COMP
_B
(Ch)
CHANNEL
A:
UART,
FLASH SRAM
I/Os
I/Os
BSL
TYPE
DEVICE(1) (2)
Timer_A(3) Timer_B(4)
PACKAGE
CHANNEL
B:
(KB)
(KB)
DVCC(5) DVIO(6)
SPI, I2C
IrDA, SPI
64 RGC,
80 ZXH,
80 ZQE
10 ext,
2 int
MSP430F5259
MSP430F5258
MSP430F5257
MSP430F5256
MSP430F5255
MSP430F5254
MSP430F5253
MSP430F5252
128
128
128
128
128
128
128
128
32
32
16
16
32
32
16
16
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
7
7
7
7
7
7
7
7
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
18
18
18
18
18
18
18
18
35
35
35
35
35
35
35
35
I2C
I2C
64 RGC,
80 ZXH,
80 ZQE
N/A
64 RGC,
80 ZXH,
80 ZQE
10 ext,
2 int
I2C
64 RGC,
80 ZXH,
80 ZQE
N/A
I2C
64 RGC,
80 ZXH,
80 ZQE
10 ext,
2 int
UART
UART
UART
UART
64 RGC,
80 ZXH,
80 ZQE
N/A
64 RGC,
80 ZXH,
80 ZQE
10 ext,
2 int
64 RGC,
80 ZXH,
80 ZQE
N/A
(1) For the most current package and ordering information, see the Package Option Addendum in 节11, or see the TI website at
www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/
packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) All of these I/Os are on a single voltage rail supplied by DVCC.
(6) All of these I/Os are on a single voltage rail supplied by DVIO.
6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power microcontrollers
One platform. One ecosystem. Endless possibilities.
Companion products for MSP430F5259
Review products that are frequently purchased or used in conjunction with this product.
Reference designs
Find reference designs that leverage the best in TI technology to solve your system-level challenges.
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7 Terminal Configuration and Functions
7.1 Pin Diagrams
图7-1 shows the pinout of the 64-pin RGC package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P6.0/TA2CLK/SMCLK/CB0/A0
P6.1/TA2.0/CB1/A1
P6.2/TA2.1/CB2/A2
P6.3/TA2.2/CB3/A3
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
P5.0/A8/VeREF+
P5.1/A9/VeREF-
AVCC
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P4.7/PM_UCA3RXD/PM_UCA3SOMI
P4.6/PM_UCA3TXD/PM_UCA3SIMO
P4.5/PM_UCA1RXD/PM_UCA1SOMI
P4.4/PM_UCA1TXD/PM_UCA1SIMO
P4.3/PM_UCB1CLK/PM_UCA1STE
P4.2/PM_UCB1SOMI/PM_UCB1SCL
P4.1/PM_UCB1SIMO/PM_UCB1SDA
P4.0/PM_UCB1STE/PM_UCA1CLK
DVIO
10
11
12
13
14
15
16
DVSS
P3.4/UCA0RXD/UCA0SOMI
P3.3/UCA0TXD/UCA0SIMO
P3.2/UCB0CLK/UCA0STE
P3.1/UCB0SOMI/UCB0SCL
P3.0/UCB0SIMO/UCB0SDA
P2.7/UCB0STE/UCA0CLK
P5.4/XIN
P5.5/XOUT
AVSS
DVCC
DVSS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Supplied by DVIO
图7-1. 64-Pin RGC Package (Top View)
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图7-2 shows the pinout of the 80-pin ZXH or ZQE package.
TEST RST/NMI P7.5
P7.4
A7
P7.3
A8
P7.1
A9
P6.0 RSTDVCC PJ.2
A1
A2
A3
A4
A5
A6
P6.2
B1
P6.1
B2
PJ.3
B3
P5.3
B4
P5.2 BSLEN P7.2
P7.0
B5
B6
C6
D6
E6
F6
B7
B8
B9
P6.4
C1
P6.3
C2
PJ.1
C4
PJ.0
C5
P4.7
C7
P4.6
C8
P4.5
C9
P6.6
D1
P6.5
D2
P4.4
D7
P4.3
D8
P4.2
D9
P6.7
D3
D4
E4
F4
D5
E5
F5
DVIO
E9
P4.0
E8
P4.1
E7
P5.0
E1
P5.1
E2
E3
F3
G3
P5.4 AVCC
F1 F2
DVSS
F9
F7
F8
P5.5 AVSS
G1 G2
P1.3
G4
P1.6
G5
P2.1
G6
P3.4
G7
P3.2
G8
P3.3
G9
DVCC P1.0
P1.1
H3
P1.4
H4
P1.7
H5
P2.3
H6
P2.7
H7
P3.0
H8
P3.1
H9
H1
H2
DVSS
J1
VCORE P1.2
J2 J3
P1.5
J4
P2.0
J5
P2.2
J6
P2.4
J7
P2.5
J8
P2.6
J9
Supplied by DVIO
图7-2. 80-Pin ZXH or ZQE Package (Top View)
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7.2 Signal Descriptions
表7-1 describes the device signals.
表7-1. Terminal Functions
TERMINAL
NO.(2)
I/O(1)
SUPPLY
DESCRIPTION
NAME
ZXH,
ZQE
RGC
General-purpose digital I/O with port interrupt
TA2 clock signal TA2CLK input
SMCLK output
P6.0/TA2CLK/SMCLK/CB0/A0
1
A1
I/O
DVCC
Comparator_B input CB0
Analog input A0 for ADC (not available on all device types)
General-purpose digital I/O with port interrupt
TA2 CCR0 capture: CCI0A input, compare: Out0 output
Comparator_B input CB1
P6.1/TA2.0/CB1/A1
2
B2
I/O
DVCC
Analog input A1 for ADC (not available on all device types)
BSL transmit output
General-purpose digital I/O with port interrupt
TA2 CCR1 capture: CCI1A input, compare: Out1 output
Comparator_B input CB2
P6.2/TA2.1/CB2/A2
P6.3/TA2.2/CB3/A3
3
4
B1
C2
I/O
I/O
DVCC
DVCC
Analog input A2 for ADC (not available on all device types)
BSL receive input
General-purpose digital I/O with port interrupt
TA2 CCR2 capture: CCI2A input, compare: Out2 output
Comparator_B input CB3
Analog input A3 for ADC (not available on all device types)
General-purpose digital I/O with port interrupt
Comparator_B input CB4
P6.4/CB4/A4
P6.5/CB5/A5
P6.6/CB6/A6
P6.7/CB7/A7
5
6
7
8
C1
D2
D1
D3
I/O
I/O
I/O
I/O
DVCC
DVCC
DVCC
DVCC
Analog input A4 for ADC (not available on all device types)
General-purpose digital I/O with port interrupt
Comparator_B input CB5
Analog input A5 for ADC (not available on all device types)
General-purpose digital I/O with port interrupt
Comparator_B input CB6
Analog input A6 for ADC (not available on all device types)
General-purpose digital I/O with port interrupt
Comparator_B input CB7
Analog input A7 for ADC (not available on all device types)
General-purpose digital I/O
Analog input A8 for ADC (not available on all device types)
P5.0/A8/VeREF+
9
E1
I/O
I/O
DVCC
DVCC
Input for an external reference voltage to the ADC (not
available on all device types)
General-purpose digital I/O
Analog input A9 for ADC (not available on all device types)
P5.1/A9/VeREF-
AVCC
10
11
E2
F2
Negative terminal for the ADC reference voltage for an external
applied reference voltage (not available on all device types)
Analog power supply
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表7-1. Terminal Functions (continued)
TERMINAL
NO.(2)
I/O(1)
SUPPLY
DESCRIPTION
NAME
ZXH,
ZQE
RGC
General-purpose digital I/O
P5.4/XIN
12
F1
I/O
I/O
DVCC
DVCC
Input terminal for crystal oscillator XT1(3)
General-purpose digital I/O
Output terminal of crystal oscillator XT1
Analog ground supply
P5.5/XOUT
13
G1
AVSS
DVCC
DVSS
14
15
16
G2
H1
J1
Digital power supply
Digital ground supply
Regulated core power supply output (internal use only, no
external current loading)
VCORE(4)
17
J2
DVCC
DVIO
General-purpose digital I/O with port interrupt
TA0 clock signal TA0CLK input
P1.0/TA0CLK/ACLK(5)
18
H2
I/O
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
P1.1/TA0.0(5)
P1.2/TA0.1(5)
P1.3/TA0.2(5)
P1.4/TA0.3(5)
P1.5/TA0.4(5)
19
20
21
22
23
H3
J3
I/O
I/O
I/O
I/O
I/O
DVIO
DVIO
DVIO
DVIO
DVIO
G4
H4
J4
P1.6/TA1CLK/CBOUT(5)
24
G5
I/O
DVIO
Comparator_B output
General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O with port interrupt
Slave in, master out –USCI_B3 SPI mode
I2C data –USCI_B3 I2C mode
P1.7/TA1.0(5)
P2.0/TA1.1(5)
P2.1/TA1.2(5)
25
26
27
H5
J5
I/O
I/O
I/O
DVIO
DVIO
DVIO
G6
P2.2/UCB3SIMO/UCB3SDA(5)
P2.3/UCB3SOMI/UCB3SCL(5)
28
29
J6
I/O
I/O
DVIO
DVIO
General-purpose digital I/O with port interrupt
Slave out, master in –USCI_B3 SPI mode
I2C clock –USCI_B3 I2C mode
H6
General-purpose digital I/O with port interrupt
Clock signal input –USCI_B3 SPI slave mode
Clock signal output –USCI_B3 SPI master mode
Slave transmit enable –USCI_A3 SPI mode
P2.4/UCB3CLK/UCA3STE(5)
30
J7
I/O
DVIO
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表7-1. Terminal Functions (continued)
TERMINAL
NO.(2)
I/O(1)
SUPPLY
DESCRIPTION
NAME
ZXH,
ZQE
RGC
General-purpose digital I/O with port interrupt
Slave transmit enable –USCI_B3 SPI mode
Clock signal input –USCI_A3 SPI slave mode
Clock signal output –USCI_A3 SPI master mode
General-purpose digital I/O with port interrupt
RTC clock output for calibration
P2.5/UCB3STE/UCA3CLK(5)
P2.6/RTCCLK/DMAE0(5)
31
J8
I/O
I/O
I/O
DVIO
DVIO
DVIO
32
33
J9
DMA external trigger input
General-purpose digital I/O
Slave transmit enable –USCI_B0 SPI mode
Clock signal input –USCI_A0 SPI slave mode
Clock signal output –USCI_A0 SPI master mode
General-purpose digital I/O
P2.7/UCB0STE/UCA0CLK(5)
H7
P3.0/UCB0SIMO/UCB0SDA(5)
P3.1/UCB0SOMI/UCB0SCL(5)
34
35
H8
H9
I/O
I/O
DVIO
DVIO
Slave in, master out –USCI_B0 SPI mode
I2C data –USCI_B0 I2C mode
General-purpose digital I/O
Slave out, master in –USCI_B0 SPI mode
I2C clock –USCI_B0 I2C mode
General-purpose digital I/O
Clock signal input –USCI_B0 SPI slave mode
Clock signal output –USCI_B0 SPI master mode
Slave transmit enable –USCI_A0 SPI mode
General-purpose digital I/O
P3.2/UCB0CLK/UCA0STE(5)
36
G8
I/O
DVIO
P3.3/UCA0TXD/UCA0SIMO(5)
P3.4/UCA0RXD/UCA0SOMI(5)
37
38
G9
G7
I/O
I/O
DVIO
DVIO
Transmit data –USCI_A0 UART mode
Slave in, master out –USCI_A0 SPI mode
General-purpose digital I/O
Receive data –USCI_A0 UART mode
Slave out, master in –USCI_A0 SPI mode
Digital ground supply
DVSS
39
40
F9
E9
DVIO(6)
Digital I/O power supply
General-purpose digital I/O with reconfigurable port mapping
secondary function
Default mapping: Slave transmit enable –USCI_B1 SPI mode
P4.0/PM_UCB1STE/
PM_UCA1CLK(5)
41
42
E8
E7
I/O
I/O
DVIO
DVIO
Default mapping: Clock signal input –USCI_A1 SPI slave
mode
Default mapping: Clock signal output –USCI_A1 SPI master
mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.1/PM_UCB1SIMO/
PM_UCB1SDA(5)
Default mapping: Slave in, master out –USCI_B1 SPI mode
Default mapping: I2C data –USCI_B1 I2C mode
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表7-1. Terminal Functions (continued)
TERMINAL
NO.(2)
I/O(1)
SUPPLY
DESCRIPTION
NAME
ZXH,
ZQE
RGC
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.2/PM_UCB1SOMI/
PM_UCB1SCL(5)
43
D9
I/O
DVIO
Default mapping: Slave out, master in –USCI_B1 SPI mode
Default mapping: I2C clock –USCI_B1 I2C mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
Default mapping: Clock signal input –USCI_B1 SPI slave
mode
P4.3/PM_UCB1CLK/
PM_UCA1STE(5)
44
D8
I/O
DVIO
Default mapping: Clock signal output –USCI_B1 SPI master
mode
Default mapping: Slave transmit enable –USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.4/PM_UCA1TXD/
PM_UCA1SIMO(5)
45
46
47
48
D7
C9
C8
C7
I/O
I/O
I/O
I/O
DVIO
DVIO
DVIO
DVIO
Default mapping: Transmit data –USCI_A1 UART mode
Default mapping: Slave in, master out –USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.5/PM_UCA1RXD/
PM_UCA1SOMI(5)
Default mapping: Receive data –USCI_A1 UART mode
Default mapping: Slave out, master in –USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.6/PM_UCA3TXD/
PM_UCA3SIMO(5)
Default mapping: Transmit data –USCI_A3 UART mode
Default mapping: Slave in, master out –USCI_A3 SPI mode
General-purpose digital I/O with reconfigurable port mapping
secondary function
P4.7/PM_UCA3RXD/
PM_UCA3SOMI(5)
Default mapping: Receive data –USCI_A3 UART mode
Default mapping: Slave out, master in –USCI_A3 SPI mode
General-purpose digital I/O
P7.0/UCA2TXD/UCA2SIMO(5)
P7.1/UCA2RXD/UCA2SOMI(5)
49
50
B8, B9
A9
I/O
I/O
DVIO
DVIO
Transmit data –USCI_A2 UART mode
Slave in, master out –USCI_A2 SPI mode
General-purpose digital I/O
Receive data –USCI_A2 UART mode
Slave out, master in –USCI_A2 SPI mode
General-purpose digital I/O
Clock signal input –USCI_B2 SPI slave mode
Clock signal output –USCI_B2 SPI master mode
Slave transmit enable –USCI_A2 SPI mode
General-purpose digital I/O
P7.2/UCB2CLK/UCA2STE(5)
51
B7
I/O
DVIO
P7.3/UCB2SIMO/UCB2SDA(5)
P7.4/UCB2SOMI/UCB2SCL(5)
52
53
A8
A7
I/O
I/O
DVIO
DVIO
Slave in, master out –USCI_B2 SPI mode
I2C data –USCI_B2 I2C mode
General-purpose digital I/O
Slave out, master in –USCI_B2 SPI mode
I2C clock –USCI_B2 I2C mode
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表7-1. Terminal Functions (continued)
TERMINAL
NO.(2)
I/O(1)
SUPPLY
DESCRIPTION
NAME
ZXH,
ZQE
RGC
General-purpose digital I/O
Slave transmit enable –USCI_B2 SPI mode
Clock signal input –USCI_A2 SPI slave mode
Clock signal output –USCI_A2 SPI master mode
BSL enable with internal pulldown
Reset input active low(7) (8)
P7.5/UCB2STE/UCA2CLK(5)
54
A6
I/O
DVIO
BSLEN(5)
55
56
B6
A5
I
I
DVIO
DVIO
RST/NMI(5)
Nonmaskable interrupt input(7)
General-purpose digital I/O
Input terminal for crystal oscillator XT2(9)
P5.2/XT2IN
57
58
59
60
61
62
63
B5
B4
A4
C5
C4
A3
B3
I/O
I/O
I
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
General-purpose digital I/O
P5.3/XT2OUT
TEST/SBWTCK(10)
PJ.0/TDO(11)
Output terminal of crystal oscillator XT2
Test mode pin –Selects four wire JTAG operation
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
General-purpose digital I/O
I/O
I/O
I/O
I/O
JTAG test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK(11)
PJ.2/TMS(11)
JTAG test data input or test clock input
General-purpose digital I/O
JTAG test mode select
General-purpose digital I/O
PJ.3/TCK(11)
JTAG test clock
Reset input active low(12)
RSTDVCC/SBWTDIO(11)
64
A2
I/O
DVCC
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation
activated
(13)
Reserved
QFN Pad
N/A
Pad
Reserved
N/A
QFN package pad. Connection to VSS recommended.
(1) I = input, O = output
(2) N/A = not available
(3) When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to
DVCC or DVSS to DVIO. In this case, the pin must be configured properly for the intended input swing.
(4) VCORE is for internal use only. No external current loading is possible. VCORE should be connected only to the recommended
capacitor value, CVCORE (see 节8.3).
(5) This pin function is supplied by DVIO. See 节8.8 for input and output requirements.
(6) The voltage on DVIO is not supervised or monitored.
(7) This pin is configurable as reset or NMI and resides on the DVIO supply domain. When driven from external, the input swing levels
from DVSS to DVIO are required.
(8) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(9) When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS
to DVCC or DVSS to DVIO. In this case, the must pin be configured properly for the intended input swing.
(10) See 节9.5.1 and 节9.6 for use with BSL and JTAG functions, respectively.
(11) See 节9.6 for use with JTAG function.
(12) This nonconfigurable reset resides on the DVCC supply domain and has an internal pullup to DVCC. When driven from external, input
swing levels from DVSS to DVCC are required. This reset must be used for Spy-Bi-Wire communication and is not the same RST/NMI
reset as found on other devices in the MSP430 family. Refer to 节9.5.1 and 节9.6 for details regarding the use of this pin.
(13) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
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8 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
4.1
UNIT
V
Voltage applied at VCC to VSS
–0.3
–0.3
–0.3
–0.3
Voltage applied at VIO to VSS
2.2
V
Voltage applied to any pin (excluding VCORE and VIO pins)(2)
Voltage applied to VIO pins
VCC + 0.3
VIO + 0.2
±2
V
V
Diode current at any device pin
mA
°C
(3)
Storage temperature, Tstg
150
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
8.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.
8.3 Recommended Operating Conditions
MIN NOM
MAX UNIT
PMMCOREVx = 0
1.8
2.0
3.6
3.6
Supply voltage during program execution
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
(1) (2)
VCC
and flash programming (AVCC = DVCC
)
V
(3)
2.2
3.6
PMMCOREVx = 0, 1, 2, 3
2.4
3.6
(2)
VIO
Supply voltage applied to DVIO referenced to VSS
Supply voltage (AVSS = DVSS
1.62
1.98
V
V
VSS
TA
)
0
Operating free-air temperature
Operating junction temperature
Recommended capacitor at VCORE(4)
85
85
°C
°C
nF
–40
–40
470
TJ
CVCORE
CDVCC
CVCORE
/
Capacitor ratio of DVCC to VCORE
10
0
PMMCOREVx = 0 (default condition),
1.8 V ≤VCC ≤3.6 V
8.0
Processor frequency (maximum MCLK
frequency)(5) (see 图8-3)
0
0
0
12.0
20.0
25.0
PMMCOREVx = 1, 2.0 V ≤VCC ≤3.6 V
PMMCOREVx = 2, 2.2 V ≤VCC ≤3.6 V
PMMCOREVx = 3, 2.4 V ≤VCC ≤3.6 V
fSYSTEM
MHz
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
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(2) During VCC and VIO power up, it is required that VIO ≥VCC during the ramp up phase of VIO. During VCC and VIO power down, it is
required that VIO ≥VCC during the ramp down phase of VIO (see 图8-1).
(3) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the 节8.28 threshold parameters for the
exact values and further details.
(4) TI recommends a capacitor tolerance of ±20% or better.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
VCC
VIO
VIO,min
VSS
t
VCC ≤ VIO
VIO ≤ VCC
VCC ≤ VIO
while VIO < VIO,min
while VIO < VIO,min
NOTE: The device supports continuous operation with VCC = VSS while VIO is fully within its specification. During this time, the general-
purpose I/Os that reside on the VIO supply domain are configured as inputs and pulled down to VSS through their internal pulldown
resistors. RST/NMI is high impedance. BSLEN is configured as an input and is pulled down to VSS through its internal pulldown resistor.
When VCC reaches above the BOR threshold, the general-purpose I/Os become high-impedance inputs (no pullup or pulldown
enabled), RST/NMI becomes an input pulled up to VIO through its internal pullup resistor, and BSLEN remains pulled down to VSS
through its internal pulldown resistor.
NOTE: Under certain condtions during the rising transition of VCC, the general-purpose I/Os that reside on the VIO supply domain may
actively transition high momentarily before settling to high-impedance inputs. These voltage transitions are temporary (typically
resolving to high impedance inputs when VCC exceeds approximately 0.9 V) and are bounded by the VIO supply.
图8-1. VCC and VIO Power Sequencing
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VCC
V(SVSH_+), min
tWAKE_UP_RESET
tWAKE_UP_RESET
tWAKE_UP_RESET
DVCC
VCC
VIT+
RSTDVCC
VCC ≥ VRSTDVCC
VRSTDVCC = VCC
VIO
tWAKE_UP_RESET
tWAKE_UP_RESET
DVIO
VIO
VIT+
RST
VIO ≥ VRST
VRST = VIO
t
NOTE:The device remains in reset based on the conditions of the RSTDVCC and RST pins and the voltage present on DVCC voltage
supply. If RSTDVCC or RST is held at a logic low or if DVCC is below the SVSH_+ minimum threshold, the device remains in its reset
condition; that is, these conditions form a logical OR with respect to device reset.
图8-2. Reset Timing
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25
20
12
3
2, 3
2
1, 2
1, 2, 3
1
8
0
0, 1
0, 1, 2
0, 1, 2, 3
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.
图8-3. Maximum System Frequency
8.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK
8 MHz 12 MHz 20 MHz
TYP MAX TYP MAX
)
EXECUTION
MEMORY
PARAMETER
VCC
PMMCOREVx
1 MHz
25 MHz
UNIT
TYP
MAX
TYP
MAX
TYP
10.1
5.3
MAX
11.0
6.2
0
1
2
3
0
1
2
3
0.36
0.40
0.44
0.46
0.20
0.22
0.24
0.26
0.47
2.32
2.65
2.90
3.10
1.20
1.35
1.50
1.60
2.60
4.0
4.3
4.6
4.4
IAM, Flash
Flash
3.0 V
mA
7.1
7.6
7.7
4.2
0.29
1.30
2.0
2.2
2.4
2.2
IAM, RAM
RAM
3.0 V
mA
3.7
3.9
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing.
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.
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8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREVx
25°C
TYP
60°C
TYP
85°C
TYP
UNIT
–40°C
TYP
MAX
MAX
91
MAX
MAX
103
124
29
2.2 V
3.0 V
2.2 V
3.0 V
0
3
0
3
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
73
89
78
95
84
101
10.6
11.6
3.4
3.6
3.8
3.6
3.8
3.9
4.0
2.6
2.8
2.9
2.9
2.6
2.7
2.8
2.8
0.26
93
112
13
ILPM0,1MHz
Low-power mode 0(3) (9)
Low-power mode 2(4) (9)
µA
µA
105
12
6.7
7.2
1.8
1.9
2.0
2.0
2.1
2.2
2.3
1.3
1.3
1.4
1.5
1.1
1.3
1.4
1.5
0.15
6.7
7.2
2.1
2.2
2.4
2.3
2.5
2.6
2.7
1.6
1.6
1.7
1.8
1.3
1.4
1.4
1.5
0.18
ILPM2
13
14
30
8.4
8.7
9.0
8.6
8.9
9.2
9.2
8.5
8.8
9.2
9.2
7.5
7.7
7.9
7.9
0.5
2.2 V
Low-power mode 3, crystal
mode(5) (9)
ILPM3,XT1LF
3.1
24
µA
µA
3.0 V
4.1
2.9
25
24
Low-power mode 3,
VLO mode(6) (9)
ILPM3,VLO
3.0 V
3.2
1.7
25
22
ILPM4
Low-power mode 4(7) (9)
Low-power mode 4.5(8)
3.0 V
3.0 V
µA
µA
1.8
23
ILPM4.5
0.35
1.0
Current supplied from DVIO
while DVCC = AVCC = 0 V,
DVIO = 1.62 V to 1.98 V,
All DVIO I/O floating
including BSLEN and
RST/NMI
IDVIO_START
0 V
1.40
1.40
2.0
1.45
1.5
2.1
µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Current for the watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
(4) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz, DCO setting = 1-
MHz operation, DCO bias generator enabled.)
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(7) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(8) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) Current for brownout and high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor
(SVML) disabled. High-side monitor (SVMH) disabled. RAM retention enabled.
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8.6 Thermal Resistance Characteristics
THERMAL METRIC(1) (2)
VALUE
29.3
52.0
14.2
23.9
1.1
UNIT
VQFN 64 (RGC)
BGA 80 (ZQE)
VQFN 64 (RGC)
BGA 80 (ZQE)
VQFN 64 (RGC)
BGA 80 (ZQE)
VQFN 64 (RGC)
BGA 80 (ZQE)
VQFN 64 (RGC)
BGA 80 (ZQE)
VQFN 64 (RGC)
BGA 80 (ZQE)
Junction-to-ambient thermal resistance, still air
Junction-to-case (top) thermal resistance
°C/W
RθJA
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(TOP)
RθJC(BOTTOM)
RθJB
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
N/A(3)
8.2
29.3
0.2
Junction-to-package-top thermal characterization parameter
Junction-to-board thermal characterization parameter
ΨJT
0.5
8.1
ΨJB
29.3
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) N/A = not applicable
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8.7 Schmitt-Trigger Inputs –General-Purpose I/O DVCC Domain
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
0.80
1.50
0.45
0.75
0.3
TYP
MAX UNIT
1.40
V
2.10
VIT+
VIT–
Vhys
Positive-going input threshold voltage
1.8 V
3 V
1.00
V
1.65
Negative-going input threshold voltage
1.8 V
3 V
0.8
V
1.0
Input voltage hysteresis (VIT+ –VIT–
)
0.4
For pullup: VIN = VSS
For pulldown: VIN = VCC
,
RPull
CI
Pullup or pulldown resistor
Input capacitance
20
35
5
50
kΩ
VIN = VSS or VCC
pF
(1) These same parametrics apply to the clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
8.8 Schmitt-Trigger Inputs –General-Purpose I/O DVIO Domain
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
MIN
0.8
1.1
0.3
0.5
0.3
TYP
MAX UNIT
1.62 V
1.25
V
1.40
VIT+
Positive-going input threshold voltage
VCC = 3.0 V
1.98 V
1.62 V
0.7
V
1.0
VIT–
Negative-going input threshold voltage
VCC = 3.0 V
1.98 V
Vhys
RPull
CI
VCC = 3.0 V
1.62 V to 1.98 V
0.8
50
V
Input voltage hysteresis (VIT+ –VIT–
Pullup or pulldown resistor(1)
Input capacitance
)
For pullup: VIN = VSS
,
20
35
5
kΩ
For pulldown: VIN = VIO
VIN = VSS or VIO
pF
(1) Also applies to the RST pin when the pullup or pulldown resistor is enabled.
8.9 Inputs –Interrupts DVCC Domain Port P6
(P6.0 to P6.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
t(int)
External interrupt timing(1)
External trigger pulse duration to set interrupt flag
1.8 V, 3 V
20
ns
(1) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
8.10 Inputs –Interrupts DVIO Domain Ports P1 and P2
(P1.0 to P1.7, P2.0 to P2.7)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(2)
PARAMETER
TEST CONDITIONS
VIO
MIN
MAX UNIT
External trigger pulse duration to set interrupt flag,
VCC = 1.8 V or 3.0 V
t(int)
External interrupt timing(1)
1.62 V to 1.98 V
20
ns
(1) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
(2) In all test conditions, VIO ≤VCC
.
.
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8.11 Leakage Current –General-Purpose I/O DVCC Domain
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See (1) (2)
VCC
MIN
MAX UNIT
50 nA
Ilkg(Px.y)
High-impedance leakage current
1.8 V, 3 V
–50
(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
8.12 Leakage Current –General-Purpose I/O DVIO Domain
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
See (2) (3)
VIO
MIN
MAX UNIT
50 nA
Ilkg(Px.y)
High-impedance leakage current
1.62 V to 1.98 V
–50
(1) In all test conditions, VIO ≤VCC
.
(2) The leakage current is measured with VSS or VIO applied to the corresponding pins, unless otherwise noted.
(3) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
8.13 Outputs –General-Purpose I/O DVCC Domain (Full Drive Strength)
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
VCC
MIN
VCC –0.25
VCC –0.60
VCC –0.25
VCC –0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –10 mA(2)
I(OHmax) = –5 mA(1)
I(OHmax) = –15 mA(2)
I(OLmax) = 3 mA(1)
VCC
VOH
High-level output voltage
V
VCC
3 V
1.8 V
3 V
VCC
VSS VSS + 0.25
I(OLmax) = 10 mA(2)
I(OLmax) = 5 mA(1)
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
I(OLmax) = 15 mA(2)
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
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8.14 Outputs –General-Purpose I/O DVCC Domain (Reduced Drive Strength)
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(1)
VCC
MIN
VCC –0.25
VCC –0.60
VCC –0.25
VCC –0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(1)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(1)
I(OLmax) = 3 mA(2)
I(OLmax) = 2 mA(1)
I(OLmax) = 6 mA(2)
VCC
VOH
High-level output voltage
V
VCC
3.0 V
1.8 V
3.0 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
(3) Selecting reduced drive strength may reduce EMI.
8.15 Outputs –General-Purpose I/O DVIO Domain (Full Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(2)
PARAMETER
TEST CONDITIONS
I(OHmax) = –100 µA(1)
VIO
MIN
VIO –0.05
VIO –0.25
VIO –0.50
MAX UNIT
VIO
I(OHmax) = –3 mA(1)
I(OHmax) = –6 mA(1)
I(OLmax) = 3 mA(1)
I(OLmax) = 6 mA(1)
VOH
High-level output voltage
1.62 V to 1.98 V
VIO
VIO
V
V
VSS VSS + 0.25
VSS VSS + 0.50
VOL
Low-level output voltage
1.62 V to 1.98 V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) In all test conditions, VIO ≤VCC
.
8.16 Outputs –General-Purpose I/O DVIO Domain (Reduced Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(2)
(3)
PARAMETER
TEST CONDITIONS
I(OHmax) = –100 µA(1)
VIO
MIN
VIO –0.05
VIO –0.25
VIO –0.50
MAX UNIT
VIO
I(OHmax) = –1 mA(1)
I(OHmax) = –2 mA(1)
I(OLmax) = 1 mA(1)
I(OLmax) = 2 mA(1)
VOH
High-level output voltage
1.62 V to 1.98 V
VIO
VIO
V
V
VSS VSS + 0.25
VSS VSS + 0.50
VOL
Low-level output voltage
1.62 V to 1.98 V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) Selecting reduced drive strength may reduce EMI.
(3) In all test conditions, VIO ≤VCC
.
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8.17 Output Frequency –General-Purpose I/O DVCC Domain
(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
VCC = 1.8 V,
PMMCOREVx = 0
16
Port output frequency
(with load)
fPx.y
See (1) (2)
MHz
25
VCC = 3 V,
PMMCOREVx = 3
VCC = 1.8 V,
PMMCOREVx = 0
16
ACLK, SMCLK, or MCLK,
CL = 20 pF(2)
fPort_CLK
Clock output frequency
MHz
25
VCC = 3 V,
PMMCOREVx = 3
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
.
8.18 Output Frequency –General-Purpose I/O DVIO Domain
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
VIO = 1.62 V to 1.98 V(3)
PMMCOREVx = 0
,
,
,
,
16
Port output frequency
(with load)
fPx.y
See (1) (2)
MHz
25
VIO = 1.62 V to 1.98 V(3)
PMMCOREVx = 3
VIO = 1.62 V to 1.98 V(3)
PMMCOREVx = 0
16
ACLK, SMCLK, or MCLK,
CL = 20 pF(2)
fPort_CLK
Clock output frequency
MHz
25
VIO = 1.62 V to 1.98 V(3)
PMMCOREVx = 3
(1) A resistive divider with 2 × R1 between VIO and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS
(2) The output voltage reaches at least 10% and 90% VIO at the specified toggle frequency.
.
(3) In all test conditions, VIO ≤VCC
.
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8.19 Typical Characteristics –Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
25.0
20.0
15.0
10.0
5.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
TA = 25°C
TA = 85°C
VCC = 3.0 V
Px.y
VCC = 1.8 V
Px.y
TA = 25°C
TA = 85°C
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
图8-5. Typical Low-Level Output Current vs
图8-4. Typical Low-Level Output Current vs
Low-Level Output Voltage
Low-Level Output Voltage
0.0
0.0
VCC = 1.8 V
VCC = 3.0 V
Px.y
Px.y
−1.0
−5.0
−2.0
−3.0
−4.0
−10.0
TA = 85°C
−5.0
−15.0
TA = 85°C
−6.0
TA = 25°C
−20.0
TA = 25°C
−7.0
−8.0
−25.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
图8-6. Typical High-Level Output Current vs
图8-7. Typical High-Level Output Current vs
High-Level Output Voltage
High-Level Output Voltage
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8.20 Typical Characteristics –Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
60.0
24
20
16
12
8
TA = 25°C
TA = 85°C
VCC = 1.8 V
Px.y
VCC = 3.0 V
Px.y
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
TA = 25°C
TA = 85°C
4
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
图8-8. Typical Low-Level Output Current vs
图8-9. Typical Low-Level Output Current vs
Low-Level Output Voltage
Low-Level Output Voltage
0.0
0
VCC = 1.8 V
Px.y
VCC = 3.0 V
−5.0
Px.y
−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−4
−8
−12
−45.0
TA = 85°C
−16
TA = 85°C
−50.0
−55.0
TA = 25°C
−60.0
TA = 25°C
−20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
图8-10. Typical High-Level Output Current vs
图8-11. Typical High-Level Output Current vs
High-Level Output Voltage
High-Level Output Voltage
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8.21 Crystal Oscillator, XT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
TA = 25°C
0.075
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2,
TA = 25°C
3.0 V
0.170
µA
ΔIDVCC.LF
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C
0.290
XT1 oscillator crystal frequency,
LF mode
fXT1,LF0
XTS = 0, XT1BYPASS = 0
32768
Hz
XT1 oscillator logic-level square-
wave input frequency, LF mode
XTS = 0, XT1BYPASS = 1(2) (3)
XT1BYPASSLV = 0 or 1
fXT1,LF,SW
10 32.768
210
50 kHz
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
LF crystals(4)
OALF
kΩ
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
XTS = 0, XCAPx = 0(6)
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
Integrated effective load
capacitance, LF mode(5)
CL,eff
pF
8.5
12.0
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
30%
70%
XTS = 0,
Oscillator fault frequency,
LF mode(7)
fFault,LF
XT1BYPASS = 1(8)
,
10
10000
Hz
ms
XT1BYPASSLV = 0 or 1
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
TA = 25°C, CL,eff = 6 pF
1000
500
tSTART,LF
Start-up time, LF mode
3.0 V
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
TA = 25°C, CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square-wave with parametrics defined
in the Schmitt-Trigger Inputs section of this data sheet. When in crystal bypass mode, XIN can be configured so that it can support an
input digital waveform with swing levels from DVSS to DVCC (XT1BYPASSLV = 0) or DVSS to DVIO (XT1BYPASSLV = 1). In this
case, it is required that the pin be configured properly for the intended input swing.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but each application should be evaluated based on the actual crystal selected:
•
•
•
•
For XT1DRIVEx = 0, CL,eff ≤6 pF
For XT1DRIVEx = 1, 6 pF ≤CL,eff ≤9 pF
For XT1DRIVEx = 2, 6 pF ≤CL,eff ≤10 pF
For XT1DRIVEx = 3, CL,eff ≥6 pF
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(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
8.22 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 0,
200
fOSC = 12 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 1,
260
325
450
XT2 oscillator crystal current
consumption
IDVCC.XT2
3.0 V
µA
fOSC = 20 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 2,
fOSC = 32 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 3,
XT2 oscillator crystal
frequency, mode 0
fXT2,HF0
fXT2,HF1
fXT2,HF2
fXT2,HF3
XT2DRIVEx = 0, XT2BYPASS = 0(3)
XT2DRIVEx = 1, XT2BYPASS = 0(3)
XT2DRIVEx = 2, XT2BYPASS = 0(3)
XT2DRIVEx = 3, XT2BYPASS = 0(3)
4
8
8
MHz
XT2 oscillator crystal
frequency, mode 1
16 MHz
24 MHz
32 MHz
XT2 oscillator crystal
frequency, mode 2
16
24
XT2 oscillator crystal
frequency, mode 3
XT2 oscillator logic-level
square-wave input frequency,
bypass mode
XT2BYPASS = 1(4) (3)
XT2BYPASSLV = 0 or 1
fXT2,HF,SW
0.7
32 MHz
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
450
320
200
200
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
Oscillation allowance for
HF crystals(5)
OAHF
Ω
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
fOSC = 6 MHz,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
0.5
0.3
tSTART,HF
Start-up time
3.0 V
ms
pF
fOSC = 20 MHz,
XT2BYPASS = 0, XT2DRIVEx = 2,
TA = 25°C, CL,eff = 15 pF
Integrated effective load
CL,eff
1
capacitance, HF mode(6) (1)
Duty cycle
Measured at ACLK, fXT2,HF2 = 20 MHz
40%
30
50%
60%
300
XT2BYPASS = 1(8)
XT2BYPASSLV = 0 or 1
,
fFault,HF
Oscillator fault frequency(7)
kHz
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
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•
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square-wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet. When in crystal bypass mode, XT2IN can be configured so that it can support
an input digital waveform with swing levels from DVSS to DVCC (XT2BYPASSLV = 0) or DVSS to DVIO (XT2BYPASSLV = 1). In this
case, it is required that the pin be configured properly for the intended input swing.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the
effective load capacitance should always match the specification of the used crystal.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals. Typically, an effective load capacitance of up to 18
pF can be supported.
8.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
MIN
TYP
9.4
0.5
4
MAX UNIT
14 kHz
%/°C
fVLO
Measured at ACLK
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
6
dfVLO/dT
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
%/V
40%
50%
60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C –(–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)
8.24 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
3
MAX UNIT
µA
IREFO
REFO oscillator current consumption
REFO frequency calibrated
TA = 25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
3 V
Measured at ACLK
Full temperature range
TA = 25°C
32768
Hz
3.5%
1.5%
%/°C
%/V
fREFO
–3.5%
–1.5%
REFO absolute tolerance calibrated
REFO frequency temperature drift
dfREFO/dT
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
40%/60% duty cycle
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
0.01
1.0
dfREFO/dVCC REFO frequency supply voltage drift
Duty cycle
40%
50%
25
60%
tSTART
REFO start-up time
µs
(1) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C –(–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)
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8.25 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
MIN
0.07
0.70
0.15
1.47
0.32
3.17
0.64
6.07
1.3
TYP
MAX UNIT
0.20 MHz
1.70 MHz
0.36 MHz
3.45 MHz
0.75 MHz
7.38 MHz
1.51 MHz
14.0 MHz
3.2 MHz
fDCO(0,0)
fDCO(0,31)
fDCO(1,0)
fDCO(1,31)
fDCO(2,0)
fDCO(2,31)
fDCO(3,0)
fDCO(3,31)
fDCO(4,0)
fDCO(4,31)
fDCO(5,0)
fDCO(5,31)
fDCO(6,0)
fDCO(6,31)
fDCO(7,0)
fDCO(7,31)
DCO frequency (0, 0)(1)
DCO frequency (0, 31)(1)
DCO frequency (1, 0)(1)
DCO frequency (1, 31)(1)
DCO frequency (2, 0)(1)
DCO frequency (2, 31)(1)
DCO frequency (3, 0)(1)
DCO frequency (3, 31)(1)
DCO frequency (4, 0)(1)
DCO frequency (4, 31)(1)
DCO frequency (5, 0)(1)
DCO frequency (5, 31)(1)
DCO frequency (6, 0)(1)
DCO frequency (6, 31)(1)
DCO frequency (7, 0)(1)
DCO frequency (7, 31)(1)
12.3
2.5
28.2 MHz
6.0 MHz
23.7
4.6
54.1 MHz
10.7 MHz
88.0 MHz
19.6 MHz
135 MHz
39.0
8.5
60
Frequency step between range
DCORSEL and DCORSEL + 1
SDCORSEL
SDCO
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
1.2
2.3 ratio
Frequency step between tap DCO
and DCO + 1
1.02
40%
1.12 ratio
Duty cycle
Measured at SMCLK
fDCO = 1 MHz
50%
0.1
60%
%/°C
%/V
dfDCO/dT
DCO frequency temperature drift(2)
dfDCO/dVCC DCO frequency voltage drift(3)
fDCO = 1 MHz
1.9
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤fDCO ≤fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO
frequency, range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n,
tap 31 (DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the
actual fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report
that the selected range is at its minimum or maximum tap setting.
(2) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C –(–40°C))
(3) Calculated using the box method: (MAX(1.8 V to 3.6 V) –MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V –1.8 V)
100
VCC = 3.0 V
TA = 25°C
10
DCOx = 31
1
DCOx = 0
0.1
0
1
2
3
4
5
6
7
DCORSEL
图8-12. Typical DCO Frequency
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8.26 PMM, Brownout Reset (BOR)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s
MIN TYP MAX UNIT
VDVCC_BOR_IT–
VDVCC_BOR_IT+
VDVCC_BOR_hys
tRESET
BORH on voltage, DVCC falling level
BORH off voltage, DVCC rising level
BORH hysteresis
1.45
V
V
0.80 1.30 1.50
50
2
250 mV
µs
Pulse duration required at RST/NMI pin to accept a reset
8.27 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2.4 V ≤DVCC ≤3.6 V
2.2 V ≤DVCC ≤3.6 V
2.0 V ≤DVCC ≤3.6 V
1.8 V ≤DVCC ≤3.6 V
2.4 V ≤DVCC ≤3.6 V
2.2 V ≤DVCC ≤3.6 V
2.0 V ≤DVCC ≤3.6 V
1.8 V ≤DVCC ≤3.6 V
MIN
TYP
1.90
1.80
1.60
1.40
1.94
1.84
1.64
1.44
MAX UNIT
VCORE3(AM)
VCORE2(AM)
VCORE1(AM)
VCORE0(AM)
VCORE3(LPM)
VCORE2(LPM)
VCORE1(LPM)
VCORE0(LPM)
Core voltage, active mode, PMMCOREV = 3
Core voltage, active mode, PMMCOREV = 2
Core voltage, active mode, PMMCOREV = 1
Core voltage, active mode, PMMCOREV = 0
Core voltage, low-current mode, PMMCOREV = 3
Core voltage, low-current mode, PMMCOREV = 2
Core voltage, low-current mode, PMMCOREV = 1
Core voltage, low-current mode, PMMCOREV = 0
V
V
V
V
V
V
V
V
8.28 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVSHE = 0, DVCC = 3.6 V
0
nA
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
SVSHE = 1, SVSHRVL = 0
200
1.5
µA
1.57
1.79
1.98
2.10
1.62
1.88
2.07
2.20
2.32
2.52
2.90
2.90
1.68
1.88
2.08
2.18
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
2.5
1.78
SVSHE = 1, SVSHRVL = 1
1.98
V
V(SVSH_IT–) SVSH on voltage level(1)
SVSHE = 1, SVSHRVL = 2
2.21
SVSHE = 1, SVSHRVL = 3
2.31
1.85
2.07
2.28
SVSHE = 1, SVSMHRRL = 0
SVSHE = 1, SVSMHRRL = 1
SVSHE = 1, SVSMHRRL = 2
SVSHE = 1, SVSMHRRL = 3
2.42
V
V(SVSH_IT+) SVSH off voltage level(1)
SVSHE = 1, SVSMHRRL = 4
2.55
SVSHE = 1, SVSMHRRL = 5
2.88
3.23
3.23
SVSHE = 1, SVSMHRRL = 6
SVSHE = 1, SVSMHRRL = 7
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
SVSHE = 0 →1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
SVSHE = 0 →1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
tpd(SVSH)
SVSH propagation delay
SVSH on or off delay time
µs
µs
20
12.5
100
t(SVSH)
dVDVCC/dt DVCC rise time
0
1000
V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use.
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8.29 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0
MAX UNIT
SVMHE = 0, DVCC = 3.6 V
nA
I(SVMH)
SVMH current consumption
SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
200
1.5
µA
1.85
1.62
1.88
2.07
2.20
2.32
2.52
2.90
2.90
1.74
1.94
2.14
2.30
2.40
2.70
3.10
3.10
3.75
2.5
SVMHE = 1, SVSMHRRL = 1
2.07
SVMHE = 1, SVSMHRRL = 2
2.28
SVMHE = 1, SVSMHRRL = 3
2.42
V(SVMH)
SVMH on or off voltage level(1)
SVMHE = 1, SVSMHRRL = 4
2.55
2.88
3.23
3.23
V
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
SVMHE = 0 →1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
SVMHE = 0 →1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
tpd(SVMH)
SVMH propagation delay
SVMH on or off delay time
µs
µs
20
12.5
100
t(SVMH)
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide on recommended settings and use.
8.30 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVSLE = 0, PMMCOREV = 2
0
nA
µA
µs
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
200
1.5
2.5
20
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
SVSLE = 0 →1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 0 →1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
tpd(SVSL)
SVSL propagation delay
SVSL on or off delay time
12.5
100
t(SVSL)
µs
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8.31 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVMLE = 0, PMMCOREV = 2
0
nA
µA
µs
I(SVML)
SVML current consumption
SVMLE= 1, PMMCOREV = 2, SVMLFP = 0
200
1.5
2.5
20
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
SVMLE = 0 →1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 0 →1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
tpd(SVML)
SVML propagation delay
SVML on or off delay time
12.5
100
t(SVML)
µs
8.32 Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
3.5
7.5
f
MCLK ≥4.0 MHz
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-FAST
µs
9
1.0 MHz < fMCLK
4.0 MHz
<
4.5
Wake-up time from LPM2,
LPM3 or LPM4 to active
mode(2) (3)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-SLOW
150
175
µs
Wake-up time from LPM4.5
to active mode(4)
tWAKE-UP-LPM5
tWAKE-UP-RESET
2
2
3
3
ms
ms
Wake-up time from RST or
BOR event to active mode(4)
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in
full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx
Family User's Guide.
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in
normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430x5xx and MSP430x6xx
Family User's Guide.
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by
the performance mode settings as for LPM2, LPM3, and LPM4.
(4) This value represents the time from the wake-up event to the reset vector execution.
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8.33 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VIO
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: TACLK,
Duty cycle = 50% ±10%
1.8 V
1.62 V to 1.8 V
25
fTA
Timer_A input clock frequency
MHz
3.0 V
1.8 V
3.0 V
1.62 V to 1.98 V
1.62 V to 1.8 V
1.62 V to 1.98 V
25
All capture inputs, minimum
pulse duration required for
capture
20
20
tTA,cap Timer_A capture timing(1)
ns
(1) The external signal sets the interrupt flag every time the minimum parameters are met. It may be set even with trigger signals shorter
than tTA,cap
.
8.34 Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VIO
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: TBCLK,
Duty cycle = 50% ±10%
1.8 V
1.62 V to 1.8 V
25
fTB
Timer_B input clock frequency
MHz
3.0 V
1.8 V
3.0 V
1.62 V to 1.98 V
1.62 V to 1.8 V
1.62 V to 1.98 V
25
All capture inputs, minimum
pulse duration required for
capture
20
20
tTB,cap Timer_B capture timing(1)
ns
(1) The external signal sets the interrupt flag every time the minimum parameters are met. It may be set even with trigger signals shorter
than tTB,cap
.
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8.35 USCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
fBITCLK BITCLK clock frequency (equals baud rate in MBaud)
1
MHz
8.36 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
1.8 V
3.0 V
VIO
MIN
MAX UNIT
1.62 V to 1.80 V
1.62 V to 1.98 V
50
600
ns
600
tτ
UART receive deglitch time(1)
50
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
8.37 USCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX UNIT
fUSCI
USCI input clock frequency
Internal: SMCLK or ACLK, Duty cycle = 50% ±10%
fSYSTEM MHz
8.38 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see 图8-13 and 图8-14)
PARAMETER
TEST CONDITIONS
SMCLK or ACLK,
VCC
VIO
MIN
MAX UNIT
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.8 V
3.0 V
2.4 V
3.0 V
1.62 V to 1.80 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.80 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.80 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.80 V
1.62 V to 1.98 V
1.62 V to 1.98 V
1.62 V to 1.98 V
55
55
35
35
0
PMMCOREV = 0
tSU,MI
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time(2)
ns
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
0
tHD,MI
ns
0
0
20
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
20
ns
16
tVALID,MO
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
16
–10
–10
–10
–10
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
tHD,MO
SIMO output data hold time(3)
ns
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in 图8-13 and 图8-14.
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(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in 图8-13
and 图8-14.
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
图8-13. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
图8-14. SPI Master Mode, CKPH = 1
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8.39 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see 图8-15 and 图8-16)
PARAMETER
TEST CONDITIONS
PMMCOREV = 0
VCC
VIO
MIN
12
12
10
10
6
MAX UNIT
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
1.8 V 1.62 V to 1.80 V
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE low to clock
ns
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
6
STE lag time, Last clock to STE high
ns
6
6
65
65
ns
45
STE access time, STE low to SOMI
data out
45
35
35
ns
25
STE disable time, STE high to SOMI
high impedance
25
5
5
5
5
5
5
5
5
SIMO input data setup time
SIMO input data hold time
ns
tHD,SI
ns
UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 0
75
75
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
tVALID,SO
SOMI output data valid time(2)
SOMI output data hold time(3)
ns
UCLK edge to SOMI valid,
CL = 20 pF,
PMMCOREV = 3
50
50
1.8 V 1.62 V to 1.80 V
3.0 V 1.62 V to 1.98 V
2.4 V 1.62 V to 1.98 V
3.0 V 1.62 V to 1.98 V
10
10
10
10
CL = 20 pF,
PMMCOREV = 0
tHD,SO
ns
CL = 20 pF,
PMMCOREV = 3
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in 图8-15 and 图8-16.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in 图8-15
and 图8-16.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SI
tLO/HI
tLO/HI
tHD,SI
SIMO
SOMI
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
图8-15. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
SOMI
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
图8-16. SPI Slave Mode, CKPH = 1
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8.40 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图8-17)
(1)
PARAMETER
TEST CONDITIONS
VCC
VIO
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2.2 V, 3 V
2.2 V, 3 V
1.62 V to 1.98 V
1.62 V to 1.98 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
f
SCL ≤100 kHz
fSCL > 100 kHz
SCL ≤100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
f
tSU,STA
Setup time for a repeated START
2.2 V, 3 V
1.62 V to 1.98 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V, 3 V
2.2 V, 3 V
1.62 V to 1.98 V
1.62 V to 1.98 V
ns
ns
250
4.0
0.6
f
SCL ≤100 kHz
tSU,STO
Setup time for STOP
2.2 V, 3 V
2.2 V, 3 V
1.62 V to 1.98 V
1.62 V to 1.98 V
µs
fSCL > 100 kHz
Pulse duration of spikes
suppressed by input filter
tSP
50
600
ns
(1) In all test conditions, VIO ≤VCC
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
图8-17. I2C Mode Timing
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MAX UNIT
8.41 10-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
AVCC
V(Ax)
Analog supply voltage
1.8
3.6
V
V
All ADC10_A pins: P1.0 to P1.5 and P3.6 and
P3.7 terminals
Analog input voltage range(2)
0
AVCC
Operating supply current into fADC10CLK = 5.0 MHz, ADC10ON = 1,
AVCC terminal, REF module REFON = 0, SHT0 = 0, SHT1 = 0,
2.2 V
3 V
60
75
100
110
µA
and reference buffer off
ADC10DIV = 0, ADC10SREF = 00
Operating supply current into fADC10CLK = 5.0 MHz, ADC10ON = 1,
AVCC terminal, REF module REFON = 1, SHT0 = 0, SHT1 = 0,
3 V
3 V
113
105
150
140
µA
µA
on, reference buffer on
ADC10DIV = 0, ADC10SREF = 01
fADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 10,
VEREF = 2.5 V
IADC10_A
Operating supply current into
AVCC terminal, REF module
off, reference buffer on
fADC10CLK = 5.0 MHz, ADC10ON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADC10DIV = 0, ADC10SREF = 11,
VEREF = 2.5 V
Operating supply current into
AVCC terminal, REF module
off, reference buffer off
3 V
70
110
µA
Only one terminal Ax can be selected at one
time from the pad to the ADC10_A capacitor
array including wiring and pad
CI
RI
Input capacitance
2.2 V
3.5
pF
36
96
AVCC > 2 V, 0 V ≤VAx ≤AVCC
Input MUX ON resistance
kΩ
1.8 V < AVCC < 2 V, 0 V ≤VAx ≤AVCC
(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The
external reference voltage requires decoupling capacitors. See 节8.44.
8.42 10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC10_A
linearity parameters
fADC10CLK
fADC10OSC
2.2 V, 3 V
0.45
5
5.5 MHz
Internal ADC10_A
oscillator(3)
ADC10DIV = 0, fADC10CLK = fADC10OSC
2.2 V, 3 V
2.2 V, 3 V
4.2
2.4
4.8
5.4 MHz
REFON = 0, Internal oscillator,
12 ADC10CLK cycles, 10-bit mode
fADC10OSC = 4 MHz to 5 MHz
3.0
µs
tCONVERT
Conversion time
External fADC10CLK from ACLK, MCLK or
12 ×
1 / fADC10CLK
SMCLK, ADC10SSEL ≠0
Turnon settling time of
the ADC
tADC10ON
See (1)
100
ns
1.8 V
3.0 V
3
1
µs
µs
RS = 1000 Ω, RI = 96 k Ω, CI = 3.5 pF(2)
tSample
Sampling time
(1) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
(2) Approximately 8 Tau (τ) are needed to get an error of less than ±0.5 LSB
(3) The ADC10OSC is sourced directly from MODOSC inside the UCS.
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8.43 10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
±1.0
LSB
±1.0
1.4 V ≤(VeREF+ –VeREF–) ≤1.6 V, CVeREF+ = 20 pF
1.6 V < (VeREF+ –VeREF–) ≤VAVCC, CVeREF+ = 20 pF
Integral
linearity error
EI
2.2 V, 3 V
Differential
linearity error
ED
EO
EG
ET
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
±1.0 LSB
±1.0 LSB
±1.0 LSB
±2.0 LSB
1.4 V ≤(VeREF+ –VeREF–), CVeREF+ = 20 pF
1.4 V ≤(VeREF+ –VeREF–), CVeREF+ = 20 pF,
Internal impedance of source RS < 100 Ω
Offset error
Gain error
1.4 V ≤(VeREF+ –VeREF–), CVeREF+ = 20 pF,
ADC10SREFx = 11b
Total unadjusted
error
1.4 V ≤(VeREF+ –VeREF–), CVeREF+ = 20 pF,
ADC10SREFx = 11b
±1.0
8.44 REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Positive external reference
voltage input
(2)
VeREF+
VeREF+ > VeREF–
1.4
AVCC
1.2
V
V
V
Negative external reference
voltage input
(3)
(4)
VeREF–
VeREF+ > VeREF–
VeREF+ > VeREF–
0
Differential external reference
voltage input
(VeREF+
VeREF–
–
)
1.4
AVCC
1.4 V ≤VeREF+ ≤VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
2.2 V, 3 V
2.2 V, 3 V
26
1
µA
–26
IVeREF+
IVeREF–
,
Static input current
1.4 V ≤VeREF+ ≤VAVCC , VeREF– = 0 V,
fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
µA
µF
–1
CVREF+
CVREF-
,
Capacitance at VeREF+ or
VeREF- terminal
See (5)
10
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is
also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide.
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MAX UNIT
8.45 REF, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.445 2.486 2.527
1.94 1.97 2.01
TYP
REFVSEL = {2} for 2.5 V
REFON = 1
3 V
Positive built-in reference
voltage
REFVSEL = {1} for 2.0 V
REFON = 1
VREF+
3 V
V
V
REFVSEL = {0} for 1.5 V
REFON = 1
2.2 V, 3 V
1.461 1.485 1.511
REFVSEL = {0} for 1.5 V
REFVSEL = {1} for 2.0 V
REFVSEL = {2} for 2.5 V
1.8
2.2
2.7
AVCC minimum voltage,
Positive built-in reference
active
AVCC(min)
fADC10CLK = 5.0 MHz
REFON = 1, REFBURST = 0,
REFVSEL = {2} for 2.5 V
3 V
3 V
3 V
18
24
21
µA
µA
µA
fADC10CLK = 5.0 MHz
REFON = 1, REFBURST = 0,
REFVSEL = {1} for 2.0 V
Operating supply current
into AVCC terminal(1)
IREF+
15.5
fADC10CLK = 5.0 MHz
REFON = 1, REFBURST = 0,
REFVSEL = {0} for 1.5 V
13.5
30
21
50
Temperature coefficient of IVREF+ = 0 A
ppm/
°C
TCREF+
built-in reference(2)
REFVSEL = {0, 1, 2}, REFON = 1
2.2 V
3 V
20
20
22
22
Operating supply current
into AVCC terminal(4)
REFON = 0, INCH = 0Ah,
ADC10ON = N/A, TA = 30°C
ISENSOR
µA
mV
V
2.2 V
3 V
770
770
1.1
1.5
ADC10ON = 1, INCH = 0Ah,
TA = 30°C
VSENSOR
See (5)
2.2 V
3 V
1.06
1.46
1.14
1.54
ADC10ON = 1, INCH = 0Bh,
VMID
AVCC divider at channel 11
V
MID ≈0.5 × VAVCC
ADC10ON = 1, INCH = 0Ah,
Error of conversion result ≤1 LSB
Sample time required if
channel 10 is selected(6)
tSENSOR(sample)
tVMID(sample)
PSRR_DC
30
1
µs
µs
ADC10ON = 1, INCH = 0Bh,
Error of conversion result ≤1 LSB
Sample time required if
channel 11 is selected(7)
Power supply rejection ratio AVCC = AVCC(min) to AVCC(max),
120
6.4
75
µV/V
(DC)
TA = 25°C, REFVSEL = {0, 1, 2}, REFON = 1
AVCC = AVCC(min) to AVCC(max),
TA = 25°C, f = 1 kHz, ΔVpp = 100 mV,
REFVSEL = {0, 1, 2}, REFON = 1
Power supply rejection ratio
(AC)
PSRR_AC
tSETTLE
mV/V
µs
AVCC = AVCC(min) to AVCC(max),
REFVSEL = {0, 1, 2}, REFON = 0 →1
Settling time of reference
voltage(3)
(1) The internal reference current is supplied from terminal AVCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
(2) Calculated using the box method: (MAX(–40°C to 85°C) –MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C –(–40°C)).
(3) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
(4) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+
.
(5) The temperature sensor offset can be significant. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
(6) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
(7) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
.
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8.46 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VCC
Supply voltage
1.8
3.6
38
38
39
V
1.8 V
2.2 V
3 V
CBPWRMD = 00, CBON = 1,
CBRSx = 00
31
32
Comparator operating
supply current into AVCC,
Excludes reference
resistor ladder
IAVCC_COMP
µA
CBPWRMD = 01, CBON = 1,
CBRSx = 00
2.2 V, 3 V
2.2 V, 3 V
10
17
CBPWRMD = 10, CBON = 1,
CBRSx = 00
0.2
0.85
CBREFLx = 01, CBREFACC = 0
CBREFLx = 10, CBREFACC = 0
CBREFLx = 11, CBREFACC = 0
1.400
1.864
2.32
1.43
1.90
2.37
1.472
1.960
2.44
≥1.8V
≥2.2V
≥3.0V
VREF
Reference voltage level
V
CBREFACC = 0, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
Quiescent current of
resistor ladder into AVCC,
Includes REF module
current
2.2 V, 3 V
2.2 V, 3 V
33
17
40
22
IAVCC_REF
µA
CBREFACC = 1, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
Common mode input
range
VIC
0
V
VCC –1
CBPWRMD = 00
20
10
–20
–10
VOFFSET
CIN
Input offset voltage
Input capacitance
mV
CBPWRMD = 01, 10
5
3
pF
kΩ
On (switch closed)
4
RSIN
Series input resistance
Off (switch open)
50
MΩ
CBPWRMD = 00, CBF = 0
CBPWRMD = 01, CBF = 0
CBPWRMD = 10, CBF = 0
450
600
50
ns
µs
Propagation delay,
response time
tPD
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 00
0.35
0.6
1.0
1.8
0.6
1.0
1.8
3.4
1
1.5
1.8
3.4
6.5
2
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 01
Propagation delay with
filter active
tPD,filter
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 10
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 11
CBON = 0 →1,
CBPWRMD = 00 or 01
tEN_CMP
Comparator enable time
µs
µs
CBON = 0 →1,
CBPWRMD = 10
100
1.5
Resistor reference enable
time
tEN_REF
TCREF
1.0
CBON = 0 →1
Temperature coefficient
reference
50 ppm/ °C
VIN ×
VIN ×
VIN ×
Reference voltage for a
given tap
VIN = reference into resistor ladder,
n = 0 to 31
VCB_REF
(n + 0.5) / (n + 1) / (n + 1.5) /
32 32 32
V
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MAX UNIT
8.47 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
DVCC(PGM/ERASE) Program and erase supply voltage
1.8
3.6
5
V
mA
IPGM
Average supply current from DVCC during program
3
6
6
IERASE
Average supply current from DVCC during erase
Average supply current from DVCC during mass erase or bank erase
Cumulative program time(1)
15
15
16
mA
IMERASE, IBANK
tCPT
mA
ms
Program and erase endurance
104
100
64
105
cycles
years
µs
tRetention
tWord
Data retention duration
25°C
Word or byte program time(2)
85
65
tBlock, 0
Block program time for first byte or word(2)
49
µs
Block program time for each additional byte or word, except for last byte
or word(2)
tBlock, 1–(N–1)
37
49
µs
tBlock, N
tErase
Block program time for last byte or word(2)
55
23
73
32
µs
Erase time for segment, mass erase, and bank erase when available(2)
ms
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)
fMCLK,MGR
0
1
MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write mode and block write mode.
(2) These values are hardwired into the state machine of the flash controller.
8.48 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
VIO
MIN
TYP
MAX UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V 1.62 V to 1.98 V
2.2 V, 3 V 1.62 V to 1.98 V
0
20 MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
0.025
15
1
µs
µs
µs
Spy-Bi-Wire enable time (TEST high to acceptance of first
clock edge)(1)
tSBW, En
tSBW,Rst
1.62 V to 1.98 V
Spy-Bi-Wire return to normal operation time
TCK input frequency for 4-wire JTAG(2)
Internal pulldown resistance on TEST
2.2 V, 3 V 1.62 V to 1.98 V
15
0
100
5
2.2 V
3 V
1.62 V to 1.98 V
1.62 V to 1.98 V
fTCK
MHz
0
10
80
Rinternal
2.2 V, 3 V 1.62 V to 1.98 V
45
60
kΩ
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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8.49 DVIO BSL Entry
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see 图8-18)
PARAMETER
Setup time, BSLEN to RST/NMI(1)
Hold time, BSLEN to RST/NMI(2)
VCC
VIO
MIN
100
350
MAX UNIT
tSU, BSLEN
tHO, BSLEN
2.2 V, 3 V 1.62 V to 1.98 V
2.2 V, 3 V 1.62 V to 1.98 V
ns
µs
(1) AVCC, DVCC, DVIO stable and within specification.
(2) BSLEN must remain logic high long enough for the boot code to detect its level and enter the BSL sequence. After the minimum hold
time is achieved, BSLEN is a don't care.
BSLEN
VIT+
VIT-
tHO,BSLEN
VIT+
VIT-
RST/NMI
(DVIO domain)
t
tSU,BSLEN
图8-18. DVIO BSL Entry Timing
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9 Detailed Description
9.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are
general-purpose registers (see 图9-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed with
all instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Program Counter
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
图9-1. Integrated CPU Registers
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9.2 Operating Modes
These MCUs have one active mode and six software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
Software can configure the following seven operating modes:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wake-up input from RST/NMI, P1, or P2
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9.3 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see 表 9-1).
The vector contains the 16-bit address of the interrupt-handler instruction sequence.
表9-1. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power up
External reset
Watchdog time-out, password
violation
WDTIFG, KEYV (SYSRSTIV)(1) (3)
Reset
0FFFEh
63, highest
Flash memory password violation
PMM password violation
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV)(1)
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
62
61
User NMI
NMI
Oscillator fault
NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)
(1) (3)
Flash memory access violation
COMP_B
USCI_A0 receive or transmit
USCI_B0 receive or transmit
Watchdog timer interval timer mode
USCI_A1 receive or transmit
USCI_B1 receive or transmit
ADC10_A
Comparator B interrupt flags (CBIV)(1) (2)
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (2)
UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (2)
WDTIFG
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
0FFE8h
0FFE6h
60
59
58
57
56
55
54
53
52
51
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (2)
UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (2)
ADC10IFG0(1) (2) (5)
USCI_A2 receive or transmit
USCI_B2 receive or transmit
TA0
UCA2RXIFG, UCA2TXIFG (UCA2IV)(1) (2)
UCB2RXIFG, UCB2TXIFG (UCB2IV)(1) (2)
TA0CCR0 CCIFG0(2)
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1) (2)
TA0
Maskable
0FFE4h
50
Reserved
DMA
Reserved(4)
Maskable
Maskable
Maskable
Maskable
Maskable
0FFE2h
0FFE0h
0FFDEh
0FFDCh
0FFDAh
49
48
47
46
45
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (2)
UCA3RXIFG, UCA3TXIFG (UCA3IV)(1) (2)
UCB3RXIFG, UCB3TXIFG (UCB3IV)(1) (2)
TB0CCR0 CCIFG0 (2)
USCI_A3 receive or transmit
USCI_B3 receive or transmit
TB0
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TB0IV)(1) (2)
TB0
TA1
TA1
Maskable
Maskable
Maskable
0FFD8h
0FFD6h
0FFD4h
44
43
42
TA1CCR0 CCIFG0(2)
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1) (2)
I/O port P1
TA2
P1IFG.0 to P1IFG.7 (P1IV)(1) (2)
TA2CCR0 CCIFG0(2)
Maskable
Maskable
0FFD2h
0FFD0h
41
40
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1) (2)
TA2
Maskable
Maskable
Maskable
Maskable
0FFCEh
0FFCCh
0FFCAh
0FFC8h
39
38
37
36
I/O port P2
RTC_A
P2IFG.0 to P2IFG.7 (P2IV)(1) (2)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RT0PSIFG, RT1PSIFG (RTCIV)(1) (2)
I/O Port P6
P6IFG.0 to P6IFG.7 (P6IV)(1) (2)
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表9-1. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
0FFC6h
35
Reserved
Reserved(4)
⋮
⋮
0FF80h
0, lowest
(1) Multiple source flags
(2) Interrupt flags are in the module.
(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To
maintain compatibility with other devices, TI recommends reserving these locations.
(5) Only on devices with ADC, otherwise reserved
9.4 Memory Organization
表9-2 summarizes the memory map of the microcontrollers.
表9-2. Memory Organization
MSP430F5259, MSP430F5258,
MSP430F5255, MSP430F5254
MSP430F5257, MSP430F5256,
MSP430F5253, MSP430F5252
Memory (flash)
Total Size
128KB
128KB
Main: interrupt vector
00FFFFh to 00FF80h
00FFFFh to 00FF80h
32KB
32KB
Bank D
Bank C
Bank B
Bank A
Sector 7
Sector 6
Sector 5
Sector 4
Sector 3
Sector 2
Sector 1
Sector 0
A
002A3FFh to 0022400h
002A3FFh to 0022400h
32KB
32KB
00223FFh to 001A400h
00223FFh to 001A400h
Main: code memory
32KB
32KB
001A3FFh to 0012400h
001A3FFh to 0012400h
32KB
32KB
00123FFh to 00A400h
00123FFh to 00A400h
4KB
N/A(1)
00A3FFh to 009400h
4KB
N/A
0093FFh to 008400h
4KB
N/A
0083FFh to 007400h
4KB
N/A
0073FFh to 006400h
RAM
4KB
4KB
0063FFh to 005400h
0063FFh to 005400h
4KB
4KB
0053FFh to 004400h
0053FFh to 004400h
4KB
4KB
0043FFh to 003400h
0043FFh to 003400h
4KB
4KB
0033FFh to 002400h
0033FFh to 002400h
128 bytes
001BFFh to 001B80h
128 bytes
001BFFh to 001B80h
128 bytes
001B7Fh to 001B00h
128 bytes
001B7Fh to 001B00h
B
TI factory memory (ROM)
128 bytes
001AFFh to 001A80h
128 bytes
001AFFh to 001A80h
C
128 bytes
001A7Fh to 001A00h
128 bytes
001A7Fh to 001A00h
D
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表9-2. Memory Organization (continued)
MSP430F5259, MSP430F5258,
MSP430F5255, MSP430F5254
MSP430F5257, MSP430F5256,
MSP430F5253, MSP430F5252
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
Info A
Info B
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
Size
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
Information memory (flash)
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
Bootloader (BSL) memory (flash)
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
4KB
000FFFh to 0h
4KB
000FFFh to 0h
Peripherals
(1) N/A = Not available
9.5 Bootloader (BSL)
Note
Devices from TI come factory programmed with either an I2C-based BSL or a timer-based UART BSL.
See 表6-1 to determine which BSL type is implemented.
9.5.1 Bootloader –I2C
The I2C BSL enables users to program the flash memory or RAM using a I2C serial interface. Access to the
device memory through the BSL is protected by an user-defined password.
When using the BSL, it requires a specific entry sequence on the RST/NMI and BSLEN pins. 表 9-3 lists the
required pins and their functions. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the
BSL and its implementation, see the MSP430 Flash Devices Bootloader (BSL) User's Guide. BSL firmware
images are available for download in the Custom BSL430 package.
Note
To invoke the BSL from the DVIO domain, the RST/NMI pin and BSLEN pins must be used for the
entry sequence. It is critical not to confuse the RST/NMI pin with the RSTDVCC/SBWTDIO pin. In
many other MSP430 devices, SBWTDIO is shared with the RST/NMI pin, and RSTDVCC does not
exist. Additional information can be found in Designing With MSP430F522x and MSP430F521x
Devices.
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表9-3. BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
External reset
Enable BSL
RST/NMI
BSLEN
P4.1/PM_UCB1SDA
P4.2/ PM_UCB1SCL
DVCC, AVCC
DVIO
I2C data
I2C clock
Device power supply
I/O power supply
Ground supply
DVSS
9.5.2 Bootloader –UART
The UART BSL enables users to program the flash memory or RAM using a UART serial interface. Access to
the device memory through the BSL is protected by an user-defined password. Because the F525x have split I/O
power domains, it is possible to interface with the BSL from either the DVCC or DVIO supply domains. This is
useful when the MSP430 is interfacing to a host on the DVIO supply domain. The BSL interface on the DVIO
supply domain (see 表 9-5) uses the USCI_A0 module configured as a UART. The BSL interface on the DVCC
supply domain (see 表9-4) uses a timer-based UART.
For applications that have BSL communication based on the DVCC supply domain, entry to the BSL requires a
specific sequence on the RSTDVCC/SBWTDIO and TEST/SBWTCK pins.
Note
Devices that are factory programmed with an UART BSL use the DVCC power supply domain pin
configuration per default (see 表9-4).
Note
To invoke the BSL from the DVCC domain, the RSTDVCC/SBWTDIO pin and TEST/SBWTCK pin
must be used for the entry sequence. It is critical not to confuse the RST/NMI pin with the RSTDVCC/
SBWTDIO pin. In many other MSP430 devices, SBWTDIO is shared with the RST/NMI pin, and
RSTDVCC does not exist. Additional information can be found in Designing With MSP430F522x and
MSP430F521x Devices.
表9-4. DVCC BSL Pin Requirements and Functions
DEVICE SIGNAL
RSTDVCC/SBWTDIO
TEST/SBWTCK
P6.1
BSL FUNCTION
External reset
Enable BSL
Data transmit
P6.2
Data receive
DVCC, AVCC
DVIO
Device power supply
I/O power supply
Ground supply
DVSS
When using the DVIO supply domain for the BSL, entry to the BSL requires a specific sequence on the RST/NMI
and BSLEN pins. 表 9-5 lists the required pins and their functions. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete
description of the features of the BSL and its implementation, see the MSP430 Flash Device Bootloader (BSL)
User's Guide. BSL firmware images are available for download in the Custom BSL430 package. The BSL on the
DVIO supply domain uses the USCI_A0 module configured as a UART.
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Note
To invoke the BSL from the DVIO domain, the RST/NMI pin and the BSLEN pin must be used for the
entry sequence (see 节 8.49). It is critical not to confuse the RST/NMI pin with the RSTDVCC/
SBWTDIO pin. In many other MSP430 devices, SBWTDIO is shared with the RST/NMI pin, and
RSTDVCC does not exist. Additional information can be found in Designing With MSP430F522x and
MSP430F521x Devices.
表9-5. DVIO BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI
BSLEN
BSL FUNCTION
External reset
Enable BSL
P3.3
Data transmit
P3.4
Data receive
DVCC, AVCC
DVIO
Device power supply
I/O power supply
Ground supply
DVSS
9.6 JTAG Operation
9.6.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RSTDVCC/SBWTDIO is required to interface with MSP430
development tools and device programmers. 表 9-6 lists the JTAG pin requirements. For further details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a
complete description of the features of the JTAG interface and its implementation, see MSP430 Programming
With the JTAG Interface. Additional information can be found in Designing With MSP430F522x and
MSP430F521x Devices.
Note
All JTAG I/O pins are supplied by DVCC.
Note
Traditionally, on other MSP430 devices, the RST/NMI pin is used for SBWTDIO, so care must be
taken not to mistakenly use the incorrect pin. On the F525x series of devices, it is required to use
RSTDVCC for SBWTDIO as shown in 表 9-6. Additional information can be found in Designing With
MSP430F522x and MSP430F521x Devices.
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表9-6. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
PJ.3/TCK
IN
IN
JTAG clock input
PJ.2/TMS
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RSTDVCC/SBWTDIO
DVCC, AVCC
DVIO
IN
Device power supply
I/O power supply
Ground supply
DVSS
9.6.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-
Bi-Wire can be used to interface with MSP430 development tools and device programmers. 表 9-7 lists the Spy-
Bi-Wire interface pin requirements. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the
JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface. Additional
information can be found in Designing With MSP430F522x and MSP430F521x Devices.
Note
All SBW I/O pins are supplied by DVCC.
Note
Traditionally, on other MSP430 devices, the RST/NMI pin is used for SBWTDIO, so care must be
taken not to mistakenly use the incorrect pin. On the F525x series of devices, it is required to use
RSTDVCC for SBWTDIO as shown in 表 9-7. Additional information can be found in Designing With
MSP430F522x and MSP430F521x Devices.
表9-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RSTDVCC/SBWTDIO
DVCC, AVCC
DVIO
DIRECTION
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Device power supply
I/O power supply
IN
IN, OUT
DVSS
Ground supply
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9.7 Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually. Segments A to D are also called information memory.
• Segment A can be locked separately.
9.8 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to reduce leakage; however, all
data are lost during power down.
Features of the RAM include:
• RAM memory has n sectors. The sizes of the sectors can be found in 节9.4, Memory Organization.
• Each sector 0 to n can be complete disabled; however, all data in a sector are lost when it is disabled.
• Each sector 0 to n automatically enters low-power retention mode when possible.
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9.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be managed
using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's
Guide.
9.9.1 Digital I/O
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Drive strength on all ports is programmable.
• Edge-selectable interrupt and LPM4.5 wake-up input capability is available for all bits of ports P1, P2.
• All bits of port P6 support edge-selectable interrupt input.
• All instructions support read and write access to port-control registers.
• Ports can be accessed byte-wise or word-wise in pairs.
9.9.2 Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (see 表
9-8).
表9-8. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
DVSS
0
PM_NONE
None
PM_CBOUT0
COMP_B output
–
1
2
3
PM_TB0CLK
TB0 clock input
–
PM_ADC10CLK
PM_DMAE0
ADC10CLK
–
DMAE0 input
–
PM_SVMOUT
PM_TB0OUTH
PM_TB0CCR0A
PM_TB0CCR1A
PM_TB0CCR2A
PM_TB0CCR3A
PM_TB0CCR4A
PM_TB0CCR5A
PM_TB0CCR6A
PM_UCA1RXD
PM_UCA1SOMI
PM_UCA1TXD
PM_UCA1SIMO
PM_UCA1CLK
PM_UCB1STE
PM_UCB1SOMI
PM_UCB1SCL
PM_UCB1SIMO
PM_UCB1SDA
PM_UCB1CLK
PM_UCA1STE
PM_CBOUT1
SVM output
–
TB0 high-impedance input TB0OUTH
TB0 CCR0 capture input CCI0A
TB0 CCR1 capture input CCI1A
TB0 CCR2 capture input CCI2A
TB0 CCR3 capture input CCI3A
TB0 CCR4 capture input CCI4A
TB0 CCR5 capture input CCI5A
TB0 CCR6 capture input CCI6A
–
4
5
TB0 CCR0 compare output Out0
TB0 CCR1 compare output Out1
TB0 CCR2 compare output Out2
TB0 CCR3 compare output Out3
TB0 CCR4 compare output Out4
TB0 CCR5 compare output Out5
TB0 CCR6 compare output Out6
6
7
8
9
10
USCI_A1 UART RXD (direction controlled by USCI –input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
USCI_A1 UART TXD (direction controlled by USCI –output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
USCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
11
12
13
14
15
16
17
18
None
None
COMP_B output
MCLK
PM_MCLK
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表9-8. Port Mapping Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
19
PM_RTCCLK
None
RTCCLK output
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCB0STE
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0CLK
PM_UCA0STE
PM_UCA3RXD
PM_UCA3SOMI
PM_UCA3TXD
PM_UCA3SIMO
PM_UCB3SIMO
PM_UCB3SDA
PM_UCB3SOMI
PM_UCB3SCL
Reserved
USCI_A0 UART RXD (direction controlled by USCI –input)
USCI_A0 SPI slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (direction controlled by USCI –output)
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI)
USCI_B0 SPI slave transmit enable (direction controlled by USCI)
USCI_B0 SPI slave out master in (direction controlled by USCI)
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI)
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI)
USCI_A0 SPI slave transmit enable (direction controlled by USCI)
USCI_A3 UART RXD (direction controlled by USCI –input)
USCI_A3 SPI slave out master in (direction controlled by USCI)
USCI_A3 UART TXD (direction controlled by USCI –output)
USCI_A3 SPI slave in master out (direction controlled by USCI)
USCI_B3 SPI slave in master out (direction controlled by USCI)
USCI_B3 I2C data (open drain and direction controlled by USCI)
USCI_B3 SPI slave out master in (direction controlled by USCI)
USCI_B3 I2C clock (open drain and direction controlled by USCI)
Reserved
20
21
22
23
24
25
26
27
28
29
30
Disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals
31 (0FFh)(1)
PM_ANALOG
(1) The value of the PM_ANALOG mnemonic is 0FFh. The port mapping registers are only 5 bits wide, and the upper bits are ignored,
which results in a read value of 31.
表9-9 lists the default settings for all pins that support port mapping.
表9-9. Default Mapping
PIN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
USCI_A1 clock input/output (direction controlled by USCI)
P4.0/P4MAP0
PM_UCB1STE/PM_UCA1CLK
USCI_B1 SPI slave in master out (direction controlled by USCI)
USCI_B1 I2C data (open drain and direction controlled by USCI)
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
P4.7/P4MAP7
PM_UCB1SIMO/PM_UCB1SDA
PM_UCB1SOMI/PM_UCB1SCL
PM_UCB1CLK/PM_UCA1STE
PM_UCA1TXD/PM_UCA1SIMO
PM_UCA1RXD/PM_UCA1SOMI
PM_UCA3TXD/PM_UCA3SIMO
PM_UCA3RXD/PM_UCA3SOMI
USCI_B1 SPI slave out master in (direction controlled by USCI)
USCI_B1 I2C clock (open drain and direction controlled by USCI)
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
USCI_B1 clock input/output (direction controlled by USCI)
USCI_A1 UART TXD (Direction controlled by USCI –output)
USCI_A1 SPI slave in master out (direction controlled by USCI)
USCI_A1 UART RXD (Direction controlled by USCI –input)
USCI_A1 SPI slave out master in (direction controlled by USCI)
USCI_A3 UART TXD (Direction controlled by USCI –output)
USCI_A3 SPI slave in master out (direction controlled by USCI)
USCI_A3 UART RXD (Direction controlled by USCI –input)
USCI_A3 SPI slave out master in (direction controlled by USCI)
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9.9.3 Oscillator and System Clock
The clock system is supported by the Unified Clock System (UCS) module, which includes support for a 32-kHz
watch crystal oscillator (XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power low-
frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally
controlled oscillator (DCO), and a high-frequency crystal oscillator (XT2). The UCS module is designed to meet
the requirements of both low system cost and low power consumption. The UCS module features digital
frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency
to a programmable multiple of the selected FLL reference frequency. The internal DCO provides a fast turnon
clock source and stabilizes in 3.5 µs (typical). The UCS module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally
controlled oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
9.9.4 Power-Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, and brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS
and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
9.9.5 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations
with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed
and unsigned multiply-and-accumulate operations.
9.9.6 Real-Time Clock (RTC_A)
The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-
time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that
can be cascaded to form a 16-bit timer or counter. Both timers can be read and written by software. Calendar
mode integrates an internal calendar that compensates for months with less than 31 days and includes leap year
correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
9.9.7 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
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9.9.8 System Module (SYS)
The SYS module handles many of the system functions within the device. These functions include power-on
reset (POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators, bootloader (BSL) entry mechanisms, and configuration management (device descriptors). The SYS
module also includes a data exchange mechanism using JTAG that is called a JTAG mailbox and that can be
used in the application. 表9-10 lists the SYS module interrupt vector registers.
表9-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR
ADDRESS
INTERRUPT EVENT
VALUE
PRIORITY
REGISTER
No interrupt pending
Brownout (BOR)
RST/NMI (BOR)
PMMSWBOR (BOR)
Wakeup from LPMx.5
Security violation (BOR)
SVSL (POR)
00h
02h
Highest
04h
06h
08h
0Ah
0Ch
SVSH (POR)
0Eh
SVML_OVP (POR)
SVMH_OVP (POR)
PMMSWPOR (POR)
WDT time-out (PUC)
WDT password violation (PUC)
KEYV flash password violation (PUC)
Reserved
10h
SYSRSTIV, System Reset
019Eh
12h
14h
16h
18h
1Ah
1Ch
Peripheral area fetch (PUC)
PMM password violation (PUC)
Reserved
1Eh
20h
22h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVMLIFG
02h
SVMHIFG
04h
SVSMLDLYIFG
SVSMHDLYIFG
VMAIFG
06h
08h
SYSSNIV, System NMI
019Ch
0Ah
JMBINIFG
0Ch
JMBOUTIFG
0Eh
SVMLVLRIFG
10h
SVMHVLRIFG
12h
Reserved
14h to 1Eh
00h
Lowest
Highest
No interrupt pending
NMIIFG
02h
OFIFG
04h
SYSUNIV, User NMI
019Ah
ACCVIFG
06h
Reserved
08h
Reserved
0Ah to 1Eh
Lowest
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9.9.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC10_A conversion memory to RAM.
Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces
system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move
data to or from a peripheral (see 表9-11).
表9-11. DMA Trigger Assignments
CHANNEL
TRIGGER(1)
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
UCA2RXIFG
UCA2TXIFG
UCB2RXIFG
UCB2TXIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
UCA2RXIFG
UCA2TXIFG
UCB2RXIFG
UCB2TXIFG
Reserved
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
UCA2RXIFG
UCA2TXIFG
UCB2RXIFG
UCB2TXIFG
Reserved
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC10IFG0(2)
UCA3RXIFG
UCA3TXIFG
UCB3RXIFG
UCB3TXIFG
MPY ready
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC10IFG0(2)
UCA3RXIFG
UCA3TXIFG
UCB3RXIFG
UCB3TXIFG
MPY ready
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
ADC10IFG0(2)
UCA3RXIFG
UCA3TXIFG
UCB3RXIFG
UCB3TXIFG
MPY ready
DMA2IFG
DMA0IFG
DMA1IFG
DMAE0
DMAE0
DMAE0
(1) If a reserved trigger source is selected, no trigger is generated.
(2) Only on devices with ADC; reserved on devices without ADC
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9.9.10 Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baud-rate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3- or 4-pin) or I2C.
The MSP430F525x include four complete USCI modules (n = 0, 1, 2, 3).
9.9.11 TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 supports multiple captures
or compares, PWM outputs, and interval timing (see 表 9-12). TA0 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
表9-12. TA0 Signal Connections
INPUT PIN
NUMBER
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
RGC, ZXH, ZQE
DEVICE INPUT MODULE INPUT
MODULE
BLOCK
SIGNAL
SIGNAL
RGC, ZXH, ZQE
18, H2 - P1.0
TA0CLK
ACLK (internal)
SMCLK (internal)
TA0CLK
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
CCR0
NA
NA
18, H2 - P1.0
19, H3 - P1.1
TA0.0
19, H3 - P1.1
20, J3 - P1.2
DVSS
TA0
TA0.0
DVSS
DVCC
VCC
20, J3 - P1.2
TA0.1
CCI1A
CBOUT
(internal)
ADC10 (internal)
ADC10SHSx = {1}
CCI1B
CCR1
TA1
TA0.1
DVSS
DVCC
GND
VCC
21, G4 - P1.3
22, H4 - P1.4
23, J4 - P1.5
TA0.2
CCI2A
CCI2B
GND
VCC
21, G4 - P1.3
22, H4 - P1.4
23, J4 - P1.5
ACLK (internal)
DVSS
CCR2
CCR3
CCR4
TA2
TA3
TA4
TA0.2
TA0.3
TA0.4
DVCC
TA0.3
CCI3A
CCI3B
GND
VCC
DVSS
DVSS
DVCC
TA0.4
CCI4A
CCI4B
GND
VCC
DVSS
DVSS
DVCC
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9.9.12 TA1
TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 supports multiple
captures or compares, PWM outputs, and interval timing (see 表 9-13). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
表9-13. TA1 Signal Connections
INPUT PIN
NUMBER
OUTPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
OUTPUT SIGNAL
DEVICE OUTPUT
SIGNAL
MODULE BLOCK
RGC, ZQE
RGC, ZQE
24, G5 - P1.6
TA1CLK
ACLK (internal)
SMCLK (internal)
TA1CLK
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
NA
TA0
TA1
TA2
NA
24, G5 - P1.6
25, H5 - P1.7
TA1.0
25, H5 - P1.7
26, J5 - P2.0
27, G6 - P2.1
DVSS
CCR0
CCR1
CCR2
TA1.0
TA1.1
TA1.2
DVSS
DVCC
VCC
26, J5 - P2.0
27, G6 - P2.1
TA1.1
CCI1A
CCI1B
GND
CBOUT (internal)
DVSS
DVCC
VCC
TA1.2
CCI2A
CCI2B
GND
ACLK (internal)
DVSS
DVCC
VCC
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9.9.13 TA2
TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 supports multiple
captures or compares, PWM outputs, and interval timing (see 表 9-14). TA2 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
表9-14. TA2 Signal Connections
INPUT PIN
NUMBER
OUTPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE
OUTPUT SIGNAL
DEVICE OUTPUT
SIGNAL
MODULE BLOCK
RGC, ZXH, ZQE
RGC, ZXH, ZQE
1, A1 - P6.0
TA2CLK
ACLK (internal)
SMCLK (internal)
TA2CLK
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
NA
TA0
TA1
TA2
NA
1, A1 - P6.0
2, B2 - P6.1
TA2.0
2, B2 - P6.1
3, B1 - P6.2
4, C2 - P6.3
DVSS
CCR0
CCR1
CCR2
TA2.0
TA2.1
TA2.2
DVSS
DVCC
VCC
3, B1 - P6.2
4, C2 - P6.3
TA2.1
CCI1A
CCI1B
GND
CBOUT (internal)
DVSS
DVCC
VCC
TA2.2
CCI2A
CCI2B
GND
ACLK (internal)
DVSS
DVCC
VCC
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9.9.14 TB0
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 supports multiple
captures or compares, PWM outputs, and interval timing (see 表 9-15). TB0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
表9-15. TB0 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
RGC, ZXH, ZQE
DEVICE INPUT
SIGNAL
MODULE INPUT
SIGNAL
MODULE OUTPUT DEVICE OUTPUT
MODULE BLOCK
SIGNAL
SIGNAL
RGC, ZXH, ZQE
(1)
TB0CLK
ACLK (internal)
SMCLK (internal)
TB0CLK
TBCLK
ACLK
Timer
NA
NA
SMCLK
TBCLK
CCI0A
(1)
(1)
(1)
TB0.0
ADC10 (internal)
ADC10SHSx = {2}
(1)
TB0.0
CCI0B
CCR0
CCR1
TB0
TB1
TB0.0
TB0.1
DVSS
DVCC
TB0.1
GND
VCC
(1)
(1)
CCI1A
ADC10 (internal)
ADC10SHSx = {3}
CBOUT (internal)
CCI1B
DVSS
DVCC
TB0.2
GND
VCC
(1)
(1)
(1)
(1)
(1)
(1)
(1)
CCI2A
CCI2B
GND
VCC
TB0.2
CCR2
CCR3
CCR4
CCR5
CCR6
TB2
TB3
TB4
TB5
TB6
TB0.2
TB0.3
TB0.4
TB0.5
TB0.6
DVSS
DVCC
TB0.3
(1)
(1)
CCI3A
CCI3B
GND
VCC
TB0.3
DVSS
DVCC
TB0.4
(1)
(1)
CCI4A
CCI4B
GND
VCC
TB0.4
DVSS
DVCC
TB0.5
(1)
(1)
CCI5A
CCI5B
GND
VCC
TB0.5
DVSS
DVCC
TB0.6
(1)
CCI6A
CCI6B
GND
VCC
ACLK (internal)
DVSS
DVCC
(1) Timer functions can be selected by the port mapping controller.
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9.9.15 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
9.9.16 ADC10_A
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and a conversion result buffer. A window comparator with lower
and upper limits allows CPU-independent result monitoring with three window comparator interrupt flags.
9.9.17 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
9.9.18 Reference (REF) Module Voltage Reference
The REF module generates all of the critical reference voltages that can be used by the various analog
peripherals in the device.
9.9.19 Embedded Emulation Module (EEM) (S Version)
The EEM supports real-time in-system debugging. The S version of the EEM has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
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9.9.20 Peripheral File Map
表9-16 lists the base address for the registers of each peripheral module.
表9-16. Peripherals
OFFSET ADDRESS
RANGE
MODULE NAME
BASE ADDRESS
0100h
0120h
0140h
0150h
0158h
015Ch
0160h
0180h
01B0h
01C0h
01E0h
0200h
0220h
0240h
0260h
0320h
0340h
0380h
03C0h
0400h
04A0h
04C0h
0500h
0510h
0520h
0530h
05C0h
05E0h
0600h
0620h
0640h
0660h
0680h
06A0h
0740h
08C0h
000h to 01Fh
000h to 010h
000h to 00Fh
000h to 007h
000h to 001h
000h to 001h
000h to 01Fh
000h to 01Fh
000h to 001h
000h to 002h
000h to 007h
000h to 01Fh
000h to 00Bh
000h to 01Fh
000h to 00Bh
000h to 01Fh
000h to 02Eh
000h to 02Eh
000h to 02Eh
000h to 02Eh
000h to 01Bh
000h to 02Fh
000h to 00Fh
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 00Fh
Special Functions (see 表9-17)
PMM (see 表9-18)
Flash Control (see 表9-19)
CRC16 (see 表9-20)
RAM Control (see 表9-21)
Watchdog (see 表9-22)
UCS (see 表9-23)
SYS (see 表9-24)
Shared Reference (see 表9-25)
Port Mapping Control (see 表9-26)
Port Mapping Port P4 (see 表9-26)
Port P1, P2 (see 表9-27)
Port P3, P4 (see 表9-28)
Port P5, P6 (see 表9-29)
Port P7 (see 表9-30)
Port PJ (see 表9-31)
TA0 (see 表9-32)
TA1 (see 表9-33)
TB0 (see 表9-34)
TA2 (see 表9-35)
Real-Time Clock (RTC_A) (see 表9-36)
32-Bit Hardware Multiplier (see 表9-37)
DMA General Control (see 表9-38)
DMA Channel 0 (see 表9-38)
DMA Channel 1 (see 表9-38)
DMA Channel 2 (see 表9-38)
USCI_A0 (see 表9-39)
USCI_B0 (see 表9-40)
USCI_A1 (see 表9-41)
USCI_B1 (see 表9-42)
USCI_A2 (see 表9-39)
USCI_B2 (see 表9-40)
USCI_A3 (see 表9-41)
USCI_B3 (see 表9-42)
ADC10_A (see 表9-47)
Comparator_B (see 表9-48)
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表9-17. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SFR interrupt enable
SFR interrupt flag
SFRIE1
00h
02h
04h
SFRIFG1
SFR reset pin control
SFRRPCR
表9-18. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
OFFSET
PMM control 0
PMMCTL0
00h
02h
04h
06h
0Ch
0Eh
10h
PMM control 1
PMMCTL1
SVSMHCTL
SVSMLCTL
PMMIFG
SVS high-side control
SVS low-side control
PMM interrupt flags
PMM interrupt enable
PMM power mode 5 control
PMMIE
PM5CTL0
表9-19. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
Flash control 1
Flash control 3
Flash control 4
FCTL1
FCTL3
FCTL4
00h
04h
06h
表9-20. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
CRC data input
CRC16DI
00h
02h
04h
06h
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
CRCDIRB
CRCINIRES
CRCRESR
表9-21. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
RAM control 0
RCCTL0
00h
00h
表9-22. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
Watchdog timer control
WDTCTL
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表9-23. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
OFFSET
UCS control 0
UCS control 1
UCS control 2
UCS control 3
UCS control 4
UCS control 5
UCS control 6
UCS control 7
UCS control 8
UCS control 9
UCSCTL0
UCSCTL1
UCSCTL2
UCSCTL3
UCSCTL4
UCSCTL5
UCSCTL6
UCSCTL7
UCSCTL8
UCSCTL9
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
表9-24. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
02h
06h
08h
0Ah
0Ch
0Eh
1Ah
1Ch
1Eh
Bootloader configuration area
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSUNIV
SYSSNIV
SYSRSTIV
表9-25. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
Shared reference control
REFCTL
00h
表9-26. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)
REGISTER DESCRIPTION
REGISTER
Port mapping key/ID
Port mapping control
Port P4.0 mapping
Port P4.1 mapping
Port P4.2 mapping
Port P4.3 mapping
Port P4.4 mapping
Port P4.5 mapping
Port P4.6 mapping
Port P4.7 mapping
PMAPKEYID
00h
02h
00h
01h
02h
03h
04h
05h
06h
07h
PMAPCTL
P4MAP0
P4MAP1
P4MAP2
P4MAP3
P4MAP4
P4MAP5
P4MAP6
P4MAP7
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表9-27. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P1 input
P1IN
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
Port P1 output
P1OUT
P1DIR
P1REN
P1DS
P1SEL
P1IV
Port P1 direction
Port P1 resistor enable
Port P1 drive strength
Port P1 selection
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2DS
P2SEL
P2IV
Port P2 direction
Port P2 resistor enable
Port P2 drive strength
Port P2 selection
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
表9-28. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P3 input
P3IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P3 output
P3OUT
P3DIR
P3REN
P3DS
Port P3 direction
Port P3 resistor enable
Port P3 drive strength
Port P3 selection
Port P4 input
P3SEL
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4DS
Port P4 direction
Port P4 resistor enable
Port P4 drive strength
Port P4 selection
P4SEL
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表9-29. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
Port P5 output
P5OUT
P5DIR
P5REN
P5DS
P5SEL
P6IN
Port P5 direction
Port P5 resistor enable
Port P5 drive strength
Port P5 selection
Port P6 input
Port P6 output
P6OUT
P6DIR
P6REN
P6DS
P6SEL
P6IV
Port P6 direction
Port P6 resistor enable
Port P6 drive strength
Port P6 selection
Port P6 interrupt vector word
Port P6 interrupt edge select
Port P6 interrupt enable
Port P6 interrupt flag
P6IES
P6IE
P6IFG
表9-30. Port P7 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
02h
04h
06h
08h
0Ah
Port P7 output
P7OUT
P7DIR
P7REN
P7DS
Port P7 direction
Port P7 resistor enable
Port P7 drive strength
Port P7 selection
P7SEL
表9-31. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port PJ input
PJIN
00h
02h
04h
06h
08h
Port PJ output
PJOUT
PJDIR
PJREN
PJDS
Port PJ direction
Port PJ resistor enable
Port PJ drive strength
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表9-32. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA0 control
TA0CTL
00h
02h
04h
06h
08h
0Ah
10h
12h
14h
16h
18h
1Ah
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
TA0 counter
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0CCTL3
TA0CCTL4
TA0R
Capture/compare 0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0CCR3
TA0CCR4
TA0EX0
TA0 interrupt vector
TA0IV
表9-33. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA1 control
TA1CTL
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1 interrupt vector
TA1IV
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表9-34. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
TB0 counter
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0CCTL3
TB0CCTL4
TB0CCTL5
TB0CCTL6
TB0R
Capture/compare 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0CCR3
TB0CCR4
TB0CCR5
TB0CCR6
TB0EX0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Capture/compare 5
Capture/compare 6
TB0 expansion 0
TB0 interrupt vector
TB0IV
表9-35. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TA2 control
TA2CTL
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA2 counter
TA2CCTL0
TA2CCTL1
TA2CCTL2
TA2R
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2CCR2
TA2EX0
TA2 interrupt vector
TA2IV
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表9-36. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTC control 0
RTCCTL0
00h
01h
02h
03h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
RTC control 1
RTCCTL1
RTC control 2
RTCCTL2
RTC control 3
RTCCTL3
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTCPS0CTL
RTCPS1CTL
RTCPS0
RTC prescaler 1
RTCPS1
RTC interrupt vector word
RTC seconds/counter 1
RTC minutes/counter 2
RTC hours/counter 3
RTC day of week/counter 4
RTC days
RTCIV
RTCSEC/RTCNT1
RTCMIN/RTCNT2
RTCHOUR/RTCNT3
RTCDOW/RTCNT4
RTCDAY
RTC month
RTCMON
RTC year low
RTCYEARL
RTCYEARH
RTCAMIN
RTC year high
RTC alarm minutes
RTC alarm hours
RTC alarm day of week
RTC alarm days
RTCAHOUR
RTCADOW
RTCADAY
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表9-37. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 –multiply
MPYS
MAC
16-bit operand 1 –signed multiply
16-bit operand 1 –multiply accumulate
16-bit operand 1 –signed multiply accumulate
16-bit operand 2
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 –multiply low word
32-bit operand 1 –multiply high word
32-bit operand 1 –signed multiply low word
32-bit operand 1 –signed multiply high word
32-bit operand 1 –multiply accumulate low word
32-bit operand 1 –multiply accumulate high word
32-bit operand 1 –signed multiply accumulate low word
32-bit operand 1 –signed multiply accumulate high word
32-bit operand 2 –low word
OP2H
32-bit operand 2 –high word
RES0
32 × 32 result 0 –least significant word
32 × 32 result 1
RES1
32 × 32 result 2
RES2
RES3
32 × 32 result 3 –most significant word
MPY32 control 0
MPY32CTL0
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表9-38. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
REGISTER DESCRIPTION
REGISTER
OFFSET
DMA channel 0 control
DMA0CTL
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Eh
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA module control 0
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
DMA module control 1
DMA module control 2
DMA module control 3
DMA module control 4
DMA interrupt vector
表9-39. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA0CTL1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA0CTL0
UCA0BR0
USCI baud rate 0
USCI baud rate 1
UCA0BR1
USCI modulation control
USCI status
UCA0MCTL
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA0IFG
UCA0IV
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表9-40. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
UCB0CTL1
UCB0CTL0
UCB0BR0
UCB0BR1
UCB0STAT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA
UCB0I2CSA
UCB0IE
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB0IFG
USCI interrupt vector word
UCB0IV
表9-41. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA1CTL1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA1CTL0
UCA1BR0
USCI baud rate 0
USCI baud rate 1
UCA1BR1
USCI modulation control
USCI status
UCA1MCTL
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA1IFG
UCA1IV
表9-42. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
UCB1CTL1
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB1CTL0
UCB1BR0
UCB1BR1
UCB1STAT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA
UCB1I2CSA
UCB1IE
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB1IFG
USCI interrupt vector word
UCB1IV
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表9-43. USCI_A2 Registers (Base Address: 0640h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA2CTL1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 0
UCA2CTL0
UCA2BR0
USCI baud rate 0
USCI baud rate 1
UCA2BR1
USCI modulation control
USCI status
UCA2MCTL
UCA2STAT
UCA2RXBUF
UCA2TXBUF
UCA2ABCTL
UCA2IRTCTL
UCA2IRRCTL
UCA2IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA2IFG
UCA2IV
表9-44. USCI_B2 Registers (Base Address: 0660h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
UCB2CTL1
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB2CTL0
UCB2BR0
UCB2BR1
UCB2STAT
UCB2RXBUF
UCB2TXBUF
UCB2I2COA
UCB2I2CSA
UCB2IE
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB2IFG
USCI interrupt vector word
UCB2IV
表9-45. USCI_A3 Registers (Base Address: 0680h)
REGISTER DESCRIPTION
REGISTER
OFFSET
USCI control 1
UCA3CTL1
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
USCI control 0
UCA3CTL0
UCA3BR0
USCI baud rate 0
USCI baud rate 1
UCA3BR1
USCI modulation control
USCI status
UCA3MCTL
UCA3STAT
UCA3RXBUF
UCA3TXBUF
UCA3ABCTL
UCA3IRTCTL
UCA3IRRCTL
UCA3IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
UCA3IFG
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表9-45. USCI_A3 Registers (Base Address: 0680h) (continued)
REGISTER DESCRIPTION
REGISTER
OFFSET
OFFSET
USCI interrupt vector word
UCA3IV
1Eh
表9-46. USCI_B3 Registers (Base Address: 06A0h)
REGISTER DESCRIPTION
REGISTER
USCI synchronous control 1
USCI synchronous control 0
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
UCB3CTL1
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
UCB3CTL0
UCB3BR0
UCB3BR1
UCB3STAT
UCB3RXBUF
UCB3TXBUF
UCB3I2COA
UCB3I2CSA
UCB3IE
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
UCB3IFG
USCI interrupt vector word
UCB3IV
表9-47. ADC10_A Registers (Base Address: 0740h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC10_A control 0
ADC10CTL0
00h
02h
04h
06h
08h
0Ah
12h
1Ah
1Ch
1Eh
ADC10_A control 1
ADC10CTL1
ADC10CTL2
ADC10LO
ADC10_A control 2
ADC10_A window comparator low threshold
ADC10_A window comparator high threshold
ADC10_A memory control 0
ADC10_A conversion memory
ADC10_A interrupt enable
ADC10_A interrupt flags
ADC10HI
ADC10MCTL0
ADC10MEM0
ADC10IE
ADC10IGH
ADC10IV
ADC10_A interrupt vector word
表9-48. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Comp_B control 0
Comp_B control 1
Comp_B control 2
Comp_B control 3
Comp_B interrupt
CBCTL0
00h
02h
04h
06h
0Ch
0Eh
CBCTL1
CBCTL2
CBCTL3
CBINT
Comp_B interrupt vector word
CBIV
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9.10 Input/Output Diagrams
9.10.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
图9-2 shows the port diagram. 表9-49 summarizes the selection of the pin function.
Pad Logic
P1REN.x
DVSS
DVIO
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
From module
P1OUT.x
0
1
From module
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
P1.4/TA0.3
P1.5/TA0.4
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
EN
D
To module
P1IRQ.x
P1IE.x
EN
Q
P1IFG.x
Set
P1SEL.x
P1IES.x
Interrupt
Edge
Select
图9-2. Port P1 (P1.0 to P1.7) Diagram
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表9-49. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P1.x)
x
FUNCTION
P1DIR.x
P1SEL.x
P1.0 (I/O)
TA0CLK
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
0
0
ACLK
1
P1.1 (I/O)
TA0.CCI0A
TA0.0
I: 0; O: 1
1
2
3
4
5
6
7
0
1
P1.2 (I/O)
TA0.CCI1A
TA0.1
I: 0; O: 1
P1.2/TA0.1
0
1
P1.3 (I/O)
TA0.CCI2A
TA0.2
I: 0; O: 1
P1.3/TA0.2
0
1
P1.4 (I/O)
TA0.CCI3A
TA0.3
I: 0; O: 1
P1.4/TA0.3
0
1
P1.5 (I/O)
TA0.CCI4A
TA0.4
I: 0; O: 1
P1.5/TA0.4
0
1
P1.6 (I/O)
TA1CLK
I: 0; O: 1
P1.6/TA1CLK/CBOUT
P1.7/TA1.0
0
CBOUT comparator B
P1.7 (I/O)
TA1.CCI0A
TA1.0
1
I: 0; O: 1
0
1
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9.10.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
图9-3 shows the port diagram. 表9-50 summarizes the selection of the pin function.
Pad Logic
P2REN.x
DVSS
DVIO
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
From module
P2OUT.x
0
1
From module
P2.0/TA1.1
P2.1/TA1.2
P2DS.x
0: Low drive
1: High drive
P2SEL.x
P2IN.x
P2.2/UCB3SIMO/UCB3SDA
P2.3/UCB3SOMI/UCB3SCL
P2.4/UCB3CLK/UCA3STE
P2.5/UCB3STE/UCA3CLK
P2.6/RTCCLK/DMAE0
EN
D
P2.7/UB0STE/UCA0CLK
To module
To module
P2IE.x
EN
Q
P2IFG.x
Set
P2SEL.x
P2IES.x
Interrupt
Edge
Select
图9-3. Port P2 (P2.0 to P2.7) Diagram
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表9-50. Port P2 (P2.0 to P2.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2.0 (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
P2.0/TA1.1
P2.1/TA1.2
0
TA1.CCI1A
TA1.1
0
1
P2.1 (I/O)
I: 0; O: 1
1
TA1.CCI2A
TA1.2
0
1
P2.2 (I/O)
I: 0; O: 1
P2.2/UCB3SIMO/UCB3SDA
P2.3/UCB3SOMI/UCB3SCL
P2.4/UCB3CLK/UCA3STE
P2.5/UCB3STE/UCA3CLK
2
3
4
5
UCB3SIMO/UCB3SDA
P2.3 (I/O)
X
I: 0; O: 1
UCB3SOMI/UCB3SCL
X
P2.4 (I/O)
I: 0; O: 1
UCB3CLK/UCA3STE(2) (3)
P2.5 (I/O)
X
I: 0; O: 1
UCB3STE/UCA3CLK(2) (4)
X
P2.6 (I/O)
I: 0; O: 1
P2.6/RTCCLK/DMAE0
6
7
DMAE0
0
RTCCLK
1
I: 0; O: 1
X
P2.7 (I/O)
P2.7/UCB0STE/UCA0CLK
(1) X = Don't care
UCB0STE/UCA0CLK(2) (5)
(2) The pin direction is controlled by the USCI module.
(3) UCB3CLK function takes precedence over UCA3STE function. If the pin is required as UCB3CLK input or output, USCI A3 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(4) UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI_B3 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(5) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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9.10.3 Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
图9-4 shows the port diagram. 表9-51 summarizes the selection of the pin function.
Pad Logic
P3REN.x
DVSS
DVIO
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
From module
P3OUT.x
0
1
From module
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
P3.4/UCA0RXD/UCA0SOMI
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
EN
D
To module
图9-4. Port P3 (P3.0 to P3.4) Diagram
表9-51. Port P3 (P3.0 to P3.4) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
P3.0/UCB0SIMO/UCB0SDA
P3.1/UCB0SOMI/UCB0SCL
P3.2/UCB0CLK/UCA0STE
P3.3/UCA0TXD/UCA0SIMO
x
0
1
2
3
4
FUNCTION
P3DIR.x
P3SEL.x
P3.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
UCB0SIMO/UCB0SDA(2) (3)
X
P3.1 (I/O)
I: 0; O: 1
UCB0SOMI/UCB0SCL(2) (3)
P3.2 (I/O)
X
I: 0; O: 1
UCB0CLK/UCA0STE(2) (4)
X
I: 0; O: 1
X
P3.3 (I/O)
UCA0TXD/UCA0SIMO(2)
P3.4 (I/O)
I: 0; O: 1
X
P3.4/UCA0RXD/UCA0SOMI
(1) X = Don't care
UCA0RXD/UCA0SOMI(2)
(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
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9.10.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
图9-5 shows the port diagram. 表9-52 summarizes the selection of the pin function.
Pad Logic
P4REN.x
DVSS
DVIO
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
From Port Mapping Control
P4OUT.x
0
1
From Port Mapping Control
P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
P4.7/P4MAP7
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
EN
D
To Port Mapping Control
图9-5. Port P4 (P4.0 to P4.7) Diagram
表9-52. Port P4 (P4.0 to P4.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P4.x)
P4.0/P4MAP0
P4.1/P4MAP1
P4.2/P4MAP2
P4.3/P4MAP3
P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
x
0
1
2
3
4
5
6
7
FUNCTION
P4DIR.x(2)
P4SEL.x
P4MAPx
P4.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
≤30
X
Mapped secondary digital function
P4.1 (I/O)
X
I: 0; O: 1
Mapped secondary digital function
P4.2 (I/O)
X
≤30
X
I: 0; O: 1
Mapped secondary digital function
P4.3 (I/O)
X
≤30
X
I: 0; O: 1
Mapped secondary digital function
P4.4 (I/O)
X
≤30
X
I: 0; O: 1
Mapped secondary digital function
P4.5 (I/O)
X
≤30
X
I: 0; O: 1
Mapped secondary digital function
P4.6 (I/O)
X
I: 0; O: 1
X
≤30
X
Mapped secondary digital function
P4.7 (I/O)
≤30
X
I: 0; O: 1
X
P4.7/P4MAP7
Mapped secondary digital function
≤30
(1) X= Don't care
(2) The direction of some mapped secondary functions are controlled directly by the module. See 表9-8 for specific direction control
information of mapped secondary functions.
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9.10.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
图9-6 shows the port diagram. 表9-53 summarizes the selection of the pin function.
Pad Logic
To or from Reference (1)
To ADC10 (1)
INCHx = x (1)
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
P5OUT.x
0
1
From module
P5.0/(A8/VeREF+)
P5.1/(A9/VeREF–)
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
D
To module
(1) not available for MSPF430F5258
MSPF430F5256
MSPF430F5254
MSPF430F5252
图9-6. Port P5 (P5.0 and P5.1) Diagram
表9-53. Port P5 (P5.0 and P5.1) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
0
1
FUNCTION
P5DIR.x
P5SEL.x
REFOUT(3)
P5.0 (I/O)(2)
I: 0; O: 1
0
1
0
1
X
0
X
0
P5.0/A8/VeREF+
A8/VeREF+(4)
P5.1 (I/O)(2)
X
I: 0; O: 1
X
P5.1/A9/VeREF–
A9/VeREF–(5)
(1) X = Don't care
(2) Default condition
(3) REFOUT resides in the REF module.
(4) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC10_A. Channel A8, when
selected with the INCHx bits, is connected to the VeREF+ pin.
(5) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC10_A. Channel A9, when selected
with the INCHx bits, is connected to the VeREF- pin.
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9.10.6 Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
图9-7 and 图9-8 show the port diagrams. 表9-54 summarizes the selection of the pin function.
Pad Logic
To XT2
P5REN.2
DVSS
DVCC
0
1
1
P5DIR.2
0
1
P5OUT.2
0
1
Module X OUT
P5.2/XT2IN
P5DS.2
0: Low drive
1: High drive
P5SEL.2
P5IN.2
Bus
Keeper
EN
D
Module X IN
图9-7. Port P5 (P5.2) Diagram
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Pad Logic
To XT2
P5REN.3
DVSS
DVCC
0
1
1
P5DIR.3
0
1
P5OUT.3
0
1
Module X OUT
P5SEL.2
P5.3/XT2OUT
P5DS.3
0: Low drive
1: High drive
XT2BYPASS
P5SEL.3
P5IN.3
Bus
Keeper
EN
D
Module X IN
图9-8. Port P5 (P5.3) Diagram
表9-54. Port P5 (P5.2 and P5.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.2
P5SEL.3
XT2BYPASS
P5.2 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
0
X
0
1
X
0
1
P5.2/XT2IN
2
XT2IN crystal mode(2)
XT2IN bypass mode(2)
P5.3 (I/O)
X
X
I: 0; O: 1
P5.3/XT2OUT
3
XT2OUT crystal mode(3)
P5.3 (I/O)(3)
X
X
X
0
(1) X = Don't care
(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.
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9.10.7 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
图9-9 and 图9-10 show the port diagrams. 表9-55 summarizes the selection of the pin function.
Pad Logic
to XT1
P5REN.4
DVSS
DVCC
0
1
1
P5DIR.4
0
1
P5OUT.4
0
1
Module X OUT
P5.4/XIN
P5DS.4
0: Low drive
1: High drive
P5SEL.4
P5IN.4
Bus
Keeper
EN
D
Module X IN
图9-9. Port P5 (P5.4) Diagram
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Pad Logic
to XT1
P5REN.5
DVSS
DVCC
0
1
1
P5DIR.5
0
1
P5OUT.5
0
1
Module X OUT
P5.5/XOUT
P5SEL.4
P5DS.5
0: Low drive
1: High drive
XT1BYPASS
P5SEL.5
P5IN.5
Bus
Keeper
EN
D
Module X IN
图9-10. Port P5 (P5.5) Diagram
表9-55. Port P5 (P5.4 and P5.5) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.4
P5SEL.5
XT1BYPASS
P5.4 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
0
X
0
1
X
0
1
P5.4/XIN
4
XIN crystal mode(2)
XIN bypass mode(2)
P5.5 (I/O)
X
X
I: 0; O: 1
P5.5/XOUT
5
XOUT crystal mode(3)
P5.5 (I/O)(3)
X
X
X
0
(1) X = Don't care
(2) Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as
general-purpose I/O.
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9.10.8 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
图9-11 shows the port diagram. 表9-56 summarizes the selection of the pin function.
Pad Logic
To ADC10 (1)
INCHx = x (1)
To Comparator_B
From Comparator_B
CBPD.x
P6REN.x
DVSS
DVCC
0
1
1
P6DIR.x
0
1
Direction
0: Input
1: Output
P6OUT.x
0
1
From module
P6.0/TA2CLK/CB0/(A0)
P6.1/TA2.0/CB1/(A1)
P6.2/TA2.1/CB2/(A2)
P6.3/TA2.2/CB3/(A3)
P6.4/CB4/(A4)
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
P6.5/CB5/(A5)
P6.6/CB6/(A6)
P6.7/CB7/(A7)
Bus
Keeper
EN
D
To module
P6IE.x
EN
Set
P6IRQ.x
Q
P6IFG.x
(1) not available for MSPF430F5258
MSPF430F5256
MSPF430F5254
P6SEL.x
P6IES.x
Interrupt
Edge
Select
MSPF430F5252
图9-11. Port P6 (P6.0 to P6.7) Diagram
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表9-56. Port P6 (P6.0 to P6.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x
CBPD
0
P6.0 (I/O)
TA2CLK
SMCLK
A0
I: 0; O: 1
0
1
0
0
P6.0/TA2CLK/SMCLK/CB0/(A0)
0
1
1
0
X
X
X
0
1
CB0(1)
P6.1 (I/O)
TA2.CCI0A
TA2.0
X
1
I: 0; O: 1
0
0
1
0
P6.1/TA2.0/CB1/(A1)
P6.2/TA2.1/CB2/(A2)
P6.3/TA2.1/CB3/(A3)
1
2
3
1
1
0
A1
X
X
X
0
1
CB1(1)
P6.2 (I/O)
TA2.CCI1A
TA2.1
X
1
I: 0; O: 1
0
0
1
0
1
1
0
A2
X
X
X
0
1
CB2(1)
P6.3 (I/O)
TA2.CCI2A
TA2.2
X
1
I: 0; O: 1
0
0
1
0
1
1
0
A3
X
X
X
0
1
CB3(1)
P6.4 (I/O)
A4
X
1
I: 0; O: 1
0
P6.4/CB4/(A4)
P6.5/CB5/(A5)
P6.6/CB6/(A6)
P6.7/CB7/(A7)
4
5
6
7
X
X
X
0
1
CB4(1)
P6.5 (I/O)
A5
X
1
I: 0; O: 1
0
X
X
X
0
1
CB5(1)
P6.6 (I/O)
A6
X
1
I: 0; O: 1
0
X
X
X
0
1
CB6(1)
P6.7 (I/O)
A7
X
1
I: 0; O: 1
0
X
X
X
X
1
CB7(1)
1
(1) Setting the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog
signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input
buffer for that pin, regardless of the state of the associated CBPD.x bit.
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9.10.9 Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
图9-12 shows the port diagram. 表9-57 summarizes the selection of the pin function.
Pad Logic
P7REN.x
DVSS
DVIO
0
1
1
P7DIR.x
0
1
Direction
0: Input
1: Output
From module
P7OUT.x
0
1
P7.0/UCA2TXD/UCA2SIMO
P7.1/UCA2RXD/UCA2SOMI
P7.2/UCB2CLK/UCA2STE
P7.3/UCB2SIMO/UCB2SDA
P7.4/UCB2SOMI/UCB2SCL
P7.5/UCB2STE/UCA2CLK
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
EN
D
To module
图9-12. Port P7 (P7.0 to P7.5) Diagram
表9-57. Port P7 (P7.0 to P7.5) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P7.x)
x
0
1
2
3
4
5
FUNCTION
P7DIR.x
P7SEL.x
P7.0 (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
0
1
P7.0/UCA2TXD/UCA2SIMO(2)
P7.1/UCA2RXD/UCA2SOMI(2)
P7.2/UCB2CLK/UCA2STE(2)
P7.3/UCB2SIMO/UCB2SDA(2)
P7.4/UCB2SOMI/UCB2SCL(2)
P7.5/UCB2STE/UCA2CLK(2)
UCA2TXD/UCA2SIMO(1)
X
P7.1 (I/O)
I: 0; O: 1
UCA2RXD/UCA2SOMI(1)
P7.2 (I/O)
X
I: 0; O: 1
UCB2CLK/UCA2STE(1) (3)
X
P7.3 (I/O)
I: 0; O: 1
UCB2SIMO/UCB2SDA(1) (4)
P7.4 (I/O)
X
I: 0; O: 1
X
UCB2SOMI/UCB2SCL(1) (4)
P7.5 (I/O)
I: 0; O: 1
X
UCB2STE/UCA2CLK(1)
(1) Setting P7SEL.x bit disables the output driver and the input Schmitt trigger.
(2) The pin direction is controlled by the USCI module.
(3) UCB2CLK function takes precedence over UCA2STE function. If the pin is required as UCB2CLK input or output, USCI_A2 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(4) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
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9.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
图9-13 shows the port diagram. 表9-58 summarizes the selection of the pin function.
Pad Logic
PJREN.0
0
1
DVSS
DVCC
1
PJDIR.0
DVCC
0
1
PJOUT.0
0
1
From JTAG
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
图9-13. Port PJ (PJ.0) Diagram
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9.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
图9-14 shows the port diagram. 表9-58 summarizes the selection of the pin function.
Pad Logic
PJREN.x
0
1
DVSS
DVCC
1
PJDIR.x
DVSS
0
1
PJOUT.x
0
1
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJDS.x
0: Low drive
1: High drive
From JTAG
PJIN.x
EN
D
To JTAG
图9-14. Port PJ (PJ.1 to PJ.3) Diagram
表9-58. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS
OR SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
I: 0; O: 1
X
PJ.0 (I/O)(2)
PJ.0/TDO
0
1
2
3
TDO(3)
PJ.1 (I/O)(2)
TDI/TCLK(3) (4)
PJ.2 (I/O)(2)
TMS(3) (4)
I: 0; O: 1
X
PJ.1/TDI/TCLK
PJ.2/TMS
I: 0; O: 1
X
PJ.3 (I/O)(2)
TCK(3) (4)
I: 0; O: 1
X
PJ.3/TCK
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
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9.11 Device Descriptors
表 9-59 and 表 9-60 list the contents of the device descriptor tag-length-value (TLV) structure for each device
type.
表9-59. MSP430F5259, MSP430F5257, MSP430F5255, MSP430F5253 Device Descriptor Table
VALUE
SIZE
(bytes)
DESCRIPTION(1)
ADDRESS
F5259
06h
F5257
06h
F5255
06h
F5253
06h
Info length
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
1
1
2
1
1
1
1
1
1
4
2
2
2
1
1
2
2
CRC length
CRC value
06h
06h
06h
06h
Per unit
FF
Per unit
01
Per unit
03
Per unit
05
Info Block
Device ID
Device ID
81
82
82
82
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Die Record
Die X position
Die Y position
Test results
ADC10 calibration tag
ADC10 calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
ADC 1.5-V reference
Temperature sensor 85°C
ADC10
Calibration
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
REF calibration tag
REF calibration length
01A26h
01A27h
01A28h
01A2Ah
01A2Ch
1
1
2
2
2
12h
12h
12h
12h
06h
06h
06h
06h
REF Calibration
REF 1.5-V reference factor
REF 2.0-V reference factor
REF 2.5-V reference factor
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
(1) NA = Not applicable, blank = unused and reads FFh.
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表9-60. MSP430F5258, MSP430F5256, MSP430F5254, MSP430F5252 Device Descriptor Table
VALUE
SIZE
(bytes)
DESCRIPTION(1)
ADDRESS
F5258
06h
F5256
06h
F5254
06h
F5252
06h
Info length
01A00h
01A01h
01A02h
01A04h
01A05h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
1
1
2
1
1
1
1
1
1
4
2
2
2
1
1
2
2
CRC length
CRC value
06h
06h
06h
06h
Per unit
00
Per unit
02
Per unit
04
Per unit
06
Info Block
Device ID
Device ID
82
82
82
82
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
Per unit
Per unit
08h
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Per unit
Per unit
Per unit
Per unit
13h
Die Record
Die X position
Die Y position
Test results
ADC10 calibration tag
ADC10 calibration length
ADC gain factor
ADC offset
10h
10h
10h
10h
blank
blank
blank
blank
blank
blank
blank
blank
ADC 1.5-V reference
Temperature sensor 30°C
01A1Ah
01A1Ch
01A1Eh
01A20h
01A22h
01A24h
2
2
2
2
2
2
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
blank
ADC 1.5-V reference
Temperature sensor 85°C
ADC10
Calibration
ADC 2.0-V reference
Temperature sensor 30°C
ADC 2.0-V reference
Temperature sensor 85°C
ADC 2.5-V reference
Temperature sensor 30°C
ADC 2.5-V reference
Temperature sensor 85°C
REF calibration tag
REF calibration length
01A26h
01A27h
01A28h
01A2Ah
01A2Ch
1
1
2
2
2
12h
12h
12h
12h
06h
06h
06h
06h
REF Calibration
REF 1.5-V reference factor
REF 2.0-V reference factor
REF 2.5-V reference factor
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
(1) NA = Not applicable, blank = unused and reads FFh.
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10 Device and Documentation Support
10.1 Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to help with
your development, visit the MSP430 ultra-low-power sensing and measurement MCUs overview.
10.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS –Experimental device that is not necessarily representative of the final device's electrical specifications
MSP –Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. 图10-1 provides a legend for reading the complete device name.
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MSP 430 F 5 438 A I PM T -EP
Processor Family
MCU Platform
Device Type
Series
Feature Set
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: Revision
Processor Family
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
MCU Platform
Device Type
430 = MSP430 low-power microcontroller platform
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash
L = No nonvolatile memory
Specialized Application
AFE = Analog front end
BQ = Contactless power
CG = ROM medical
FE = Flash energy meter
FG = Flash medical
FW = Flash electronic flow meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD driver
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD driver
0 = Low-voltage series
Feature Set
Various levels of integration within a series
Updated version of the base part number
Optional: Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)
-HT = Extreme temperature parts (–55°C to 150°C)
-Q1 = Automotive Q100 qualified
图10-1. Device Nomenclature
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MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
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10.3 Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are
available from TI and various third parties. See them all at MSP430 ultra-low-power MCUs –Tools & software.
表 10-1 lists the debug features of the MSP430F522x MCUs. See the Code Composer Studio IDE for MSP430
MCUs User's Guide for details on the available features.
表10-1. Hardware Debug Features
BREAK-
POINTS
(N)
RANGE
BREAK-
POINTS
LPMx.5
DEBUGGING
SUPPORT
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
CLOCK
CONTROL SEQUENCER
STATE
TRACE
BUFFER
MSP430Xv2
Yes
Yes
8
Yes
Yes
Yes
Yes
No
Design Kits and Evaluation Modules
64-pin target development board and MSP-FET programmer bundle for MSP430F5x MCUs
The MSP-FET430U64C is a powerful tool that includes the hardware and software required to complete much of
your application development work. The flash memory can be erased and programmed in seconds with only a
few keystrokes, and since the MSP430 flash is extremely low power, no external power supply is required.
64-pin target development board for MSP430F5x MCUs
The MSP-TS430RGC64C is a stand-alone 64-pin ZIF socket target board used to program and debug the
MSP430 MCU in-system through the JTAG interface or the Spy Bi-Wire (2-wire JTAG) protocol.
Dual-mode Bluetooth CC2564 module with integrated antenna evaluation board
The CC2564MODAEM evaluation board contains the Bluetooth BR/EDR/LE HCI solution. Based on TI's
CC2564B dual-mode Bluetooth single-chip device, the CC2564MODA is intended for evaluation and design
purposes, reducing design effort and enabling fast time to market.
Software
MSP430Ware™ Software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 MCU design resources, MSP430Ware software also includes a high-level API called MSP Driver
Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
MSP430F525x Code Examples
C code examples that configure each of the integrated peripherals for various application needs.
MSP Driver Library
Driver Library's abstracted API keeps you above the bits and bytes of the MSP430 hardware by providing easy-
to-use function calls. Thorough documentation is delivered through a helpful API Guide, which includes details
on each function call and the recognized parameters. Developers can use Driver Library functions to write
complete projects with minimal overhead.
MSP EnergyTrace™ Technology
EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and
displays the application's energy profile and helps to optimize it for ultra-low-power consumption.
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ULP (Ultra-Low Power) Advisor
ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully utilize the unique
ultra-low power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new
microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every
last nano amp out of your application. At build time, ULP Advisor will provide notifications and remarks to
highlight areas of your code that can be further optimized for lower power.
IEC 60730 Software Package
The IEC 60730 MSP430 software package was developed to be useful in assisting customers in complying with
IEC 60730-1:2010 (Automatic Electrical Controls for Household and Similar Use – Part 1: General
Requirements) for up to Class B products, which includes home appliances, arc detectors, power converters,
power tools, e-bikes, and many others. The IEC 60730 MSP430 software package can be embedded in
customer applications running on MSP430s to help simplify the customer's certification efforts of functional
safety-compliant consumer devices to IEC 60730-1:2010 Class B.
Fixed Point Math Library for MSP
The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 devices. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath
libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430
Continuing to innovate in the low power and low cost microcontroller space, TI brings you MSPMATHLIB.
Leveraging the intelligent peripherals of our devices, this floating point math library of scalar functions brings you
up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated
in both Code Composer Studio and IAR IDEs. Read the user's guide for an in depth look at the math library and
relevant benchmarks.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports all MSP microcontroller
devices. Code Composer Studio comprises a suite of embedded software utilities used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features.
Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) files directly to the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – which allows users to
quickly begin application development on MSP low-power microcontrollers (MCU). Creating MCU software
usually requires downloading the resulting binary program to the MSP device for validation and debugging. The
MSP-FET provides a debug communication pathway between a host computer and the target MSP.
Furthermore, the MSP-FET also provides a Backchannel UART connection between the computer's USB
interface and the MSP UART. This affords the MSP programmer a convenient method for communicating serially
between the MSP and a terminal running on the computer.
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MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
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MSP-GANG Production Programmer
The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight
identical MSP430 or MSP432 Flash or FRAM devices at the same time. The MSP Gang Programmer connects
to a host PC using a standard RS-232 or USB connection and provides flexible programming options that allow
the user to fully customize the process. The MSP Gang Programmer is provided with an expansion board, called
the Gang Splitter, that implements the interconnections between the MSP Gang Programmer and multiple target
devices.
10.4 Documentation Support
The following documents describe the MSP430F525x devices. Copies of these documents are available on the
Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com (for links to the product folders, see 节 10.5). In the upper right corner, click the "Alert me"
button. This registers you to receive a weekly digest of product information that has changed (if any). For change
details, see the revision history of any revised document.
Errata
MSP430F5259 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5258 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5257 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5256 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5255 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5254 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5253 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430F5252 Device Erratasheet
Describes the known exceptions to the functional specifications.
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User's Guides
MSP430F5xx and MSP430F6xx Family User's Guide
Detailed information on the modules and peripherals available in this device family.
MSP430 Flash Devices Bootloader (BSL) User's Guide
The MSP430 bootloader (BSL, formerly known as the bootstrap loader) allows users to communicate with
embedded memory in the MSP430 microcontroller during the prototyping phase, final production, and in service.
Both the programmable memory (flash memory) and the data memory (RAM) can be modified as required. Do
not confuse the bootloader with the bootstrap loader programs found in some digital signal processors (DSPs)
that automatically load program code (and data) from external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module of the
MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition,
it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This
document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the
parallel port interface and the USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators
Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the
correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations
System-Level ESD has become increasingly demanding as silicon technology scales to lower voltages and the
need for designing cost-effective and ultra-low-power components. This application report addresses three ESD
topics to help board designers and OEMs understand and design robust system-level designs: (1) Component-
level ESD testing and system-level ESD testing; (2) General design guidelines for system-level ESD protection;
(3) Introduction to System Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD
protection.
Designing With MSP430F522x and MSP430F521x Devices
The MSP430F522x and MSP430F521x devices support a split supply I/O system that is essential in systems in
which the MCU is required to interface with external devices (such as sensors or other processors) that operate
at different voltage level compared to the MCU device supply. Additionally, the split supply input voltage range of
the F522x and F521x devices starts as low as 1.62 V (see the device data sheet specifications), and this allows
for nominal 1.8-V I/O interface without the need for external level translation. This application report describes
the various design considerations to keep in mind while designing the F522x and F521x devices in an
application.
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10.5 Related Links
表 10-2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
表10-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
MSP430F5259
MSP430F5258
MSP430F5257
MSP430F5256
MSP430F5255
MSP430F5254
MSP430F5253
MSP430F5252
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
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Click here
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Click here
Click here
Click here
Click here
Click here
Click here
Click here
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10.6 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
10.7 Trademarks
MicroStar Junior™, MSP430™, MSP430Ware™, EnergyTrace™, ULP Advisor™, Code Composer Studio™, and TI
E2E™ are trademarks of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
所有商标均为其各自所有者的财产。
10.8 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.9 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
10.10 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
MSP430F5252IRGCR
MSP430F5252IRGCT
MSP430F5253IRGCR
MSP430F5253IRGCT
MSP430F5254IRGCR
MSP430F5254IRGCT
MSP430F5255IRGCR
MSP430F5255IRGCT
MSP430F5256IRGCR
MSP430F5256IRGCT
MSP430F5257IRGCR
MSP430F5257IRGCT
MSP430F5258IRGCR
MSP430F5258IRGCT
MSP430F5259IRGCR
MSP430F5259IRGCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
F5252
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F5252
F5253
F5253
F5254
F5254
F5255
F5255
F5256
F5256
F5257
F5257
F5258
F5258
F5259
F5259
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2021
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F5252IRGCR
MSP430F5252IRGCT
MSP430F5253IRGCR
MSP430F5253IRGCT
MSP430F5254IRGCR
MSP430F5254IRGCT
MSP430F5255IRGCR
MSP430F5255IRGCT
MSP430F5256IRGCR
MSP430F5256IRGCT
MSP430F5257IRGCR
MSP430F5257IRGCT
MSP430F5258IRGCR
MSP430F5258IRGCT
MSP430F5259IRGCR
MSP430F5259IRGCT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
2000
250
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
330.0
180.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
2000
250
2000
250
2000
250
2000
250
2000
250
2000
250
2000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430F5252IRGCR
MSP430F5252IRGCT
MSP430F5253IRGCR
MSP430F5253IRGCT
MSP430F5254IRGCR
MSP430F5254IRGCT
MSP430F5255IRGCR
MSP430F5255IRGCT
MSP430F5256IRGCR
MSP430F5256IRGCT
MSP430F5257IRGCR
MSP430F5257IRGCT
MSP430F5258IRGCR
MSP430F5258IRGCT
MSP430F5259IRGCR
MSP430F5259IRGCT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
2000
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
367.0
185.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
2000
250
2000
250
2000
250
2000
250
2000
250
2000
250
2000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064B
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.15
8.85
A
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
4.25 0.1
60X
0.5
1
48
0.30
0.18
64X
49
64
PIN 1 ID
0.1
C A B
0.5
0.3
64X
0.05
4219010/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.25)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.18) TYP
(8.8)
65
SYMM
(0.695) TYP
(
0.2) TYP
VIA
33
16
32
17
(0.695) TYP
(1.18) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219010/A 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
9X ( 1.19)
65
SYMM
(8.8)
(1.39)
33
16
17
32
(1.39)
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219010/A 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2021,德州仪器 (TI) 公司
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