MSP430F2234TRHA [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430F2234TRHA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总87页 (文件大小：1774K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
D
D
Low Supply Voltage Range 1.8 V to 3.6 V
D
Two Configurable Operational Amplifiers
(MSP430x22x4 only)
Ultralow-Power Consumption
− Active Mode: 270 µA at 1 MHz, 2.2 V
− Standby Mode: 0.7 µA
− Off Mode (RAM Retention): 0.1 µA
Ultrafast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5 ns
Instruction Cycle Time
D
Brownout Detector
D
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
D
D
D
D
D
D
Bootstrap Loader
On Chip Emulation Module
Basic Clock Module Configurations:
− Internal Frequencies up to 16MHz With
Four Calibrated Frequencies to 1%
− Internal Very Low Power LF Oscillator
− 32-kHz Crystal
− High-Frequency Crystal up to 16 MHz
− Resonator
− External Digital Clock Source
− External resistor
Family Members Include:
MSP430F2232: 8KB + 256B Flash Memory
512B RAM
MSP430F2252: 16KB + 256B Flash Memory
512B RAM
MSP430F2272: 32KB + 256B Flash Memory
1KB RAM
MSP430F2234: 8KB + 256B Flash Memory
512B RAM
D
D
D
16-Bit Timer_A With Three
Capture/Compare Registers
MSP430F2254: 16KB + 256B Flash Memory
512B RAM
MSP430F2274: 32KB + 256B Flash Memory
1KB RAM
Available in a 38-Pin Plastic Small-Outline
Thin (TSSOP) Package and 40-Pin QFN
Package
For Complete Module Descriptions, Refer
to the MSP430x2xx Family User’s Guide
16-Bit Timer_B With Three
Capture/Compare Registers
Universal Serial Communication Interface
− Enhanced UART supporting
Auto-Baudrate Detection (LIN)
− IrDA Encoder and Decoder
− Synchronous SPI
D
− I2Ct
D
10-Bit, 200-ksps A/D Converter With
Internal Reference, Sample-and-Hold,
Autoscan, and Data Transfer Controller
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1 µs.
The MSP430x22xx series is an ultralow-power mixed signal microcontroller with two built-in 16-bit timers, a
universal serial communication interface, 10-bit A/D converter with integrated reference and data transfer
controller (DTC), two general purpose operational amplifiers in the MSP430x22x4 devices, and 32 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢂꢒ ꢓ ꢌꢕ ꢑ ꢔꢉ ꢓ ꢎ ꢌ ꢏꢔꢏ ꢖꢗ ꢘ ꢙꢚ ꢛ ꢜꢝ ꢖꢙꢗ ꢖꢞ ꢟꢠ ꢚ ꢚ ꢡꢗꢝ ꢜꢞ ꢙꢘ ꢢꢠꢣ ꢤꢖꢟ ꢜꢝ ꢖꢙꢗ ꢥꢜ ꢝꢡ ꢦ
ꢂꢚ ꢙ ꢥꢠꢟ ꢝ ꢞ ꢟ ꢙꢗ ꢘꢙ ꢚ ꢛ ꢝ ꢙ ꢞ ꢢꢡ ꢟ ꢖꢘ ꢖꢟꢜ ꢝꢖ ꢙꢗꢞ ꢢꢡ ꢚ ꢝꢧ ꢡ ꢝꢡ ꢚ ꢛꢞ ꢙꢘ ꢔꢡꢆ ꢜꢞ ꢉꢗꢞ ꢝꢚ ꢠꢛ ꢡꢗꢝ ꢞ
ꢞ ꢝ ꢜ ꢗꢥ ꢜ ꢚꢥ ꢨ ꢜ ꢚꢚ ꢜ ꢗ ꢝꢩꢦ ꢂꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙꢗ ꢢꢚ ꢙꢟ ꢡꢞ ꢞꢖ ꢗꢪ ꢥꢙꢡ ꢞ ꢗꢙꢝ ꢗꢡ ꢟꢡ ꢞꢞ ꢜꢚ ꢖꢤ ꢩ ꢖꢗꢟ ꢤꢠꢥ ꢡ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢪ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ
Copyright 2006 Texas Instruments Incorporated
1
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
38-PIN TSSOP
(DA)
PLASTIC
40-PIN QFN
(RHA)
T
A
MSP430F2232IDA
MSP430F2252IDA
MSP430F2272IDA
MSP430F2234IDA
MSP430F2254IDA
MSP430F2274IDA
MSP430F2232IRHA
MSP430F2252IRHA
MSP430F2272IRHA
MSP430F2234IRHA
MSP430F2254IRHA
MSP430F2274IRHA
−40°C to 85°C
−40°C to 105°C
†
†
MSP430F2232TRHA
MSP430F2232TDA
†
†
MSP430F2252TDA
MSP430F2252TRHA
†
†
MSP430F2272TDA
MSP430F2234TDA
MSP430F2254TDA
MSP430F2274TDA
MSP430F2272TRHA
MSP430F2234TRHA
MSP430F2254TRHA
MSP430F2274TRHA
†
Product Preview
2
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
MSP430x22x2 device pinout, DA package
TEST/SBWTCK
DVCC
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P1.7/TA 2/TDO /TDI
P1.6/TA 1/TDI
2
P2.5/Rosc
3
P1.5/TA 0/TMS
DVSS
4
P1.4/SMCLK /TCK
P1.3/TA 2
XOUT /P2.7
5
XIN /P2.6
6
P1.2/TA 1
RST /NMI /SBWTDIO
P2.0/ACLK /A0
P2.1/TAINCLK /SMCLK /A1
P2.2/TA 0/A2
7
P1.1/TA 0
8
P1.0/TACLK /ADC 10CLK
P2.4/TA 2/A4/VREF +/VeREF +
P2.3/TA 1/A3/VREF −/VeREF −
P3.7/A7
9
10
11
12
13
14
15
16
17
18
19
P3.0/UCB 0STE /UCA 0CLK /A5
P3.1/UCB 0SIMO /UCB 0SDA
P3.2/UCB 0SOMI /UCB 0SCL
P3.3/UCB 0CLK /UCA 0STE
AVSS
P3.6/A6
P3.5/UCA 0RXD /UCA 0SOMI
P3.4/UCA 0TXD /UCA 0SIMO
P4.7/TBCLK
AVCC
P4.6/TBOUTH /A15
P4.5/TB2/A14
P4.0/TB0
P4.1/TB1
P4.4/TB1/A13
P4.2/TB2
P4.3/TB0/A12
MSP430x22x4 device pinout, DA package
TEST /SBWTCK
DVCC
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P1.7/TA 2/TDO /TDI
P1.6/TA 1/TDI
2
P2.5/Rosc
3
P1.5/TA 0/TMS
DVSS
4
P1.4/SMCLK /TCK
XOUT /P2.7
5
P1.3/TA 2
XIN /P2.6
6
P1.2/TA 1
RST /NMI /SBWTDIO
P2.0/ACLK /A0/OA0I0
P2.1/TAINCLK /SMCLK /A1/OA0O
P2.2/TA 0/A2/OA0I1
P3.0/UCB 0STE /UCA 0CLK /A5
P3.1/UCB 0SIMO /UCB 0SDA
P3.2/UCB 0SOMI /UCB 0SCL
P3.3/UCB 0CLK /UCA 0STE
AVSS
7
P1.1/TA 0
8
P1.0/TACLK /ADC 10CLK
P2.4/TA 2/A4/VREF +/VeREF +/OA1I0
P2.3/TA 1/A3/VREF −/VeREF −/OA1I1/OA1O
P3.7/A7/OA1I2
9
10
11
12
13
14
15
16
17
18
19
P3.6/A6/OA0I2
P3.5/UCA 0RXD /UCA 0SOMI
P3.4/UCA 0TXD /UCA 0SIMO
P4.7/TBCLK
AVCC
P4.6/TBOUTH /A15/OA1I3
P4.5/TB2/A14/OA0I3
P4.4/TB1/A13/OA1O
P4.3/TB0/A12/OA0O
P4.0/TB0
P4.1/TB1
P4.2/TB2
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
MSP430x22x2 device pinout, RHA package
39 38 37 36 35 34 33 32
DVSS
XOUT /P2.7
1
2
3
4
5
6
7
8
9
30 P1.1/TA 0
29 P1.0/TACLK /ADC 10CLK
28 P2.4/TA 2/A4/VREF +/VeREF +
27 P2.3/TA 1/A3/VREF −/VeREF −
26 P3.7/A7
XIN /P2.6
DVSS
RST /NMI /SBWTDIO
P2.0/ACLK /A0
25 P3.6/A6
P2.1/TAINCLK /SMCLK /A1
P2.2/TA 0/A2
24 P3.5/UCA 0RXD /UCA 0SOMI
23 P3.4/UCA 0TXD /UCA 0SIMO
22 P4.7/TBCLK
P3.0/UCB 0STE /UCA 0CLK /A5
P3.1/UCB 0SIMO /UCB 0SDA 10
21 P4.6/TBOUTH /A15
12 13 14 15 16 17 18 19
4
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
MSP430x22x4 device pinout, RHA package
39 38 37 36 35 34 33 32
DVSS
XOUT /P2.7
1
2
3
4
5
6
7
8
9
30 P1.1/TA 0
29 P1.0/TACLK /ADC 10CLK
28 P2.4/TA 2/A4/VREF +/VeREF +/OA1I0
27 P2.3/TA 1/A3/VREF −/VeREF −/OA1I1/OA1O
26 P3.7/A7/OA1I2
XIN /P2.6
DVSS
RST /NMI /SBWTDIO
P2.0/ACLK /A0/OA0I0
P2.1/TAINCLK /SMCLK /A1/OA0O
P2.2/TA 0/A2/OA0I1
P3.0/UCB 0STE /UCA 0CLK /A5
25 P3.6/A6/OA0I2
24 P3.5/UCA 0RXD /UCA 0SOMI
23 P3.4/UCA 0TXD /UCA 0SIMO
22 P4.7/TBCLK
P3.1/UCB 0SIMO /UCB 0SDA 10
21 P4.6/TBOUTH /A15/OA1I3
12 13 14 15 16 17 18 19
5
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
MSP430x22x2 functional block diagram
VCC
VSS
P1.x/P2.x
2x8
P3.x/P4.x
2x8
XIN
XOUT
ADC10
10−Bit
Ports P1/P2
ACLK
Flash
RAM
Ports P3/P4
Basic Clock
System+
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
SMCLK
32kB
16kB
8kB
1kB
512B
512B
12
2x8 I/O
pull−up/down
resistors
Channels,
Autoscan,
DTC
MCLK
MAB
16MHz
CPU
incl. 16
Registers
MDB
Emulation
(2BP)
Timer_B3
USCI_A0:
UART/LIN,
IrDA, SPI
Watchdog
WDT+
Timer_A3
JTAG
Interface
Brownout
Protection
3 CC
Registers,
Shadow
Reg
3 CC
Registers
USCI_B0:
SPI, I2C
15/16−Bit
Spy−Bi Wire
RST/NMI
NOTE: See port schematics section for detailed I/O information.
MSP430x22x4 functional block diagram
VCC
VSS
P1.x/P2.x
2x8
P3.x/P4.x
2x8
XIN
XOUT
ADC10
10−Bit
Ports P1/P2
ACLK
Flash
RAM
Ports P3/P4
Basic Clock
System+
OA0, OA1
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
SMCLK
32kB
16kB
8kB
1kB
512B
512B
12
2x8 I/O
pull−up/down
resistors
Channels,
Autoscan,
DTC
2 Op Amps
MCLK
MAB
16MHz
CPU
incl. 16
Registers
MDB
Emulation
(2BP)
Timer_B3
USCI_A0:
UART/LIN,
IrDA, SPI
Watchdog
WDT+
Timer_A3
JTAG
Interface
Brownout
Protection
3 CC
Registers,
Shadow
Reg
3 CC
Registers
USCI_B0:
SPI, I2C
15/16−Bit
Spy−Bi Wire
RST/NMI
NOTE: See port schematics section for detailed I/O information.
6
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Terminal Functions, MSP430x22x2
TERMINAL
DA
RHA
NO.
29
DESCRIPTION
NAME
P1.0/TACLK/
I/O
NO.
31
I/O General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ADC10, conversion clock
ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
32
33
34
35
36
37
38
8
30
31
32
33
34
35
36
6
I/O General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit
I/O General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: OUT1 output
I/O General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
P1.4/SMCLK/
TCK
I/O General-purpose digital I/O pin / SMCLK signal output
Test Clock input for device programming and test
P1.5/TA0/
TMS
I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
P1.6/TA1/
TDI/TCLK
I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
P1.7/TA2/
I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
†
TDO/TDI
P2.0/ACLK/A0
I/O General-purpose digital I/O pin / ACLK output
ADC10, analog input A0
P2.1/TAINCLK/SMCLK/A1
9
7
I/O General-purpose digital I/O pin
Timer_A, clock signal at INCLK, SMCLK signal output
ADC10, analog input A1
P2.2/TA0/A2
P2.3/TA1/
10
29
8
I/O General-purpose digital I/O pin
Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
ADC10, analog input A2
27
I/O General-purpose digital I/O pin
A3/V
/V
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3 / negative reference voltage output/input
REF− eREF−
P2.4/TA2/
A4/V
30
3
28
40
3
I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output
ADC10, analog input A4 / positive reference voltage output/input
/V
REF+ eREF+
P2.5/
I/O General-purpose digital I/O pin
R
Input for external DCO resistor to define DCO frequency
OSC
XIN/P2.6
6
I/O Input terminal of crystal oscillator
General-purpose digital I/O pin
XOUT/P2.7
5
2
I/O Output terminal of crystal oscillator
General-purpose digital I/O pin
P3.0/
11
9
I/O General-purpose digital I/O pin
UCB0STE/UCA0CLK/
A5
USCI_B0 slave transmit enable / USCI_A0 clock input/output
ADC10, analog input A5
P3.1/
12
13
14
25
10
11
12
23
I/O General-purpose digital I/O pin
2
2
UCB0SIMO/UCB0SDA
USCI_B0 slave in/master out in SPI mode, SDA I C data in I C mode
P3.2/
I/O General-purpose digital I/O pin
2
2
UCB0SOMI/UCB0SCL
USCI_B0 slave out/master in in SPI mode, SCL I C clock in I C mode
P3.3/
I/O General-purpose digital I/O pin
UCB0CLK/UCA0STE
USCI_B0 clock input/output / USCI_A0 slave transmit enable
P3.4/
I/O General-purpose digital I/O pin
UCA0TXD/UCA0SIMO
USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode
7
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Terminal Functions, MSP430x22x2 (Continued)
TERMINAL
DA
NO.
26
RHA
NO.
24
DESCRIPTION
NAME
I/O
P3.5/
I/O General-purpose digital I/O pin
UCA0RXD/UCA0SOMI
USCI_A0 receive data input in UART mode, slave out/master in in SPI mode
P3.6/A6
27
28
17
18
19
20
25
26
15
16
17
18
I/O General-purpose digital I/O pin
ADC10 analog input A6
P3.7/A7
I/O General-purpose digital I/O pin
ADC10 analog input A7
P4.0/TB0
P4.1/TB1
P4.2/TB2
I/O General-purpose digital I/O pin
Timer_B, capture: CCI0A input, compare: OUT0 output
I/O General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
I/O General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
P4.3/TB0/
A12
I/O General-purpose digital I/O pin
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
P4.4/TB1
A13
21
22
23
19
20
21
I/O General-purpose digital I/O pin
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
P4.5/TB2
A14
I/O General-purpose digital I/O pin
Timer_B, compare: OUT2 output
ADC10 analog input A14
P4.6/TBOUTH
A15
I/O General-purpose digital I/O pin
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15
P4.7/TBCLK
24
7
22
5
I/O General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
RST/NMI/SBWTDIO
TEST/SBWTCK
I
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
1
37
I
Selects test mode for JTAG pins on Port1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DV
2
16
4
38, 39
14
Digital supply voltage
Analog supply voltage
Digital ground reference
Analog ground reference
CC
AV
DV
CC
1, 4
13
SS
SS
AV
15
NA
QFN Pad
Package
Pad
NA QFN package pad; connection to DV recommended.
SS
†
TDO or TDI is selected via JTAG instruction.
NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver
connection to this pad after reset.
8
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Terminal Functions, MSP430x22x4
TERMINAL
DA
RHA
NO.
29
DESCRIPTION
NAME
P1.0/TACLK/
I/O
NO.
31
I/O General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ADC10, conversion clock
ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
32
33
34
35
36
37
38
8
30
31
32
33
34
35
36
6
I/O General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit
I/O General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: OUT1 output
I/O General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
P1.4/SMCLK/
TCK
I/O General-purpose digital I/O pin / SMCLK signal output
Test Clock input for device programming and test
P1.5/TA0/
TMS
I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
P1.6/TA1/
TDI/TCLK
I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
P1.7/TA2/
I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
†
TDO/TDI
P2.0/ACLK/A0/OA0I0
I/O General-purpose digital I/O pin / ACLK output
ADC10, analog input A0 / OA0, analog input I0
P2.1/TAINCLK/SMCLK/
A1/OA0O
9
7
I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLK
SMCLK signal output
ADC10, analog input A1 / OA0, analog output
P2.2/TA0/
A2/OA0I1
10
29
8
I/O General-purpose digital I/O pin
Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output
ADC10, analog input A2 / OA0, analog input I1
P2.3/TA1/
27
I/O General-purpose digital I/O pin
A3/V
/OA1I1/OA1O
/V
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3 / negative reference voltage output/input
OA1, analog input I1 / OA1, analog output
REF− eREF−
P2.4/TA2/
30
28
I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output
ADC10, analog input A4 / positive reference voltage output/input
OA1, analog input I0
A4/V
/V
REF+ eREF+
/OA1I0
P2.5/
3
6
40
3
I/O General-purpose digital I/O pin
R
Input for external DCO resistor to define DCO frequency
OSC
XIN/P2.6
I/O Input terminal of crystal oscillator
General-purpose digital I/O pin
XOUT/P2.7
5
2
I/O Output terminal of crystal oscillator
General-purpose digital I/O pin
P3.0/
11
9
I/O General-purpose digital I/O pin
UCB0STE/UCA0CLK/
A5
USCI_B0 slave transmit enable / USCI_A0 clock input/output
ADC10, analog input A5
P3.1/
12
13
14
25
10
11
12
23
I/O General-purpose digital I/O pin
2
2
UCB0SIMO/UCB0SDA
USCI_B0 slave in/master out in SPI mode, SDA I C data in I C mode
P3.2/
I/O General-purpose digital I/O pin
2
2
UCB01SOMI/UCB0SCL
USCI_B0 slave out/master in in SPI mode, SCL I C clock in I C mode
P3.3/
I/O General-purpose digital I/O pin
UCB0CLK/UCA0STE
USCI_B0 clock input/output / USCI_A0 slave transmit enable
P3.4/
I/O General-purpose digital I/O pin
UCA0TXD/UCA0SIMO
USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode
9
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Terminal Functions, MSP430x22x4 (Continued)
TERMINAL
DA
NO.
26
RHA
NO.
24
DESCRIPTION
NAME
I/O
P3.5/
I/O General-purpose digital I/O pin
UCA0RXD/UCA0SOMI
USCI_A0 receive data input in UART mode, slave out/master in in SPI mode
P3.6/A6/OA0I2
27
28
17
18
19
20
25
26
15
16
17
18
I/O General-purpose digital I/O pin
ADC10 analog input A6 / OA0 analog input I2
P3.7/A7/OA1I2
P4.0/TB0
I/O General-purpose digital I/O pin
ADC10 analog input A7 / OA1 analog input I2
I/O General-purpose digital I/O pin
Timer_B, capture: CCI0A input, compare: OUT0 output
P4.1/TB1
I/O General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
P4.2/TB2
I/O General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
P4.3/TB0/
A12/OA0O
I/O General-purpose digital I/O pin
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12 / OA0 analog output
P4.4/TB1
A13/OA1O
21
22
23
19
20
21
I/O General-purpose digital I/O pin
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13 / OA1 analog output
P4.5/TB2
A14/OA0I3
I/O General-purpose digital I/O pin
Timer_B, compare: OUT2 output
ADC10 analog input A14 / OA0 analog input I3
P4.6/TBOUTH
A15/OA1I3
I/O General-purpose digital I/O pin
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15 / OA1 analog input I3
P4.7/TBCLK
24
7
22
5
I/O General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
RST/NMI/SBWTDIO
TEST/SBWTCK
I
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
1
37
I
Selects test mode for JTAG pins on Port1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DV
2
16
4
38, 39
14
Digital supply voltage
Analog supply voltage
Digital ground reference
Analog ground reference
CC
AV
DV
CC
1, 4
13
SS
SS
AV
15
NA
QFN Pad
Package
Pad
NA QFN package pad connection to DV recommended.
SS
†
TDO or TDI is selected via JTAG instruction.
NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver
connection to this pad after reset.
10
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g., ADD R4,R5
R4 + R5 −−−> R5
e.g., CALL
e.g., JNE
R8
PC −−> (TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
F
F
F
F
F
F
F
F
F
MOV Rs,Rd
R10 −−> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
M(MEM) −−> M(TCDAT)
M(R10) −−> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) −−> R11
R10 + 2−−> R10
F
F
MOV @Rn+,Rm
Immediate
MOV #X,TONI
#45 −−> M(TONI)
NOTE: S = source
D = destination
11
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
D
Active mode AM;
All clocks are active
Low-power mode 0 (LPM0);
−
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D
D
Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
12
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will
go into LPM4 immediately after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
PORIFG
RSTIFG
WDTIFG
KEYV
Reset
0FFFEh
31, highest
Flash key violation
PC out-of-range (see Note 1)
(see Note 2)
NMIIFG
OFIFG
ACCVIFG
NMI
Oscillator fault
Flash memory access violation
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
(see Notes 2 & 4)
Timer_B3
Timer_B3
TBCCR0 CCIFG (see Note 3)
maskable
maskable
0FFFAh
0FFF8h
29
28
TBCCR1 and TBCCR2
CCIFGs, TBIFG
(see Notes 2 & 3)
0FFF6h
0FFF4h
0FFF2h
27
26
25
Watchdog Timer
Timer_A3
WDTIFG
maskable
maskable
TACCR0 CCIFG (see Note 3)
TACCR1 CCIFG.
TACCR2 CCIFG
TAIFG (see Notes 2 & 3)
Timer_A3
maskable
maskable
0FFF0h
24
UCA0RXIFG, UCB0RXIFG
(see Notes 2)
USCI_A0/USCI_B0 Receive
0FFEEh
0FFECh
23
22
UCA0TXIFG, UCB0TXIFG
(see Notes 2)
USCI_A0/USCI_B0 Transmit
ADC10
maskable
maskable
ADC10IFG (see Note 3)
0FFEAh
0FFE8h
21
20
I/O Port P2
(eight flags)
P2IFG.0 to P2IFG.7
(see Notes 2 & 3)
maskable
maskable
0FFE6h
0FFE4h
19
18
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 & 3)
0FFE2h
0FFE0h
17
16
(see Note 5)
(see Note 6)
0FFDEh
15
0FFDCh ... 0FFC0h
14 ... 0, lowest
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from
within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
5. This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
13
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
Address
00h
7
6
5
4
3
2
1
0
ACCVIE
rw−0
NMIIE
rw−0
OFIE
rw−0
WDTIE
rw−0
WDTIE
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured
in interval timer mode.
OFIE
Oscillator fault enable
NMIIE
ACCVIE
(Non)maskable interrupt enable
Flash access violation interrupt enable
Address
01h
7
6
5
4
3
2
1
0
UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw−0 rw−0 rw−0 rw−0
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
USCI_A0 receive-interrupt enable
USCI_A0 transmit-interrupt enable
USCI_B0 receive-interrupt enable
USCI_B0 transmit-interrupt enable
14
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ꢀ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
interrupt flag register 1 and 2
Address
02h
7
6
5
4
3
2
1
0
NMIIFG
rw−0
RSTIFG
rw−(0)
PORIFG
rw−(1)
OFIFG
rw−1
WDTIFG
rw−(0)
WDTIFG
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on V power-up or a reset condition at RST/NMI pin in reset mode.
CC
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V
OFIFG
RSTIFG
PORIFG
NMIIFG
power-up
CC
Power-On interrupt flag. Set on V
power-up.
CC
Set via RST/NMI-pin
Address
03h
7
6
5
4
3
2
1
0
UCB0
TXIFG
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
rw−1
rw−0
rw−1
rw−0
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
USCI_A0 receive-interrupt flag
USCI_A0 transmit-interrupt flag
USCI_B0 receive-interrupt flag
USCI_B0 transmit-interrupt flag
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
15
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
memory organization
MSP430F223x
MSP430F225x
MSP430F227x
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
8KB Flash
0FFFFh−0FFC0h
0FFFFh−0E000h
16KB Flash
0FFFFh−0FFC0h
0FFFFh−0C000h
32KB Flash
0FFFFh−0FFC0h
0FFFFh−08000h
Information memory
Boot memory
RAM
Size
Flash
256 Byte
010FFh−01000h
256 Byte
010FFh−01000h
256 Byte
010FFh−01000h
Size
ROM
1KB
0FFFh−0C00h
1KB
0FFFh−0C00h
1KB
0FFFh−0C00h
Size
512 Byte
512 Byte
1KB
03FFh−0200h
03FFh−0200h
05FFh−0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh−0100h
0FFh−010h
0Fh−00h
01FFh−0100h
0FFh−010h
0Fh−00h
01FFh−0100h
0FFh−010h
0Fh−00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the application report, Features of the
MSP430 Bootstrap Loader, TI literature number SLAA089.
BSL Function
Data Transmit
Data Receive
DA Package Pins
32 − P1.1
RHA Package Pins
30 − P1.1
10 − P2.2
8 − P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0−n.
Segments A to D are also called information memory.
D
Segment A contains calibration data. After reset, segment A is protected against programming or erasing.
It can be unlocked, but care should be taken not to erase this segment if the calibration data is required.
16
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very low power, low frequency oscillator, an internal digitally-controlled oscillator (DCO),
and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both
low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and
stabilizes in less than 1 µs. The basic clock module provides the following clock signals:
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or the internal very
low power LF oscillator.
D
Main clock (MCLK), the system clock used by the CPU.
D
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO Calibration Data (provided from factory in flash info memory segment A, see Note)
DCO Frequency
Calibration Register
CALBC1_1MHZ
CALDCO_1MHZ
CALBC1_8MHZ
CALDCO_8MHZ
CALBC1_12MHZ
CALDCO_12MHZ
CALBC1_16MHZ
CALDCO_16MHZ
Size
byte
byte
byte
byte
byte
byte
byte
byte
Address
010FFh
010FEh
010FDh
010FCh
010FBh
010FAh
010F9h
010F8h
1 MHz
8 MHz
12 MHz
16 MHz
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pullup/pulldown resistor.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
17
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input
Pin Number
Device
Input Signal
Module
Input Name
Module
Block
Module
Output Signal
Output
Pin Number
DA
RHA
DA
RHA
31 - P1.0
29 - P1.0
TACLK
ACLK
TACLK
ACLK
Timer
CCR0
CCR1
CCR2
NA
TA0
TA1
TA2
SMCLK
TAINCLK
TA0
SMCLK
INCLK
CCI0A
CCI0B
GND
9 - P2.1
32 - P1.1
10 - P2.2
7 - P2.1
30 - P1.1
8 - P2.2
32 - P1.1
10 - P2.2
36 - P1.5
30 - P1.1
8 - P2.2
TA0
V
SS
34 - P1.5
V
CC
V
CC
33 - P1.2
29 - P2.3
31 - P1.2
27 - P2.3
TA1
TA1
CCI1A
CCI1B
GND
33 - P1.2
29 - P2.3
37 - P1.6
31 - P1.2
27 - P2.3
35 - P1.6
V
SS
V
CC
V
CC
34 - P1.3
32 - P1.3
TA2
CCI2A
CCI2B
GND
34 - P1.3
30 - P2.4
38 - P1.7
32 - P1.3
28 - P2.4
36 - P1.7
ACLK (internal)
V
SS
V
CC
V
CC
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B3 Signal Connections
Input
Pin Number
Device
Input Signal
Module
Input Name
Module
Block
Module
Output Signal
Output
Pin Number
DA
RHA
DA
RHA
24 - P4.7
22 - P4.7
TBCLK
ACLK
SMCLK
TBCLK
TB0
TBCLK
ACLK
Timer
CCR0
CCR1
CCR2
NA
SMCLK
INCLK
CCI0A
CCI0B
GND
24 - P4.7
17 - P4.0
20 - P4.3
22 - P4.7
15 - P4.0
18 - P4.3
17 - P4.0
20 - P4.3
15 - P4.0
18 - P4.3
TB0
TB0
TB1
TB2
V
SS
V
V
CC
CC
18 - P4.1
21 - P4.4
16 - P4.1
19 - P4.4
TB1
TB1
CCI1A
CCI1B
GND
18 - P4.1
21 - P4.4
16 - P4.1
19 - P4.4
V
SS
V
CC
V
CC
19 - P4.2
17 - P4.2
TB2
CCI2A
CCI2B
GND
19 - P4.2
22 - P4.5
17 - P4.2
20 - P4.5
ACLK (internal)
V
SS
V
CC
V
CC
USCI
The universal serial communication interface (USCI) module is used for serial data communication. The USCI
module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous
communication protocols like UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
19
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.
operational amplifier OA (MSP430x22x4 only)
The MSP430x22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offer a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
OA0 Signal Connections
Analog Input
Pin Number
Device Input Signal
Module Input Name
DA
RHA
6 - A0
8 - A0
OA0I0
OA0I1
OA0I1
OA0I2
OA0I3
OAxI0
OA0I1
OAxI1
OAxIA
OAxIB
10 - A2
10 - A2
27 - A6
22 - A14
8 - A2
8 - A2
25 - A6
20 - A14
OA1 Signal Connections
Analog Input
Pin Number
Device Input Signal
Module Input Name
DA
RHA
28 - A4
8 - A2
30 - A4
10 - A2
29 - A3
28 - A7
23 - A15
OA1I0
OA0I1
OA1I1
OA1I2
OA1I3
OAxI0
OA0I1
OAxI1
OAxIA
OAxIB
27 - A3
26 - A7
21 - A15
20
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
peripheral file map
PERIPHERALS WITH WORD ACCESS
ADC10
ADC data transfer start address
ADC memory
ADC control register 1
ADC control register 0
ADC analog enable 0
ADC analog enable 1
ADC data transfer control register 1
ADC data transfer control register 0
ADC10SA
1BCh
1B4h
1B2h
1B0h
04Ah
04Bh
049h
048h
ADC10MEM
ADC10CTL1
ADC10CTL0
ADC10AE0
ADC10AE1
ADC10DTC1
ADC10DTC0
Timer_B
Capture/compare register
Capture/compare register
Capture/compare register
Timer_B register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_B control
TBCCR2
TBCCR1
TBCCR0
TBR
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
0196h
0194h
0192h
0190h
0186h
0184h
0182h
0180h
011Eh
Timer_B interrupt vector
TBIV
Timer_A
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TACTL
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
Timer_A interrupt vector
TAIV
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog Timer+
Watchdog/timer control
WDTCTL
0120h
PERIPHERALS WITH BYTE ACCESS
OA1 (MSP430x22x4 only)
OA0 (MSP430x22x4 only)
USCI_B0
Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 1
OA1CTL1
OA1CTL0
0C3h
0C2h
Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 1
OA0CTL1
OA0CTL0
0C1h
0C0h
USCI_B0 transmit buffer
USCI_B0 receive buffer
USCI_B0 status
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
USCI_B0 I2C slave address
USCI_B0 I2C own address
UCB0TXBUF
UCB0RXBUF 06Eh
06Fh
UCB0STAT
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
06Dh
06Bh
06Ah
069h
068h
011Ah
0118h
UCB0OA
USCI_A0
USCI_A0 transmit buffer
USCI_A0 receive buffer
USCI_A0 status
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
UCA0TXBUF
UCA0RXBUF 066h
067h
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
065h
064h
063h
062h
061h
060h
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
UCA0IRRCTL 05Fh
UCA0IRTCTL 05Eh
UCA0ABCTL
05Dh
21
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SLAS504A − JULY 2006 − REVISED DECEMBER 2006
PERIPHERALS WITH BYTE ACCESS (continued)
Basic Clock System+
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P4
Port P3
Port P2
Port P4 resistor enable
Port P4 selection
Port P4 direction
Port P4 output
P4REN
P4SEL
P4DIR
P4OUT
P4IN
011h
01Fh
01Eh
01Dh
01Ch
Port P4 input
Port P3 resistor enable
Port P3 selection
Port P3 direction
Port P3 output
P3REN
P3SEL
P3DIR
P3OUT
P3IN
010h
01Bh
01Ah
019h
018h
Port P3 input
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P2 output
Port P2 input
Port P1
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Port P1 output
Port P1 input
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
003h
002h
001h
000h
IE1
22
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
absolute maximum ratings (see Note 1)
Voltage applied at V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
CC
SS
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
CC
Storage temperature, T (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
Storage temperature, T (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 105°C
stg
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage
SS
FB
is applied to the TEST pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
MIN
1.8
NOM
MAX
3.6
UNIT
V
Supply voltage during program execution, V
CC
Supply voltage during program/erase flash memory, V
CC
2.2
3.6
V
Supply voltage, V
SS
0
V
I Version
T Version
−40
−40
85
°C
°C
Operating free-air temperature range, T
A
105
V
= 1.8 V,
CC
Duty Cycle = 50% 10%
dc
dc
dc
4.15
12
Processor frequency f
SYSTEM
(see Notes 1, 2 and Figure 1)
(Maximum MCLK frequency)
V
= 2.7 V,
CC
Duty Cycle = 50% 10%
MHz
V
≥ 3.3 V,
CC
Duty Cycle = 50% 10%
16
NOTES: 1. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data
sheet.
Legend:
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage −V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V
of 2.2 V.
CC
Figure 1. Operating Area
23
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into DV
+ AV ) excluding external current (see Notes 1 and 2)
CC
CC
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
f
= f
= f
= 1MHz,
DCO MCLK SMCLK
f = 32,768Hz,
ACLK
2.2 V
270
390
µA
Program executes in flash,
Active mode (AM)
current (1MHz)
I
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
AM, 1MHz
AM, 1MHz
3 V
2.2 V
3 V
390
240
550
f
= f
= f
= 1MHz,
DCO MCLK SMCLK
f = 32,768Hz,
ACLK
Program executes in RAM,
Active mode (AM)
current (1MHz)
I
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
µA
340
5
f
f
f
= f =
= 32,768Hz/8 = 4,096Hz,
= 0Hz,
MCLK SMCLK
ACLK
DCO
-40−85°C
105°C
2.2 V
2.2 V
3 V
9
18
µA
10
Active mode (AM) Program executes in flash,
I
I
AM, 4kHz
current (4kHz)
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
-40−85°C
105°C
6
3 V
20
85
f
= f ≈ 100kHz,
= 0Hz,
= f
-40−85°C
105°C
2.2 V
2.2 V
3 V
60
72
MCLK SMCLK DCO(0,0)
f
ACLK
95
µA
95
Program executes in flash,
RSELx = 0, DCOx = 0,
Active mode (AM)
current (100kHz)
AM,100kHz
-40−85°C
105°C
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
3 V
105
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
24
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − active mode supply current (into DV
+ AV
)
CC
CC
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
5.0
4.0
3.0
2.0
1.0
0.0
f
f
= 16 MHz
= 12 MHz
DCO
DCO
T
= 85 °C
= 25 °C
A
T
A
V
= 3 V
CC
f
= 8 MHz
DCO
T
= 85 °C
= 25 °C
A
T
A
V
CC
= 2.2 V
f
= 1 MHz
DCO
3.5
1.5
2.0
2.5
3.0
4.0
0.0
4.0
8.0
12.0
16.0
V
CC
− Supply Voltage − V
f
DCO
− DCO Frequency − MHz
Figure 2. Active mode current vs V , T = 25°C
Figure 3. Active mode current vs DCO frequency
CC
A
25
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
low power mode supply currents (into DV
+ AV ) excluding external current (see Notes 1 and 2)
CC
CC
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
f
f
f
= 0MHz,
MCLK
= f
= 1MHz,
= 32,768Hz,
2.2 V
75
90
SMCLK DCO
Low-power mode
ACLK
I
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
µA
0 (LPM0) current,
see Note 3
LPM0, 1MHz
3 V
90
37
120
f
f
f
= 0MHz,
MCLK
2.2 V
3 V
48
µA
65
= f
SMCLK DCO(0, 0)
≈ 100kHz,
Low-power mode
0 (LPM0) current,
see Note 3
= 0Hz,
ACLK
I
I
LPM01,00kHz
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
41
22
f
= f
MCLK SMCLK
= 0MHz, f = 1MHz,
DCO
-40−85°C
105°C
29
2.2 V
3 V
f
= 32,768Hz,
ACLK
Low-power mode
2 (LPM2) current,
see Note 4
35
µA
32
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
LPM2
-40−85°C
25
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
105°C
-40°C
25°C
40
0.7
0.7
2.8
6
1.4
1.4
µA
4.5
2.2 V
3 V
85°C
Low-power mode
3 (LPM3) current,
see Note 4
f
= f = 0MHz,
= f
= 32,768Hz,
DCO MCLK SMCLK
105°C
-40°C
25°C
18
f
ACLK
I
LPM3,LFXT1
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
0.9
0.9
3.0
6.5
0.4
0.5
2.2
5.7
0.5
0.6
2.5
6.0
0.1
0.1
1.9
5.5
1.5
1.5
µA
5.0
85°C
105°C
-40°C
25°C
19
1.0
1.0
µA
4.2
2.2 V
3 V
85°C
Low-power mode
3 current, (LPM3)
see Note 4
f
= f = 0MHz,
= f
from internal LF oscillator (VLO),
DCO MCLK SMCLK
105°C
-40°C
25°C
16.5
1.2
f
ACLK
I
LPM3,VLO
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
1.2
µA
4.5
85°C
105°C
-40°C
25°C
17
0.5
0.5
f
= f = 0MHz,
= 0Hz,
= f
DCO MCLK SMCLK
Low-power mode
4 (LPM4) current,
see Note 5
f
ACLK
I
LPM4
2.2 V/3 V
µA
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
85°C
4.0
105°C
16
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs − Ports P1, P2, P3, P4, and RST/NMI
PARAMETER
TEST CONDITIONS
VCC
MIN
0.45
1.00
1.35
0.25
0.55
0.75
0.2
TYP
MAX UNIT
0.75
1.65
2.25
0.55
1.20
1.65
1.0
V
CC
V
Positive-going input threshold
voltage
2.2 V
3 V
V
IT+
V
CC
V
Negative-going input threshold
voltage
2.2 V
3 V
V
V
IT−
2.2 V
3 V
Input voltage hysteresis
V
hys
(V
IT+
− V )
IT−
0.3
1.0
For pullup: V = V
For pulldown: V = V
IN
;
IN SS
R
C
Pullup/pulldown resistor
Input Capacitance
20
35
50
kW
Pull
I
CC
V
IN
= V
SS
or V
CC
5
pF
inputs − Ports P1 and P2
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Port P1, P2: P1.x to P2.x, External
trigger puls width to set interrupt
flag, (see Note 1)
t
External interrupt timing
2.2 V/3 V
20
ns
(int)
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t
(int)
is met. It may be set even with trigger signals
shorter than t
.
(int)
leakage current − Ports P1, P2, P3 and P4
PARAMETER
TEST CONDITIONS
see Notes 1 and 2
or V applied to the corresponding pin(s), unless otherwise noted.
VCC
MIN
TYP
MAX UNIT
50 nA
I
High-impedance leakage current
2.2 V/3 V
lkg(Px.x)
NOTES: 1. The leakage current is measured with V
SS
CC
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs − Ports P1, P2, P3 and P4
PARAMETER
TEST CONDITIONS
= −1.5 mA (see Notes 1)
= −6 mA (see Notes 2)
= −1.5 mA (see Notes 1)
= −6 mA (see Notes 2)
= 1.5 mA (see Notes 1)
= 6 mA (see Notes 2)
= 1.5 mA (see Notes 1)
= 6 mA (see Notes 2)
VCC
2.2 V
2.2 V
3 V
MIN
−0.25
TYP
MAX
UNIT
I
I
I
I
I
I
I
I
V
V
CC
V
CC
V
CC
V
CC
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OLmax)
(OLmax)
(OLmax)
(OLmax)
CC
V
−0.6
High-level output
voltage
CC
−0.25
V
V
OH
OL
V
CC
3 V
V
−0.6
CC
2.2 V
2.2 V
3 V
V
V
+0.25
SS
SS
SS
SS
SS
V
V
V
V +0.6
SS
Low-level output
voltage
V
V
V
+0.25
+0.6
SS
3 V
V
SS
NOTES: 1. The maximum total current, I
voltage drop specified.
and I
, for all outputs combined, should not exceed 12 mA to hold the maximum
OHmax
OLmax
OLmax
2. The maximum total current, I
voltage drop specified.
and I
, for all outputs combined, should not exceed 48 mA to hold the maximum
OHmax
output frequency − Ports P1, P2, P3 and P4
PARAMETER
TEST CONDITIONS
P1.4/SMCLK,
= 20 pF, R = 1 kW against V /2
VCC
MIN
TYP
MAX UNIT
2.2 V
10 MHz
Port output frequency
(with load)
f
f
C
Px.y
L
L
CC
3 V
12 MHz
(see Note 1 and 2)
2.2 V
3 V
12 MHz
16 MHz
P2.0/ACLK, P1.4/SMCLK, C = 20 pF
L
(see Note 2)
Clock output frequency
Port_CLK
NOTES: 1. Alternatively a resistive divider with 2 times 2 kW between V
and V is used as load. The output is connected to the center tap
SS
CC
of the divider.
2. The output voltage reaches at least 10% and 90% V
CC
at the specified toggle frequency.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
25.0
20.0
15.0
10.0
5.0
50.0
40.0
30.0
20.0
10.0
0.0
V
CC
P4.5
= 2.2 V
T
= 25°C
V
CC
P4.5
= 3 V
A
T
= 25°C
= 85°C
A
T
= 85°C
A
T
A
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 4
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−5.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
V
= 2.2 V
CC
P4.5
V
= 3 V
CC
P4.5
−10.0
−15.0
−20.0
−25.0
T
= 85°C
A
T
A
= 85°C
T
A
= 25°C
T
= 25°C
A
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OH
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 6
Figure 7
NOTE: One output loaded at a time.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
dV /dt ≤ 3 V/s
VCC
MIN
TYP
MAX UNIT
V
V
V
(see Figure 8)
0.7 × V
V
CC(start)
CC
(B_IT−)
(see Figure 8 through Figure 10)
(see Figure 8)
dV /dt ≤ 3 V/s
1.71
210
V
(B_IT−)
hys(B_IT−)
d(BOR)
CC
dV /dt ≤ 3 V/s
70
2
130
mV
µs
CC
t
(see Figure 8)
2000
Pulse length needed at RST/NMI pin
to accepted reset internally
t
2.2 V/3 V
µs
(reset)
NOTES: 1. The current consumption of the brownout module is already included in the I
current consumption data. The voltage level
CC
V
+ V is ≤ 1.8V.
(B_IT−)
hys(B_IT−)
2. During power up, the CPU begins code execution following a period of t
after V
= V
+ V
. The default
d(BOR)
is the minimum supply voltage for the desired
CC
(B_IT−)
hys(B_IT−)
DCO settings must not be changed until V
operating frequency.
≥ V
, where V
CC(min)
CC
CC(min)
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − POR/brownout reset (BOR)
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 9. V
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
V
t
CC
pw
2
3 V
V
= 3 V
CC
Typical Conditions
1.5
1
V
CC(drop)
0.5
0
t = t
f
r
0.001
1
1000
t
t
r
f
t
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 10. V
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
CC(drop)
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D
All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D
DCO control bits DCOx have a step size as defined by parameter S
.
DCO
D
Modulation control bits MODx select how often f
is used within the period of 32 DCOCLK
DCO(RSEL,DCO+1)
cycles. The frequency f
to:
is used for the remaining cycles. The frequency is an average equal
DCO(RSEL,DCO)
32 fDCO(RSEL,DCO) fDCO(RSEL,DCO)1)
faverage
+
MOD fDCO(RSEL,DCO))(32*MOD) fDCO(RSEL,DCO)1)
DCO frequency
PARAMETER
TEST CONDITIONS
RSELx < 14
VCC
MIN
1.8
TYP
MAX UNIT
3.6
3.6
3.6
V
V
V
RSELx = 14
2.2
3.0
Vcc
Supply voltage range
RSELx = 15
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
DCO frequency (0, 0)
DCO frequency (0, 3)
DCO frequency (1, 3)
DCO frequency (2, 3)
DCO frequency (3, 3)
DCO frequency (4, 3)
DCO frequency (5, 3)
DCO frequency (6, 3)
DCO frequency (7, 3)
DCO frequency (8, 3)
DCO frequency (9, 3)
DCO frequency (10, 3)
DCO frequency (11, 3)
DCO frequency (12, 3)
DCO frequency (13, 3)
DCO frequency (14, 3)
DCO frequency (15, 3)
DCO frequency (15, 7)
Frequency step between
RSELx = 0, DCOx = 0, MODx = 0
RSELx = 0, DCOx = 3, MODx = 0
RSELx = 1, DCOx = 3, MODx = 0
RSELx = 2, DCOx = 3, MODx = 0
RSELx = 3, DCOx = 3, MODx = 0
RSELx = 4, DCOx = 3, MODx = 0
RSELx = 5, DCOx = 3, MODx = 0
RSELx = 6, DCOx = 3, MODx = 0
RSELx = 7, DCOx = 3, MODx = 0
RSELx = 8, DCOx = 3, MODx = 0
RSELx = 9, DCOx = 3, MODx = 0
RSELx = 10, DCOx = 3, MODx = 0
RSELx = 11, DCOx = 3, MODx = 0
RSELx = 12, DCOx = 3, MODx = 0
RSELx = 13, DCOx = 3, MODx = 0
RSELx = 14, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 3, MODx = 0
RSELx = 15, DCOx = 7, MODx = 0
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
3 V
0.06
0.07
0.10
0.14
0.20
0.28
0.39
0.54
0.80
1.10
1.60
2.50
3.00
4.30
6.00
8.60
12.0
16.0
0.14 MHz
0.17 MHz
0.20 MHz
0.28 MHz
0.40 MHz
0.54 MHz
0.77 MHz
1.06 MHz
1.50 MHz
2.10 MHz
3.00 MHz
4.30 MHz
5.50 MHz
7.30 MHz
9.60 MHz
13.9 MHz
18.5 MHz
26.0 MHz
DCO(0,0)
DCO(0,3)
DCO(1,3)
DCO(2,3)
DCO(3,3)
DCO(4,3)
DCO(5,3)
DCO(6,3)
DCO(7,3)
DCO(8,3)
DCO(9,3)
DCO(10,3)
DCO(11,3)
DCO(12,3)
DCO(13,3)
DCO(14,3)
DCO(15,3)
DCO(15,7)
3 V
S
S
f =
/f
/f
2.2 V/3 V
1.55
ratio
1.12
RSEL
DCO
RSDECLO(RSEL+1,DCO) DCO(RSEL,DCO)
range RSEL and RSEL+1
Frequency step between
tap DCO and DCO+1
S
S f =
DCDOCO(RSEL,DCO+1) DCO(RSEL,DCO)
2.2 V/3 V
2.2 V/3 V
1.05
40
1.08
50
Duty Cycle
Measured at P1.4/SMCLK
60
%
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies − tolerance at calibration
PARAMETER
TEST CONDITIONS
T
VCC
MIN
−1
TYP
0.2
MAX UNIT
+1
A
Frequency tolerance at calibration
25°C
3 V
%
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
f
1MHz calibration value
8MHz calibration value
25°C
3 V
3 V
3 V
3 V
0.990
7.920
11.88
15.84
1
8
1.010 MHz
8.080 MHz
CAL(1MHz)
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
f
25°C
25°C
25°C
CAL(8MHz)
BCSCTL1= CALBC1_12MHZ
12MHz calibration value DCOCTL = CALDCO_12MHZ
Gating time: 5ms
f
12 12.12 MHz
16 16.16 MHz
CAL(12MHz)
BCSCTL1= CALBC1_16MHZ
16MHz calibration value DCOCTL = CALDCO_16MHZ
Gating time: 2ms
f
CAL(16MHz)
calibrated DCO frequencies − tolerance over temperature 0°C to +85°C
PARAMETER
TEST CONDITIONS
T
VCC
3.0 V
3.0 V
3.0 V
3.0 V
2.2 V
3.0 V
3.6 V
2.2 V
3.0 V
3.6 V
2.2 V
3.0 V
3.6 V
MIN
TYP
MAX UNIT
A
1 MHz tolerance over temperature
8 MHz tolerance over temperature
12 MHz tolerance over temperature
16 MHz tolerance over temperature
0−85°C
0−85°C
0−85°C
0−85°C
−2.5
0.5
1.0
1.0
2.0
1
+2.5
+2.5
+2.5
+3.0
%
%
%
%
−2.5
−2.5
−3.0
0.970
0.975
0.970
7.760
7.800
7.600
11.70
11.70
11.70
1.030 MHz
1.025 MHz
1.030 MHz
8.400 MHz
8.200 MHz
8.240 MHz
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
1
f
1MHz calibration value
8MHz calibration value
0−85°C
0−85°C
CAL(1MHz)
1
8
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
8
f
CAL(8MHz)
8
12 12.30 MHz
12 12.30 MHz
12 12.30 MHz
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
f
12MHz calibration value
16MHz calibration value
0−85°C
0−85°C
CAL(12MHz)
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
3.0 V
3.6 V
15.52
15.00
16 16.48 MHz
16 16.48 MHz
f
CAL(16MHz)
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies − tolerance over supply voltage V
CC
PARAMETER
TEST CONDITIONS
T
VCC
MIN
−3
TYP
MAX UNIT
A
1 MHz tolerance over V
8 MHz tolerance over V
25°C
1.8 V − 3.6 V
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
2
+3
+3
+3
+3
%
%
%
%
CC
25°C
25°C
25°C
−3
−3
−6
2
2
2
CC
12 MHz tolerance over V
CC
CC
16 MHz tolerance over V
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
f
1MHz calibration value
8MHz calibration value
12MHz calibration value
16MHz calibration value
25°C
25°C
25°C
25°C
1.8 V − 3.6 V
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
0.970
7.760
11.64
15.00
1
8
1.030 MHz
8.240 MHz
CAL(1MHz)
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
f
CAL(8MHz)
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
f
12 12.36 MHz
16 16.48 MHz
CAL(12MHz)
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
f
CAL(16MHz)
calibrated DCO frequencies − overall tolerance
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
I: -40−85°C
T: -40−105°C
1 MHz tolerance overall
1.8 V − 3.6 V
−5
2
2
2
3
+5
+5
+5
+6
%
%
%
%
I: -40−85°C
T: -40−105°C
8 MHz tolerance overall
12 MHz tolerance overall
16 MHz tolerance overall
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
−5
−5
−6
I: -40−85°C
T: -40−105°C
I: -40−85°C
T: -40−105°C
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
I: -40−85°C
T: -40−105°C
f
1MHz calibration value
8MHz calibration value
12MHz calibration value
16MHz calibration value
1.8 V − 3.6 V
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
0.950
7.600
11.40
15.00
1
8
1.050 MHz
8.400 MHz
CAL(1MHz)
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
I: -40−85°C
T: -40−105°C
f
CAL(8MHz)
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
I: -40−85°C
T: -40−105°C
f
12 12.60 MHz
16 17.00 MHz
CAL(12MHz)
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
I: -40−85°C
T: -40−105°C
f
CAL(16MHz)
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
typical characteristics − calibrated 1MHz DCO frequency
1.03
1.02
V
V
= 1.8 V
= 2.2 V
CC
1.01
1.00
0.99
0.98
0.97
CC
V
CC
= 3.0 V
V
CC
= 3.6 V
−50.0 −25.0
0.0
25.0
50.0
75.0 100.0
T
A
− Temperature − °C
Figure 11. Calibrated 1 MHz Frequency vs. Temperature
1.03
1.02
T
= 105 °C
1.01
1.00
0.99
0.98
0.97
A
T
= 85 °C
= 25 °C
A
T
A
T
A
= −40 °C
1.5
2.0
2.5
3.0
3.5
4.0
V
CC
− Supply Voltage − V
Figure 12. Calibrated 1 MHz Frequency vs. V
CC
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPM3/4)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
2.2 V/3 V
2
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
2.2 V/3 V
2.2 V/3 V
3 V
1.5
DCO clock wake-up time from
LPM3/4
(see Note 1)
t
t
µs
DCO,LPM3/4
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
1
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
1
CPU wake-up time from LPM3/4
(see Note 2)
1/f
+
MCLK
CPU,LPM3/4
t
Clock,LPM3/4
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
typical characteristics − DCO clock wake-up time from LPM3/4
10.00
RSELx = 0...11
1.00
0.10
RSELx = 12...15
0.10
1.00
DCO Frequency − MHz
10.00
Figure 13. Clock wake-up time from LPM3 vs DCO frequency
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO with external resistor R
(see Note 1)
OSC
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0,
2.2 V
1.8
DCO output frequency
with R
OSC
f
MHz
DCO,ROSC
3 V
1.95
0.1
T
A
= 25°C
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
D
D
Temperature drift
2.2 V/3 V
%/°C
t
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
Drift with V
CC
2.2 V/3 V
10
%/V
V
NOTES: 1. R
= 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T = 50ppm/°C.
K
OSC
typical characteristics − DCO with external resistor R
OSC
10.00
10.00
1.00
0.10
0.01
1.00
0.10
RSELx = 4
RSELx = 4
0.01
10.00
100.00
1000.00
10000.00
10.00
100.00
1000.00
10000.00
R
− External Resistor − kOhm
R
OSC
− External Resistor − kOhm
OSC
Figure 14. DCO Frequency vs R
,
Figure 15. DCO Frequency vs R
,
OSC
OSC
VCC = 2.2 V, T = 255C
VCC = 3.0 V, T = 255C
A
A
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
R
= 100k
OSC
R
= 100k
OSC
R
R
= 270k
= 1M
R
R
= 270k
= 1M
OSC
OSC
OSC
OSC
−50.0 −25.0
0.0
T
25.0
50.0
75.0 100.0
2.0
2.5
3.0
3.5
4.0
− Temperature − 5C
V
CC
− Supply Voltage − V
A
Figure 16. DCO Frequency vs Temperature,
VCC = 3.0 V
Figure 17. DCO Frequency vs VCC,
T = 255C
A
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal
frequency, LF mode 0, 1
f
XTS = 0, LFXT1Sx = 0 or 1
1.8 V − 3.6 V
32,768
Hz
LFXT1,LF
LFXT1 oscillator logic level
square wave input frequency,
LF mode
f
XTS = 0, LFXT1Sx = 3
XTS = 0, LFXT1Sx = 0;
1.8 V − 3.6 V
10,000 32,768 50,000
Hz
kW
kW
LFXT1,LF,logic
f
C
= 32,768 kHz,
500
200
LFXT1,LF
= 6 pF
L,eff
XTS = 0, LFXT1Sx = 0;
= 32,768 kHz,
Oscillation Allowance for LF
crystals
OA
LF
f
LFXT1,LF
= 12 pF
C
L,eff
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
XTS = 0, Measured at
1
5.5
8.5
11
pF
pF
pF
pF
Integrated effective Load
Capacitance, LF mode
(see Note 1)
C
L,eff
Duty Cycle
LF mode
P1.4/ACLK, f
Hz
= 32,768
2.2 V/3 V
2.2 V/3 V
30
10
50
70
%
LFXT1,LF
Oscillator fault frequency, LF
mode (see Note 3)
XTS = 0, LFXT1Sx = 3
(see Notes 2)
f
10,000
Hz
Fault,LF
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
− Keep as short a trace as possible between the device and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
internal very low power, low frequency oscillator (VLO)
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
TYP
MAX UNIT
-40−85°C
105°C
2.2 V/3 V
2.2 V/3 V
4
12
20
f
VLO frequency
kHz
VLO
22
VLO frequency
temperature drift
I: -40−85°C
T: -40−105°C
df
/dT
(see Note 1)
(see Note 2)
2.2 V/3 V
0.5
4
%/°C
VLO
VLO frequency supply
voltage drift
df /dV
VLO CC
25°C
1.8V − 3.6V
%/V
NOTES: 1. Calculated using the box method:
I Version: (MAX(−40...85_C) − MIN(−40...85_C))/MIN(−40...85_C)/(85_C − (−40_C))
T Version: (MAX(−40...105_C) − MIN(−40...105_C))/MIN(−40...105_C)/(105_C − (−40_C))
2. Calculated using the box method: (MAX(1.8...3.6V) − MIN(1.8...3.6V))/MIN(1.8...3.6V)/(3.6V − 1.8V)
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, high frequency modes (see Note 5)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
LFXT1 oscillator crystal frequency,
HF mode 0
f
f
XTS = 1, LFXT1Sx = 0
1.8 V − 3.6 V
0.4
1
4
MHz
MHz
LFXT1,HF0
LFXT1 oscillator crystal frequency,
HF mode 1
XTS = 1, LFXT1Sx = 1
XTS = 1, LFXT1Sx = 2
1.8 V − 3.6 V
1
LFXT1,HF1
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
1.8 V − 3.6 V
2.2 V − 3.6 V
3.0 V − 3.6 V
2
2
10 MHz
12 MHz
16 MHz
10 MHz
12 MHz
16 MHz
LFXT1 oscillator crystal frequency,
HF mode 2
f
LFXT1,HF2
2
0.4
0.4
0.4
LFXT1 oscillator logic level square
wave input frequency,
HF mode
f
XTS = 1, LFXT1Sx = 3
XTS = 0, LFXT1Sx = 0,
LFXT1,HF,logic
f
C
= 1 MHz,
2700
800
300
1
W
W
LFXT1,HF
= 15 pF
L,eff
XTS = 0, LFXT1Sx = 1
= 4 MHz,
Oscillation Allowance for HF
crystals
(refer to Figure 18 and Figure 19)
f
C
OA
HF
LFXT1,HF
= 15 pF
L,eff
XTS = 0, LFXT1Sx = 2
= 16 MHz,
f
C
W
LFXT1,HF
= 15 pF
L,eff
Integrated effective Load
Capacitance, HF mode
(see Note 1)
C
XTS = 1 (see Note 2)
pF
L,eff
XTS = 1, Measured at P1.4/ACLK,
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
40
40
30
50
50
60
60
%
%
f
= 10 MHz
LFXT1,HF
XTS = 1, Measured at P1.4/ACLK,
= 16 MHz
Duty Cycle
HF mode
f
LFXT1,HF
Oscillator fault frequency, HF mode XTS = 1, LFXT1Sx = 3
(see Note 4) (see Notes 3)
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
f
300 kHz
Fault,HF
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
− Keep as short a trace as possible between the device and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
39
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − LFXT1 oscillator in HF mode (XTS = 1)
100000.00
10000.00
1000.00
LFXT1Sx = 3
100.00
LFXT1Sx = 2
10.00
LFXT1Sx = 1
1.00
10.00
0.10
100.00
Crystal Frequency − MHz
Figure 18. Oscillation Allowance vs Crystal Frequency, C
= 15 pF, T = 25°C
A
L,eff
800.0
LFXT1Sx = 3
700.0
600.0
500.0
400.0
300.0
200.0
100.0
0.0
LFXT1Sx = 2
LFXT1Sx = 1
0.0
4.0
8.0
12.0
16.0
20.0
Crystal Frequency − MHz
Figure 19. XT Oscillator Supply Current vs Crystal Frequency, C
= 15 pF, T = 25°C
A
L,eff
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK;
External: TACLK, INCLK;
Duty Cycle = 50% 10%
2.2 V
10
f
t
Timer_A clock frequency
Timer_A, capture timing
MHz
16
TA
3 V
TA0, TA1, TA2
2.2 V/3 V
20
ns
TA,cap
Timer_B
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK;
External: TBCLK;
Duty Cycle = 50% 10%
2.2 V
10
f
Timer_B clock frequency
Timer_B, capture timing
MHz
16
TB
3 V
t
TB0, TB1, TB2
2.2 V/3 V
20
ns
TB,cap
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART Mode)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% 10%
f
USCI input clock frequency
f
MHz
USCI
SYSTEM
1
BITCLK clock frequency
(equals Baudrate in MBaud)
f
t
2.2V /3 V
MHz
BITCLK
2.2 V
3 V
50
50
150
100
600
600
ns
ns
UART receive deglitch time
(see Note 1)
τ
NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode, see Figure 20 and Figure 21)
PARAMETER
TEST CONDITIONS
SMCLK, ACLK
Duty Cycle = 50% 10%
VCC
MIN
TYP
MAX UNIT
f
t
t
t
USCI input clock frequency
f
MHz
USCI
SYSTEM
2.2 V
3 V
110
75
0
ns
ns
ns
ns
ns
ns
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time
SU,MI
2.2 V
3 V
HD,MI
0
2.2 V
3 V
30
20
UCLK edge to SIMO valid;
= 20 pF
VALID,MO
C
L
USCI (SPI Slave Mode, see Figure 22 and Figure 23)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
STE lead time
STE low to clock
t
t
t
t
2.2 V/3 V
50
ns
STE,LEAD
STE,LAG
STE,ACC
STE,DIS
STE lag time
Last clock to STE high
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
10
ns
ns
ns
STE access time
STE low to SOMI data out
50
50
STE disable time
STE high to SOMI high impedance
2.2 V
3 V
20
15
10
10
ns
ns
ns
ns
t
t
t
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time
SU,SI
2.2 V
3 V
HD,SI
2.2 V
3 V
75
50
110
75
ns
ns
UCLK edge to SOMI valid;
= 20 pF
VALID,SO
C
L
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH tLOW/HIGH
tSU,MI
tHD,MI
SOMI
SIMO
tVALID,MO
Figure 20. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH tLOW/HIGH
tHD,MI
tSU,MI
SOMI
SIMO
tVALID,MO
Figure 21. SPI Master Mode, CKPH = 1
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLOW/HIGH tLOW/HIGH
tSU,SIMO
tHD,SIMO
SIMO
SOMI
tACC
tVALID,SOMI
tDIS
Figure 22. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
CKPL=1
UCLK
tLOW/HIGH tLOW/HIGH
tHD,SI
tSU,SI
SIMO
SOMI
tACC
tVALID,SO
tDIS
Figure 23. SPI Slave Mode, CKPH = 1
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C Mode, see Figure 24)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
MHz
SYSTEM
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% 10%
f
USCI input clock frequency
f
USCI
f
t
SCL clock frequency
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V
0
4.0
0.6
4.7
0.6
0
400 kHz
SCL
f
f
f
f
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
us
us
us
us
ns
ns
us
SCL
SCL
SCL
SCL
Hold time (repeated) START
HD,STA
t
Set-up time for a repeated START
SU,STA
t
t
t
Data hold time
HD,DAT
SU,DAT
SU,STO
Data set-up time
Set-up time for STOP
250
4.0
50
150
100
600
600
ns
ns
Pulse width of spikes suppressed by
input filter
t
SP
3 V
50
tHD
tSU
tHD
tBUF
,STA
,STA
,STA
SDA
tLOW
tHIGH
tSP
SCL
tSU ,DAT
tSU
,STO
tHD
,DAT
Figure 24. I2C Mode Timing
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
T
A
VCC
MIN
2.2
TYP
MAX UNIT
Analog supply voltage
range
V
CC
V
SS
= 0 V
3.6
V
All Ax terminals.
Analog inputs selected in
ADC10AE register.
Analog input voltage range
(see Note 2)
V
Ax
0
V
CC
V
f
= 5.0 MHz
ADC10CLK
2.2 V
3 V
0.52
0.6
1.05
1.2
ADC10ON = 1, REFON = 0
ADC10SHT0 = 1,
ADC10SHT1 = 0, ADC10DIV
= 0
ADC10 supply current
(see Note 3)
I: -40−85°C
T: -40−105°C
I
mA
ADC10
f
= 5.0 MHz
ADC10CLK
I: -40−85°C
T: -40−105°C
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
2.2 V/3 V
3 V
mA
mA
Reference supply current,
reference buffer disabled
(see Note 4)
I
0.25
1.1
0.4
REF+
f
= 5.0 MHz
ADC10CLK
I: -40−85°C
T: -40−105°C
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
f
= 5.0 MHz
ADC10CLK
-40−85°C
105°C
2.2 V/3 V
2.2 V/3 V
1.4
1.8
mA
mA
Reference buffer supply
current with ADC10SR=0
(see Note 4)
ADC10ON = 0,
REFON = 1, REF2_5V = 0,
REFOUT = 1,
ADC10SR=0
I
REFB,0
REFB,1
f
= 5.0 MHz
ADC10CLK
-40−85°C
105°C
2.2 V/3 V
2.2 V/3 V
0.5
0.7
0.8
mA
mA
ADC10ON = 0,
REFON = 1,
Reference buffer supply
current with ADC10SR=1
(see Note 4)
I
REF2_5V = 0,
REFOUT = 1,
ADC10SR=1
Only one terminal Ax selected I: -40−85°C
C
R
Input capacitance
27
pF
I
I
at a time
T: -40−105°C
I: -40−85°C
T: -40−105°C
Input MUX ON resistance
0V ≤ V ≤ V
Ax CC
2.2 V/3 V
2000
Ω
NOTES: 1. The leakage current is defined in the leakage current table with Px.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range V
to V
for valid conversion results.
R+
R−
3. The internal reference supply current is not included in current consumption parameter I
.
ADC10
4. The internal reference current is supplied via terminal V . Consumption is independent of the ADC10ON control bit, unless a
CC
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
46
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, built-in voltage reference
PARAMETER
TEST CONDITIONS
VCC
MIN TYP
MAX UNIT
I
I
I
I
I
≤ 1mA, REF2_5V=0
≤ 0.5mA, REF2_5V=1
≤ 1mA, REF2_5V=1
2.2
2.8
2.9
VREF+
VREF+
VREF+
Positive built-in reference analog
supply voltage range
V
V
V
CC,REF+
≤ I
max, REF2_5V=0 2.2 V/3 V
1.41
2.35
1.5
2.5
1.59
2.65
0.5
1
V
V
VREF+ VREF+
Positive built-in reference voltage
REF+
≤ I max, REF2_5V=1
VREF+ VREF+
3 V
2.2 V
3 V
I
Maximum V
REF+
load current
mA
LD,VREF+
I
= 500 µA 100 µA
VREF+
Analog input voltage V ≈ 0.75 V;
REF2_5V=0
2.2 V/3 V
3 V
2
LSB
Ax
V
load regulation
REF+
REF+
I
= 500 µA 100 µA
VREF+
Analog input voltage V ≈ 1.25 V;
REF2_5V=1
2
LSB
Ax
I
=
VREF+
100µA→900µA,
≈ 0.5 x V
ADC10SR=0
ADC10SR=1
3 V
3V
400
V
V
load regulation response time
ns
Ax
REF+
Error of conversion
result ≤ 1 LSB
2000
100
Max. capacitance at pin V
(see Note 1)
I
≤
1mA,
REF+
VREF+
C
2.2 V/3 V
2.2 V/3 V
pF
VREF+
REFON=1, REFOUT=1
I
= const. with
VREF+
0 mA ≤ I
TC
Temperature coefficient
100 ppm/°C
REF+
≤ 1 mA
VREF+
Settling time of internal reference
voltage (see Note 2)
I
= 0.5 mA, REF2_5V=0
VREF+
3.6 V
2.2 V
2.2 V
3 V
30
1
µs
µs
t
REFON
REFON = 0 → 1
I
= 0.5 mA,
VREF+
ADC10SR=0
ADC10SR=1
ADC10SR=0
ADC10SR=1
REF2_5V=0,
REFON = 1,
2.5
2
REFBURST = 1
Settling time of reference buffer
(see Note 2)
t
REFBURST
I
= 0.5 mA,
VREF+
REF2_5V=1,
REFON = 1,
µs
3 V
4.5
REFBURST = 1
NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/V
/V (REFOUT=1),
REF+ eREF+
must be limited; the reference buffer may become unstable otherwise.
2. The condition is that the error in a conversion started after t
REFON
or t is less than 0.5 LSB.
RefBuf
47
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
VCC
MIN
1.4
TYP
MAX UNIT
V
> V
eREF+
eREF−
V
V
V
V
CC
3.0
SREF1 = 1, SREF0 = 0
Positive external reference input
voltage range (see Note 2)
V
eREF+
V
≤ V
≤ V
− 0.15V
eREF−
eREF+ CC
1.4
0
SREF1 = 1, SREF0 = 1 (see Note 3)
Negative external reference input
voltage range (see Note 4)
V
V
> V
1.2
eREF−
eREF+
eREF−
Differential external reference input
voltage range
∆V
eREF
V
> V
(see Note 5)
1.4
V
V
eREF+
eREF−
CC
1
∆V
eREF
= V
− V
eREF+
eREF−
0V ≤ V
SREF1 = 1, SREF0 = 0
≤ V ,
CC
eREF+
2.2 V/3 V
µA
I
I
Static input current into V
Static input current into V
VeREF+
eREF+
0V ≤V
eREF+
≤ V − 0.15V ≤ 3V
CC
2.2 V/3 V
2.2 V/3 V
0
1
µA
µA
SREF1 = 1, SREF0 = 1 (see Note 3)
0V ≤ V ≤ V
VeREF−
eREF−
eREF− CC
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C , is also
I
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer
supply current I
REFB
. The current consumption can be limited to the sample and conversion period with REBURST = 1.
4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied
with reduced accuracy requirements.
48
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ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified
performance of
ADC10 linearity
parameters
ADC10SR=0 2.2 V/3 V
ADC10SR=1 2.2 V/3 V
0.45
6.3
f
f
ADC10 input clock frequency
MHz
1.5
ADC10CLK
0.45
3.7
ADC10DIVx=0, ADC10SSELx = 0
= f
ADC10 built-in oscillator frequency
2.2 V/3 V
2.2 V/3 V
6.3 MHz
ADC10OSC
f
ADC10CLK ADC10OSC
ADC10 built-in oscillator,
ADC10SSELx = 0
2.06
3.51
100
µs
f
= f
ADC10CLK ADC10OSC
t
t
Conversion time
CONVERT
13×
f
from ACLK, MCLK or
ADC10CLK
ADC10DIV×
1/f
µs
SMCLK: ADC10SSELx ≠ 0
ADC10CLK
Turn on settling time of the ADC
(see Note 1)
ns
ADC10ON
NOTES: 1. The condition is that the error in a conversion started after t
settled.
is less than 0.5 LSB. The reference and input signal are already
ADC10ON
10-bit ADC, linearity parameters
PARAMETER
Integral linearity error
Differential linearity error
Offset error
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
E
E
E
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
1
1
1
LSB
LSB
LSB
I
D
O
Source impedance R < 100 Ω,
S
SREFx = 010; un-buffered external
2.2 V
3 V
1.1
2
2
LSB
LSB
reference; V
eREF+
= 1.5V
SREFx = 010; un-buffered external
reference; V = 2.5V
1.1
1.1
eREF+
SREFx = 011; buffered external
reference (see Note 1);
Gain error
E
G
2.2 V
3 V
4
3
LSB
LSB
V
= 1.5V
eREF+
SREFx = 011; buffered external
reference (see Note 1);
1.1
V
= 2.5V
eREF+
SREFx = 010; un-buffered external
reference; V = 1.5V
2.2 V
3 V
2
2
5
5
LSB
LSB
eREF+
SREFx = 010; un-buffered external
reference; V = 2.5V
eREF+
SREFx = 011; buffered external
reference (see Note 1);
Total unadjusted error
E
T
2.2 V
3 V
2
2
7
6
LSB
LSB
V
= 1.5V
eREF+
SREFx = 011; buffered external
reference (see Note 1);
V
= 2.5V
eREF+
NOTES: 1. The reference buffer’s offset adds to the gain and total unadjusted error.
49
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ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, temperature sensor and built-in V
MID
PARAMETER
TEST CONDITIONS
VCC
2.2 V
3 V
MIN
TYP
40
MAX
120
160
UNIT
Temperature sensor supply
current (see Note 1)
REFON = 0, INCHx = 0Ah,
I
µA
SENSOR
T
A
= 25_C
ADC10ON = 1, INCHx = 0Ah
(see Note 2)
60
†
2.2 V/3 V
3.44
3.55
3.66 mV/°C
TC
SENSOR
ADC10ON = 1, INCHx = 0Ah
(see Note 2)
V
Sensor offset voltage
−100
1265
1195
985
100
1465
1395
1185
1095
mV
mV
mV
Offset,Sensor
Temperature sensor voltage
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
1365
1295
1085
995
at T = 105°C (T Version only)
A
Temperature sensor voltage
at T = 85°C
A
Sensor output voltage
(see Note 3)
V
Sensor
Temperature sensor voltage
at T = 25°C
A
mV
Temperature sensor voltage
895
at T = 0°C
A
Sample time required if
channel 10 is selected (see
Note 4)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
2.2 V/3 V
30
µs
t
Sensor(sample)
2.2 V
3 V
NA
NA
Current into divider at channel
11 (see Note 5)
I
ADC10ON = 1, INCHx = 0Bh,
ADC10ON = 1, INCHx = 0Bh,
µA
VMID
2.2 V
3 V
1.06
1.46
1.1
1.5
1.14
1.54
V
V
CC
divider at channel 11
V
MID
V
MID
is ≈0.5 x V
CC
Sample time required if
channel 11 is selected (see
Note 6)
2.2 V
3 V
1400
1220
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
t
ns
VMID(sample)
NOTES: 1. The sensor current I
is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal
is included in I . When REFON = 0, I applies during conversion of the temperature
SENSOR
is high). When REFON = 1, I
SENSOR
REF+ SENSOR
sensor input (INCH = 0Ah).
2. The following formula can be used to calculate the temperature sensor output voltage:
V
V
= TC
= TC
( 273 + T [°C] ) + V [mV] or
Sensor,typ
Sensor,typ
Sensor
Sensor
Offset,sensor
T [°C] + V
Sensor
(T = 0°C) [mV]
A
3. Results based on characterization and/or production test, not TC
4. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t
or V .
Offset,sensor
Sensor
.
SENSOR(on)
5. No additional current is needed. The V
is used during sampling.
MID
6. The on-time t
VMID(on)
is included in the sampling time t ; no additional on time is needed.
VMID(sample)
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
operational amplifier OA, supply specifications (MSP430x22x4 only)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
TYP
MAX
3.6
UNIT
V
CC
Supply voltage range
V
Fast Mode
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
180
290
190
80
Medium Mode
Slow Mode
110
50
I
Supply current (see Note 1)
Power supply rejection ratio
µA
CC
PSRR
Non-inverting
70
dB
NOTES: 1. Corresponding pins configured as OA inputs and outputs respectively.
operational amplifier OA, input/output specifications (MSP430x22x4 only)
PARAMETER
TEST CONDITIONS
VCC
MIN
−0.1
TYP
MAX
UNIT
V
V
I/P
Input voltage range
V
−1.2
5
CC
T
= −40 to +55_C
= +55 to +85_C
= +85 to +105_C
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
−5
−20
−50
0.5
5
nA
nA
nA
A
Input leakage current
(see Notes 1 and 2)
T
A
20
50
I
Ikg
T
A
Fast Mode
50
80
Medium Mode
Slow Mode
Fast Mode
f
= 1 kHz
V(I/P)
140
30
V
n
Voltage noise density, I/P
nV/√Hz
Medium Mode
Slow Mode
50
f
= 10 kHz
V(I/P)
65
V
IO
Offset voltage, I/P
2.2 V/3 V
2.2 V/3 V
10
mV
Offset temperature drift, I/P
see Note 3
10
µV/°C
Offset voltage drift
with supply, I/P
0.3V ≤ V ≤ V −1.0V
IN CC
2.2 V/3 V
1.5
mV/V
∆V
≤
10%, T = 25°C
CC
A
Fast Mode, I
Slow Mode,I
Fast Mode, I
Slow Mode,I
≤ −500µA
≤ −150µA
≤ +500µA
≤ +150µA
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
V
V
−0.2
−0.1
V
V
SOURCE
SOURCE
SOURCE
SOURCE
CC
CC
V
V
High-level output voltage, O/P
Low-level output voltage, O/P
V
V
OH
CC
V
CC
0.2
SS
SS
OL
V
0.1
R
= 3 kΩ, C
Load Load
= 50pF,
2.2 V/3 V
2.2 V/3 V
150
150
250
250
4
V
< 0.2 V
O/P(OAx)
Output Resistance
R
= 3 kΩ, C
= 50pF,
Load
Load
R
Ω
(see Figure 25 and Note 4)
O/P(OAx)
V
> V
− 1.2 V
O/P(OAx)
CC
R
= 3 kΩ, C
Load
= 50pF,
− 0.2 V
Load
2.2 V/3 V
2.2 V/3 V
0.1
70
0.2 V ≤ V
≤ V
CC
O/P(OAx)
CMRR
Common-mode rejection ratio
Non-inverting
dB
NOTES: 1. ESD damage can degrade input current leakage.
2. The input bias current is overridden by the input leakage current.
3. Calculated using the box method.
4. Specification valid for voltage-follower OAx configuration.
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
R
O/P(OAx)
Max
R
Load
I
Load
AV
CC
OAx
2
C
O/P(OAx)
Min
Load
0.2V
AV
−0.2V
CC
V
AV
OUT
CC
Figure 25. OAx Output Resistance Tests
operational amplifier OA, dynamic specifications (MSP430x22x4 only)
PARAMETER
TEST CONDITIONS
Fast Mode
VCC
MIN
TYP
1.2
MAX
UNIT
Medium Mode
Slow Mode
0.8
0.3
100
60
SR
Slew rate
V/µs
Open-loop voltage gain
Phase margin
dB
deg
dB
φ
m
C
C
= 50 pF
= 50 pF
L
L
Gain margin
20
Non-inverting, Fast Mode,
= 47kΩ, C = 50pF
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2
1.4
R
L
L
Gain-Bandwidth Product
(see Figure 26
and Figure 27)
Non-inverting, Medium Mode,
=300kΩ, C = 50pF
GBW
MHz
R
L
L
Non-inverting, Slow Mode,
0.5
10
R
=300kΩ, C = 50pF
L
L
t
t
Enable time on
Enable time off
t , non-inverting, Gain = 1
on
2.2 V/3 V
2.2 V/3 V
20
µs
µs
en(on)
1
en(off)
TYPICAL PHASE vs FREQUENCY
TYPICAL OPEN-LOOP GAIN vs FREQUENCY
0
−50
140
120
100
80
Fast Mode
Fast Mode
60
−100
−150
−200
−250
40
Medium Mode
20
Medium Mode
Slow Mode
0
Slow Mode
−20
−40
−60
−80
1
10
100
1000
10000
100000
1
10
100
1000
10000
100000
Input Frequency − kHz
Input Frequency − kHz
Figure 26
Figure 27
52
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
operational amplifier OA feedback network, resistor network (see Note 1. MSP430x22x4 only)
PARAMETER
TEST CONDITIONS
VCC
MIN
76
TYP
96
MAX
128
UNIT
R
R
Total resistance of resistor string
kΩ
total
unit
Unit resistor of resistor string
(see Note 2)
4.8
6
8
kΩ
NOTES: 1. A single resistor string is composed of 4 R
unit
+ 4 R
unit
+ 2 R
unit
+ 2 R
unit
+ 1 R
unit
+ 1 R
unit
+ 1 R
unit
+ 1 R
= 16 R
unit
= R .
total
unit
2. For the matching (i.e. the relative accuracy) of the unit resistors on a device refer to the gain and level specifications of the respective
configurations.
operational amplifier OA feedback network,
comparator mode (OAFCx = 3. MSP430x22x4 only)
PARAMETER
TEST CONDITIONS
OAFBRx = 1, OARRIP = 0
OAFBRx = 2, OARRIP = 0
OAFBRx = 3, OARRIP = 0
OAFBRx = 4, OARRIP = 0
OAFBRx = 5, OARRIP = 0
OAFBRx = 6, OARRIP = 0
OAFBRx = 7, OARRIP = 0
OAFBRx = 1, OARRIP = 1
OAFBRx = 2, OARRIP = 1
OAFBRx = 3, OARRIP = 1
OAFBRx = 4, OARRIP = 1
OAFBRx = 5, OARRIP = 1
OAFBRx = 6, OARRIP = 1
OAFBRx = 7, OARRIP = 1
Fast Mode, Overdrive 10mV
Fast Mode, Overdrive 100mV
Fast Mode, Overdrive 500mV
Medium Mode, Overdrive 10mV
Medium Mode, Overdrive 100mV
Medium Mode, Overdrive 500mV
Slow Mode, Overdrive 10mV
Slow Mode, Overdrive 100mV
Slow Mode, Overdrive 500mV
VCC
MIN
TYP
1/4
MAX
0.255
0.505
0.631
UNIT
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
0.245
0.495
0.619
1/2
5/8
N/A (see Note 1)
N/A (see Note 1)
N/A (see Note 1)
N/A (see Note 1)
V
Level
Comparator level
V
CC
0.061
1/16
1/8
0.065
0.128
0.192
0.255
0.383
0.505
0.122
0.184
0.245
0.367
0.495
3/16
1/4
3/8
1/2
N/A (see Note 1)
40
4
3
60
6
Propagation delay
(low−high and high−low)
t
, t
µs
PLH PHL
5
160
20
15
NOTES: 1. The level is not available due to the analog input voltage range of the operational amplifier.
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
operational amplifier OA feedback network,
non-inverting amplifier mode (OAFCx = 4. MSP430x22x4 only)
PARAMETER
TEST CONDITIONS
OAFBRx = 0
VCC
MIN
TYP
1.00
MAX
1.002
1.340
2.017
2.696
4.06
UNIT
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V
0.998
1.328
1.985
2.638
3.94
OAFBRx = 1
OAFBRx = 2
OAFBRx = 3
OAFBRx = 4
OAFBRx = 5
OAFBRx = 6
OAFBRx = 7
1.334
2.001
2.667
4.00
5.33
7.97
15.8
−60
G
Gain
5.22
5.44
7.76
8.18
15.0
16.6
Total Harmonic Distortion/
Nonlinearity
THD
all gains
dB
3 V
−70
t
Settling time (see Note 1)
all power modes
2.2 V/3 V
7
12
µs
Settle
NOTES: 1. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
operational amplifier OA feedback network,
inverting amplifier mode (OAFCx = 6, see Note 1, MSP430x22x4 only)
PARAMETER
TEST CONDITIONS
OAFBRx = 1
VCC
MIN
TYP
MAX
UNIT
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V/ 3V
2.2 V
−0.345 −0.335 −0.325
−1.023 −1.002 −0.979
−1.712 −1.668 −1.624
OAFBRx = 2
OAFBRx = 3
OAFBRx = 4
OAFBRx = 5
OAFBRx = 6
OAFBRx = 7
−3.10
−4.51
−7.37
−16.3
−3.00
−4.33
−6.97
−14.8
−60
−2.90
−4.15
−6.57
−13.1
G
Gain
Total Harmonic Distortion/
Nonlinearity
THD
all gains
dB
3 V
−70
t
Settling time (see Note 2)
all power modes
2.2 V/3 V
7
12
µs
Settle
NOTES: 1. This includes the 2 OA configuration “inverting amplifier with input buffer”. Both OA needs to be set to the same power mode OAPMx.
2. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The
settling time of the amplifier itself might be faster.
54
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2
TYP
MAX UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from V
Supply current from V
during program
during erase
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
2.2 V/3.6 V
1
1
PGM
CC
7
mA
ERASE
CPT
CC
Cumulative program time (see Note 1)
Cumulative mass erase time
Program/Erase endurance
Data retention duration
10
ms
20
ms
CMErase
4
10
5
10
cycles
years
t
T = 25°C
J
100
Retention
t
t
t
t
t
t
Word or byte program time
30
25
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
18
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 2
t
FTG
6
10593
4819
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (t
FTG
= 1/f ).
FTG
RAM
PARAMETER
TEST CONDITIONS
CPU halted
MIN
TYP
MAX UNIT
V
RAM retention supply voltage (see Note 1)
1.6
V
(RAMh)
NOTE 1: This parameter defines the minimum supply voltage V
happen during this supply voltage condition.
when the data in RAM remains unchanged. No program execution should
CC
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
JTAG and Spy-Bi-Wire Interface
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
f
t
Spy-Bi-Wire input frequency
2.2 V / 3 V
2.2 V / 3 V
0
20
15
MHz
us
SBW
Spy-Bi-Wire low clock pulse length
0.025
SBW,Low
Spy-Bi-Wire enable time
t
(TEST high to acceptance of first clock edge, see
Note 1)
2.2 V/ 3 V
1
us
SBW,En
t
f
Spy-Bi-Wire return to normal operation time
2.2 V/ 3 V
2.2 V
15
0
100
5
us
SBW,Ret
MHz
MHz
kΩ
TCK input frequency (see Note 2)
TCK
3 V
0
10
90
R
Internal pull-down resistance on TEST
2.2 V/ 3 V
25
60
Internal
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t
before applying the first SBWCLK clock edge.
time after pulling the TEST/SBWCLK pin high
SBW,En
2.
f
may be restricted to meet the timing requirements of the module selected.
TCK
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
V
V
Supply voltage during fuse-blow condition
Voltage level on TEST for fuse-blow
Supply current into TEST during fuse blow
Time to blow fuse
T
A
= 25°C
2.5
6
V
V
CC(FB)
7
100
1
FB
I
t
mA
ms
FB
FB
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test and emulation feature is possible and is switched to bypass mode.
56
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt-trigger
Pad Logic
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
0
1
P1OUT.x
Module X OUT
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1SEL.x
P1IN.x
P1.2/TA1
P1.3/TA2
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Port P1 (P1.0 to P1.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
P1.0/
0
P1.0† (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
0
1
1
TACLK/ADC10CLk
P1.1/TA0
Timer_A3.TACLK
ADC10CLK
0
1
1
2
3
P1.1† (I/O)
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA0
P1.2† (I/O)
0
1
P1.2/TA1
P1.3/TA2
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA0
P1.3† (I/O)
0
1
I: 0; O: 1
Timer_A3.CCI0A
Timer_A3.TA0
0
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P1 pin schematic: P1.4 to P1.6, input/output with Schmitt-trigger and in-system access features
Pad Logic
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
Bus
Keeper
P1SEL.x
P1IN.x
EN
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
To JTAG
From JTAG
Port P1 (P1.4 to P1.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
4-Wire JTAG
P1.4/SMCLK/TCK
4
P1.4† (I/O)
SMCLK
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
0
1
0
0
1
0
0
1
1
TCK
X
P1.5/TA0/TMS
5
6
P1.5† (I/O)
Timer_A3.TA0
TMS
I: 0; O: 1
1
X
P1.6/TA1/TDI/TCLK
P1.6† (I/O)
Timer_A3.TA1
I: 0; O: 1
1
TDI/TCLK (see Note 3)
Default after reset (PUC/POR)
X
†
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Function controlled by JTAG.
58
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P1 pin schematic: P1.7, input/output with Schmitt-trigger and in-system access features
Pad Logic
P1REN.7
DVSS
DVCC
0
1
1
P1DIR.7
0
1
Direction
0: Input
1: Output
0
1
P1OUT.7
Module X OUT
P1.7/TA2/TDO/TDI
Bus
Keeper
P1SEL.7
P1IN.7
EN
EN
D
Module X IN
P1IRQ.7
P1IE.7
EN
Q
Set
P1IFG.7
Interrupt
Edge
Select
P1SEL.7
P1IES.7
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
Port P1 (P1.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.X)
X
FUNCTION
P1DIR.x
P1SEL.x
4-Wire JTAG
P1.7/TA2/TDO/TDI
7
P1.7† (I/O)
I: 0; O: 1
0
1
0
0
1
Timer_A3.TA2
1
TDO/TDI (see Note 3)
Default after reset (PUC/POR)
X
X
†
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Function controlled by JTAG.
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P2 pin schematic: P2.0, P2.2, input/output with Schmitt-trigger
Pad Logic
To ADC10
INCHx = y
ADC10AE0.y
P2REN.x
DVSS
DVCC
0
1
1
P2DIR.x
0
1
Direction
0: Input
1: Output
0
1
P2OUT.x
Module X OUT
P2.0/ACLK/A0/OA0I0
P2.2/TA0/A2/OA0I1
Bus
Keeper
P2SEL.x
P2IN.x
EN
EN
D
Module X IN
P2IRQ.x
P2IE.x
EN
Q
Set
P2IFG.x
Interrupt
Edge
Select
P2SEL.x
P2IES.x
+
OA0
−
Port P2 (P2.0, P2.2) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
Y
FUNCTION
P2DIR.x
P2SEL.x
ADC10AE0.y
P2.0/ACLK/A0/OA0I0
0
0
P2.0† (I/O)
ACLK
I: 0; O: 1
0
1
X
0
1
1
X
0
0
1
0
0
0
1
1
A0/OA0I0 (see Note 3)
P2.2† (I/O)
X
P2.2/TA0/A2/OA0I1
2
2
I: 0; O: 1
Timer_A3.CCI0B
Timer_A3.TA0
0
1
A2/OA0I1 (see Note 3)
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
60
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P2 pin schematic: P2.1, input/output with Schmitt-trigger
Pad Logic
To ADC10
INCHx = 1
ADC10AE0.1
P2REN.1
DVSS
DVCC
0
1
1
P2DIR.1
0
1
Direction
0: Input
1: Output
0
1
P2OUT.1
Module X OUT
P2.1/TAINCLK/SMCLK/
A1/OA0O
Bus
Keeper
P2SEL.1
P2IN.1
EN
EN
D
Module X IN
P2IRQ.1
P2IE.1
EN
Q
Set
P2IFG.1
+
1
OA0
Interrupt
Edge
Select
P2SEL.1
P2IES.1
−
OAADCx
OAFCx
OAPMx
(OAADCx = 10 or OAFCx = 000) and OAPMx > 00
To OA0 Feedback Network
1
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P2 pin schematic: P2.3, input/output with Schmitt-trigger
SREF2
VSS
Pad Logic
0
1
To ADC10 V
R−
To ADC10
INCHx = 3
ADC10AE0.3
P2REN.3
P2DIR.3
DVSS
DVCC
0
1
1
0
1
Direction
0: Input
1: Output
P2OUT.3
0
1
Module X OUT
P2.3/TA1/
A3/VREF−/VeREF−/
OA1I1/OA1O
Bus
Keeper
P2SEL.3
P2IN.3
EN
EN
D
Module X IN
P2IRQ.3
P2IE.3
EN
Q
Set
P2IFG.3
Interrupt
Edge
Select
P2SEL.3
P2IES.3
+
1
OA1
−
OAADCx
OAFCx
OAPMx
(OAADCx = 10 or OAFCx = 000) and OAPMx > 00
To OA1 Feedback Network
1
62
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P2 (P2.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
Y
FUNCTION
P2DIR.x
P2SEL.x
ADC10AE0.y
P2.1/TAINCLK/SMCLK
/A1/OA0O
1
1
P2.1† (I/O)
Timer_A3.INCLK
SMCLK
I: 0; O: 1
0
1
1
X
0
0
0
1
0
1
A1/OA0O (see Note 3)
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Port P2 (P2.3) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
Y
FUNCTION
P2DIR.x
P2SEL.x
ADC10AE0.y
P2.3/TA1/
3
3
P2.3† (I/O)
I: 0; O: 1
0
1
1
X
0
0
0
1
A3/V /
/V
OA1I1/OA1O
REF− eREF−
Timer_A3.CCI1B
Timer_A3.TA1
0
1
A3/V
/V
/OA1I1/OA1O (see Note 3)
X
REF− eREF−
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P2 pin schematic: P2.4, input/output with Schmitt-trigger
Pad Logic
To/from ADC10
positive reference
To ADC10
INCHx = 4
ADC10AE0.4
P2REN.4
DVSS
0
1
1
DVCC
P2DIR.4
0
1
Direction
0: Input
1: Output
0
1
P2OUT.4
Module X OUT
P2.4/TA2/
A4/VREF+/VeREF+/
OA1I0
Bus
Keeper
P2SEL.4
P2IN.4
EN
EN
D
Module X IN
P2IRQ.4
P2IE.4
EN
Q
Set
P2IFG.4
Interrupt
Edge
Select
P2SEL.4
P2IES.4
+
OA1
−
Port P2 (P2.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
Y
FUNCTION
P2DIR.x
P2SEL.x
ADC10AE0.y
P2.4/TA2/
4
4
P2.4† (I/O)
Timer_A3.TA2
A4/V /V
I: 0; O: 1
0
1
0
0
1
A4/V /
/V
REF+ eREF+
1
OA1I0
/OA1I0 (see Note 3)
X
X
REF+ eREF+
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
64
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P2 pin schematic: P2.5, input/output with Schmitt-trigger and external R
for DCO
OSC
Pad Logic
To DCO
DCOR
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
0
1
P1OUT.x
Module X OUT
P2.5/ROSC
Bus
Keeper
P1SEL.x
P1IN.x
EN
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Port P2 (P2.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
I: 0; O: 1
P2SEL.x
DCOR
P2.5/R
OSC
5
P2.5† (I/O)
N/A
0
1
1
X
0
0
0
1
0
1
DV
SS
R
X
OSC
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P2 pin schematic: P2.6, input/output with Schmitt-trigger and crystal oscillator input
BCSCTL3.LFXT1Sx = 11
LFXT1 Oscillator
P2.7/XOUT
LFXT1 off
0
1
LFXT1CLK
Pad Logic
P2SEL.7
P2REN.6
DVSS
0
1
1
DVCC
P2DIR.6
0
1
Direction
0: Input
1: Output
0
1
P2OUT.6
Module X OUT
P2.6/XIN
Bus
Keeper
P2SEL.6
P2IN.6
EN
EN
D
Module X IN
P2IRQ.6
P2IE.6
EN
Set
Q
P2IFG.6
Interrupt
Edge
Select
P2SEL.6
P2IES.6
Port P2 (P2.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
I: 0; O: 1
X
P2SEL.x
P2.6/XIN
6
P2.6 (I/O)
XIN†
0
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
66
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P2 pin schematic: P2.7, input/output with Schmitt-trigger and crystal oscillator output
BCSCTL3.LFXT1Sx = 11
LFXT1 Oscillator
LFXT1 off
0
1
LFXT1CLK
From P2.6/XIN
P2.6/XIN
Pad Logic
P2SEL.6
P2REN.7
DVSS
0
1
1
DVCC
P2DIR.7
0
1
Direction
0: Input
1: Output
0
1
P2OUT.7
Module X OUT
P2.7/XOUT
Bus
Keeper
P2SEL.7
P2IN.7
EN
EN
D
Module X IN
P2IRQ.7
P2IE.7
EN
Set
Q
P2IFG.7
Interrupt
Edge
Select
P2SEL.7
P2IES.7
Port P2 (P2.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.X)
X
FUNCTION
P2DIR.x
I: 0; O: 1
X
P2SEL.x
XOUT/P2.7
6
P2.7 (I/O)
XOUT† (see Note 3)
0
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
67
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P3 pin schematic: P3.0, input/output with Schmitt-trigger
Pad Logic
To ADC10
INCHx = 5
ADC10AE0.5
P3REN.0
DVSS
DVCC
0
1
1
P3DIR.0
0
1
Direction
0: Input
1: Output
USCI Direction
Control
0
1
P3OUT.0
Module X OUT
P3.0/UC1STE/UC0CLK/A5
Bus
Keeper
P3SEL.0
P3IN.0
EN
EN
D
Module X IN
Port P3 (P3.0) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
Y
FUNCTION
P3DIR.x
P3SEL.x
ADC10AE0.y
P3.0/
UC1STE/UC0CLK/A5
0
5
P3.0† (I/O)
I: 0; O: 1
0
1
0
0
1
UC1STE/UC0CLK (see Notes 3, 4)
A5 (see Note 5)
X
X
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. The pin direction is controlled by the USCI module.
4. UC0CLK function takes precedence over UC1STE function. If the pin is required as UC0CLK input or output USCI1 will be forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
5. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
68
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P3 pin schematic: P3.1 to P3.5, input/output with Schmitt-trigger
Pad Logic
DVSS
P3REN.x
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
USCI Direction
Control
0
1
P3OUT.x
Module X OUT
P3.1/UC1SIMO/UC1SCL
P3.2/UC1SOMI/UC1SDA
P3.3/UC1CLK/UC0STE
P3.4/UC0TXD/UC0SIMO
P3.5/UC0RXD/UC0SOMI
Bus
Keeper
P3SEL.x
P3IN.x
EN
EN
D
Module X IN
Port P3 (P3.1 to P3.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
FUNCTION
P3DIR.x
P3SEL.x
P3.1/
UC1SIMO/UC1SDA
1
P3.1† (I/O)
I: 0; O: 1
0
1
0
1
0
1
0
1
0
1
UC1SIMO/UC1SDA (see Note 3)
P3.2† (I/O)
X
P3.2/
UC1SOMI/UC1SCL
1
1
1
1
I: 0; O: 1
UC1SOMI/UC1SCL (see Note 3)
P3.3† (I/O)
X
P3.3/
UC1CLK/UC0STE
I: 0; O: 1
UC1CLK/UC0STE (see Notes 3, 4)
P3.4† (I/O)
X
I: 0; O: 1
X
P3.4/
UC0TXD/UC0SIMO
UC0TXD/UC0SIMO (see Note 3)
P3.5† (I/O)
P3.5/
UC0RXD/UC0SOMI
I: 0; O: 1
X
UC0RXD/UC0SOMI (see Note 3)
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. The pin direction is controlled by the USCI module.
4. UC1CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output USCI0 will be forced
to 3-wire SPI mode even if 4-wire SPI mode is selected.
69
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P3 pin schematic: P3.6 to P3.7, input/output with Schmitt-trigger
Pad Logic
To ADC10
INCHx = y
ADC10AE0.y
P3REN.x
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
0
1
P3OUT.x
Module X OUT
P3.6/A6/OA0I2
P3.7/A7/OA1I2
Bus
Keeper
P3SEL.x
P3IN.x
EN
EN
D
Module X IN
+
OA0/1
−
Port P3 (P3.6, P3.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.X)
X
Y
FUNCTION
P3DIR.x
P3SEL.x
ADC10AE0.y
P3.6/A6/OA0I2
6
6
P3.6† (I/O)
I: 0; O: 1
0
X
0
0
1
0
1
A6/OA0I2 (see Note 5)
P3.7† (I/O)
X
I: 0; O: 1
X
P3.7/A7/OA1I2
7
7
A7/OA1I2 (see Note 5)
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. The pin direction is controlled by the USCI module.
4. UC1CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output USCI0 will be forced
to 3-wire SPI mode if 4-wire SPI mode is selected.
5. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
70
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P4 pin schematic: P4.0 to P4.2, input/output with Schmitt-trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15/OA1I3
Pad Logic
P4SEL.6
P4DIR.6
ADC10AE1.7
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
0
1
P4OUT.x
Module X OUT
P4.0/TB0
P4.1/TB1
P4.2/TB2
Bus
Keeper
P4SEL.x
P4IN.x
EN
EN
D
Module X IN
Port P4 (P4.0 to P4.2) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
FUNCTION
P4DIR.x
P4SEL.x
P4.0/TB0
0
P4.0† (I/O)
I: 0; O: 1
0
1
1
0
1
1
0
1
1
Timer_B3.CCI0A
Timer_B3.TB0
P4.1† (I/O)
0
1
P4.1/TB1
P4.2/TB2
1
2
I: 0; O: 1
Timer_B3.CCI1A
Timer_B3.TB1
P4.2† (I/O)
0
1
I: 0; O: 1
Timer_B3.CCI2A
Timer_B3.TB2
0
1
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
71
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P4 pin schematic: P4.3 to P4.4, input/output with Schmitt-trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15/OA1I3
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC10
†
INCHx = 8+y
ADC10AE1.y
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
0
1
P4OUT.x
Module X OUT
P4.3/TB0/A12/OA0O
P4.4/TB1/A13/OA1O
Bus
Keeper
P4SEL.x
P4IN.x
EN
EN
D
Module X IN
+
1
OA0/1
−
OAADCx
OAPMx
OAADCx = 01 and OAPMx > 00
To OA0/1 Feedback Network
1
†
If OAADCx = 11 and not OAFCx = 000 the ADC input A12 or A13 is internally connected to the OA0 or OA1 output respectively and the connections
from the ADC and the operational amplifiers to the pad are disabled.
72
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P4 (P4.3 to P4.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
Y
FUNCTION
P4DIR.x
P4SEL.x
ADC10AE1.y
P4.3/TB0/A12/OA0O
3
4
P4.3† (I/O)
I: 0; O: 1
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
Timer_B3.CCI0B
Timer_B3.TB0
0
1
A12/OA0O (see Note 3)
P4.4† (I/O)
X
P4.4/TB1/A13/OA1O
4
5
I: 0; O: 1
Timer_B3.CCI1B
Timer_B3.TB1
0
1
A13/OA1O (see Note 3)
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
73
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P4 pin schematic: P4.5, input/output with Schmitt-trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15/OA1I3
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC10
INCHx = 14
ADC10AE1.6
P4REN.5
DVSS
DVCC
0
1
1
P4DIR.5
0
1
Direction
0: Input
1: Output
0
1
P4OUT.5
Module X OUT
P4.5/TB3/A14/OA0I3
Bus
Keeper
P4SEL.5
P4IN.5
EN
EN
D
Module X IN
+
OA0
−
74
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P4 (P4.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
Y
FUNCTION
P4DIR.x
P4SEL.x
ADC10AE1.y
P4.5/TB3/A14/OA0I3
5
6
P4.5† (I/O)
I: 0; O: 1
0
1
0
0
1
Timer_B3.TB2
1
A14/OA0I3 (see Note 3)
X
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
75
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P4 pin schematic: P4.6, input/output with Schmitt-trigger
Pad Logic
To ADC10
INCHx = 15
ADC10AE1.7
P4REN.6
DVSS
0
1
1
DVCC
P4DIR.6
0
1
Direction
0: Input
1: Output
0
1
P4OUT.6
Module X OUT
P4.6/TBOUTH/
A15/OA1I3
Bus
Keeper
P4SEL.6
P4IN.6
EN
EN
D
Module X IN
+
OA1
−
Port P4 (P4.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
Y
FUNCTION
P4DIR.x
P4SEL.x
ADC10AE1.y
P4.6/TBOUTH/
A15/OA1I3
6
7
P4.6† (I/O)
TBOUTH
I: 0; O: 1
0
1
1
X
0
0
0
1
0
1
DV
SS
A15/OA1I3 (see Note 3)
X
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when
applying analog signals.
76
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Port P4 pin schematic: P4.7, input/output with Schmitt-trigger
Pad Logic
DVSS
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
0
1
P4OUT.x
Module X OUT
P4.7/TBCLK
Bus
Keeper
P4SEL.x
P4IN.x
EN
EN
D
Module X IN
Port P4 (P4.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
FUNCTION
P4DIR.x
P4SEL.x
P4.7/TBCLK
7
P4.7† (I/O)
Timer_B3.TBCLK
DV
I: 0; O: 1
0
1
1
0
1
SS
†
Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
77
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢇꢆꢇ ꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢇꢇ ꢆ ꢃ
ꢀ ꢉ ꢊ ꢋꢌ ꢁꢉ ꢍꢎ ꢏ ꢐ ꢀꢉ ꢑ ꢒꢓꢑ ꢓꢎ ꢔꢒ ꢓꢐ ꢐꢋ ꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
TF
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS
is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
TF
I
TEST
Figure 28. Fuse Check Mode Current, MSP430F22xx
NOTE:
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader
access key is used. Also, see the bootstrap loader section for more information.
78
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢇ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢇꢆ ꢃ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS504A − JULY 2006 − REVISED DECEMBER 2006
Data Sheet Revision History
Literature
Number
Summary
SLAS504
Preliminary data sheet release.
Production data sheet release.
SLAS504A
Updated specification and added characterization graphs.
Updated/corrected port pin schematics.
NOTE: The referring page and figure numbers are referred to the respective document revision.
79
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2007
PACKAGING INFORMATION
Orderable Device
MSP430F2232IDA
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DA
38
38
40
40
38
38
40
40
38
38
40
40
38
38
40
40
38
38
40
40
38
38
40
40
38
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MSP430F2232IDAR
MSP430F2232IRHAR
MSP430F2232IRHAT
MSP430F2232TDA
MSP430F2232TDAR
MSP430F2232TRHAR
MSP430F2232TRHAT
MSP430F2234IDA
TSSOP
QFN
DA
RHA
RHA
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
QFN
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RHA
RHA
DA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
QFN
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MSP430F2234IDAR
MSP430F2234IRHAR
MSP430F2234IRHAT
MSP430F2234TDA
MSP430F2234TDAR
MSP430F2234TRHAR
MSP430F2234TRHAT
MSP430F2252IDA
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RHA
RHA
DA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
QFN
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RHA
RHA
DA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
QFN
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MSP430F2252IDAR
MSP430F2252IRHAR
MSP430F2252IRHAT
MSP430F2252TDA
MSP430F2252TDAR
MSP430F2252TRHAR
MSP430F2252TRHAT
MSP430F2254IDA
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RHA
RHA
DA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
QFN
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RHA
RHA
DA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2007
Orderable Device
MSP430F2254IDAR
MSP430F2254IRHAR
MSP430F2254IRHAT
MSP430F2254TDA
MSP430F2254TDAR
MSP430F2254TRHAR
MSP430F2254TRHAT
MSP430F2272IDA
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DA
38
40
40
38
38
40
40
38
38
40
40
38
38
40
40
38
38
40
40
38
38
40
40
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
QFN
RHA
RHA
DA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
QFN
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RHA
RHA
DA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
QFN
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MSP430F2272IDAR
MSP430F2272IRHAR
MSP430F2272IRHAT
MSP430F2272TDA
MSP430F2272TDAR
MSP430F2272TRHAR
MSP430F2272TRHAT
MSP430F2274IDA
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RHA
RHA
DA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
QFN
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RHA
RHA
DA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
QFN
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MSP430F2274IDAR
MSP430F2274IRHAR
MSP430F2274IRHAT
MSP430F2274TDA
MSP430F2274TDAR
MSP430F2274TRHAR
MSP430F2274TRHAT
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RHA
RHA
DA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TSSOP
TSSOP
QFN
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
DA
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
RHA
RHA
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2007
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
IMPORTANT NOTICE
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