MSP430F110_技术文档

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

D

Low Supply Voltage Range 1.8 V to 3.6 V

D

Family Members Include:

MSP430F110: 1KB + 128B Flash Memory

128B RAM

MSP430F112: 4KB + 256B Flash Memory

256B RAM

Available in a 20-Pin Plastic Small-Outline

Wide Body (SOWB) Package and 20-Pin

Plastic Thin Shrink Small-Outline Package

(TSSOP)

Ultralow-Power Consumption:

− Active Mode: 200 µA at 1 MHz, 2.2 V

− Standby Mode: 0.8 µA

− Off Mode (RAM Retention): 0.1 µA

Wake-Up From Standby Mode in less

than 6 µs

16-Bit RISC Architecture, 125 ns

Instruction Cycle Time

D

For Complete Module Descriptions, Refer

to the MSP430x1xx Family User’s Guide,

Literature Number SLAU049

Basic Clock Module Configurations:

− Various Internal Resistors

− Single External Resistor

− 32 kHz Crystal

− High Frequency Crystal

− Resonator

DW OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

TEST

P1.7/TA2/TDO/TDI

P1.6/TA1/TDI

P1.5/TA0/TMS

P1.4/SMCLK/TCK

P1.3/TA2

P1.2/TA1

P1.1/TA0

P1.0/TACLK

P2.4/TA2

P2.3/TA1

V

− External Clock Source

CC

P2.5/R

osc

D

16-Bit Timer_A With Three

Capture/Compare Registers

V

SS

XOUT/TCLK

XIN

Serial Onboard Programming,

No External Programming Voltage

Needed

RST/NMI

P2.0/ACLK

P2.1/INCLK

P2.2/TA0

description

The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low power

modes is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.

The MSP430F11x series is an ultralow-power mixed signal microcontroller with a built in 16-bit timer and

fourteen I/O pins.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then

process the data and display them or transmit them to a host system. Stand alone RF sensor front-end is another

area of application.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  1999 − 2004, Texas Instruments Incorporated

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1

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC

20-PIN SOWB

(DW)

PLASTIC

20-PIN TSSOP

(PW)

T

A

MSP430F110IDW

MSP430F112IDW

MSP430F110IPW

MSP430F112IPW

−40°C to 85°C

functional block diagram

P1

XIN XOUT

V

RST/NMI

P2

V

CC

SS

JTAG

8

6

R

OSC

Oscillator

ACLK

4KB Flash

1KB Flash

256B RAM

128B RAM

I/O Port 1

8 I/Os, with 6 I/Os, with

Interrupt

Capability

I/O Port 2

System

Clock

SMCLK

Interrupt

Capability

MCLK

MAB,

4 Bit

Test

MAB,M1A6BB,it16-Bit

JTAG

CPU

MCB

Incl. 16 Reg.

Bus

Conv

MDB, 16-Bit

MDB, 16 Bit

MDB, 8 Bit

TEST

†

Watchdog

Timer

Timer_A3

3 CC Reg

POR

15/16-Bit

†

A pulldown resistor of 30 kΩ is needed on F11x devices.

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

Terminal Functions

TERMINAL

NAME

P1.0/TACLK

I/O

DESCRIPTION

NO.

13

14

15

16

17

I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input

P1.1/TA0

I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit

I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output

I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output

P1.2/TA1

P1.3/TA2

P1.4/SMCLK/TCK

I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming

and test

P1.5/TA0/TMS

18

I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for

device programming and test

P1.6/TA1/TDI

19

20

I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal

†

P1.7/TA2/TDO/TDI

I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input

during programming

P2.0/ACLK

P2.1/INCLK

P2.2/TA0

8

9

I/O General-purpose digital I/O pin/ACLK output

I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK

10

11

12

3

I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0 output/BSL receive

I/O General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1 output

I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output

P2.3/TA1

P2.4/TA2

P2.5/R

OSC

I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency

RST/NMI

TEST

7

I

Reset or nonmaskable interrupt input

Selects test mode for JTAG pins on Port1. Must be tied low with less than 30 kΩ.

Supply voltage

1

V

2

CC

4

Ground reference

SS

XIN

6

I

Input terminal of crystal oscillator

XOUT/TCLK

5

I/O Output terminal of crystal oscillator or test clock input

†

TDO or TDI is selected via JTAG instruction.

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

short-form description

CPU

Program Counter

Stack Pointer

PC/R0

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in

conjunction with seven addressing modes for

source operand and four addressing modes for

destination operand.

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3

R4

General-Purpose Register

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

register-to-register operation execution time is

one cycle of the CPU clock.

R5

R6

R7

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator respectively. The

remaining registers are general-purpose

registers.

R8

R9

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled

with all instructions.

R10

R11

instruction set

R12

R13

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 1 shows examples of the three types of

instruction formats; the address modes are listed

in Table 2.

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

e.g. ADD R4,R5

R4 + R5 −−−> R5

e.g. CALL

e.g. JNE

R8

PC −−>(TOS), R8−−> PC

Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE

Register

S

D

SYNTAX

MOV Rs,Rd

EXAMPLE

MOV R10,R11

MOV 2(R5),6(R6)

OPERATION

D D

R10 −−> R11

Indexed

D D

MOV X(Rn),Y(Rm)

MOV EDE,TONI

M(2+R5)−−> M(6+R6)

M(EDE) −−> M(TONI)

M(MEM) −−> M(TCDAT)

M(R10) −−> M(Tab+R6)

Symbolic (PC relative) D D

Absolute

Indirect

D D MOV &MEM,&TCDAT

D

MOV @Rn,Y(Rm)

MOV @Rn+,Rm

MOV #X,TONI

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

Indirect

autoincrement

M(R10) −−> R11

R10 + 2−−> R10

Immediate

#45 −−> M(TONI)

NOTE: S = source

D = destination

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the five low-power modes, service the request and restore back to

the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D

Active mode AM;

All clocks are active

Low-power mode 0 (LPM0);

−

CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

D

Low-power mode 1 (LPM1);

−

CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

DCO’s dc-generator is disabled if DCO not used in active mode

Low-power mode 2 (LPM2);

−

CPU is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator remains enabled

ACLK remains active

D

Low-power mode 3 (LPM3);

−

CPU is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator is disabled

ACLK remains active

Low-power mode 4 (LPM4);

−

CPU is disabled

ACLK is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator is disabled

Crystal oscillator is stopped

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the memory with an address range of

0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction

sequence.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up

External reset

Watchdog

WDTIFG (Note1)

KEYV (Note 1)

Reset

0FFFEh

15, highest

NMI

Oscillator fault

Flash memory access violation

(non)-maskable,

(non)-maskable

NMIIFG (Notes 1 and 5)

OFIFG (Notes 1 and 5)

ACCVIFG (Notes 1 and 5)

0FFFCh

14

0FFFAh

0FFF8h

0FFF6h

0FFF4h

13

12

11

10

Watchdog timer

Timer_A3

WDTIFG

maskable

TACCR0 CCIFG

(Note 2)

0FFF2h

9

TACCR1 and TACCR2

CCIFGs, TAIFG

Timer_A3

maskable

0FFF0h

8

(Notes 1 and 2)

0FFEEh

0FFECh

0FFEAh

0FFE8h

7

6

5

4

I/O Port P2

(eight flags − see Note 3)

P2IFG.0 to P2IFG.7

(Notes 1 and 2)

maskable

0FFE6h

0FFE4h

3

2

I/O Port P1

(eight flags)

P1IFG.0 to P1IFG.7

(Notes 1 and 2)

0FFE2h

0FFE0h

1

0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module

3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’11x devices.

4. Nonmaskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.

5. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

that are not allocated to a functional purpose are not physically present in the device. Simple software access

is provided with this arrangement.

interrupt enable 1 and 2

7

6

5

4

3

2

1

0

Address

0h

OFIE

WDTIE

ACCVIE

NMIIE

rw-0

WDTIE:

Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer

is configured in interval timer mode.

OFIE:

Oscillator fault enable

NMIIE:

ACCVIE:

Nonmaskable interrupt enable

Flash access violation interrupt enable

7

6

5

4

3

2

1

0

Address

01h

interrupt flag register 1 and 2

7

6

5

4

1

0

Address

02h

NMIIFG

OFIFG

WDTIFG

rw-0

rw-1

rw-(0)

WDTIFG:

Set on Watchdog Timer overflow (in watchdog mode) or security key violation.

Reset on V power-up or a reset condition at RST/NMI pin in reset mode.

Flag set on oscillator fault

Set via RST/NMI-pin

CC

OFIFG:

NMIIFG:

7

6

5

4

3

2

1

0

Address

03h

Legend rw:

Bit can be read and written.

rw-0,1:

Bit can be read and written. It is Reset or Set by PUC.

Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device.

rw-(0,1):

7

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

memory organization

MSP430F110

MSP430F112

Int. Vector

FFFFh

FFE0h

FFFFh

Int. Vector

FFE0h

FFDFh

1 KB Flash

Segment0,1

FFDFh

4 KB

Flash

Segment0−7

Main

FC00h

Memory

F000h

10FFh

1080h

128B Flash

SegmentA

2 × 128B

Flash

SegmentA,B

Information

Memory

1000h

0FFFh

0C00h

1 KB

Boot ROM

0C00h

02FFh

256B RAM

027Fh

128B RAM

16b Per.

8b Per.

SFR

0200h

01FFh

0200h

01FFh

0100h

00FFh

0010h

000Fh

0000h

16b Per.

8b Per.

SFR

0100h

00FFh

0010h

000Fh

0000h

bootstrap loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial

interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete

description of the features of the BSL and its implementation, see the Application report Features of the MSP430

Bootstrap Loader, Literature Number SLAA089.

BSL Function

Data Transmit

Data Receive

DW & PW Package Pins

14 - P1.1

10 - P2.2

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The

CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D

Flash memory has n segments of main memory and two segments of information memory (A and B) of 128

bytes each. Each segment in main memory is 512 bytes in size.

D

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A and B can be erased individually, or as a group with segments 0−n.

Segments A and B are also called information memory.

D

New devices may have some bytes programmed in the information memory (needed for test during

manufacturing). The user should perform an erase of the information memory prior to the first use.

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

flash memory (continued)

0FFFFh

0FE00h

Segment0 w/

Interrupt Vectors

0FDFFh

0FC00h

Segment1

Segment2

Segment3

Segment4

Segment5

Segment6

Segment7

SegmentA

SegmentB

0FBFFh

0FA00h

0F9FFh

0F800h

0F7FFh

0F600h

0F5FFh

0F400h

0F3FFh

0F200h

0F1FFh

0F000h

010FFh

01080h

0107Fh

01000h

NOTE: All segments not implemented on all devices.

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using

all instructions. For complete module descriptions, refer to the MSP430x1xx Family User’s Guide, literature

number SLAU049.

oscillator and system clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock

module is designed to meet the requirements of both low system cost and low-power consumption. The internal

DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the

following clock signals:

D

Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.

Main clock (MCLK), the system clock used by the CPU.

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

digital I/O

There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external

pins):

D

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of port P2.

Read/write access to port-control registers is supported by all instructions.

NOTE:

Six bits of port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for port

P2 are implemented.

watchdog timer

The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_A3 Signal Connections

Input Pin Number Device Input Signal Module Input Name

Module Block

Module Output Signal

Output Pin Number

13 - P1.0

TACLK

ACLK

SMCLK

INCLK

TA0

TACLK

ACLK

Timer

NA

SMCLK

INCLK

CCI0A

CCI0B

GND

9 - P2.1

14 - P1.1

10 - P2.2

14 - P1.1

18 - P1.5

10 - P2.2

TA0

CCR0

CCR1

CCR2

TA0

TA1

TA2

DV

SS

CC

DV

V

CC

15 - P1.2

11 - P2.3

TA1

CCI1A

CCI1B

GND

15 - P1.2

19 - P1.6

11 - P2.3

DV

SS

DV

V

CC

16 - P1.3

TA2

ACLK (internal)

CCI2A

CCI2B

GND

16 - P1.3

20 - P1.7

12 - P2.4

DV

SS

V

CC

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

peripheral file map

PERIPHERALS WITH WORD ACCESS

Timer_A

Reserved

Capture/compare register

Timer_A register

Reserved

Capture/compare control

Timer_A control

Timer_A interrupt vector

017Eh

017Ch

017Ah

0178h

0176h

0174h

0172h

0170h

016Eh

016Ch

016Ah

0168h

0166h

0164h

0162h

0160h

012Eh

TACCR2

TACCR1

TACCR0

TAR

TACCTL2

TACCTL1

TACCTL0

TACTL

TAIV

Flash Memory

Flash control 3

Flash control 2

Flash control 1

FCTL3

FCTL2

FCTL1

012Ch

012Ah

0128h

Watchdog

Watchdog/timer control

WDTCTL

0120h

PERIPHERALS WITH BYTE ACCESS

Basic Clock

Basic clock sys. control2

Basic clock sys. control1

DCO clock freq. control

BCSCTL2 058h

BCSCTL1 057h

DCOCTL

056h

Port P2

Port P2 selection

P2SEL

P2IE

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

Port P2 interrupt enable

Port P2 interrupt edge select

Port P2 interrupt flag

Port P2 direction

Port P2 output

Port P2 input

P2IES

P2IFG

P2DIR

P2OUT

P2IN

Port P1

Port P1 selection

P1SEL

P1IE

026h

025h

024h

023h

022h

021h

020h

Port P1 interrupt enable

Port P1 interrupt edge select

Port P1 interrupt flag

Port P1 direction

Port P1 output

Port P1 input

P1IES

P1IFG

P1DIR

P1OUT

P1IN

Special Function

SFR interrupt flag2

SFR interrupt flag1

SFR interrupt enable2

SFR interrupt enable1

IFG2

IFG1

IE2

003h

002h

001h

000h

IE1

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

†

absolute maximum ratings

Voltage applied at V

to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V

CC

SS

Voltage applied to any pin (referenced to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V

Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA

SS

CC

Storage temperature, T (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

stg

Storage temperature, T (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltages referenced to V

.

SS

recommended operating conditions

MIN

1.8

NOM

MAX UNITS

Supply voltage during program execution, V

CC

(see Note 1)

3.6

V

Supply voltage during program/erase flash memory, V

CC

2.7

Supply voltage, V

SS

0

V

Operating free-air temperature range, T

−40

85

°C

Hz

A

LF mode selected, XTS=0

Watch crystal

Ceramic resonator

Crystal

32768

LFXT1 crystal frequency,

(see Note 2)

450

1000

dc

8000

f

(LFXT1)

XT1 mode selected, XTS=1

kHz

8000

V

CC

V

CC

V

CC

= 1.8 V

= 2.2 V

= 3.6 V

2

5

8

MHz

Processor frequency f

(system)

(MCLK signal)

dc

NOTES: 1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 MΩ from XOUT to V

SS

when V <2.5 V.

CC

The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at V

The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at V

≥ 2.2 V.

≥ 2.8 V.

CC

2. The LFXT1 oscillator in LF-mode requires a watch crystal. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or crystal.

MSP430F11x Devices

9

8

7

6

5

4

3

2

8 MHz at

3.6 V

5 MHz at

2.2 V

2 MHz at

1.8 V

1

0

1

2

3

4

V

CC

− Supply Voltage − V

NOTE: Minimum processor frequency is defined by system clock. Flash

program or erase operations require a minimum V of 2.7 V.

CC

Figure 1. Frequency vs Supply Voltage

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

supply current (into V ) excluding external current

CC

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

T

= −40°C +85°C,

V

= 2.2 V

= 3 V

200

300

250

350

A

CC

µA

f

= f

= 1 MHz,

(MCLK) (SMCLK)

CC

= 32,768 Hz

f(ACLK)

I

Active mode

(AM)

V

= 2.2 V

= 3 V

1.6

3

T

= −40°C +85°C,

CC

A

µA

f

= f

= 4096 Hz

4.3

(MCLK) (SMCLK) (ACLK)

CC

T

= −40°C +85°C,

V

CC

V

CC

V

CC

V

CC

= 2.2 V

= 3 V

32

55

11

17

45

70

14

22

A

I

Low-power mode, (LPM0)

Low-power mode, (LPM2)

f

= 0, f

= 32,768 Hz

= 1 MHz,

(CPUOff)

(MCLK)

(SMCLK)

f(ACLK)

T

= −40°C +85°C,

= 2.2 V

= 3 V

A

µA

f

= f

= 0 MHz,

(LPM2)

(MCLK) (SMCLK)

= 32,768 Hz, SCG0 = 0

f(ACLK)

T

A

= −40°C

0.8

0.7

1.6

1.8

1.6

2.3

0.1

0.8

1.2

1

T

A

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

V

= 2.2 V

= 3 V

CC

T

A

2.3

2.2

1.9

3.4

0.5

1.9

I

Low-power mode, (LPM3)

(LPM3)

(LPM4)

T

A

T

A

µA

CC

T

A

T

A

f

= 0 MHz

= 0 MHz,

(MCLK)

(SMCLK)

I

Low-power mode, (LPM4)

T

A

V

= 2.2 V/3 V

CC

= 0 Hz, SCG0 = 1

f(ACLK)

T

A

NOTE: All inputs are tied to 0 V or V . Outputs do not source or sink any current.

CC

current consumption of active mode versus system frequency, F version

= I × f [MHz]

I

AM

AM[1 MHz]

system

current consumption of active mode versus supply voltage, F version

= I + 120 µA/V × (V −3 V)

I

AM

AM[3 V]

CC

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5

PARAMETER

TEST CONDITIONS

MIN

1.1

1.5

0.4

.90

0.3

0.5

TYP

MAX

1.3

1.8

0.9

1.2

1

UNIT

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2.2 V

= 3 V

V

IT+

V

IT−

V

hys

Positive-going input threshold voltage

V

= 2.2 V

= 3 V

Negative-going input threshold voltage

V

= 2.2 V

= 3 V

Input voltage hysteresis, (V

IT+

− V )

IT−

1.4

standard inputs − RST/NMI; TCK, TMS, TDI

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

Low-level input voltage

High-level input voltage

V

SS

V

+0.6

SS

IL

V

CC

= 2.2 V / 3 V

0.8×V

V

CC

V

IH

CC

inputs Px.x, TAx

PARAMETER

TEST CONDITIONS

V

CC

MIN

TYP

MAX

UNIT

2.2 V/3 V

2.2 V

3 V

1.5

62

50

1.5

62

50

cycle

Port P1, P2: P1.x to P2.x, External trigger signal

for the interrupt flag, (see Note 1)

t

External interrupt timing

Timer_A, capture timing

(int)

ns

cycle

ns

2.2 V/3 V

2.2 V

3 V

t

TA0, TA1, TA2 (see Note 2)

(cap)

2.2 V

3 V

8

10

8

Timer_A clock frequency

externally applied to pin

f

TACLK, INCLK t

= t

MHz

(TAext)

(H) (L)

2.2 V

3 V

Timer_A clock frequency

SMCLK or ACLK signal selected

(TAint)

10

NOTES: 1. The external signal sets the interrupt flag every time the minimum t

cycle and time parameters are met. It may be set even with

(int)

. Both the cycle and timing specifications must be met to ensure the flag is set. t

trigger signals shorter than t

MCLK cycles.

is measured in

(int)

2. The external capture signal triggers the capture event every time the mimimum t

cycle and time parameters are met. A capture

(cap)

may be triggered with capture signals even shorter than t . Both the cycle and timing specifications must be met to ensure a

(cap)

correct capture of the 16-bit timer value and to ensure the flag is set.

leakage current

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Port P1: P1.x, 0 ≤ × ≤ 7

(see Notes 1 and 2)

V

CC

= 2.2 V/3 V,

50

I

High-impedance leakage current

nA

lkg(Px.x)

Port P2: P2.x, 0 ≤ × ≤ 5

(see Notes 1 and 2)

V

CC

= 2.2 V/3 V,

50

NOTES: 1. The leakage current is measured with V

SS

or V applied to the corresponding pin(s), unless otherwise noted.

CC

2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional

pullup or pulldown resistor.

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

outputs Port 1 to Port 2; P1.0 to P1.7, P2.0 to P2.5

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I

= −1.5 mA

= −6 mA

= −1.5 mA

= −6 mA

= −1 mA

= −3.4 mA

= −1 mA

= −3.4 mA

= 1.5 mA

= 6 mA

See Note 1

See Note 2

See Note 1

See Note 2

See Note 3

See Note 1

See Note 2

See Note 1

See Note 2

V

−0.25

V

(OHmax)

(OLmax)

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2.2 V

= 3 V

V

−0.6

CC

−0.25

High-level output voltage

Port 1

V

OH

V

OH

V

OL

V

CC

V

−0.6

CC

−0.25

V

CC

= 2.2 V

= 3 V

V

−0.6

CC

−0.25

High-level output voltage

Port 2

V

CC

V

−0.6

CC

V

+0.25

SS

= 2.2 V

= 3 V

V

+0.6

SS

Low-level output voltage

Port 1 and Port 2

= 1.5 mA

= 6 mA

V

SS

+0.25

V

+0.6

SS

NOTES: 1. The maximum total current, I

drop specified.

and I

, for all outputs combined, should not exceed 12 mA to hold the maximum voltage

OHmax

OLmax

2. The maximum total current, I

drop specified.

and I

, for all outputs combined, should not exceed 48 mA to hold the maximum voltage

OHmax

3. One output loaded at a time.

outputs P1.x, P2.x, TAx

PARAMETER

TEST CONDITIONS

P2.0/ACLK, C = 20 pF

V

MIN

TYP

MAX

UNIT

CC

f

2.2 V/3 V

f

(P20)

L

System

TA0, TA1, TA2, C = 20 pF

L

Internal clock source, SMCLK signal applied

(See Note 1)

Output frequency

MHz

2.2 V/3 V

dc

(TAx)

System

f

= f

40%

35%

60%

65%

SMCLK LFXT1 XT1

f

= f

SMCLK

LFXT1 LF

2.2 V/3 V

P1.4/SMCLK, C = 20 pF

L

50%−

15 ns

50%+

15 ns

f

50%

LFXT1/n

DCOCLK

50%−

15 ns

50%+

15 ns

t

Duty cycle of O/P

frequency

(Xdc)

= f

SMCLK

f

= f

40%

30%

60%

70%

P20 LFXT1 XT1

= f

P2.0/ACLK, C = 20 pF

L

2.2 V/3 V

P20

LFXT1 LF

50%

0

LFXT1/n

TA0, TA1, TA2, C = 20 pF, Duty cycle = 50%

50

ns

(TAdc)

L

NOTE 1: The limits of the system clock MCLK have to be met. MCLK and SMCLK can have different frequencies.

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

PUC/POR

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

250

1.8

UNIT

µs

V

t

150

(POR_Delay)

T

= −40°C

= 25°C

= 85°C

1.4

1.1

0.8

0

A

V

POR

T

A

1.5

V

CC

= 2.2 V/3 V

T

A

1.2

V

(min)

0.4

V

t

PUC/POR

Reset is accepted internally

2

µs

(reset)

V

VCC

V

POR

No POR

POR

V

(min)

t

Figure 2. Power-On Reset (POR) vs Supply Voltage

2.0

1.8

1.6

1.5

Max

1.4

1.2

Min

1.0

0.8

0.6

0.4

0.2

1.1

0.8

25°C

0

−40

−20

0

20

40

60

80

Temperature [°C]

Figure 3. V

vs Temperature

POR

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

wake-up from lower power modes (LPMx)

PARAMETER

TEST CONDITIONS

= 2.2 V/3 V

MIN

TYP

100

MAX

UNIT

t

V

(LPM0)

CC

ns

= 2.2 V/3 V

(LPM2)

CC

f

= 1 MHz,

= 2 MHz,

= 3 MHz,

V

= 2.2 V/3 V

6

(MCLK)

CC

t

µs

(LPM3)

Delay time (see Note 1)

f

= 1 MHz,

= 2 MHz,

= 3 MHz,

V

CC

V

CC

V

CC

= 2.2 V/3 V

6

(MCLK)

(LPM4)

NOTE 1: Parameter applicable only if DCOCLK is used for MCLK.

RAM

PARAMETER

MIN

1.6

TYP

MAX

UNIT

V

CPU halted (see Note 1)

V

(RAMh)

NOTE 1: This parameter defines the minimum supply voltage V

when the data in the program memory RAM remains unchanged. No program

CC

execution should happen during this supply voltage condition.

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

DCO

PARAMETER

TEST CONDITIONS

MIN

0.08

0.14

0.22

0.37

0.61

TYP

0.12

0.13

0.19

0.18

0.30

0.28

0.49

0.47

0.77

0.75

MAX

0.15

0.16

0.23

0.22

0.36

0.34

0.59

0.56

0.93

0.9

UNIT

V

= 2.2 V

= 3 V

CC

f

R

= 0, DCO = 3, MOD = 0, DCOR = 0,

= 1, DCO = 3, MOD = 0, DCOR = 0,

= 2, DCO = 3, MOD = 0, DCOR = 0,

T

A

= 25°C

MHz

(DCO03)

(DCO13)

(DCO23)

sel

= 2.2 V

= 3 V

T

A

MHz

= 2.2 V

= 3 V

T

A

= 2.2 V

= 3 V

f

R

= 3, DCO = 3, MOD = 0, DCOR = 0,

= 4, DCO = 3, MOD = 0, DCOR = 0,

= 5, DCO = 3, MOD = 0, DCOR = 0,

= 6, DCO = 3, MOD = 0, DCOR = 0,

= 7, DCO = 3, MOD = 0, DCOR = 0,

T

A

= 25°C

MHz

(DCO33)

(DCO43)

(DCO53)

(DCO63)

(DCO73)

sel

= 2.2 V

= 3 V

T

A

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2.2 V

= 3 V

1

1.2

1.3

1.9

2.0

2.9

3.2

4.5

4.9

1.5

T

A

= 2.2 V

= 3 V

1.6

1.69

2.4

2.7

4

2.2

T

A

2.29

3.4

= 2.2 V

= 3 V

T

A

3.65

4.9

= 2.2 V

= 3 V

f

R

= 7, DCO = 7, MOD = 0, DCOR = 0,

= 4, DCO = 7, MOD = 0, DCOR = 0,

T

A

= 25°C

MHz

ratio

(DCO77)

(DCO47)

sel

4.4

5.4

F

DCO40

x1.7

DCO40

x2.1

DCO40

x2.5

f

T

A

V

CC

= 2.2 V/3 V

S

= f

/f

DCO DCO+1 DCO

V

CC

V

CC

V

CC

V

CC

= 2.2 V/3 V

= 2.2 V

1.35

1.07

1.65

1.12

2

1.16

(Rsel)

R

Rsel+1 Rsel

S

= f /f

(DCO)

−0.31

−0.33

−0.36

−0.38

−0.40

−0.43

Temperature drift, R

(see Note 1)

= 4, DCO = 3, MOD = 0

sel

D

%/°C

t

= 3 V

Drift with V

CC

(see Note 1)

variation, R = 4, DCO = 3, MOD = 0

sel

V

CC

= 2.2 V/3 V

0

5

10

%/V

V

NOTE 1: These parameters are not production tested.

Max

f

(DCOx7)

(DCOx0)

Min

Max

Min

0

1

2

3

4

5

6

7

2.2 V

3 V

V

CC

DCO Steps

Figure 4. DCO Characteristics

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (continued)

main DCO characteristics

D

Individual devices have a minimum and maximum operation frequency. The specified parameters for

to f are valid for all devices.

f

DCOx0)

DCOx7)

(

D

All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.

DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter S

.

DCO

Modulation control bits MOD0 to MOD4 select how often f

is used within the period of 32 DCOCLK

DCO+1)

(

cycles. The frequency f

is used for the remaining cycles. The frequency is an average equal to:

(DCO)

32 f_(DCO) f_(DCO)1)

f_average

+

MOD f_(DCO))(32*MOD) f_(DCO)1)

crystal oscillator, LFXT1

PARAMETER

TEST CONDITIONS

XTS=0; LF mode selected.

= 2.2 V / 3 V

MIN

TYP

MAX

UNIT

12

V

CC

XTS=1; XT1 mode selected.

= 2.2 V / 3 V (Note 1)

C

Input capacitance

pF

XIN

2

12

2

V

CC

XTS=0; LF mode selected.

= 2.2 V / 3 V

V

CC

Output capacitance

Input levels at XIN

pF

V

XOUT

XTS=1; XT1 mode selected.

V

= 2.2 V / 3 V (Note 1)

CC

V

SS

0.2×V

IL

CC

= 2.2 V/3 V (see Note 2)

CC

0.8×V

V

CC

IH

CC

NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.

2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

19

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

Flash Memory

TEST

CONDITIONS

PARAMETER

V

CC

MIN NOM

MAX

UNIT

V

CC(PGM/

ERASE)

Program and Erase supply voltage

Flash Timing Generator frequency

2.7

3.6

V

f

I

t

257

476

5

kHz

mA

FTG

Supply current from DV

during program

during erase

2.7 V/ 3.6 V

3

PGM

CC

3

5

mA

ERASE

CPT

CC

Cumulative program time

see Note 1

see Note 2

4

ms

Cumulative mass erase time

Program/Erase endurance

Data retention duration

200

ms

CMErase

4

5

10

100

cycles

years

t

T = 25°C

J

Retention

t

Word or byte program time

35

30

Word

st

Block program time for 1 byte or word

Block, 0

Block program time for each additional byte or word

Block program end-sequence wait time

Mass erase time

21

Block, 1-63

Block, End

Mass Erase

Seg Erase

see Note 3

t

FTG

6

5297

4819

Segment erase time

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f

,max = 5297x1/476kHz). To

FTG

achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.

(A worst case minimum of 19 cycles are required).

3. These values are hardwired into the Flash Controller’s state machine (t

FTG

= 1/f

FTG

).

JTAG Interface

TEST

CONDITIONS

PARAMETER

V

CC

MIN NOM

MAX

UNIT

2.2 V

3 V

0

5

10

90

MHz

kΩ

f

TCK input frequency

see Note 1

TCK

R

Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2

may be restricted to meet the timing requirements of the module selected.

2.2 V/ 3 V

25

60

Internal

NOTES: 1. f

TCK

2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.

20

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic

Port P1, P1.0 to P1.3, input/output with Schmitt-trigger

P1SEL.x

0

P1DIR.x

1

0

Direction Control

From Module

Pad Logic

P1.0 − P1.3

P1OUT.x

1

Module X OUT

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

Interrupt

Edge

Select

EN

Q

P1IFG.x

Set

Interrupt

Flag

P1IES.x

P1SEL.x

NOTE: x = Bit/identifier, 0 to 3 for port P1

Direction

PnSel.x

PnDIR.x

control from

module

PnOUT.x

Module X OUT

PnIN.x

Module X IN

PnIE.x

PnIFG.x

PnIES.x

†

P1Sel.0

P1Sel.1

P1Sel.2

P1Sel.3

P1DIR.0

P1DIR.1

P1DIR.2

P1DIR.3

P1DIR.0

P1DIR.1

P1DIR.2

P1DIR.3

P1OUT.0

P1OUT.1

P1OUT.2

P1OUT.3

V

P1IN.0

P1IN.1

P1IN.2

P1IN.3

TACLK

P1IE.0

P1IE.1

P1IE.2

P1IE.3

P1IFG.0

P1IFG.1

P1IFG.2

P1IFG.3

P1IES.0

P1IES.1

P1IES.2

P1IES.3

SS

†

Out0 signal

Out1 signal

Out2 signal

CCI0A

CCI1A

CCI2A

†

Signal from or to Timer_A

21

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features

P1SEL.x

0

P1DIR.x

1

Direction Control

From Module

0

Pad Logic

P1OUT.x

P1.4−P1.7

1

Module X OUT

TST

Bus Keeper

P1IN.x

EN

D

Module X IN

TEST

TST

Fuse

P1IRQ.x

P1IE.x

P1IFG.x

Interrupt

Edge

Select

60 kΩ

Typical

EN

Set

Q

GND

Fuse

Blow

Interrupt

Flag

Control By JTAG

P1IES.x

NOTE: Fuse not implemented

in F11x

TST

Control

P1SEL.x

P1.x

TDO

Controlled By JTAG

P1.7/TDI/TDO

P1.x

Controlled by JTAG

TDI

TST

P1.6/TDI/TCLK

P1.x

NOTE: The test pin should be protected from potential EMI

and ESD voltage spikes. This may require a smaller

external pulldown resistor in some applications.

TMS

TCK

P1.5/TMS

P1.x

x = Bit identifier, 4 to 7 for port P1

TST

During programming activity and during blowing

the fuse, the pin TDO/TDI is used to apply the test

input for JTAG circuitry.

P1.4/TCK

Direction

PnSel.x

PnDIR.x

control from

module

PnOUT.x

Module X OUT

SMCLK

PnIN.x

Module X IN

PnIE.x

PnIFG.x

PnIES.x

P1Sel.4

P1Sel.5

P1Sel.6

P1Sel.7

P1DIR.4

P1DIR.5

P1DIR.6

P1DIR.7

P1DIR.4

P1DIR.5

P1DIR.6

P1DIR.7

P1OUT.4

P1OUT.5

P1OUT.6

P1OUT.7

P1IN.4

P1IN.5

P1IN.6

P1IN.7

unused

P1IE.4

P1IE.5

P1IE.6

P1IE.7

P1IFG.4

P1IFG.5

P1IFG.6

P1IFG.7

P1IES.4

P1IES.5

P1IES.6

P1IES.7

†

Out0 signal

Out1 signal

Out2 signal

†

Signal from or to Timer_A

22

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

Port P2, P2.0 to P2.4, input/output with Schmitt-trigger

P2SEL.x

0

P2DIR.x

0: Input

1: Output

1

Direction Control

From Module

Pad Logic

0

1

P2.0 − P2.4

P2OUT.x

Module X OUT

P2IN.x

EN

D

Module X IN

P2IRQ.x

P2IE.x

Interrupt

Edge

Select

EN

Q

P2IFG.x

Set

Interrupt

Flag

P2IES.x

P2SEL.x

NOTE: x = Bit Identifier, 0 to 4 For Port P2

PnSel.x

PnDIR.x

Direction

control from

module

PnOUT.x

Module X

OUT

PnIN.x

Module X

PnIE.x

PnIFG.x

PnIES.x

IN

P2Sel.0

P2Sel.1

P2Sel.2

P2Sel.3

P2Sel.4

P2DIR.0

P2DIR.1

P2DIR.2

P2DIR.3

P2DIR.4

P2DIR.0

P2DIR.1

P2DIR.2

P2DIR.3

P2DIR.4

P2OUT.0

P2OUT.1

P2OUT.2

P2OUT.3

P2OUT.4

ACLK

P2IN.0

P2IN.1

P2IN.2

P2IN.3

P2IN.4

unused

P2IE.0

P2IE.1

P2IE.2

P2IE.3

P2IE.4

P2IFG.0

P2IFG.1

P2IFG.2

P2IFG.3

P2IFG.4

P1IES.0

P1IES.1

P1IES.2

P1IES.3

P1IES.4

†

V

SS

INCLK

CCI0B

CCI1B

†

Out0 signal

Out1 signal

Out2 signal

unused

†

Signal from or to Timer_A

23

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

Port P2, P2.5, input/output with Schmitt-trigger and R

function for the Basic Clock module

OSC

P2SEL.5

0: Input

Pad Logic

0

1: Output

P2DIR.5

1

Direction Control

From Module

0

1

P2.5

P2OUT.5

Module X OUT

Bus Keeper

P2IN.5

EN

D

Module X IN

P2IRQ.5

Internal to

Basic Clock

Module

P2IE.5

Interrupt

Edge

Select

1

0

V

CC

EN

Q

P2IFG.5

Set

Interrupt

Flag

P2IES.5

DC

Generator

DCOR

P2SEL.5

CAPD.5

NOTE: DCOR: Control bit from basic clock module if it is set, P2.5 Is disconnected from P2.5 pad

Direction

PnSel.x

PnDIR.x

control from

module

PnOUT.x

Module X OUT

PnIN.x

Module X IN

PnIE.x

P2IE.5

PnIFG.x

P2IFG.5

PnIES.x

P2IES.5

P2Sel.5

P2DIR.5

P2OUT.5

V

SS

P2IN.5

unused

24

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

Port P2, unbonded bits P2.6 and P2.7

P2SEL.x

P2DIR.x

0: Input

1: Output

0

1

Direction Control

From Module

0

1

P2OUT.x

Module X OUT

P2IN.x

Node Is Reset With PUC

Bus Keeper

EN

Module X IN

D

P2IRQ.x

P2IE.x

PUC

Interrupt

Edge

Select

EN

Set

Q

P2IFG.x

Interrupt

Flag

P2IES.x

P2SEL.x

NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins

Direction

P2Sel.x

P2DIR.x

control from

module

P2OUT.x

Module X OUT

P2IN.x

Module X IN

P2IE.x

P2IFG.x

P2IES.x

P2Sel.6

P2Sel.7

P2DIR.6

P2DIR.7

P2DIR.6

P2DIR.7

P2OUT.6

P2OUT.7

V

P2IN.6

P2IN.7

unused

P2IE.6

P2IE.7

P2IFG.6

P2IFG.7

P2IES.6

P2IES.7

SS

NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal

other than from software. They work then as a soft interrupt.

25

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SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

JTAG fuse check mode

The JTAG protection fuse is not implemented in the MSP430F11x devices.

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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型号：	MSP430F110
厂家：	TEXAS INSTRUMENTS
描述：	MIXED SIGNAL MICROCONTROLLER 混合信号微控制器微控制器
文件：	总29页 (文件大小：469K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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