MSP430C413IPM [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430C413IPM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总55页 (文件大小：1196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ
SLAS340G − MAY 2001 − REVISED JUNE 2004
D
D
Low Supply-Voltage Range, 1.8 V . . . 3.6 V
D
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Ultralow-Power Consumption:
− Active Mode: 200 µA at 1 MHz, 2.2 V
− Standby Mode: 0.7 µA
− Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
D
D
Bootstrap Loader in Flash Devices
D
D
Family Members Include:
− MSP430C412: 4KB ROM, 256B RAM
− MSP430C413: 8KB ROM, 256B RAM
− MSP430F412: 4KB + 256B Flash
256B RAM
− MSP430F413: 8KB + 256B Flash
256B RAM
− MSP430F415: 16KB + 256B Flash
512B RAM
Wake-Up From Standby Mode in less
than 6 µs
Frequency-Locked Loop, FLL+
D
D
16-Bit RISC Architecture, 125-ns
Instruction Cycle Time
†
‡
D
16-Bit Timer_A With Three or Five
Capture/Compare Registers
− MSP430F417: 32KB + 256B Flash
1KB RAM
D
D
D
D
Integrated LCD Driver for 96 Segments
On-Chip Comparator
D
D
Available in 64-Pin Quad Flat Pack (QFP)
and 64-pin QFN
Brownout Detector
Supply Voltage Supervisor/Monitor -
Programmable Level Detection on
MSP430F415/417 devices only
For Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide,
Literature Number SLAU056
†
‡
’x412 and ’x413 devices
’F415 and ’F417 devices
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430x41x series are microcontroller configurations with one or two built-in 16-bit timers, a comparator,
96 LCD segment drive capability, and 48 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process the data and transmit them to a host system. The comparator and timer make the configurations ideal
for industrial meters, counter applications, handheld meters, etc.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 64-PIN QFP (PM)
PLASTIC 64-PIN QFN (RTD)
§
MSP430C412IPM
MSP430C413IPM
MSP430F412IPM
MSP430F413IPM
MSP430F415IPM
MSP430F417IPM
MSP430C412IRTD
§
MSP430C413IRTD
MSP430F412IRTD
MSP430F413IRTD
−40°C to 85°C
§
MSP430F415IRTD
MSP430F417IRTD
§
§
Preliminary
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2001 − 2004, Texas Instruments Incorporated
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1
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SLAS340G − MAY 2001 − REVISED JUNE 2004
pin designation, MSP430x412, MSP430x413
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P2.2/S23
P2.3/S22
P2.4/S21
DV
CC
P6.3
P6.4
P6.5
P6.6
P6.7
NC
2
3
4
5
6
7
XIN
8
MSP430x412
MSP430x413
XOUT
NC
9
10
11
NC
P5.1/S0 12
P5.0/S1 13
P4.7/S2 14
P4.6/S3 15
P4.5/S4 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC − No internal connection. External connection to V
recommended.
SS
2
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SLAS340G − MAY 2001 − REVISED JUNE 2004
pin designation, MSP430x415, MSP430x417
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
P1.5/TA0CLK/ACLK
P1.6/CA0
DV
CC
P6.3
P6.4
P6.5
P6.6
P6.7
NC
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3
P1.7/CA1
4
P2.0/TA0.2
P2.1/TA1.1
P5.7/R33
5
6
7
P5.6/R23
P5.5/R13
XIN
8
MSP430x415
MSP430x417
XOUT
9
R03
AV
10
11
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P2.2/TA1.2/S23
P2.3/TA1.3/S22
P2.4/TA1.4/S21
SS2
NC
P5.1/S0 12
P5.0/S1 13
P4.7/S2 14
P4.6/S3 15
P4.5/S4 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC − No internal connection. External connection to V
recommended.
SS
3
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SLAS340G − MAY 2001 − REVISED JUNE 2004
functional block diagram, MSP430x412, MSP430x413
P1
XIN XOUT
DV
RST/NMI
P2
P3
P4
P5
P6
DV
AV
AV
SS
CC
SS
CC
8
8
8
8
8
8
Oscillator
FLL+
ACLK
4KB/8KB
256B RAM
I/O Port 1/2 I/O Port 3/4 I/O Port 5/6
16 I/Os,
with
16 I/Os
16 I/Os
SMCLK
Flash-F41x
ROM-C41x
Interrupt
Capability
MCLK
MAB,
4 Bit
Test
MAB,16-Bit
JTAG
CPU
MCB
Incl. 16 Reg.
Bus
Conv
MDB, 16-Bit
MDB, 8 Bit
4
TMS
TCK
Watchdog
Timer
Timer_A3
3 CC Reg
POR/
SVS/
Brownout
Comparator
A
Basic
Timer 1
LCD
96
Segments
TDI/TCLK
TDO/TDI
15/16-Bit
1 Interrupt
Vector
1,2,3,4 MUX
f
LCD
functional block diagram, MSP430x415, MSP430x417
P1
XIN XOUT
DV
RST/NMI
P2
P3
P4
P5
P6
DV
AV
AV
CC SS1
AV
CC
SS
SS2
8
8
8
8
8
8
Oscillator
FLL+
ACLK
16KB Flash 512B RAM
I/O Port 1/2 I/O Port 3/4 I/O Port 5/6
16 I/Os,
with
16 I/Os
16 I/Os
SMCLK
32KB Flash
1KB RAM
Interrupt
Capability
MCLK
MAB,
4 Bit
Test
MAB,16-Bit
JTAG
CPU
MCB
Incl. 16 Reg.
Bus
Conv
MDB, 16-Bit
MDB, 8 Bit
4
TMS
TCK
Timer1_A5
5 CC Reg
LCD
96
Segments
Watchdog
Timer
Timer0_A3
3 CC Reg
POR/
Multilevel
SVS/
Comparator
A
Basic
Timer 1
TDI/TCLK
TDO/TDI
15/16-Bit
Brownout
1 Interrupt
Vector
1,2,3,4 MUX
f
LCD
4
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SLAS340G − MAY 2001 − REVISED JUNE 2004
Terminal Functions
MSP430x412, MSP430x413
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AV
AV
64
Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD
resistive divider circuitry; must not power up prior to DV
CC
.
CC
Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A. Needs to be externally
connected to DV
62
SS
.
SS
DV
DV
1
Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AV
.
CC
SS
CC
Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
AV /AV
63
.
CC SS
NC
7, 10, 11
53
Not internally connected. Connection to V
recommended.
SS
P1.0/TA0
I/O
I/O
General-purpose digital I/O/Timer_A. Capture: CCI0A input, compare: Out0 output/BSL transmit
P1.1/TA0/MCLK
52
General-purpose digital I/O/Timer_A. Capture: CCI0B input/MCLK output. Note: TA0 is only an input
on this pin/BSL receive
P1.2/TA1
51
50
49
48
47
46
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O/Timer_A, capture: CCI1A input, compare: Out1 output
General-purpose digital I/O/SVS: output of SVS comparator
General-purpose digital I/O
P1.3/SVSOUT
P1.4
P1.5/TACLK/ ACLK
P1.6/CA0
General-purpose digital I/O/input of Timer_A clock/output of ACLK
General-purpose digital I/O/Comparator_A input
P1.7/CA1
General-purpose digital I/O/Comparator_A input
P2.0/TA2
P2.1
45
44
35
34
33
32
31
30
29
28
27
26
25
24
23
22
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O/ Timer_A capture: CCI2A input, compare: Out2 output
General-purpose digital I/O
P2.2/S23
P2.3/S22
P2.4/S21
P2.5/S20
P2.6/CAOUT/S19
P2.7/S18
P3.0/S17
P3.1/S16
P3.2/S15
P3.3/S14
P3.4/S13
P3.5/S12
P3.6/S11
P3.7/S10
General-purpose digital I/O/LCD segment output 23 (see Note 1)
General-purpose digital I/O/LCD segment output 22 (see Note 1)
General-purpose digital I/O/LCD segment output 21 (see Note 1)
General-purpose digital I/O/LCD segment output 20 (see Note 1)
General-purpose digital I/O/Comparator_A output/LCD segment output 19 (see Note 1)
General-purpose digital I/O/LCD segment output 18 (see Note 1)
General-purpose digital I/O/ LCD segment output 17 (see Note 1)
General-purpose digital I/O/ LCD segment output 16 (see Note 1)
General-purpose digital I/O/ LCD segment output 15 (see Note 1)
General-purpose digital I/O/ LCD segment output 14 (see Note 1)
General-purpose digital I/O/LCD segment output 13 (see Note 1)
General-purpose digital I/O/LCD segment output 12 (see Note 1)
General-purpose digital I/O/LCD segment output 11 (see Note 1)
General-purpose digital I/O/LCD segment output 10 (see Note 1)
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
5
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SLAS340G − MAY 2001 − REVISED JUNE 2004
Terminal Functions (Continued)
MSP430x412, MSP430x413 (continued)
TERMINAL
I/O
DESCRIPTION
NAME
P4.0/S9
NO.
21
20
19
18
17
16
15
14
13
12
36
37
38
39
40
41
42
43
59
60
61
2
I/O General-purpose digital I/O/LCD segment output 9 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 8 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 7 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 6 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 5 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 4 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 3 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 2 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 1 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 0 (see Note 1)
P4.1/S8
P4.2/S7
P4.3/S6
P4.4/S5
P4.5/S4
P4.6/S3
P4.7/S2
P5.0/S1
P5.1/S0
COM0
O
Common output. COM0−3 are used for LCD backplanes
P5.2/COM1
P5.3/COM2
P5.4/COM3
R03
I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
I
Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13
P5.6/R23
P5.7/R33
P6.0
I/O General-purpose digital I/O/input port of third most positive analog LCD level (V4 or V3)
I/O General-purpose digital I/O/input port of second most positive analog LCD level (V2)
I/O General-purpose digital I/O/output port of most positive analog LCD level (V1)
I/O General-purpose digital I/O
P6.1
I/O General-purpose digital I/O
P6.2
I/O General-purpose digital I/O
P6.3
I/O General-purpose digital I/O
P6.4
3
I/O General-purpose digital I/O
P6.5
4
I/O General-purpose digital I/O
P6.6
5
I/O General-purpose digital I/O
P6.7
6
I/O General-purpose digital I/O
RST/NMI
TCK
58
57
55
54
56
8
I
I
I
Reset input or nonmaskable interrupt input port
Test clock. TCK is the clock input port for device programming and test.
Test data input or test clock input. The device protection fuse is connected to TDI.
TDI/TCLK
TDO/TDI
TMS
I/O Test data output port. TDO/TDI data output or programming data input terminal.
I
I
Test mode select. TMS is used as an input port for device programming and test.
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output terminal of crystal oscillator XT1.
XIN
XOUT
9
O
QFN Pad
NA
NA QFN package pad connection to V recommended.
SS
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
6
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SLAS340G − MAY 2001 − REVISED JUNE 2004
Terminal Functions (Continued)
MSP430x415, MSP430x417
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AV
AV
64
Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD
resistive divider circuitry; must not power up prior to DV
CC
.
CC
Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A. Needs to be externally
connected to DV
62
SS1
.
SS
DV
DV
1
Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AV
.
CC
SS
CC
Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
AV /AV
63
.
CC SS
AV
10
Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A. Needs to be externally
connected to DV
SS2
.
SS
Not internally connected. Connection to V
NC
7, 11
53
recommended.
SS
P1.0/TA0.0
P1.1/TA0.0/MCLK
I/O
I/O
General-purpose digital I/O/Timer0_A. Capture: CCI0A input, compare: Out0 output/BSL transmit
52
General-purpose digital I/O/Timer0_A. Capture: CCI0B input/MCLK output. Note: TA0 is only an input
on this pin/BSL receive
P1.2/TA0.1
51
50
I/O
I/O
General-purpose digital I/O/Timer0_A, capture: CCI1A input, compare: Out1 output
P1.3/TA1.0/
SVSOUT
General-purpose digital I/O/Timer1_A, capture: CCI0B input/SVS: output of SVS comparator
P1.4/TA1.0
49
48
I/O
I/O
General-purpose digital I/O/Timer1_A, capture: CCI0A input, compare: Out0 output
General-purpose digital I/O/input of Timer0_A clock/output of ACLK
P1.5/TA0CLK/
ACLK
P1.6/CA0
P1.7/CA1
47
46
I/O
I/O
General-purpose digital I/O/Comparator_A input
General-purpose digital I/O/Comparator_A input
P2.0/TA0.2
45
44
35
I/O
I/O
I/O
General-purpose digital I/O/ Timer0_A capture: CCI2A input, compare: Out2 output
General-purpose digital I/O/Timer1_A, capture: CCI1A input, compare: Out1 output
P2.1/TA1.1
P2.2/TA1.2/S23
General-purpose digital I/O/Timer1_A, capture: CCI2A input, compare: Out2 output/LCD segment
output 23 (see Note 1)
P2.3/TA1.3/S22
P2.4/TA1.4/S21
34
33
I/O
I/O
General-purpose digital I/O/Timer1_A, capture: CCI3A input, compare: Out3 output/LCD segment
output 22 (see Note 1)
General-purpose digital I/O/Timer1_A, capture: CCI4A input, compare: Out4 output/LCD segment
output 21 (see Note 1)
P2.5/TA1CLK/S20
P2.6/CAOUT/S19
P2.7/S18
32
31
30
29
28
27
26
25
24
23
22
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O/input of Timer1_A clock/LCD segment output 20 (see Note 1)
General-purpose digital I/O/Comparator_A output/LCD segment output 19 (see Note 1)
General-purpose digital I/O/LCD segment output 18 (see Note 1)
General-purpose digital I/O/ LCD segment output 17 (see Note 1)
General-purpose digital I/O/ LCD segment output 16 (see Note 1)
General-purpose digital I/O/ LCD segment output 15 (see Note 1)
General-purpose digital I/O/ LCD segment output 14 (see Note 1)
General-purpose digital I/O/LCD segment output 13 (see Note 1)
General-purpose digital I/O/LCD segment output 12 (see Note 1)
General-purpose digital I/O/LCD segment output 11 (see Note 1)
General-purpose digital I/O/LCD segment output 10 (see Note 1)
P3.0/S17
P3.1/S16
P3.2/S15
P3.3/S14
P3.4/S13
P3.5/S12
P3.6/S11
P3.7/S10
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
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SLAS340G − MAY 2001 − REVISED JUNE 2004
Terminal Functions (Continued)
MSP430x415, MSP430x417 (continued)
TERMINAL
I/O
DESCRIPTION
NAME
P4.0/S9
NO.
21
20
19
18
17
16
15
14
13
12
36
37
38
39
40
41
42
43
59
60
61
2
I/O General-purpose digital I/O/LCD segment output 9 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 8 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 7 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 6 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 5 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 4 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 3 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 2 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 1 (see Note 1)
I/O General-purpose digital I/O/LCD segment output 0 (see Note 1)
P4.1/S8
P4.2/S7
P4.3/S6
P4.4/S5
P4.5/S4
P4.6/S3
P4.7/S2
P5.0/S1
P5.1/S0
COM0
O
Common output. COM0−3 are used for LCD backplanes
P5.2/COM1
P5.3/COM2
P5.4/COM3
R03
I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
I
Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13
P5.6/R23
P5.7/R33
P6.0
I/O General-purpose digital I/O/input port of third most positive analog LCD level (V4 or V3)
I/O General-purpose digital I/O/input port of second most positive analog LCD level (V2)
I/O General-purpose digital I/O/output port of most positive analog LCD level (V1)
I/O General-purpose digital I/O
P6.1
I/O General-purpose digital I/O
P6.2
I/O General-purpose digital I/O
P6.3
I/O General-purpose digital I/O
P6.4
3
I/O General-purpose digital I/O
P6.5
4
I/O General-purpose digital I/O
P6.6
5
I/O General-purpose digital I/O
P6.7/SVSIN
RST/NMI
TCK
6
I/O General-purpose digital I/O/SVS, analog input
58
57
55
54
56
8
I
I
I
Reset input or nonmaskable interrupt input port
Test clock. TCK is the clock input port for device programming and test.
Test data input or test clock input. The device protection fuse is connected to TDI.
TDI/TCLK
TDO/TDI
TMS
I/O Test data output port. TDO/TDI data output or programming data input terminal.
I
I
Test mode select. TMS is used as an input port for device programming and test.
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
Output terminal of crystal oscillator XT1.
XIN
XOUT
9
O
QFN Pad
NA
NA QFN package pad connection to V recommended.
SS
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
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SLAS340G − MAY 2001 − REVISED JUNE 2004
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
Constant Generator
SR/CG1/R2
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g. ADD R4,R5
R4 + R5 −−−> R5
e.g. CALL
e.g. JNE
R8
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
MOV Rs,Rd
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
D D
R10 −−> R11
Indexed
D D
MOV X(Rn),Y(Rm)
MOV EDE,TONI
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
M(MEM) −−> M(TCDAT)
M(R10) −−> M(Tab+R6)
Symbolic (PC relative) D D
Absolute
Indirect
D D MOV &MEM,&TCDAT
D
D
D
MOV @Rn,Y(Rm)
MOV @Rn+,Rm
MOV #X,TONI
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) −−> R11
R10 + 2−−> R10
Immediate
#45 −−> M(TONI)
NOTE: S = source
D = destination
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SLAS340G − MAY 2001 − REVISED JUNE 2004
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
D
Active mode AM;
All clocks are active
Low-power mode 0 (LPM0);
−
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ Loop control remains active
D
D
Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ Loop control is disabled
Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and FLL+ loop control and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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SLAS340G − MAY 2001 − REVISED JUNE 2004
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range
0FFFFh − 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
Watchdog
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
Flash memory
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
0FFFAh
0FFF8h
14
13
12
Timer1_A5 (see Note 4)
TA1CCR0 CCIFG (see Note 2)
Maskable
TA1CCR1 to TA1CCR4
CCIFGs and TA1CTL TAIFG
(see Notes 1 and 2)
Timer1_A5 (see Note 4)
Maskable
Comparator_A
CMPAIFG
WDTIFG
Maskable
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
11
10
9
Watchdog Timer
8
7
Timer_A3/Timer0_A3
TACCR0/TA0CCR0 CCIFG
(see Note 2)
Maskable
6
TACCR1/TA0CCR1 and
TACCR2/TA0CCR2 CCIFGs,
and TACLT/TA0CTL TAIFG
(see Notes 1 and 2)
Timer_A3/Timer0_A3
I/O port P1 (eight flags)
Maskable
Maskable
0FFEAh
0FFE8h
5
4
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
0FFE6h
0FFE4h
3
2
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
I/O port P2 (eight flags)
Maskable
Maskable
0FFE2h
0FFE0h
1
Basic Timer1
BTIFG
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
4. Implemented in MSP430x415 and MSP430x417 devices only.
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SLAS340G − MAY 2001 − REVISED JUNE 2004
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7
6
6
5
4
3
3
2
2
1
0
Address
0h
ACCVIE
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
7
5
4
1
0
Address
1h
BTIE
rw-0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is config-
ured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
Nonmaskable-interrupt enable
Flash access violation interrupt enable
Basic Timer1 interrupt enable
NMIIE:
ACCVIE:
BTIE:
interrupt flag register 1 and 2
7
6
6
5
5
4
3
3
2
2
1
0
Address
02h
NMIIFG
OFIFG
WDTIFG
rw-0
rw-1
rw-(0)
7
4
1
0
Address
3h
BTIFG
rw-0
WDTIFG:
Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with V
power-up,
CC
or a reset condition at the RST/NMI pin in reset mode.
OFIFG:
NMIIFG:
BTIFG:
Flag set on oscillator fault
Set via RST/NMI pin
Basic Timer1 interrupt flag
module enable registers 1 and 2
7
6
5
4
3
2
1
0
Address
04h/05h
Legend: rw:
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device
rw-0:
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SLAS340G − MAY 2001 − REVISED JUNE 2004
memory organization
MSP430F412
MSP430F413
MSP430F415
MSP430F417
Memory
Size
4KB
8KB
16KB
32KB
Interrupt vector
Code memory
Flash
Flash
0FFFFh − 0FFE0h
0FFFFh − 0F000h
0FFFFh − 0FFE0h
0FFFFh − 0E000h
0FFFFh − 0FFE0h
0FFFFh − 0C000h
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory
Boot memory
RAM
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
256 Byte
256 Byte
512 Byte
1 KB
02FFh − 0200h
02FFh − 0200h
03FFh − 0200h
05FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
MSP430C412
MSP430C413
Memory
Interrupt vector
Code memory
Size
ROM
ROM
4KB
8KB
0FFFFh − 0FFE0h
0FFFFh − 0F000h
0FFFFh − 0FFE0h
0FFFFh − 0E000h
Information memory
Boot memory
RAM
Size
Size
Size
NA
NA
NA
NA
256 Byte
256 Byte
02FFh − 0200h
02FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
Data Transmit
Data Receive
PM, RTD Package Pins
53 - P1.0
52 - P1.1
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SLAS340G − MAY 2001 − REVISED JUNE 2004
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
8KB
16KB
32KB
4KB
0FFFFh 0FFFFh
0FFFFh 0FFFFh
Segment 0
With Interrupt Vectors
0FE00h 0FE00h
0FDFFh 0FDFFh
0FE00h 0FE00h
0FDFFh 0FDFFh
Segment 1
Segment 2
0FC00h 0FC00h
0FBFFh 0FBFFh
0FC00h 0FC00h
0FBFFh 0FBFFh
0FA00h 0FA00h
0F9FFh 0F9FFh
0FA00h 0FA00h
0F9FFh 0F9FFh
Main Memory
0C400h 08400h
0C3FFh 083FFh
0F400h 0E400h
0F3FFh 0E3FFh
Segment n−1
Segment n
Segment A
Segment B
0C200h 08200h
0C1FFh 081FFh
0F200h 0E200h
0F1FFh 0E1FFh
0C000h 08000h
010FFh 010FFh
0F000h 0E000h
010FFh 010FFh
01080h 01080h
0107Fh 0107Fh
01080h 01080h
0107Fh 0107Fh
Information Memory
01000h 01000h
01000h 01000h
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SLAS340G − MAY 2001 − REVISED JUNE 2004
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature
number SLAU056.
oscillator and system clock
The clock system in the MSP430x41x family of devices is supported by the FLL+ module that includes support
for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module
provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a fixed
level or user selectable level (MSP430x415 & MSP430x417 only) and supports both supply voltage supervision
(the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V
may not
CC
have ramped to V
reaches V
at that time. The user must insure the default FLL+ settings are not changed until V
CC(min)
CC
. If desired, the SVS circuit can be used to determine when V
reaches V
.
CC(min)
CC
CC(min)
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
15
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SLAS340G − MAY 2001 − REVISED JUNE 2004
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
comparator_A
The primary function of the comparator_A module is to support precision slope analog−to−digital conversions,
battery−voltage supervision, and monitoring of external analog signals.
timer_A3/timer0_A3
Timer_A3/Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3/Timer0_A3 can
support multiple capture/compares, PWM outputs, and interval timing. Timer_A3/Timer0_A3 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of
the capture/compare registers.
Timer_A3/Timer0_A3 Signal Connections
Input Pin Number Device Input Signal Module Input Name
Module Block
Module Output Signal
Output Pin Number
48 - P1.5
TACLK/TA0CLK
ACLK
TACLK
ACLK
Timer
NA
SMCLK
SMCLK
INCLK
CCI0A
CCI0B
GND
48 - P1.5
53 - P1.0
52 - P1.1
TACLK/TA0CLK
TA0/TA0.0
TA0/TA0.0
53 - P1.0
51 - P1.2
45 - P2.0
CCR0
CCR1
CCR2
TA0/TA0.0
TA1/TA0.1
TA2/TA0.2
DV
DV
SS
V
CC
CC
51 - P1.2
45 - P2.0
TA1/TA0.1
CCI1A
CCI1B
GND
CAOUT (internal)
DV
DV
SS
V
CC
CC
TA2/TA0.2
CCI2A
CCI2B
GND
ACLK (internal)
DV
DV
SS
V
CC
CC
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SLAS340G − MAY 2001 − REVISED JUNE 2004
timer1_A5 (MSP430x415 and MSP430x417 only)
Timer1_A5 is a 16-bit timer/counter with five capture/compare registers. Timer1_A5 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A5 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer1_A5 Signal Connections
Input Pin Number Device Input Signal Module Input Name
Module Block
Module Output Signal
Output Pin Number
32 - P2.5
TA1CLK
ACLK
TACLK
ACLK
Timer
NA
SMCLK
TA1CLK
TA1.0
SMCLK
INCLK
CCI0A
CCI0B
GND
32 - P2.5
49 - P1.4
50 - P1.3
49 - P1.4
44 - P2.1
35 - P2.2
34 - P2.3
33 - P2.4
TA1.0
CCR0
CCR1
CCR2
CCR3
CCR4
TA1.0
TA1.1
TA1.2
TA1.3
TA1.4
DV
DV
SS
V
CC
CC
44 - P2.1
35 - P2.2
34 - P2.3
33 - P2.4
TA1.1
CCI1A
CCI1B
GND
CAOUT (internal)
DV
DV
SS
V
CC
CC
TA1.2
CCI2A
CCI2B
GND
Not Connected
DV
SS
CC
DV
V
CC
TA1.3
CCI3A
CCI3B
GND
Not Connected
DV
SS
CC
DV
V
CC
TA1.4
CCI4A
CCI4B
GND
Not Connected
DV
SS
CC
DV
V
CC
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SLAS340G − MAY 2001 − REVISED JUNE 2004
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog Timer control
Timer1_A interrupt vector
Timer1_A control
WDTCTL
TA1IV
0120h
011Eh
0180h
0182h
0184h
0186h
0188h
018Ah
018Ch
018Eh
0190h
0192h
0194h
0196h
0198h
019Ah
019Ch
019Eh
012Eh
0160h
Timer1_A5
(MSP430x415 and
MSP430x417 only)
TA1CTL
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Reserved
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1CCTL3
TA1CCTL4
Reserved
Timer1_A register
TA1R
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
Capture/compare register 3
Capture/compare register 4
Reserved
TA1CCR0
TA1CCR1
TA1CCR2
TA1CCR3
TA1CCR4
Reserved
Timer_A3/Timer0_A3
Timer_A/Timer0_A interrupt vector
Timer_A/Timer0_A control
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Reserved
TAIV/TA0IV
TACTL/TA0CTL
TACCTL0/TA0CCTL0 0162h
TACCTL1/TA0CCTL1 0164h
TACCTL2/TA0CCTL2 0166h
0168h
016Ah
016Ch
016Eh
Reserved
Reserved
Reserved
Timer_A/Timer0_A register
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
Reserved
TAR/TA0R
0170h
0172h
0174h
0176h
0178h
017Ah
017Ch
017Eh
012Ch
012Ah
0128h
TACCR0/TA0CCR0
TACCR1/TA0CCR1
TACCR2/TA0CCR2
Reserved
Reserved
Reserved
Flash
Flash control 3
FCTL3
FCTL2
FCTL1
Flash control 2
Flash control 1
18
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SLAS340G − MAY 2001 − REVISED JUNE 2004
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD memory 20
LCD
LCDM20
:
0A4h
:
:
LCD memory 16
LCD memory 15
:
LCDM16
LCDM15
:
0A0h
09Fh
:
LCD memory 1
LCDM1
LCDCTL
CAPD
091h
090h
05Bh
05Ah
059h
056h
054h
053h
052h
051h
050h
047h
046h
040h
037h
036h
035h
034h
033h
032h
031h
030h
01Fh
01Eh
01Dh
01Ch
01Bh
01Ah
019h
018h
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
LCD control and mode
Comparator_A port disable
Comparator_A control2
Comparator_A control1
SVS control register
FLL+ Control1
Comparator_A
CACTL2
CACTL1
SVSCTL
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
SCFI0
BTCNT2
BTCNT1
BTCTL
P6SEL
P6DIR
P6OUT
P6IN
Brownout, SVS
FLL+ Clock
FLL+ Control0
System clock frequency control
System clock frequency integrator
System clock frequency integrator
BT counter2
Basic Timer1
Port P6
BT counter1
BT control
Port P6 selection
Port P6 direction
Port P6 output
Port P6 input
Port P5
Port P4
Port P3
Port P2
Port P5 selection
Port P5 direction
Port P5 output
P5SEL
P5DIR
P5OUT
P5IN
Port P5 input
Port P4 selection
Port P4 direction
Port P4 output
P4SEL
P4DIR
P4OUT
P4IN
Port P4 input
Port P3 selection
Port P3 direction
Port P3 output
P3SEL
P3DIR
P3OUT
P3IN
Port P3 input
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt-edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P2 input
19
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SLAS340G − MAY 2001 − REVISED JUNE 2004
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P1
Port P1 selection
P1SEL
026h
025h
024h
023h
022h
021h
020h
005h
004h
003h
002h
001h
000h
Port P1 interrupt enable
Port P1 interrupt-edge select
Port P1 interrupt flag
Port P1 direction
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
ME2
Port P1 output
Port P1 input
Special Functions
SFR module enable 2
SFR module enable 1
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
ME1
IFG2
IFG1
IE2
IE1
†
absolute maximum ratings
Voltage applied at V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 4.1 V
CC
SS
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
+ 0.3 V
CC
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is applied
SS
FB
to the TDI/TCLK pin when blowing the JTAG fuse.
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SLAS340G − MAY 2001 − REVISED JUNE 2004
recommended operating conditions
PARAMETER
MIN
NOM
MAX UNITS
Supply voltage during program execution, SVS disabled
MSP430x41x
MSP430x41x
MSP430F41x
1.8
3.6
3.6
3.6
V
V
V
V
CC
(AV
CC
= DV
CC
= V )
CC
Supply voltage during program execution, SVS enabled (see Note 1),
(AV = DV = V
2.2
2.7
V
CC
)
CC CC CC
Supply voltage during programming of flash memory,
V
CC
(AV
CC
= DV
= V )
CC
CC
Supply voltage, V
(AV
SS/1/2
= DV
SS
= V
)
0
0
V
SS
SS
Operating free-air temperature range, T
MSP430x41x
Watch crystal
−40
85
°C
A
LF selected, XTS_FLL=0
XT1 selected, XTS_FLL=1
XT1 selected, XTS_FLL=1
32768
Hz
LFXT1 crystal frequency, f
(see Note 2)
(LFXT1)
Ceramic resonator
Crystal
450
1000
DC
8000
8000
4.15
8
kHz
kHz
V
V
= 1.8 V
= 3.6 V
CC
Processor frequency (signal MCLK), f
(System)
MHz
DC
CC
NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.
2. The LFXT1 oscillator in LF-mode requires a watch crystal.
f (MHz)
Supply Voltage Range
During Programming of
the Flash Memory
8 MHz
Supply Voltage Range, x41x
During Program Execution
4.15 MHz
1.8 V
2.7 V 3 V
3.6 V
V
CC
− Supply Voltage − V
Figure 1. Frequency vs Supply Voltage
21
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AV + DV excluding external current, (see Note 1)
CC
CC
PARAMETER
TEST CONDITIONS
MIN NOM
160
MAX
200
300
250
350
UNIT
V
V
V
V
= 2.2 V
= 3 V
CC
CC
CC
CC
Active mode,
C41x
F41x
240
f
f
= f
= 1 MHz,
(MCLK)
(SMCLK)
I
T
= −40°C to 85°C
= −40°C to 85°C
A
µA
(AM)
A
= 32,768 Hz, XTS_FLL = 0
= 2.2 V
= 3 V
200
(ACLK)
(F41x: Program executes in flash)
300
Low-power mode, (LPM0)
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
32
55
57
92
45
70
f
f
= f
= 0.5 MHz,
(MCLK)
(SMCLK)
I
T
µA
(LPM0)
= 32,768 Hz, XTS_FLL = 0
(ACLK)
FN_8=FN_4=FN_3=FN_2=0
C41x
F41x
Low-power mode, (LPM0)
= 2.2 V
= 3 V
70
f
f
= f
= 1 MHz,
(MCLK)
(SMCLK)
I
I
T
A
= −40°C to 85°C
= −40°C to 85°C
µA
µA
(LPM0)
= 32,768 Hz, XTS_FLL = 0
(ACLK)
100
FN_8=FN_4=FN_3=FN_2=0
V
V
= 2.2 V
= 3 V
11
17
14
22
CC
Low-power mode, (LPM2)
T
A
(LPM2)
CC
T
= −40°C
= −10°C
= 25°C
= 60°C
= 85°C
= −40°C
= −10°C
= 25°C
= 60°C
= 85°C
= −40°C
= 25°C
= 85°C
0.95
0.8
0.7
0.95
1.6
1.1
1.0
0.9
1.1
2.0
0.1
0.1
0.8
1.4
1.3
1.2
1.4
2.3
1.7
1.6
1.5
1.7
2.6
0.5
0.5
2.5
A
T
A
T
A
V
= 2.2 V
CC
T
A
T
A
I
Low-power mode, (LPM3) (see Note 2)
µA
(LPM3)
T
A
T
A
T
A
V
V
= 3 V
CC
T
A
T
A
T
A
T
A
I
Low-power mode, (LPM4)
= 2.2 V/3 V
µA
(LPM4)
CC
T
A
NOTES: 1. All inputs are tied to 0 V or V . Outputs do not source or sink any current. The current consumption is measured with active Basic
CC
Timer1 and LCD (ACLK selected).
The current consumption of the Comparator_A and the SVS module are specified in the respective sections.
2. The LPM3 currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal.
current consumption of active mode versus system frequency, F version
I
= I
× f
(AM) [1 MHz] (System) [MHz]
(AM)
current consumption of active mode versus supply voltage, F version
I
= I
+ 140 µA/V × (V – 3 V)
(AM) [3 V] CC
(AM)
22
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
V
MIN
1.1
TYP
MAX
1.5
1.9
0.9
1.3
1.1
1
UNIT
CC
2.2 V
3 V
V
IT+
V
IT−
V
hys
Positive-going input threshold voltage
V
1.5
2.2 V
3 V
0.4
Negative-going input threshold voltage
V
V
0.9
2.2 V
3 V
0.3
Input voltage hysteresis (V
IT+
− V )
IT−
0.45
standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
V
MIN
TYP
TYP
MAX
UNIT
V
CC
V
V
Low-level input voltage
High-level input voltage
V
SS
V
+0.6
SS
IL
2.2 V/3 V
0.8×V
V
CC
V
IH
CC
inputs Px.x, TAx/TAx.x
PARAMETER
TEST CONDITIONS
V
CC
MIN
1.5
62
MAX
UNIT
2.2 V/3 V
2.2 V
3 V
cycle
Port P1, P2: P1.x to P2.x, External
trigger signal for the interrupt flag,
(see Note 1)
t
External interrupt timing
Timer_A, capture timing
(int)
ns
ns
50
2.2 V
3 V
62
t
f
f
TAx/TAx.y
(cap)
50
2.2 V
3 V
8
10
8
Timer_A clock frequency externally
applied to pin
TACLK/TAxCLK, INCLK t
= t
MHz
MHz
(TAext)
(H) (L)
2.2 V
3 V
Timer_A clock frequency
SMCLK or ACLK signal selected
(TAint)
10
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
(int)
cycle and time parameters are met. It may be set even with
is measured in
trigger signals shorter than t
MCLK cycles.
. Both the cycle and timing specifications must be met to ensure the flag is set. t
(int)
(int)
leakage current (see Note 1)
PARAMETER
TEST CONDITIONS
(see Note 2)
V
MIN NOM
MAX
UNIT
CC
I
I
Port P1
Port P6
V
V
50
50
lkg(P1.x)
(P1.x)
Leakage current
2.2 V/3 V
nA
(see Note 2)
lkg(P6.x)
(P6.x)
NOTES: 1. The leakage current is measured with V
SS
or V applied to the corresponding pin(s), unless otherwise noted.
CC
2. The port pin must be selected as an input.
23
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
I
I
= −1.5 mA,
= −6 mA,
= −1.5 mA,
= −6 mA,
= 1.5 mA,
= 6 mA,
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V,
= 2.2 V,
= 3 V,
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
V
−0.25
V
V
V
V
OH(max)
OH(max)
OH(max)
OH(max)
OL(max)
OL(max)
OL(max)
OL(max)
CC
CC
CC
CC
CC
V
−0.6
CC
−0.25
V
High-level output voltage
V
OH
OL
V
CC
= 3 V,
V
−0.6
CC
= 2.2 V,
= 2.2 V,
= 3 V,
V
V
+0.25
SS
SS
SS
SS
SS
V
V
V
V
+0.6
SS
V
Low-level output voltage
V
= 1.5 mA,
= 6 mA,
V
SS
+0.25
= 3 V,
V
+0.6
SS
NOTES: 1. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 12 mA to satisfy the maximum
OH(max)
OL(max),
OL(max),
2. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 24 mA to satisfy the maximum
OH(max)
output frequency
PARAMETER
TEST CONDITIONS
MIN
DC
DC
TYP
MAX
10
UNIT
V
= 2.2 V
= 3 V
C
I
= 20 pF,
CC
CC
L
L
f
(1 ≤ x ≤ 6, 0 ≤ y ≤ 7)
MHz
Px.y
=
1.5mA
V
12
f
f
f
V
V
= 2.2 V
= 3 V
8
ACLK,
MCLK,
SMCLK
CC
CC
P1.1/TA0/MCLK, P1.5/TACLK/ACLK
Duty cycle of output frequency
C
= 20 pF
MHz
L
12
f
f
f
= f
= f
40%
30%
60%
70%
ACLK LFXT1 XT1
P1.5/TACLK/ACLK,
C
= f
= f
= 20 pF
= 2.2 V / 3 V
ACLK LFXT1 LF
= f
L
V
CC
50%
50%
ACLK LFXT1/n
t
Xdc
50%−
15 ns
50%+
15 ns
f
= f
MCLK LFXT1/n
P1.1/TA0/MCLK,
C
V
= 20 pF,
= 2.2 V / 3 V
L
50%−
15 ns
50%+
15 ns
f
= f
50%
CC
MCLK DCOCLK
24
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
MSP430x412, MSP430x413 outputs − Ports P1, P2, P3, P4, P5, and P6 (see Note)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
16
14
12
10
8
25
20
15
10
5
V
CC
P1.0
= 2.2 V
T
= 25°C
V
CC
P1.0
= 3 V
A
T
= 25°C
A
T
= 85°C
A
T
= 85°C
A
6
4
2
0
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 2
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
−2
0
−5
V
CC
P1.0
= 2.2 V
V
CC
P1.0
= 3 V
−4
−10
−15
−20
−25
−30
−6
−8
T
A
= 85°C
−10
−12
−14
T
A
= 85°C
T
A
= 25°C
T
A
= 25°C
0.0
0.5
OH
1.0
1.5
2.0
2.5
0.0
0.5
V
1.0
1.5
2.0
2.5
3.0
3.5
V
− High-Level Output Voltage − V
− High-Level Output Voltage − V
OH
Figure 4
Figure 5
NOTE A: One output loaded at a time
25
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
MSP430x415, MSP430x417 outputs − Ports P1, P2, P3, P4, P5, and P6 (see Note)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
25
20
15
10
5
40
35
30
25
20
15
10
5
T
A
= 25°C
V
CC
P2.4
= 2.2 V
V
CC
P2.4
= 3 V
T
= 25°C
A
T
A
= 85°C
T
= 85°C
A
0
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 6
Figure 7
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
−5
0
−5
V
= 2.2 V
V
= 3 V
CC
P2.4
CC
P2.4
−10
−15
−20
−25
−30
−35
−40
−45
−50
−10
−15
−20
−25
T
A
= 85°C
T
= 85°C
A
T
A
= 25°C
T
A
= 25°C
0.0
0.5
OH
1.0
1.5
2.0
2.5
0.0
0.5
V
1.0
1.5
2.0
2.5
3.0
3.5
V
− High-Level Output Voltage − V
− High-Level Output Voltage − V
OH
Figure 8
Figure 9
NOTE B: One output loaded at a time
26
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
f = 1 MHz
MIN
TYP
TYP
MAX
UNIT
6
6
6
f = 2 MHz
f = 3 MHz
t
Delay time
V
CC
= 2.2 V/3 V
µs
d(LPM3)
RAM (see Note 1)
PARAMETER
TEST CONDITIONS
CPU halted (see Note 1)
MIN
MAX
UNIT
VRAMh
1.6
V
NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program
execution should take place during this supply voltage condition.
LCD
PARAMETER
TEST CONDITIONS
Voltage at P5.7/R33
MIN
TYP
MAX
V +0.2
CC
UNIT
V
V
V
V
I
2.5
(33)
(23)
(13)
Voltage at P5.6/R23
Voltage at P5.5/R13
Voltage at R33/R03
(V −V ) × 2/3 + V
33 03 03
Analog voltage
Input leakage
V
= 3 V
V
CC
(V
−V
) × 1/3 + V
(33) (03) (03)
V
2.5
V
+0.2
(33) − (03)
CC
20
R03 = V
SS
No load at all
segment and
common lines,
(R03)
(R13)
(R23)
I
I
P5.5/R13 = V /3
CC
20
20
nA
V
P5.6/R23 = 2 × V /3
V
CC
= 3 V
CC
V
V
V
V
V
(03)
V
− 0.1
(Sxx0)
(Sxx1)
(Sxx2)
(Sxx3)
(03)
(13)
(23)
(33)
V
(13)
V
V
V
− 0.1
− 0.1
+ 0.1
Segment line
voltage
I
= −3 µA,
V
CC
= 3 V
(Sxx)
V(
23)
33)
V(
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
MAX
40
UNIT
V
V
= 2.2 V
= 3 V
CC
I
CAON = 1, CARSEL = 0, CAREF = 0
µA
(CC)
45
30
60
50
CC
CAON = 1, CARSEL = 0,
CAREF = 1/2/3,
No load at P1.6/CA0 and P1.7/CA1
V
= 2.2 V
= 3 V
CC
CC
I
µA
(Refladder/RefDiode)
V
45
71
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.6/CA0 and P1.7/CA1
Voltage @ 0.25 V
node
CC
V
V
V
= 2.2 V / 3 V
= 2.2V / 3 V
0.23
0.47
0.24
0.25
(Ref025)
(Ref050)
CC
V
CC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.6/CA0 and P1.7/CA1
Voltage @ 0.5 V
node
CC
V
0.48
0.50
CC
V
CC
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1.6/CA0 and P1.7/CA1;
V
V
= 2.2 V
= 3.0 V
390
400
480
490
540
550
CC
(see Figure 10 and
Figure 11)
V
V
mV
V
(RefVT)
T
A
= 85°C
CC
Common-mode input
voltage range
CAON = 1
V
CC
= 2. 2V/3 V
0
V
CC
−1.0
(IC)
V
V
Offset voltage
See Note 2
CAON = 1
VCC = 2.2 V/3 V
−30
0
30
1.4
300
240
3.4
2.6
300
240
3.4
2.6
mV
mV
(offset)
Input hysteresis
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V / 3 V
= 2.2 V
= 3 V
0.7
210
150
1.9
hys
160
80
T
A
= 25°C,
ns
µs
ns
µs
Overdrive 10 mV, without filter: CAF = 0
t
(response LH)
= 2.2 V
= 3 V
1.4
0.9
130
80
T
A
= 25°C
Overdrive 10 mV, with filter: CAF = 1
1.5
= 2.2 V
= 3 V
210
150
1.9
T
A
= 25°C
Overdrive 10 mV, without filter: CAF = 0
t
(response HL)
= 2.2 V
= 3.0 V
1.4
0.9
T
A
= 25°C,
Overdrive 10 mV, with filter: CAF = 1
1.5
NOTES: 1. The leakage current for the Comparator_A terminals is identical to I
specification.
lkg(Px.x)
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
28
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
REFERENCE VOLTAGE
vs
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
650
600
550
500
450
400
650
600
550
500
450
400
V
= 2.2 V
V
CC
= 3 V
CC
Typical
Typical
−45
−25
−5
15
35
55
75
95
−45
−25
−5
15
35
55
75
95
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 11
Figure 10
0 V
V
CC
CAF
0
1
CAON
To Internal
Modules
Low Pass Filter
0
1
0
1
+
_
V+
V−
CAOUT
Set CAIFG
Flag
τ ≈ 2 µs
Figure 12. Block Diagram of Comparator_A Module
V
CAOUT
Overdrive
V−
400 mV
V+
t
(response)
Figure 13. Overdrive Definition
29
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR brownout, reset (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µs
t
2000
d(BOR)
V
V
V
dV /dt ≤ 3 V/s (see Figure 14)
CC
0.7 × V
(B_IT−)
V
CC(start)
dV /dt ≤ 3 V/s (see Figure 14, Figure 15, Figure 16)
CC
1.71
180
V
(B_IT−)
Brownout
dV /dt ≤ 3 V/s (see Figure 14)
CC
70
2
130
mV
hys(B_IT−)
Pulse length needed at RST/NMI pin to accepted reset internally,
t
µs
(reset)
V
CC
= 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the I
current consumption data. The voltage level V
(B_IT−)
CC
+ V
is ≤ 1.8 V.
2. During power up, the CPU begins code execution following a period of t
hys(B_IT−)
after V
CC
= V
(B_IT−)
+ V . The default
hys(B_IT−)
d(BOR)
FLL+ settings must not be changed until V ≥ V
on the brownout/SVS circuit.
. See the MSP430x4xx Family User’s Guide (SLAU056) for more information
CC CC(min)
V
CC
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
1
0
t
d(BOR)
Figure 14. POR/Brownout Reset (BOR) vs Supply Voltage
30
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
V
CC
t
2
pw
3 V
V
= 3 V
cc
Typical Conditions
1.5
1
V
CC(min)
0.5
0
0.001
1
1000
1 ns
1 ns
− Pulse Width − µs
t
− Pulse Width − µs
t
pw
pw
Figure 15. V
Level With a Square Voltage Drop to Generate a POR/Brownout Signal
CC(min)
V
CC
t
pw
2
3 V
V
= 3 V
cc
Typical Conditions
1.5
1
V
CC(min)
0.5
0
t = t
f
r
0.001
1
1000
t
t
t
r
f
− Pulse Width − µs
t
− Pulse Width − µs
pw
pw
Figure 16. V
Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
CC(min)
SVS (supply voltage supervisor/monitor, see Notes 1 and 2) MSP430x412, MSP430x413 only
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
150
2000
150
1.7
UNIT
µs
dV /dt > 30V/ms (see Note 2)
CC
dV /dt ≤ 30V/ms (see Note 2)
5
t
t
d(SVSR)
µs
CC
SVSon, switch from 0 to 1, V
CC
dV /dt ≤ 3 V/s (see Figure 17)
= 3 V (see Note 2)
20
µs
d(SVSon)
V
V
V
1.55
1.95
100
V
(SVSstart)
(SVS_IT−)
hys(SVS_IT−)
CC(SVS)
CC
SVS
dV /dt ≤ 3 V/s (see Figure 17)
1.8
70
2.2
V
CC
dV /dt ≤ 3 V/s (see Figure 17)
155
mV
CC
VLD ≠ 0 (VLD bits are in SVSCTL register), V
I
= 2.2V/ 3V
10
15
µA
CC
(see Note 1)
NOTES: 1. The current consumption of the SVS module is not included in the I
2. The SVS is not active at power up.
current consumption data.
CC
31
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SVS (supply voltage supervisor/monitor, see Notes 1 and 2) MSP430x415, MSP430x417 only
PARAMETER
TEST CONDITIONS
dV /dt > 30 V/ms (see Figure 17)
MIN
NOM
MAX
150
2000
150
12
UNIT
µs
5
CC
t
d(SVSR)
dV /dt ≤ 30 V/ms
CC
µs
t
t
SVSon, switch from VLD=0 to VLD ≠ 0, V
= 3 V
20
µs
d(SVSon)
CC
‡
VLD ≠ 0
µs
settle
V
VLD ≠ 0, V /dt ≤ 3 V/s (see Figure 17)
CC
1.55
120
1.7
V
(SVSstart)
VLD = 1
70
155
mV
V
/dt ≤ 3 V/s (see Figure 17)
V
V
CC
CC
(SVS_IT−)
x 0.004
(SVS_IT−)
x 0.008
VLD = 2 .. 14
V
hys(SVS_IT−)
V
/dt ≤ 3 V/s (see Figure 17), external voltage applied
VLD = 15
4.4
10.4
mV
on SVSIN
VLD = 1
VLD = 2
VLD = 3
VLD = 4
VLD = 5
VLD = 6
VLD = 7
VLD = 8
VLD = 9
VLD = 10
VLD = 11
VLD = 12
VLD = 13
VLD = 14
1.8
1.9
2.1
2.05
2.25
2.37
2.48
2.6
1.94
2.05
2.14
2.24
2.33
2.46
2.58
2.69
2.83
2.94
3.11
3.24
3.43
2.2
2.3
2.4
2.5
2.71
2.86
3
2.65
2.8
V
CC
/dt ≤ 3 V/s (see Figure 17)
V
V
(SVS_IT−)
2.9
3.13
3.29
3.42
3.05
3.2
†
†
†
3.35
3.5
3.61
3.76
3.99
†
3.7
V
/dt ≤ 3 V/s (see Figure 17), external voltage applied
CC
VLD = 15
1.1
1.2
10
1.3
15
on SVSIN
I
CC(SVS)
(see Note 1)
VLD ≠ 0, V
= 2.2 V/3 V
µA
CC
†
‡
The recommended operating voltage range is limited to 3.6 V.
is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
t
settle
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTES: 1. The current consumption of the SVS module is not included in the I
2. The SVS is not active at power up.
current consumption data.
CC
32
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SVS is Active
Software Sets VLD>0:
V
CC
V
hys(SVS_IT−)
V
V
(SVS_IT−)
(SVSstart)
V
hys(B_IT−)
V
(B_IT−)
V
CC(start)
Brownout
Region
Brownout
Region
Brownout
1
0
t
t
d(BOR)
SVS out
1
d(BOR)
SVS Circuit is Active From VLD > to V < V
CC
(B_IT−)
0
t
d(SVSon)
Set POR
1
t
d(SVSR)
Undefined
0
Figure 17. SVS Reset (SVSR) vs Supply Voltage
V
CC
t
pw
3 V
2
Rectangular Drop
V
CC(min)
1.5
1
Triangular Drop
1 ns
1 ns
V
CC
3 V
t
pw
0.5
0
1
10
100
− Pulse Width − µs
1000
t
pw
V
CC(min)
t = t
f
r
t
t
r
f
t − Pulse Width − µs
Figure 18. V
With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
CC(min)
33
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO
PARAMETER
TEST CONDITIONS
V
MIN
TYP
1
MAX
UNIT
CC
f
N
=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0
(DCO)
2.2 V/3 V
2.2 V
3 V
MHz
(DCOCLK)
0.3
0.3
2.5
2.7
0.7
0.8
5.7
6.5
1.2
1.3
9
0.65
0.7
5.6
6.1
1.3
1.5
10.8
12.1
2
1.25
1.3
10.5
11.3
2.3
2.5
18
f
f
f
f
f
f
f
f
f
f
FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
(DCO2)
2.2 V
3 V
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1, (see Note 1)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
(DCO27)
(DCO2)
(DCO27)
(DCO2)
(DCO27)
(DCO2)
(DCO27)
(DCO2)
(DCO27)
2.2 V
3 V
2.2 V
3 V
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1, (see Note 1)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1, (see Note 1)
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1, (see Note 1)
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
20
2.2 V
3 V
3
2.2
15.5
17.9
2.8
3.4
21.5
26.6
4.2
6.3
32
3.5
25
2.2 V
3 V
10.3
1.8
2.1
13.5
16
28.5
4.2
5.2
33
2.2 V
3 V
2.2 V
3 V
41
2.2 V
3 V
2.8
4.2
21
6.2
9.2
46
2.2 V
3 V
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1, (see Note 1)
Step size between adjacent DCO taps:
30
46
70
1 < TAP ≤ 20
TAP = 27
2.2 V
3 V
1.06
1.07
–0.2
–0.2
1.11
1.17
–0.4
–0.4
S
n
S
n
= f
/ f
, (see Figure 20 for taps 21 to 27)
DCO(Tap n+1) DCO(Tap n)
–0.3
–0.3
Temperature drift, N
(DCO)
= 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0, (see Note 2)
D
D
%/C
t
Drift with V variation, N = 01E0h, FN_8=FN_4=FN_3=FN_2=0
CC (DCO)
0
5
15
%/V
V
D = 2; DCOPLUS = 0 (see Note 2)
NOTES: 1. Do not exceed the maximum system frequency.
2. This parameter is not production tested.
f
f
(DCO)
(DCO)
f
f
5
(DCO3V)
(DCO20 C)
1.0
1.0
0
1.8
2.4
3.0
3.6
−40
−20
0
20
40
60
85
V
CC
− V
T − °C
A
Figure 19. DCO Frequency vs Supply Voltage V
and vs Ambient Temperature
CC
34
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 20. DCO Tap Step Size
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
2
5
to 2 in SCFI1 {N }
{DCO}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_3=x
FN_4=x
FN_8=1
Figure 21. Five Overlapping DCO Ranges Controlled by FN_x Bits
35
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
OSCCAPx = 0h
OSCCAPx = 1h
OSCCAPx = 2h
OSCCAPx = 3h
OSCCAPx = 0h
OSCCAPx = 1h
OSCCAPx = 2h
OSCCAPx = 3h
V
MIN
TYP
0
MAX
UNIT
CC
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
10
14
18
0
C
C
Integrated load capacitance
pF
XIN
10
14
18
Integrated load capacitance
Input levels at XIN
pF
V
XOUT
V
V
V
0.2×V
CC
IL
SS
0.8×V
see Note 3
2.2 V/3 V
V
CC
IH
CC
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2pF. The effective load capacitor for the crystal is
(C x C ) / (C + C ). It is independent of XTS_FLL.
XIN
XOUT XIN XOUT
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines must be
observed:
• Keep as short a trace as possible between the ’x41x and the crystal.
• Design a good ground plane around oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to XIN an XOUT pins.
• Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
• Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation.
This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
36
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SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Flash Memory
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
2.7
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from DV
Supply current from DV
during program
during erase
2.7 V/ 3.6 V
2.7 V/ 3.6 V
2.7 V/ 3.6 V
2.7 V/ 3.6 V
3
PGM
CC
3
7
mA
ERASE
CPT
CC
Cumulative program time
see Note 1
see Note 2
4
ms
Cumulative mass erase time
Program/Erase endurance
Data retention duration
200
ms
CMErase
4
5
10
10
100
cycles
years
t
T = 25°C
J
Retention
t
t
t
t
t
t
Word or byte program time
35
30
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
21
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 3
t
FTG
6
5297
4819
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f
,max = 5297x1/476kHz). To
FTG
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (t
FTG
= 1/f
FTG
).
JTAG Interface
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
2.2 V
3 V
0
0
5
10
90
MHz
MHz
kΩ
f
TCK input frequency
see Note 1
TCK
R
Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2
may be restricted to meet the timing requirements of the module selected.
2.2 V/ 3 V
25
60
Internal
NOTES: 1. f
TCK
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
V
Supply voltage during fuse-blow condition
Voltage level on TDI/TCLK for fuse-blow - ’C41x
Voltage level on TDI/TCLK for fuse-blow - ’F41x
Supply current into TDI/TCLK during fuse blow
Time to blow fuse
T
A
= 25°C
2.5
3.5
6
V
V
CC(FB)
3.9
7
FB
V
I
t
100
1
mA
ms
FB
FB
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
37
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
Pad Logic
CAPD.x
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
1
0
1
From Module
P1.x
P1OUT.x
Module X OUT
Bus
MSP430x412,
MSP430x413 only
keeper
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1IN.x
EN
D
P1.3/SVSOUT
P1.4
P1.5/TACLK/ACLK
MSP430x415,
Module X IN
P1IRQ.x
MSP430x417 only
P1IE.x
EN
Interrupt
Edge
Select
P1.0/TA0.0
P1.1/TA0.0/MCLK
P1.2/TA0.1
Q
P1IFG.x
Set
P1.3/TA1.0/SVSOUT
P1.4/TA1.0
P1.5/TA0CLK/ACLK
P1IES.x P1SEL.x
NOTE: 0 ≤ x ≤ 5.
Port Function is Active if CAPD.x = 0
Direction
Control
From Module
Module X
OUT
PnOUT.x
PnIE.x
PnIES.x
PnIN.x
Module X IN
PnSEL.x
PnDIR.x
PnIFG.x
†
†
P1SEL.0
P1SEL.1
P1OUT.0
P1DIR.0
P1DIR.1
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR.5
P1IN.0
P1IN.1
P1IN.2
P1IN.3
P1IN.4
P1IN.5
Out0 Sig.
MCLK
CCI0A
P1IE.0
P1IE.1
P1IE.2
P1IE.3
P1IE.4
P1IE.5
P1IFG.0
P1IFG.1
P1IFG.2
P1IFG.3
P1IFG.4
P1IFG.5
P1IES.0
P1IES.1
P1IES.2
P1IES.3
P1IES.4
P1IES.5
†
P1OUT.1
P1OUT.2
P1OUT.3
P1OUT.4
P1OUT.5
CCI0B
†
†
P1SEL.2
P1SEL.3
P1SEL.4
P1DIR.2
P1DIR.3
P1DIR.4
Out1 Sig.
CCI1A
SVSOUT
Unused
§
‡
§
Unused
DVSS
Out0 Sig.
‡
CCI0A
†
P1SEL.5
P1DIR.5
ACLK
TACLK
†
‡
§
Timer_A3/Timer0_A3
Timer1_A5 (MSP430x415, MSP430x417 only)
MSP430x412, MSP430x413 only
38
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.6, P1.7 input/output with Schmitt-trigger
Pad Logic
Note: Port Function Is Active if CAPD.6 = 0
CAPD.6
P1SEL.6
0: Input
1: Output
0
P1DIR.6
1
P1DIR.6
P1.6/
CA0
0
P1OUT.6
1
DVSS
Bus
Keeper
P1IN.6
EN
unused
D
P1IE.7
P1IFG.7
P1IRQ.07
EN
Set
Interrupt
Edge
Select
Q
P1IES.x
P1SEL.x
Comparator_A
CAF
P2CA
AVcc
CAREF
CAEX
CA0
CA1
+
CCI1B
to Timer_Ax
−
2
Reference Block
CAREF
Pad Logic
Note: Port Function Is Active if CAPD.7 = 0
CAPD.7
P1SEL.7
P1DIR.7
P1DIR.7
0: Input
1: Output
0
1
0
1
P1.7/
CA1
P1OUT.7
DVSS
Bus
Keeper
P1IN.7
EN
D
unused
P1IE.7
EN
P1IRQ.07
Interrupt
Edge
Select
Q
P1IFG.7
Set
P1IES.7
P1SEL.7
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.7, input/output with Schmitt-trigger
P2.0, P2.1
LCDM.5
LCDM.6
P2.2 to P2.5
LCDM.7
0: Port Active
1: Segment xx
Function Active
P2.6, P2.7
Pad Logic
Segment xx
P2SEL.x
0: Input
1: Output
0
1
0
1
P2DIR.x
Direction Control
From Module
P2.x
P2OUT.x
MSP430x412,
MSP430x413 only
P2.0/TA2
Module X OUT
Bus
keeper
P2.1
P2IN.x
P2.2/S23
P2.3/S22
P2.4/S21
P2.5/S20
P2.6/CAOUT/S19
P2.7/S18
EN
D
Module X IN
P2IRQ.x
MSP430x415,
MSP430x417 only
P2.0/TA0.2
P2.1/TA1.1
P2.2/TA1.2/S23
P2.3/TA1.3/S22
P2.4/TA1.4/S21
P2.5/TA1CLK/S20
P2.6/CAOUT/S19
P2.7/S18
P2IE.x
EN
Interrupt
Edge
Select
Q
P2IFG.x
Set
P2IES.x P2SEL.x
NOTE: 0 ≤ x ≤ 7
Direction
Control
From Module
Module X
OUT
PnOUT.x
PnIE.x
PnIES.x
PnIN.x
Module X IN
PnSEL.x
PnDIR.x
PnIFG.x
†
†
CCI2A
Out2 Sig.
P2SEL.0
P2SEL.1
P2SEL.2
P2SEL.3
P2SEL.4
P2SEL.5
P2SEL.6
P2SEL.7
P2DIR.0
P2DIR.1
P2DIR.2
P2DIR.3
P2DIR.4
P2DIR.5
P2DIR.6
P2DIR.7
P2DIR.0
P2DIR.1
P2DIR.2
P2DIR.3
P2DIR.4
P2DIR.5
P2DIR.6
P2DIR.7
P2OUT.0
P2OUT.1
P2OUT.2
P2OUT.3
P2OUT.4
P2OUT.5
P2OUT.6
P2OUT.7
P2IN.0
P2IN.1
P2IN.2
P2IN.3
P2IN.4
P2IN.5
P2IN.6
P2IN.7
P2IE.0
P2IE.1
P2IE.2
P2IE.3
P2IE.4
P2IE.5
P2IE.6
P2IE.7
P2IFG.0
P2IFG.1
P2IFG.2
P2IFG.3
P2IFG.4
P2IFG.5
P2IFG.6
P2IFG.7
P2IES.0
P2IES.1
P2IES.2
P2IES.3
P2IES.4
P2IES.5
P2IES.6
P2IES.7
Unused§
DVSS§
‡
‡
CCI1A
Out1 Sig.
DVSS§
Unused§
‡
‡
CCI2A
Out2 Sig.
Unused§
DVSS§
‡
‡
‡
CCI3A
Out3 Sig.
DVSS§
Out4 Sig.
Unused§
‡
CCI4A
Unused§
DVSS
CAOUT
DVSS
‡
TA1CLK
Unused
Unused
†
‡
§
Timer_A3/Timer0_A3
Timer1_A5 (MSP430x415, MSP430x417 only)
MSP430x412, MSP430x413 only
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0, P3.7, input/output with Schmitt-trigger
LCDM.5
P3.2 to P3.7
LCDM.6
LCDM.7
P3.0, P3.1
0: Port Active
1: Segment xx
Function Active
Pad Logic
Segment xx
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
1
0
1
From Module
P3.x
P3OUT.x
Module X OUT
Bus
keeper
P3.0/S17
P3.1/S16
P3.2/S15
P3.3/S14
P3.4/S13
P3.5/S12
P3.6/S11
P3.7/S10
P3IN.x
EN
D
Module X IN
NOTE: 0 ≤ x ≤ 7
Direction
Control
From Module
Module X
OUT
PnOUT.x
PnIN.x
Module X IN
PnSEL.x
PnDIR.x
P3IN.0
P3IN.1
P3IN.2
P3IN.3
P3IN.4
P3IN.5
P3IN.6
P3IN.7
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
P3SEL.0
P3SEL.1
P3SEL.2
P3SEL.3
P3SEL.4
P3SEL.5
P3SEL.6
P3SEL.7
P3DIR.0
P3DIR.1
P3DIR.2
P3DIR.3
P3DIR.4
P3DIR.5
P3DIR.6
P3DIR.7
P3DIR.0
P3OUT.0
P3OUT.1
P3OUT.2
P3OUT.3
P3OUT.4
P3OUT.5
P3OUT.6
P3OUT.7
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
P3DIR.1
P3DIR.2
P3DIR.3
P3DIR.4
P3DIR.5
P3DIR.6
P3DIR.7
DVSS
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.0 to P4.7, input/output with Schmitt-trigger
LCDM.5
0: Port Active
LCDM.6
1: Segment xx
LCDM.7
Function Active
Pad Logic
Segment xx
P4SEL.x
0: Input
1: Output
0
1
0
1
P4DIR.x
Direction Control
From Module
P4.x
P4OUT.x
Module X OUT
Bus
keeper
P4.0/S9
P4.1/S8
P4.2/S7
P4.3/S6
P4.4/S5
P4.5/S4
P4.6/S3
P4.7/S2
P4IN.x
EN
D
Module X IN
NOTE: 0 ≤ x ≤ 7
Direction
Control
From Module
Module X
OUT
PnOUT.x
PnIN.x
Module X IN
PnSEL.x
PnDIR.x
P4IN.0
P4IN.1
P4IN.2
P4IN.3
P4IN.4
P4IN.5
P4IN.6
P4IN.7
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
P4SEL.0
P4SEL.1
P4SEL.2
P4SEL.3
P4SEL.4
P4SEL.5
P4SEL.6
P4SEL.7
P4DIR.0
P4DIR.1
P4DIR.2
P4DIR.3
P4DIR.4
P4DIR.5
P4DIR.6
P4DIR.7
P4DIR.0
P4OUT.0
P4OUT.1
P4OUT.2
P4OUT.3
P4OUT.4
P4OUT.5
P4OUT.6
P4OUT.7
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
P4DIR.1
P4DIR.2
P4DIR.3
P4DIR.4
P4DIR.5
P4DIR.6
P4DIR.7
DVSS
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.0, P5.1, input/output with Schmitt-trigger
LCDM.5
0: Port Active
LCDM.6
1: Segment
LCDM.7
Function Active
Pad Logic
Segment xx or
COMx or Rxx
P5SEL.x
0: Input
1: Output
0
1
0
1
P5DIR.x
Direction Control
From Module
P5.x
P5OUT.x
Module X OUT
Bus
P5.0/S1
P5.1/S0
keeper
P5IN.x
EN
D
Module X IN
NOTE: x = 0, 1
Direction
Control
From Module
Module X
OUT
PnOUT.x
Segment
PnIN.x
Module X IN
PnSEL.x
PnDIR.x
P5IN.0
P5IN.1
Unused
Unused
S1
S0
P5SEL.0
P5SEL.1
P5DIR.0
P5DIR.1
P5DIR.0
P5DIR.1
P5OUT.0
P5OUT.1
DVSS
DVSS
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.2, P5.4, input/output with Schmitt-trigger
0: Port Active
1: COMx Function
Active
Pad Logic
COMx
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
1
0
1
From Module
P5.x
P5OUT.x
Module X OUT
Bus
P5.2/COM1
P5.3/COM2
P5.4/COM3
keeper
P5IN.x
EN
D
Module X IN
NOTE: 2 ≤ x ≤ 4
Direction
Control
From Module
Module X
OUT
PnOUT.x
COMx
PnIN.x
Module X IN
PnSEL.x
PnDIR.x
P5IN.2
P5IN.3
P5IN.4
Unused
Unused
Unused
COM1
COM2
COM3
P5SEL.2
P5SEL.3
P5SEL.4
P5DIR.2
P5DIR.3
P5DIR.4
P5DIR.2
P5DIR.3
P5DIR.4
P5OUT.2
P5OUT.3
P5OUT.4
DVSS
DVSS
DVSS
NOTE:
The direction control bits P5SEL.2, P5SEL.3, and P5SEL.4 are used to distinguish between port
and common functions. Note that a 4MUX LCD requires all common signals COM3 to COM0, a
3MUX LCD requires COM2 to COM0, 2MUX LCD requires COM1 to COM0, and a static LCD
requires only COM0.
44
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ꢀ ꢈꢉꢊ ꢋ ꢁꢈ ꢌ ꢍꢎꢏ ꢀ ꢈꢐꢑꢒ ꢐꢒ ꢍꢓ ꢑꢒ ꢏꢏ ꢊꢑ
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.5 to P5.7, input/output with Schmitt-trigger
0: Port Active
1: Rxx Function
Active
Pad Logic
Rxx
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
1
0
1
From Module
P5.x
P5OUT.x
Module X OUT
Bus
P5.5/R13
P5.6/R23
P5.7/R33
keeper
P5IN.x
EN
D
Module X IN
NOTE: 5 ≤ x ≤ 7
Direction
Control
From Module
Module X
OUT
PnOUT.x
Rxx
PnIN.x
Module X IN
PnSEL.x
PnDIR.x
P5SEL.5
P5SEL.6
P5SEL.7
P5DIR.5
P5DIR.6
P5DIR.7
P5DIR.5
P5DIR.6
P5DIR.7
P5OUT.5
P5OUT.6
P5OUT.7
DVSS
DVSS
DVSS
P5IN.5
P5IN.6
P5IN.7
Unused
Unused
Unused
R13
R23
R33
NOTE:
The direction control bits P5SEL.5, P5SEL.6, and P5SEL.7 are used to distinguish between port
and LCD analog level functions. Note that 4MUX and 3MUX LCDs require all Rxx signals R33 to
R03, a 2MUX LCD requires R33, R13, and R03, and a static LCD requires only R33 and R03.
45
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.0 to P6.6, input/output with Schmitt-trigger
P6SEL.x
0: Input
1: Output
0
P6DIR.x
Direction Control
1
0
1
From Module
P6.x
P6OUT.x
Module X OUT
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6IN.x
EN
D
Module X IN
NOTE: 0 ≤ x ≤ 6
Direction
Control
From Module
Module X
OUT
PnOUT.x
PnIN.x
Module X IN
PnSEL.x
PnDIR.x
P6IN.0
P6IN.1
P6IN.2
P6IN.3
P6IN.4
P6IN.5
P6IN.6
Unused
Unused
Unused
Unused
Unused
Unused
Unused
P6SEL.0
P6SEL.1
P6SEL.2
P6SEL.3
P6SEL.4
P6SEL.5
P6SEL.6
P6DIR.0
P6DIR.1
P6DIR.2
P6DIR.3
P6DIR.4
P6DIR.5
P6DIR.6
P6DIR.0
P6DIR.1
P6DIR.2
P6DIR.3
P6DIR.4
P6DIR.5
P6DIR.6
P6OUT.0
P6OUT.1
P6OUT.2
P6OUT.3
P6OUT.4
P6OUT.5
P6OUT.6
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
46
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.7 input/output with Schmitt-trigger
MSP430x412/413 only
P6SEL.7
0: Input
1: Output
0
P6DIR.7
Direction Control
1
0
1
From Module
P6.x
P6.7
P6OUT.7
Module X OUT
P6IN.7
EN
D
Module X IN
Direction
Control
From Module
Module X
OUT
PnOUT.x
PnIN.x
Module X IN
PnSEL.x
PnDIR.x
P6IN.7
P6SEL.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
Unused
47
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.7 input/output with Schmitt-trigger
MSP430F415/417 only
SVS VLDx=15
P6SEL.7
0
0: Input
P6DIR.7
1: Output
1
0
1
Pad Logic
P6.7/SVSIN
P6OUT.7
DVss
Bus Keeper
P6IN.7
EN
D
Module X IN
SVS VLDx=15
To SVS
1
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin.
SVS VLDx = 15
P6SEL.7
P6DIR.7
Port Function
P6.7 Input
P6.7 Output
Undefined
SVSIN
0
0
0
1
0
0
1
X
0
1
X
X
48
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
DV
CC
by JTAG
TDI
Burn and Test
Fuse
TDI/TCLK
Test
and
DV
CC
TMS
TCK
Emulation
Module
TMS
DV
CC
TCK
RST/NMI
Tau ~ 50 ns
Brownout
D
U
S
G
G
D
U
S
TCK
49
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SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I , of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
TF
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 22). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
The JTAG pins are terminated internally, and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I
TF
I
TDI/TCLK
Figure 22. Fuse Check Mode Current, MSP430C41x, MSP430F41x
50
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MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
0°–7°
11,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040152/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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