MSC1213Y5 [TI]
Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converters (DACs) with 8051 Microcontroller and Flash Memory; 高精度模拟数字转换器（ ADC ）和数字 - 模拟转换器（DAC ）与8051微控制器和闪存
| 型号： | MSC1213Y5 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converters (DACs) with 8051 Microcontroller and Flash Memory |
| 文件： | 总105页 (文件大小：912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂꢃ ꢄ ꢃꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢄ
ꢀ ꢁꢂꢃ ꢄ ꢃ ꢆ ꢅ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢇ
SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
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ꢒ ꢏꢛ ꢗ ꢌꢔ ꢌꢖ ꢒ ꢓꢕ ꢖ ꢎꢕ ꢑ ꢏꢒꢓ ꢎꢔ ꢂ ꢎꢏꢘꢊ ꢉ ꢖ ꢊꢉ ꢍ ꢙ ꢗꢑ ꢂꢍ ꢚ
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Peripheral Features
34 I/O Pins
FEATURES
ANALOG FEATURES
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Additional 32-Bit Accumulator
Three 16-Bit Timer/Counters
System Timers
D
24 Bits No Missing Codes
22 Bits Effective Resolution at 10Hz
− Low Noise: 75nV
D
Programmable Watchdog Timer
Full-Duplex Dual USARTs
Master/Slave SPI with DMA
D
D
PGA From 1 to 128
Precision On-Chip Voltage Reference
− Accuracy: 0.2%
2
Multi-master I C (MSC1211 and MSC1213)
− Drift: 5ppm/°C
16-Bit PWM
Power Management Control
Internal Clock Divider
Idle Mode Current < 200µA
Stop Mode Current < 100nA
Programmable Brownout Reset
Programmable Low-Voltage Detect
21 Interrupt Sources
D
D
D
D
D
D
D
D
8 Differential/Single-Ended Channels
On-Chip Offset/Gain Calibration
Offset Drift: 0.02ppm/°C
Gain Drift: 0.5ppm/°C
On-Chip Temperature Sensor
Selectable Buffer Input
Burnout Detect
16-Bit Monotonic Voltage DACS:
− Quad Voltage DACs (MSC1211, MSC1212)
− Dual Voltage DACs (MSC1213, MSC1214)
Two Hardware Breakpoints
GENERAL FEATURES
D
D
D
D
Pin-Compatible with MSC1210
Package: TQFP-64
DIGITAL FEATURES
Microcontroller Core
Low Power: 4mW
Industrial Temperature Range:
−40°C to +125°C
Power Supply: 2.7V to 5.25V
D
8051-Compatible
High-Speed Core
− 4 Clocks per Instruction Cycle
DC to 40MHz at +85ꢀ C
Single Instruction 100ns
Dual Data Pointer
D
D
D
D
D
AD PPLICATIONS
Memory
Industrial Process Control
D
D
D
Up To 32kB Flash Memory
D
D
D
D
D
D
D
D
D
D
Instrumentation
Liquid/Gas Chromatography
Blood Analysis
Smart Transmitters
Portable Instruments
Weigh Scales
Pressure Transducers
Intelligent Sensors
Portable Applications
DAS Systems
Flash Memory Partitioning
Endurance 1M Erase/Write Cycles,
100-Year Data Retention
D
D
D
D
D
D
In-System Serially Programmable
External Program/Data Memory (64kB)
1,280 Bytes Data SRAM
Flash Memory Security
2kB Boot ROM
Programmable Wait State Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
I C is a trademark of Philips corporation. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners.
ꢈꢤ ꢥ ꢗꢦ ꢂ ꢧꢨ ꢥꢩ ꢗ ꢑꢧꢑ ꢌꢏ ꢪꢎ ꢉ ꢢꢒ ꢖꢌꢎꢏ ꢌꢍ ꢋꢫ ꢉ ꢉ ꢊꢏꢖ ꢒꢍ ꢎꢪ ꢬꢫꢭ ꢓꢌꢋ ꢒꢖꢌ ꢎꢏ ꢛꢒ ꢖꢊꢮ ꢈꢉ ꢎꢛꢫ ꢋꢖꢍ
ꢋ ꢎꢏ ꢪꢎꢉ ꢢ ꢖꢎ ꢍ ꢬꢊ ꢋ ꢌ ꢪꢌ ꢋ ꢒ ꢖꢌ ꢎꢏꢍ ꢬ ꢊꢉ ꢖꢝꢊ ꢖꢊ ꢉ ꢢꢍ ꢎꢪ ꢧꢊꢯ ꢒꢍ ꢨꢏꢍ ꢖꢉ ꢫꢢ ꢊꢏꢖ ꢍ ꢍꢖ ꢒꢏꢛ ꢒꢉ ꢛ ꢜ ꢒꢉ ꢉ ꢒ ꢏꢖꢣꢮ
ꢈꢉ ꢎ ꢛꢫꢋ ꢖ ꢌꢎ ꢏ ꢬꢉ ꢎ ꢋ ꢊ ꢍ ꢍ ꢌꢏ ꢔ ꢛꢎ ꢊ ꢍ ꢏꢎꢖ ꢏꢊ ꢋꢊ ꢍꢍ ꢒꢉ ꢌꢓ ꢣ ꢌꢏꢋ ꢓꢫꢛ ꢊ ꢖꢊ ꢍꢖꢌ ꢏꢔ ꢎꢪ ꢒꢓ ꢓ ꢬꢒ ꢉ ꢒꢢ ꢊꢖꢊ ꢉ ꢍꢮ
Copyright 2004−2005, Texas Instruments Incorporated
www.ti.com
ꢀ ꢁ ꢂꢃ ꢄ ꢃꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢃ ꢄ
ꢀ ꢁ ꢂꢃ ꢄ ꢃ ꢆꢅ ꢀ ꢁꢂ ꢃꢄ ꢃ ꢇ
www.ti.com
SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
(1)
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
FLASH
MEMORY
16-BIT
DACS
PACKAGE
DESIGNATOR
PACKAGE
MARKING
2
PRODUCT
MSC1211Y2
MSC1211Y3
MSC1211Y4
MSC1211Y5
MSC1212Y2
MSC1212Y3
MSC1212Y4
MSC1212Y5
MSC1213Y2
MSC1213Y3
MSC1213Y4
MSC1213Y5
MSC1214Y2
MSC1214Y3
MSC1214Y4
MSC1214Y5
I C
PACKAGE-LEAD
4k
8k
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
Y
Y
Y
Y
N
N
N
N
Y
Y
Y
Y
N
N
N
N
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
MSC1211Y2
MSC1211Y3
MSC1211Y4
MSC1211Y5
MSC1212Y2
MSC1212Y3
MSC1212Y4
MSC1212Y4
MSC1213Y2
MSC1213Y3
MSC1213Y4
MSC1213Y5
MSC1214Y2
MSC1214Y3
MSC1214Y4
MSC1214Y5
16k
32k
4k
8k
16k
32k
4k
8k
16k
32k
4k
8k
16k
32k
(1)
For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet, or refer to our
web site at www.ti.com.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
(1)
ABSOLUTE MAXIMUM RATINGS
MSC1211/12/13/14
UNITS
Analog Inputs
Momentary
Continuous
100
10
mA
mA
V
Input current
Input voltage
AGND − 0.3 to AV + 0.3
DD
Power Supply
DV
to DGND
to AGND
−0.3 to +6
−0.3 to +6
−0.3 to +0.3
V
V
DD
AV
DD
AGND to DGND
to AGND
V
V
−0.3 to AV
DD
+ 0.3
+ 0.3
V
REF
Digital input voltage to DGND
Digital output voltage to DGND
−0.3 to DV
V
DD
−0.3 to DV
+ 0.3
V
DD
Maximum junction temperature (T Max)
J
Operating temperature range
+150
°C
°C
°C
°C
°C/W
°C/W
°C/W
W
−40 to +125
−65 to +150
+235
Storage temperature range
Lead temperature (soldering, 10s)
High K (2s 2p)
Low K (1s)
48.9
Junction to ambient (q
)
JA
72.9
Thermal resistance
Junction to case (q
)
12.2
JC
Package power dissipation
Output current, all pins
Output pin short-circuit
Digital Outputs
(T Max − T
)/q
J
AMBIENT JA
200
10
mA
s
Output current
Continuous
100
100
300
mA
mA
mA
I/O source/sink current
Power pin maximum
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for
extended periods may affect device reliability.
2
ꢀ ꢁꢂꢃ ꢄ ꢃꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢄ
ꢀ ꢁꢂꢃ ꢄ ꢃ ꢆ ꢅ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢇ
www.ti.com
SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
MSC121xYX FAMILY FEATURES
(1)
(2)
(2)
(2)
(2)
MSC121xY5
FEATURES
MSC121xY2
MSC121xY3
MSC121xY4
Up to 16k
Up to 16k
256
Flash Program Memory (Bytes)
Flash Data Memory (Bytes)
Internal Scratchpad SRAM (Bytes)
Internal MOVX RAM (Bytes)
Externally Accessible Memory (Bytes)
Up to 4k
Up to 4k
256
Up to 8k
Up to 8k
Up to 32k
Up to 32k
256
256
1024
1024
1024
1024
64k Program, 64k Data
64k Program, 64k Data
64k Program, 64k Data
64k Program, 64k Data
(1)
(2)
All peripheral features are the same on all devices; the flash memory size is the only difference.
The last digit of the part number (N) represents the onboard flash size = (2N)kBytes.
ELECTRICAL CHARACTERISTICS: AVDD = 5V
3
All specifications from T
to T
, DV
= +2.7V to 5.25V, AV
= +5V, f
= 15.625kHz, PGA = 1, filter = Sinc , Buffer ON, f
= 10Hz, Bipolar, f
= 8MHz,
= 200pF, unless otherwise noted.
MIN
MAX
DD
DD
MOD
, V
DAC REF
DATA
CLK
and V
REF
≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For V
= AV , R
DD LOAD
= 10kΩ, and C
LOAD
MSC1211/12/13/14
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Analog Inputs (AIN0−AIN7, AINCOM)
Buffer OFF
Buffer ON
AGND − 0.1
AV
AV
+ 0.1
V
V
DD
DD
Analog Input Range
AGND + 50mV
− 1.5
/PGA
Full-Scale Input Voltage Range
Differential Input Impedance
Input Current
(AIN+) − (AIN−)
Buffer OFF
Buffer ON
V
V
REF
(1)
7/PGA
MΩ
nA
0.5
Fast Settling Filter
2
−3dB
0.469 • fDATA
0.318 • fDATA
0.262 • fDATA
Sinc Filter
−3dB
Bandwidth
3
Sinc Filter
−3dB
Programmable Gain Amplifier
Input Capacitance
User-Selectable Gain Range
Buffer ON
1
128
9
0.5
2
pF
pA
µA
Input Leakage Current
Burnout Current Sources
Multiplexer Channel ON, T = +25°C
Buffer ON
ADC Offset DAC
Offset DAC Range
Bipolar Mode
V /(2 • PGA)
REF
V
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
8
Bits
1.5
1
% of Range
ppm/°C
System Performance
Resolution
24
Bits
Bits
ENOB
See Typical Characteristics
22
Output Noise
See Typical Characteristics
No Missing Codes
Integral Nonlinearity
Offset Error
Sinc3 Filter, Decimation >360
End Point Fit, Bipolar Mode
After Calibration
24
Bits
%FSR
ppm of FS
ppm of FS/°C
%
3
0.0015
3.5
(2)
Offset Drift
Before Calibration
0.001
−0.002
0.5
(3)
Gain Error
After Calibration
(2)
Gain Error Drift
Before Calibration
ppm/°C
% of FS
% of FS
dB
System Gain Calibration Range
System Offset Calibration Range
80
120
50
−50
At DC
115
130
120
120
100
100
92
f
f
f
f
f
= 60Hz, f
= 50HZ, f
= 60Hz, f
= 10Hz
= 50Hz
= 60Hz
= 50Hz
= 60Hz
dB
CM
CM
CM
SIG
SIG
DATA
DATA
DATA
Common-Mode Rejection
Normal-Mode Rejection
dB
dB
= 50Hz, f
= 60Hz, f
dB
DATA
dB
DATA
(4)
Power-Supply Rejection
(1)
At DC, dB = −20log(∆VOUT/∆V
)
dB
DD
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Calibration can minimize these errors.
The self gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
∆V is change in digital result.
OUT
9pF switched capacitor at fSAMP clock frequency (see Figure 14).
Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
Ensured by design and characterization; not production tested.
Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).
3
ꢀ ꢁ ꢂꢃ ꢄ ꢃꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢃ ꢄ
ꢀ ꢁ ꢂꢃ ꢄ ꢃ ꢆꢅ ꢀ ꢁꢂ ꢃꢄ ꢃ ꢇ
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued)
3
All specifications from T
to T
, DV
= +2.7V to 5.25V, AV
= +5V, f
= 15.625kHz, PGA = 1, filter = Sinc , Buffer ON, f
= 10Hz, Bipolar, f
= 8MHz,
= 200pF, unless otherwise noted.
MIN
MAX
DD
DD
MOD
, V
DAC REF
DATA
CLK
and V
REF
≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For V
= AV , R
DD LOAD
= 10kΩ, and C
LOAD
MSC1211/12/13/14
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Voltage Reference Inputs
(3)
DD
Reference Input Range
REF IN+, REF IN−
AGND
0.1
AV
V
V
V
≡ (REF IN+) − (REF IN−)
2.5
110
1
AV
V
REF
REF
At DC
DD
V
Common-Mode Rejection
(5)
dB
µA
kΩ
REF
Input Current
V
= 2.5V, ADC Only
REF
DAC Reference Input Resistance
For Each DAC, PGA = 1
20
On-Chip Voltage Reference
VREFH = 1 at +25°C, REFCLK = 250kHz
VREFH = 0 at +25°C, REFCLK = 250kHz
2.495
2.5
1.25
65
2.505
V
V
Output Voltage
Power-Supply Rejection Ratio
Short-Circuit Current Source
Short-Circuit Current Sink
Short-Circuit Duration
dB
mA
µA
2.6
50
Sink or Source
Indefinite
5
Drift
ppm/°C
Ω
Output Impedance
Sourcing 100µA
3
Startup Time from Power ON
Temperature Sensor Voltage
Temperature Sensor Coefficient
C
= 0.1µF
8
ms
REFOUT
Buffer ON, T = +25°C
Buffer ON
115
375
mV
µV/°C
(6)
Voltage DAC Static Performance
Resolution
16
Bits
%
Relative Accuracy
Differential Nonlinearity
Zero Code Error
0.05
0.146
1
Ensured Monotonic by Design
All 0s Loaded to DAC Register
All 1s Loaded to DAC Register
LSB
+13
0
+35
mV
Full-Scale Error
−1.25
−1.25
% of FSR
% of FSR
µV/°C
Gain Error
0
+1.25
Zero Code Error Drift
Gain Temperature Coefficient
20
5
ppm of FSR/°C
(7)
Voltage DAC Output Characteristics
Output Voltage Range
Output Voltage Settling Time
Slew Rate
REF IN+ = AV
DD
To 0.003% FSR, 0200h to FD00h
AGND
AV
DD
V
µs
V/µs
Ω
8
1
DC Output Impedance
Short-Circuit Current
7
All 1s Loaded to DAC Register
20
mA
IDAC Output Characteristics
Full-Scale Output Current
Maximum V
REF
= 2.5V
25
mA
Maximum Short-Circuit Current Duration
Compliance Voltage
Relative Accuracy
Indefinite
AV
DD
− 1.5
V
0.185
% of FSR
µA
% of FSR
% of FSR
Zero Code Error
All 0s Loaded to DAC Register
All 1s Loaded to DAC Register
0.5
Full-Scale Error
−0.4
−0.6
Gain Error
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Calibration can minimize these errors.
The self gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
∆V is change in digital result.
OUT
9pF switched capacitor at fSAMP clock frequency (see Figure 14).
Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
Ensured by design and characterization; not production tested.
Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).
4
ꢀ ꢁꢂꢃ ꢄ ꢃꢃ ꢅ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢄ
ꢀ ꢁꢂꢃ ꢄ ꢃ ꢆ ꢅ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢇ
www.ti.com
SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued)
3
All specifications from T
to T
, DV
= +2.7V to 5.25V, AV
= +5V, f
= 15.625kHz, PGA = 1, filter = Sinc , Buffer ON, f
= 10Hz, Bipolar, f
= 8MHz,
= 200pF, unless otherwise noted.
MIN
MAX
DD
DD
MOD
, V
DAC REF
DATA
CLK
and V
REF
≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise noted. For V
= AV , R
DD LOAD
= 10kΩ, and C
LOAD
MSC1211/12/13/14
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Analog Power-Supply Requirements
Analog Power-Supply Voltage
Analog Off Current
AV
DD
4.75
5
5.25
V
(8)
Analog OFF, PDCON = 48h
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
< 1
200
500
240
850
250
nA
µA
µA
µA
µA
µA
ADC Current (I
)
ADC
Analog
Power-Supply
Current
PGA = 128, Buffer ON
VDAC Current (I
)
Excluding Load Current, External Reference
VDAC
V
Supply Current
)
REF
ADC ON, V
DAC
OFF
250
µA
(I
VREF
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Calibration can minimize these errors.
The self gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
∆V is change in digital result.
OUT
9pF switched capacitor at fSAMP clock frequency (see Figure 14).
Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
Ensured by design and characterization; not production tested.
Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).
ELECTRICAL CHARACTERISTICS: AVDD = 3V
3
All specifications from T
to T
, DV
= +2.7V to 5.25V, AV
= +3V, f
= 15.625kHz, PGA = 1, filter = Sinc , Buffer ON, f
= 10Hz, Bipolar, f
= 8MHz,
MIN
MAX
DD
DD
MOD
DATA
CLK
and V
REF
≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For V
, V
= AV , R
DD LOAD
= 10kΩ, and C = 200pF, unless otherwise noted.
LOAD
DAC REF
MSC1211/12/13/14
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Analog Inputs (AIN0−AIN7, AINCOM)
Buffer OFF
Buffer ON
AGND − 0.1
AV
AV
+ 0.1
V
V
DD
DD
Analog Input Range
AGND + 50mV
− 1.5
/PGA
Full-Scale Input Voltage Range
Differential Input Impedance
Input Current
(AIN+) − (AIN−)
Buffer OFF
Buffer ON
−3dB
V
V
REF
(1)
7/PGA
MΩ
nA
0.5
Fast Settling Filter
2
0.469 • f
0.318 • f
0.262 • f
DATA
DATA
DATA
Sinc Filter
−3dB
Bandwidth
3
Sinc Filter
−3dB
Programmable Gain Amplifier
Input Capacitance
User-Selectable Gain Range
Buffer ON
1
128
9
0.5
2
pF
pA
µA
Input Leakage Current
Burnout Current Sources
Modulator OFF, T = +25°C
Sensor Input Open Circuit
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Calibration can minimize these errors.
The gain calibration cannot have a REF IN+ of more than AV
−1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
DD
∆V
OUT
is change in digital result.
9pF switched capacitor at f
clock frequency (see Figure 14).
SAMP
Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
Ensured by design and characterization; not production tested.
Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).
5
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued)
3
All specifications from T
to T
, DV
= +2.7V to 5.25V, AV
= +3V, f
= 15.625kHz, PGA = 1, filter = Sinc , Buffer ON, f
= 10Hz, Bipolar, f
= 8MHz,
= 200pF, unless otherwise noted.
MIN
MAX
DD
DD
MOD
DATA
CLK
and V
REF
≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For V
, V
= AV , R
DD LOAD
= 10kΩ, and C
LOAD
DAC REF
MSC1211/12/13/14
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
ADC Offset DAC
Offset DAC Range
Bipolar Mode
V
/(2•PGA)
V
REF
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
8
Bits
1.5
1
% of Range
ppm/°C
System Performance
Resolution
24
24
Bits
Bits
ENOB
22
Output Noise
See Typical Characteristics
3
No Missing Codes
Integral Nonlinearity
Offset Error
Sinc Filter
Bits
%FSR
ppm of FS
ppm of FS/°C
%
End Point Fit, Bipolar Mode
After Calibration
3
0.0015
3.5
(2)
Offset Drift
Before Calibration
After Calibration
0.001
−0.002
1.0
(3)
Gain Error
(2)
Gain Error Drift
Before Calibration
ppm/°C
% of FS
% of FS
dB
System Gain Calibration Range
System Offset Calibration Range
80
120
50
−50
At DC
115
130
120
120
100
100
92
f
f
f
f
f
= 60Hz, f
= 50Hz, f
= 60Hz, f
= 10Hz
= 50Hz
= 60Hz
= 50Hz
= 60Hz
dB
CM
CM
CM
SIG
SIG
DATA
DATA
DATA
Common-Mode Rejection
dB
dB
= 50Hz, f
= 60Hz, f
dB
DATA
Normal Mode Rejection
dB
DATA
(4)
Power-Supply Rejection
Voltage Reference Inputs
Reference Input Range
At DC, dB = −20log(∆VOUT/∆V
)
dB
DD
(3)
DD
REF IN+, REF IN−
AGND
0.1
AV
V
V
V
V
≡ (REF IN+) − (REF IN−)
1.25
110
3
AV
DD
V
REF
REF
At DC
Common-Mode Rejection
(5)
dB
µA
kΩ
REF
Input Current
V
= 1.25V, ADC Only
REF
DAC Reference Input Resistance
For Each DAC, PGA = 1
20
On-Chip Voltage Reference
Output Voltage
VREFH = 0 at +25°C, REFCLK = 250kHz
1.245
1.25
1.255
V
Power-Supply Rejection Ratio
Short-Circuit Current Source
Short-Circuit Current Sink
Short-Circuit Duration
Drift
65
dB
mA
µA
2.6
50
Sink or Source
Indefinite
5
3
ppm/°C
Ω
Output Impedance
Sourcing 100µA
CREFOUT = 0.1µF
Buffer ON, T = +25°C
Buffer ON
Startup Time from Power ON
Temperature Sensor Voltage
Temperature Sensor Coefficient
8
ms
115
375
mV
µV/°C
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Calibration can minimize these errors.
The gain calibration cannot have a REF IN+ of more than AV
−1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
DD
∆V
OUT
is change in digital result.
9pF switched capacitor at f
clock frequency (see Figure 14).
SAMP
Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
Ensured by design and characterization; not production tested.
Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).
6
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www.ti.com
SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued)
3
All specifications from T
to T
, DV
= +2.7V to 5.25V, AV
= +3V, f
= 15.625kHz, PGA = 1, filter = Sinc , Buffer ON, f
= 10Hz, Bipolar, f
= 8MHz,
= 200pF, unless otherwise noted.
MIN
MAX
DD
DD
MOD
DATA
CLK
and V
REF
≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. For V
, V
= AV , R
DD LOAD
= 10kΩ, and C
LOAD
DAC REF
MSC1211/12/13/14
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
(6)
Voltage DAC Static Performance
Resolution
16
Bits
% of FSR
LSB
Relative Accuracy
Differential Nonlinearity
Zero Code Error
0.05
0.146
1
Ensured Monotonic by Design
All 0s Loaded to DAC Register
All 1s Loaded to DAC Register
+13
0
+35
mV
Full-Scale Error
−1.25
−1.25
% of FSR
% of FSR
µV/°C
Gain Error
0
1.25
AVDD
Zero Code Error Drift
Gain Temperature Coefficient
20
5
ppm of FSR/°C
(7)
Voltage DAC Output Characteristics
Output Voltage Range
Output Voltage Settling Time
Slew Rate
AGND
V
µs
V/µs
Ω
To 0.003% FSR, 0200h to FD00h
8
1
DC Output Impedance
Short-Circuit Current
7
All 1s Loaded to DAC Register
Maximum VREF = 1.25V
16
mA
IDAC Output Characteristics
Full-Scale Output Current
25
mA
Maximum Short-Circuit Current Duration
Compliance Voltage
Relative Accuracy
Indefinite
AV
DD
− 1.5
V
Over Full Range
0.185
0.5
% of FSR
% of FSR
% of FSR
% of FSR
Zero Code Error
Full-Scale Error
−0.4
−0.6
Gain Error
Analog Power-Supply Requirements
Analog Power-Supply Voltage
Analog Off Current
AV
DD
2.7
3.0
< 1
3.6
V
(8)
Analog OFF, PDCON = 47h
PGA = 1, Buffer OFF
PGA = 128, Buffer ON
PGA = 1, Buffer OFF
PGA = 128, Buffer ON
nA
µA
µA
µA
µA
200
500
240
850
ADC Current (I
)
ADC
Analog
Power-Supply
Current
Excluding Load Current, External
Reference
VDAC Current (I
)
250
250
µA
µA
VDAC
V
Supply Current
)
REF
(I
VDAC
(1)
The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64).
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Calibration can minimize these errors.
The gain calibration cannot have a REF IN+ of more than AV
−1.5V with Buffer ON. To calibrate gain, turn Buffer OFF.
DD
∆V
OUT
is change in digital result.
9pF switched capacitor at f
clock frequency (see Figure 14).
SAMP
Linearity calculated using a reduced code range of 512 to 65024; output unloaded.
Ensured by design and characterization; not production tested.
Analog Brownout Detect OFF (HCR1.3 = 1), Analog LVD OFF (LVDCON.7 = 1).
7
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V
All specifications from T
to T
, FMCON = 10h, all digital outputs high, PDCON = 00h (all peripherals ON) or PDCON = FFh (all peripherals OFF), PSEN and
MIN
MAX
ALE enabled (all peripherals ON) or PSEN and ALE disabled (all peripherals OFF), unless otherwise specified.
MSC1211/12/13/14
TYP
MIN
MAX
PARAMETER
CONDITIONS
UNITS
Digital Power-Supply Requirements
DV
DD
2.7
3
3.6
V
Normal Mode, f
OSC
= 1MHz, peripherals OFF
0.9
1.1
5.7
7.5
100
5
mA
mA
mA
mA
nA
Normal Mode, f
Normal Mode, f
= 1MHz, peripherals ON
= 8MHz, peripherals OFF
= 8MHz, peripherals ON
OSC
OSC
Digital Power-Supply Current
Normal Mode, f
OSC
(1)
Crystal Operation Stop Mode
DV
DD
4.75
5.25
V
Normal Mode, f
OSC
= 1MHz, peripherals OFF
= 1MHz, peripherals ON
= 8MHz, peripherals OFF
= 8MHz, peripherals ON
1.7
2.4
11
mA
mA
mA
mA
nA
Normal Mode, f
Normal Mode, f
OSC
OSC
Digital Power-Supply Current
Normal Mode, f
14.8
100
OSC
(1)
Crystal Operation Stop Mode
DIGITAL INPUT/OUTPUT (CMOS)
V
(except XIN pin)
(except XIN pin)
0.6 • DV
DV
DD
V
V
IH
IL
DD
Logic Level
V
DGND
0.2 • DV
DD
I/O Pin Hysteresis
700
< 1
< 1
mV
pA
pA
V
Ports 0−3, Input Leakage Current, Input Mode
Pins EA, RST Input Leakage Current
V
= DV
DD
or V = 0V
IH
IH
I
= −1mA
DGND
0.4
OL
= −30mA (5V), −20mA (3V)
V
, ALE, PSEN, Ports 0−3, All Output Modes
OL
I
1.5
V
OL
I
= 1mA
DV
− 0.4
DV
DV
− 0.1
− 1.5
DV
V
OH
= 30mA (5V), 20mA (5V)
DD
DD
DD
V
, ALE, PSEN, Ports 0−3, Strong Drive Output
OH
I
V
OH
DD
9
Ports 0−3, Pull-Up Resistors
kΩ
kΩ
Pins ALE, PSEN, Pull-Up Resistors During Reset
OSCILLATOR/CLOCK INPUT/OUTPUT
Flash Programming Mode Only
9
V
(except XIN pin)
(except XIN pin)
XOUT must be unconnected
XOUT must be unconnected
0.6 • DV
DV
V
V
IH
IL
DD
DD
External Oscillator/Clock
(1)
V
DGND
0.2 • DV
DD
Digital Brownout Detect disabled (HCR1.2 = 1), Low Voltage Detect disabled (LVDCON.3 = 1). Ports configured for input or CMOS output.
FLASH MEMORY CHARACTERISTICS: DVDD = 2.7V to 5.25V
MSC1211/12/13/14
TYP
MIN
100,000
100
MAX
PARAMETER
CONDITIONS
UNITS
Flash Memory Endurance
1,000,000
Cycles
Years
ms
Flash Memory Data Retention
Mass and Page Erase Time
Flash Memory Write Time
Set with FER in FTCON
Set with FWR in FTCON
10
30
40
10
25
µs
DV
= 3.0V
= 5.0V
mA
DD
DD
(1)
Flash Programming Current
DV
mA
(1)
Peak current during Mass and Page Erase Time and Memory Write Time.
8
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
AC ELECTRICAL CHARACTERISTICS(1)(2): DVDD = 2.7V to 5.25V
2.7V to 3.6V
4.75V to 5.25V
MAX
MIN
MAX
MIN
SYMBOL
System Clock
(3)
FIGURE
PARAMETER
UNITS
f
4
External Crystal Frequency (f
)
OSC
1
0
0
1
24
24
22
12
1
0
0
1
33
40
36
12
MHz
MHz
MHz
MHz
OSC
External Clock Frequency (f
External Clock Frequency (f
) at +85°C
) at +125°C
OSC
(3)
1/t
OSC
4
4
OSC
(3)
f
OSC
External Ceramic Resonator Frequency (f
)
OSC
Program Memory
t
t
t
t
t
t
t
t
t
t
t
1
1
1
1
1
1
1
1
1
1
1
ALE Pulse Width
1.5t
− 5
1.5t
− 5
− 7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
AVLL
LLAX
LLIV
CLK
CLK
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
0.5t
− 10
0.5t
CLK
CLK
0.5t
0.5t
CLK
CLK
2.5t
− 35
2.5t
− 25
CLK
CLK
0.5t
0.5t
CLK
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLK
PSEN Pulse Width
2t
CLK
− 5
2t
CLK
− 5
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Address to Valid Instruction In
PSEN Low to Address Float
2t
CLK
− 40
2t − 30
CLK
5
−5
t
− 5
t
CLK
CLK
3t
CLK
0
− 40
3t
CLK
0
− 25
Data Memory
(4)
RD Pulse Width (t
RD Pulse Width (t
= 0)
> 0)
2t
− 5
− 5
− 5
− 5
2t
− 5
− 5
− 5
− 5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCS
CLK
CLK
t
MCS
t
2
3
RLRH
(4)
(4)
t
MCS
MCS
WR Pulse Width (t
WR Pulse Width (t
= 0)
> 0)
2t
CLK
2t
CLK
MCS
t
WLWH
(4)
t
t
MCS
MCS
MCS
(4)
RD Low to Valid Data In (t
RD Low to Valid Data In (t
= 0)
> 0)
2t
− 40
− 40
2t
− 30
− 30
MCS
CLK
CLK
t
t
t
2
2
2
RLDV
RHDX
RHDZ
(4)
t
t
MCS
MCS
MCS
Data Hold After Read
−5
−5
(4)
Data Float After Read (t
Data Float After Read (t
= 0)
> 0)
t
t
CLK
MCS
CLK
(4)
(4)
2t
2t
CLK
MCS
CLK
ALE Low to Valid Data In (t
ALE Low to Valid Data In (t
= 0)
2.5t
− 40
2.5t
− 25
MCS
MCS
MCS
MCS
CLK
CLK
t
t
t
t
2
LLDV
AVDV
LLWL
AVWL
(4)
> 0)
t
+ t
− 40
t
+ t
− 25
CLK MCS
CLK MCS
(4)
Address to Valid Data In (t
Address to Valid Data In (t
= 0)
> 0)
3t
− 40
3t
− 25
CLK
+t
CLK
+t
2
(4)
1.5t
−4 0
1.5t
−25
+ 5
CLK MCS
CLK MCS
(4)
ALE Low to RD or WR Low (t
ALE Low to RD or WR Low (t
= 0)
0.5t
− 5
0.5t
+ 5
0.5t
− 5
0.5t
CLK
MCS
MCS
MCS
MCS
CLK
CLK
CLK
2, 3
2, 3
(4)
> 0)
t
t
− 5
− 5
− 5
t
+ 5
t
t
− 5
t
+ 5
CLK
CLK
CLK
CLK
CLK
(4)
Address to RD or WR Low (t
Address to RD or WR Low (t
= 0)
> 0)
− 5
− 5
CLK
(4)
2t
CLK
2t
CLK
t
t
t
3
3
2
Data Valid to WR Transition
Data Hold After WR
−8
− 8
−5
− 5
QVWX
WHQX
RLAZ
t
t
CLK
CLK
RD Low to Address Float
−0.5t
− 5
−0.5t
− 5
CLK
5
CLK
5
(4)
(4)
RD or WR High to ALE High (t
RD or WR High to ALE High (t
= 0)
> 0)
−5
− 5
−5
− 5
MCS
t
2, 3
WHLH
t
t
+ 5
t
t
+ 5
MCS
CLK
CLK
CLK
CLK
External Clock
(5)
t
t
t
t
4
4
4
4
High Time
15
15
10
10
ns
ns
ns
ns
HIGH
LOW
R
(5)
Low Time
(5)
Rise Time
5
5
5
5
(5)
Fall Time
F
(1)
(2)
(3)
(4)
(5)
Parameters are valid over operating temperature range, unless otherwise specified.
Load capacitance for Port 0, ALE, and PSEN = 100pF; load capacitance for all other outputs = 80pF.
tCLK = 1/f = one oscillator clock period for clock divider = 1.
OSC
tMCS is a time period related to the Stretch MOVX selection. The following table shows the value of t
These values are characterized, but not 100% production tested.
for each stretch selection:
MCS
MD2
MD1
MD0
MOVX DURATION
2 Machine Cycles
3 Machine Cycles (default)
4 Machine Cycles
5 Machine Cycles
6 Machine Cycles
7 Machine Cycles
8 Machine Cycles
9 Machine Cycles
t
MCS
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4t
8t
CLK
CLK
12t
16t
20t
24t
28t
CLK
CLK
CLK
CLK
CLK
9
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
EXPLANATION OF THE AC SYMBOLS
Each Timing Symbol has five characters. The first character is always ’t’ (= time). The other characters, depending on their positions, indicate the name of a signal
or the logical status of that signal. The designators are:
AAddress
RRD Signal
tTime
CClock
DInput Data
VValid
HLogic Level High
IInstruction (program memory contents)
LLogic Level Low, or ALE
PPSEN
WWR Signal
XNo Longer a Valid Logic Level
ZFloat
Examples:
QOutput Data
(1) t
(2) t
= Time for address valid to ALE Low.
= Time for ALE Low to PSEN Low.
AVLL
LLPL
tLHLL
ALE
tPLPH
tAVLL
tLLPL
tLLIV
tPLIV
PSEN
tPXIZ
tLLAX
tPLAZ
tPXIX
INSTR IN
PORT 0
A0−A7
A0−A7
tAVIV
PORT 2
A8−A15
A8−A15
Figure 1. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL
tRHDZ
tLLAX
tRLDV
tRLAZ
tRHDX
A0−A7
from RI or DPL
PORT 0
PORT 2
DATA IN
A0−A7 from PCL
INSTR IN
tAVWL
tAVDV
P2.0−P2.7 or A8−A15 from DPH
A8−A15 from PCH
Figure 2. External Data Memory Read Cycle
10
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
ALE
tWHLH
PSEN
tLLWL
tWLWH
WR
tQVWX
tAVLL
tLLAX
tWHQX
tDW
DATA OUT
A0−A7
from RI or DPL
PORT 0
A0−A7 from PCL
INSTR IN
tAVWL
PORT 2
P2.0−P2.7 or A8−A15 from DPH
A8−A15 from PCH
Figure 3. External Data Memory Write Cycle
tHIGH
tr
tf
VIH1
0.8V
VIH1
0.8V
VIH1
0.8V
VIH1
0.8V
tLOW
tOSC
Figure 4. External Clock Drive CLK
11
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
RESET AND POWER-ON TIMING
tRW
RST
tRFD
tRRD
PSEN
tRFD
tRRD
ALE
tRS
tRH
EA
NOTE: PSEN and ALE are internally pulled up with ~9kΩduring RST high.
Figure 5. Reset Timing, User Application Mode
tRW
RST
PSEN
ALE
tRFD
tRRD
tRS
tRH
tRRD
Ω
NOTE: PSEN and ALE are internally pulled up with ~9k during RST high.
Figure 6. Parallel Flash Programming Power-On Timing (EA is ignored)
tRW
RST
PSEN
ALE
tRS
tRH
tRRD
tRFD
tRRD
Ω
NOTE: PSEN and ALE are internally pulled up with ~9k during RST high.
Figure 7. Serial Flash Programming Power-On Timing (EA is ignored)
Table 1. Serial/Parallel Flash Programming Timing
SYMBOL
PARAMETER
MIN
MAX
—
UNIT
—
t
RST width
2t
RW
OSC
—
t
RST rise to PSEN ALE internal pull high
RST falling to PSEN and ALE start
Input signal to RST falling setup time
RST falling to input signal hold time
5
µs
RRD
17
t
—
(2 + 512)t
—
RFD
OSC
t
t
—
—
—
RS
RH
OSC
17
(2 + 512)t
OSC
t
—
12
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
47
XOUT
XIN
EA
P0.6/AD6
P3.0/RxD0
P3.1/TxD0
P3.2/INT0
3
46 P0.7/AD7
45
4
ALE
5
44 PSEN/OSCCLK/MODCLK
43 P2.7/A15
P3.3/INT1/TONE/PWM
P3.4/T0
6
7
42 DVDD
MSC1211
MSC1212
MSC1213
MSC1214
P3.5/T1
8
41 DGND
9
40
39
38
P3.6/WR
P2.6/A14
P2.5/A13
P2.4/A12
10
11
P3.7/RD
DVDD
DGND 12
37 P2.3/A11
13
14
15
16
36
35
34
33
RST
DVDD
P2.2/A10
P2.1/A09
P2.0/A08
NC(3)
DVDD
RDAC0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES: (1) SCL and SDA are only available on the MSC1211 and MSC1213.
(2) VDAC2 and VDAC3 are only available on the MSC1211 and MSC1212.
(3) NC pin should be left unconnected.
13
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
PIN DESCRIPTIONS
PIN #
NAME
DESCRIPTION
1
XOUT
The crystal oscillator pin XOUT supports parallel resonant AT-cut fundamental frequency crystals and ceramic
resonators. XOUT serves as the output of the crystal amplifier.
2
XIN
The crystal oscillator pin XIN supports parallel resonant AT-cut fundamental frequency crystals and ceramic
resonators. XIN can also be an input if there is an external clock source instead of a crystal.
3-10
P3.0-P3.7
Port 3 is a bidirectional I/O port. The alternate functions for Port 3 are listed below. Refer to P3DDR, SFR B3h−B4h.
Port
Alternate Name(s)
Alternate Use
P3.0
RxD0
Serial port 0 input
P3.1
TxD0
Serial port 1 input
P3.2
INT0
External interrupt 0
P3.3
INT1/TONE/PWM
External interrupt 1/TONE/PWM output
Timer 0 external input
P3.4
T0
P3.5
T1
Timer 1 external input
P3.6
WR
RD
External memory data write strobe
External memory data read strobe
P3.7
11, 14, 15, 42, 58
DV
DD
Digital Power Supply
Digital Ground
12, 41, 57
DGND
RST
13
16
Holding the reset input high for two tOSC periods will reset the device.
IDAC0 Reference Resistor Pin
RDAC0
17
VDAC0
VDAC0 Output
27
AGND
Analog Ground
18
AIN0/IDAC0
AIN1/IDAC1
AIN2/VDAC2
AIN3V/DAC3
AIN4
Analog Input Channel 0 / IDAC0 Output
Analog Input Channel 1 / IDAC1 Output
19
20
Analog Input Channel 2 / VDAC2 Output (MSC1211 and MSC1212 only)
Analog Input Channel 3 / VDAC3 Output (MSC1211 and MSC1212 only)
Analog Input Channel 4
21
22
23
AIN5
Analog Input Channel 5
24
AIN6/EXTD
AIN7/EXTA
AINCOM
Analog Input Channel 6 / LVD Comparator Input, Generates DLVD Interrupt
Analog Input Channel 7 / LVD Comparator Input, Generates ALVD Interrupt
Analog Common; can be used like any analog input except during Offset − Inputs shorted to this pin.
Analog Power Supply
25
26
28
AV
DD
29
REF IN−
Voltage Reference Negative Input (must be tied to AGND for internal V use)
REF
30
REFOUT/REF IN+ Internal Voltage Reference Output / Voltage Reference Positive Input
31
VDAC1
RDAC1
NC
VDAC1 Output
32
IDAC1 Reference Resistor Pin
No Connection; leave unconnected.
33
34-40, 43
P2.0-P2.7
Port 2 is a bidirectional I/O port. The alternate functions for Port 2 are listed below. Refer to P2DDR, SFR B1h−B2h.
Port
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
Alternate Name
Alternate Use
Address bit 8
Address bit 9
Address bit 10
Address bit 11
Address bit 12
Address bit 13
Address bit 14
Address bit 15
A8
A9
A10
A11
A12
A13
A14
A15
14
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
PIN DESCRIPTIONS (continued)
PIN #
NAME
DESCRIPTION
44
PSEN
OSCCLK
MODCLK
Program Store Enable: Connected to optional external memory as a chip enable. PSEN will provide an active low pulse.
In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode.
PSEN is held high for parallel programming and held low for serial programming. This pin can also be selected (when not
using external memory) to output the Oscillator clock, Modulator clock, high, or low. Care should be taken so that loading
on this pin should not inadvertently cause the device to enter programming mode.
ALE
NC
0
PSEN
NC
NC
0
Program Mode Selection During Reset
Normal operation (User Application mode)
Parallel programming
NC
0
Serial programming
0
Reserved
45
ALE
Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted at
a constant rate of 1/4 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is skipped
during each access to external data memory. In programming mode, ALE is used as an input along with PSEN to define
serial or parallel programming mode. ALE is held high for serial programming and held low for parallel programming. This pin
can also be selected (when not using external memory) to output high or low. Care should be taken so that loading on this
pin should not inadvertently cause the device to enter programming mode.
48
EA
External Access Enable: EA must be externally held low to enable the device to fetch code from external program
memory locations starting with 0000h. No internal pull-up on this pin.
46, 47, 49-54
P0.0-P0.7
Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below.
Port
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Alternate Name
Alternate Use
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Address/Data bit 0
Address/Data bit 1
Address/Data bit 2
Address/Data bit 3
Address/Data bit 4
Address/Data bit 5
Address/Data bit 6
Address/Data bit 7
55, 56, 59-64
P1.0-P1.7
Port 1 is a bidirectional I/O port. The alternate functions for Port 1 are listed below. Refer to P1DDR, SFR AEh−AFh.
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate Name(s)
T2
Alternate Use
T2 input
T2EX
T2 external input
RxD1
Serial port input
TxD1
Serial port output
INT2/SS
INT3/MOSI
External Interrupt / Slave Select
External Interrupt / Master Out-Slave In
External Interrupt / Master In-Slave Out / SDA
External Interrupt / Serial Clock
(1)
INT4/MISO/SDA
(1)
INT5/SCK/SCL
(1)
SDA and SCL are only available on the MSC1213.
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
3
AV = +5V, DV = +5V, f
= 8MHz, PGA = 1, f
= 15.625kHz, Bipolar, filter = Sinc , Buffer ON, and V ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise
REF
DD
DD
OSC
MOD
specified.
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS vs DATA RATE
23
22
21
20
19
18
17
16
15
14
13
12
PGA8
PGA4
PGA2
PGA1
22
21
20
19
18
17
16
15
14
13
12
11
10
PGA1
PGA8
PGA32
PGA64
PGA128
PGA32
PGA64
PGA128
PGA16
Sinc3 Filter, Buffer OFF
Sinc3 Filter, Buffer OFF
1
10
100
Data Rate (SPS)
1000
0
0
0
500
1000
Decimation Ratio =
1500
fMOD
2000
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA8
PGA4
PGA8
PGA2
PGA4
PGA2
PGA1
PGA1
PGA32
PGA128
PGA16
PGA64
PGA128
PGA64
PGA32
PGA16
Sinc3 Filter, Buffer ON
AVDD = 3V, Sinc3 Filter,
VREF = 1.25V, Buffer OFF
500
1000
Decimation Ratio =
1500
2000
0
500
1000
Decimation Ratio =
1500
fMOD
2000
fMOD
fDATA
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA2
PGA4
PGA4
PGA8
PGA2
PGA8
PGA1
PGA1
PGA16 PGA64
PGA32
PGA128
PGA32
PGA128
PGA64
PGA16
Sinc2 Filter
AVDD = 3V, Sinc3 Filter,
VREF = 1.25V, Buffer ON
0
500
1000
Decimation Ratio =
1500
2000
500
1000
1500
2000
fMOD
fMOD
Decimation Ratio =
fDATA
fDATA
16
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (Continued)
3
AV = +5V, DV = +5V, f
= 8MHz, PGA = 1, f
= 15.625kHz, Bipolar, filter = Sinc , Buffer ON, and V
≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise
DD
DD
OSC
MOD
REF
specified.
EFFECTIVE NUMBER OF BITS vs fMOD
(set with ACLK)
FAST SETTLING FILTER
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
25
20
15
10
5
20
19
18
17
16
15
14
13
12
11
10
fMOD = 203kHz
Gain 1
fMOD = 15.6kHz
fMOD = 31.25kHz
fMOD = 110kHz
Gain 16
Gain 128
fMOD = 62.5kHz
0
1
10
100
1k
10k
100k
0
500
1000
1500
2000
Data Rate (SPS)
Decimation Value
EFFECTIVE NUMBER OF BITS vs INPUT SIGNAL
EFFECTIVE NUMBER OF BITS vs f
MOD
(set with ACLK)
WITH FIXED DECIMATION, PGA = 1
(Internal and External VREF
)
25
20
15
10
5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
DEC = 2020
External
DEC = 500
DEC = 50
Internal
DEC = 255
DEC = 20
DEC = 10
10k
0
−
−
−
0.5
2.5
1.5
0.5
1.5
2.5
10
100
1k
100k
Data Rate (SPS)
V
IN (V)
NOISE vs INPUT SIGNAL
INL ERROR vs PGA
100
90
80
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−
−
−
0.5
2.5
1.5
0.5
1.5
2.5
1
2
4
8
16
32
64
128
VIN (V)
PGA Setting
17
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (Continued)
3
AV = +5V, DV = +5V, f
= 8MHz, PGA = 1, f
= 15.625kHz, Bipolar, filter = Sinc , Buffer ON, and V ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise
REF
DD
DD
OSC
MOD
specified.
ADC INTEGRAL NONLINEARITY
vs INPUT SIGNAL
ADC INTEGRAL NONLINEARITY
vs INPUT SIGNAL
15
10
5
15
10
5
AVDD = 5V
VREF = 2.5V
Buffer ON
AVDD = 5V
VREF = 2.5V
Buffer OFF
_
+25 C
_
+85 C
0
0
_
+125 C
_
+85 C
_
+125 C
_
+25 C
−
5
−
5
−
_
55 C
−
_
40 C
−
−
10
−
10
−
_
40 C
15
−
−
15
−
−
−
−
−
0.5
2.5
2
1.5
1
0
0.5
1
1.5
2
2.5
−
−
−
−
2.5 2.0 1.5 1.0 0.5
0
0.5 1.0 1.5 2.0 2.5
VIN (V)
VIN (V)
ADC INTEGRAL NONLINEARITY
vs INPUT SIGNAL
ADC INTEGRAL NONLINEARITY
vs VREF
35
30
25
20
15
10
5
30
20
10
0
VREF = AVDD
Buffer OFF
VIN = VREF
Buffer OFF
AVDD = 3V
AVDD = 5V
−
−
−
10
20
30
0
−
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VREF (V)
VIN
=
VREF
0
VIN = +VREF
V
IN (V)
ANALOG SUPPLY CURRENT
vs ANALOG SUPPLY VOLTAGE
ADC CURRENT vs PGA
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
900
800
700
600
500
400
300
200
100
0
_
+125 C
PGA = 128, ADC ON,
Brownout Detect ON,
All VDACs ON = FFFFh,
VDACs REF = AVDD
AVDD = 5V, Buffer = ON
Buffer = OFF
_
+85 C
_
+25 C
AVDD = 3V, Buffer = ON
Buffer = OFF
−
_
40 C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
1
2
4
8
16
32
64
128
Analog Supply Voltage (V)
PGA Setting
18
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (Continued)
3
AV = +5V, DV = +5V, f
= 8MHz, PGA = 1, f
= 15.625kHz, Bipolar, filter = Sinc , Buffer ON, and V
≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise
DD
DD
OSC
MOD
REF
specified.
PGA SUPPLY CURRENT
NORMALIZED GAIN vs PGA
101
100
300
250
200
150
100
50
AVDD = DVDD
fCLK = 8MHz
VIN = 0V
Buffer OFF
AVDD = 5.0V
99
98
97
96
Buffer ON
AVDD = 3.0V
0
32
1
2
4
8
16
64
128
1
2
4
8
16
32
64
128
PGA Setting
PGA Gain
HISTOGRAM OF
ADC OFFSET vs TEMPERATURE
_
TEMPERATURE SENSOR VALUES
(Offset Calibration at +25 C Only)
200
150
100
50
10
8
6
4
2
0
−
−
−
−
2
4
6
8
−
0
10
−
−
25
50
0
25
50
75
100
125
150
_
Temperature ( C)
Temperature Sensor Value (mV)
OFFSET DAC: OFFSET vs TEMPERATURE
OFFSET DAC: GAIN vs TEMPERATURE
20
15
10
5
1.00008
1.00006
1.00004
1.00002
1
0
−
5
0.99998
0.99996
0.99994
0.99992
−
−
−
10
15
20
−
−
40
+25
+125
40
+25
+125
_
_
Temperature ( C)
Temperature ( C)
19
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (Continued)
3
AV = +5V, DV = +5V, f
= 8MHz, PGA = 1, f
= 15.625kHz, Bipolar, filter = Sinc , Buffer ON, and V ≡ (REF IN+) − (REF IN−) = +2.5V, unless otherwise
REF
DD
DD
OSC
MOD
specified.
HISTOGRAM OF OUTPUT DATA
VREFOUT vs LOAD CURRENT
4500
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
4000
3500
3000
2500
2000
1500
1000
500
0
−
2
−
−
−
1.5
1
0.5
0
0.5
1
1.5
2
0
1
0
0.4
0.8
1.2
1.6
2.0
2.4
ppm of FS
VREFOUT Current Load (mA)
DIGITAL SUPPLY CURRENT vs FREQUENCY
DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER
Divider Values
100
10
1
100
10
1
OFF
2
I
, DV = 5V
DD
MIN
4
8
I
, DV = 5V
DD
MAX
I
I
, DV = 3V
DD
MAX
16
32
1024
2048
4096
, DV = 3V
MIN
DD
I
IDLE, DV = 5V
DD
MAX
I
IDLE, DV = 3V
MIN
DD
IMIN: PDCON = FFh, PSEN and ALE disabled, LVDCON = FFh
IMAX: PDCON = 00h, PSEN and ALE enabled, LVDCON = 00h
0.1
10
100
1
10
100
Clock Frequency (MHz)
Clock Frequency (MHz)
DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE
CMOS DIGITAL OUTPUT
15
10
5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5V
Low
Output
_
+125 C
3V
Low
_
+25 C
−
_
40 C
Output
5V
3V
2.5
3.0
3.5
4.0
4.5
5.0
5.5
10
20
30
40
50
60
70
Supply Voltage (V)
Output Current (mA)
20
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS: VDACs
3
AV = +5V, DV
= +5V, f
= 8MHz, PGA = 1, f
= 15.625kHz, Bipolar, filter = Sinc , Buffer ON, and V
≡ (REF IN+) − (REF IN−) = +2.5V, unless
DD
DD
OSC
MOD
REF
otherwise specified. For V : V
DAC REF
= AV
R
= 10kΩ, and C
= 200pF unless otherwise noted.
DD LOAD
LOAD
,
VDAC DIFFERENTIAL NONLINEARITY vs CODE
VDAC INTEGRAL NONLINEARITY vs CODE
40
20
0
1.0
0.8
0.6
0.4
0.2
0
_
+125 C
_
+85 C
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
_
+25 C
−
20
−
_
40 C
−
40
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
DAC Code
0000h 2000h 4000h 6000h 8000h A000h C000h E000h FFFFh
DAC Code
VDAC SOURCE CURRENT CAPABILITY
VDAC SINK CURRENT CAPABILITY
5.0
0.6
DAC = All 0s
DAC = All 1s
0.5
0.4
0.3
0.2
0.1
0
4.9
4.8
4.7
4.6
4.5
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
ISOURCE (mA)
ISINK (mA)
VDAC FULL−SCALE ERROR vs LOAD RESISTOR
1
0
1
2
3
4
5
−
−
−
−
−
0.5
1
10
100
Load Resistor (k )
1k
10k
Ω
21
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS: VDACs (Continued)
3
AV = +5V, DV
= +5V, f
= 8MHz, PGA = 1, f
= 15.625kHz, Bipolar, filter = Sinc , Buffer ON, and V ≡ (REF IN+) − (REF IN−) = +2.5V, unless
DD
DD
OSC
MOD
REF
otherwise specified. For V : V
DAC REF
= AV
R
= 10kΩ, and C
= 200pF unless otherwise noted.
DD LOAD
LOAD
,
VDAC FULL−SCALE SETTLING TIME
VDAC FULL−SCALE SETTLING TIME
Scope Trigger (5.0V/div)
Scope Trigger (5.0V/div)
Full−Scale Code Change
0200H to FFFFH
Output Loaded with
Ω
10k and 200pF to GND
Large−Signal Output (1.0V/div)
Full−Scale Code Change
FFFFH to 0200H
Output Loaded with
Large−Signal Output (1.0V/div)
Ω
10k and 200pF to GND
Time (1µs/div)
Time (1µs/div)
VDAC HALF−SCALE SETTLING TIME
VDAC HALF−SCALE SETTLING TIME
Scope Trigger (5.0V/div)
Half−Scale Code Change
Scope Trigger (5.0V/div)
4000H to C000H
Output Loaded with
Half−Scale Code Change
Ω
10k and 200pF to GND
C000H to 4000H
Output Loaded with
Ω
10k and 200pF to GND
Large−Signal Output (1.0V/div)
Large−Signal Output (1.0V/div)
Time (1µs/div)
Time (1µs/div)
22
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DESCRIPTION
The MSC1211/12/13/14 are completely integrated
The microcontroller core is 8051 instruction set
compatible. The microcontroller core is an optimized 8051
core that executes up to three times faster than the
standard 8051 core, given the same clock source. This
design makes it possible to run the devices at a lower
external clock frequency and achieve the same
performance at lower power than the standard 8051 core.
families of mixed-signal devices incorporating
a
high-resolution delta-sigma (∆Σ) ADC, 16-bit DACs,
8-channel multiplexer, burnout detect current sources,
selectable buffered input, offset DAC, Programmable Gain
Amplifier (PGA), temperature sensor, voltage reference,
8-bit microcontroller, Flash Program Memory, Flash Data
Memory, and Data SRAM, as shown in Figure 8.
The MSC1211/12/13/14 allow users to uniquely configure the
Flash and SRAM memory maps to meet the needs of their
applications. The Flash is programmable down to 2.7V using
both serial and parallel programming methods. The Flash
endurance is 100k Erase/Write cycles. In addition, 1280
bytes of RAM are incorporated on-chip.
On-chip peripherals include an additional 32-bit
accumulator, an SPI-compatible serial port with FIFO, dual
USARTs, multiple digital input/output ports, a watchdog
timer, low-voltage detect, on-chip power-on reset, 16-bit
PWM, breakpoints, brownout reset, three timer/counters,
and a system clock divider. The MSC1211 and MSC1213
also contain a hardware I2C peripheral.
The parts have separate analog and digital supplies, which
can be independently powered from 2.7V to +5.5V. At +3V
operation, the power dissipation for each part is typically
less than 4mW. The MSC1211/12/13/14 are all available
in a TQFP-64 package.
The devices accept low-level differential or single-ended
signals directly from a transducer. The ADC provides 24
bits of resolution and 24 bits of no-missing-code
performance using a Sinc3 filter with a programmable
sample rate. The ADC also has a selectable filter that
allows for high-resolution, single-cycle conversion.
The MSC1211/12/13/14 are designed for high-resolution
measurement applications in smart transmitters, industrial
process control, weigh scales, chromatography, and
portable instrumentation.
(1)
AV
AGND
REFOUT/REF IN+ REF IN−
DV
DGND
DD
DD
AVDD
V
Burnout
Detect
REF
Timers/
Counters
LVD
EA
ALE
PSEN
BOR
8−Bit
Offset DAC
WDT
Temperature
Sensor
AIN0/IDAC0
AIN1/IDAC1
Alternate
Functions
(3)
AIN2/VDAC2
ADDR
DATA
(3)
AIN3/VDAC3
PORT0
PORT1
PORT2
PORT3
8
8
8
8
Digital
Filter
BUFFER
AIN4
AIN5
Modulator
MUX
PGA
T2
2
(2)
SPI/EXT/I C
USART1
Up to 32K
FLASH
AIN6/EXTD
AIN7/EXTA
AINCOM
32−Bit
Accumulator
V/I
Converter
VDAC0
VDAC1
ADDR
1.2K
SRAM
USART0
EXT
T0
T1
PWM
RW
V/I
Converter
8051
IDAC0/
AIN1
SFR
(3)
AIN2
AIN3
VDAC2
SPI
FIFO
IDAC1/
AIN1
Burnout
Detect
(3)
VDAC3
SYS Clock
Divider
Clock
Generator
RST
POR
AGND
VDAC0 VDAC1
RDAC0
RDAC1
XIN XOUT
NOTES:
−
(1) REF IN must be tied to AGND when using internal VREF
.
(2) I2C only available on the MSC1213.
(3) VDAC2 and VDAC3 only available on MSC1211 and MSC1212.
Figure 8. Block Diagram
23
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ENHANCED 8051 CORE
Single-Byte, Single-Cycle
Instruction
All instructions in the MSC1211/12/13/14 families perform
exactly the same functions as they would in a standard
8051. The effects on bits, flags, and registers is the same;
however, the timing is different. The MSC1211/12/13/14
families utilize an efficient 8051 core which results in an
improved instruction execution speed of between 1.5 and
3 times faster than the original core for the same external
clock speed (4 clock cycles per instruction versus 12 clock
cycles per instruction, as shown in Figure 9). This
efficiency translates into an effective throughput
improvement of more than 2.5 times, using the same code
and same external clock speed. Therefore, a device
frequency of 40MHz for the MSC1211/12/13/14 actually
performs at an equivalent execution speed of 100MHz
compared to the standard 8051 core. This increased
performance allows the the device to be run at slower
external clock speeds, which reduces system noise and
power consumption, but provides greater throughput. This
performance difference can be seen in Figure 10. The
timing of software loops will be faster with the
MSC1211/12/13/14. However, the timer/counter operation
of the MSC1211/12/13/14 may be maintained at 12 clocks
per increment, or optionally run at 4 clocks per increment.
ALE
PSEN
AD0−AD7
PORT 2
4 Cycles
CLK
12 Cycles
ALE
PSEN
AD0−AD7
PORT 2
Single-Byte, Single-Cycle
Instruction
Figure 10. Comparison of MSC1211/12/13/14
Timing to Standard 8051 Timing
The MSC1211/12/13/14 also provide dual data pointers
(DPTRs) to speed block Data Memory moves.
Additionally, both devices can stretch the number of
memory cycles to access external Data Memory from
between two and nine instruction cycles in order to
accommodate different speeds of memory or devices, as
shown in Table 2. The MSC1211/12/13/14 provide an
external memory interface with a 16-bit address bus (P0
and P2). The 16-bit address bus makes it necessary to
multiplex the low address byte through the P0 port. To
enhance P0 and P2 for high-speed memory access,
hardware configuration control is provided to configure the
ports for external memory/peripheral interface or
general-purpose I/O.
RD or WR
STROBE
WIDTH
RD or WR
STROBE
WIDTH
CKCON
(8Eh)
MD2:MD0
INSTRUCTION
CYCLES
(for MOVX)
(SYS CLKs)
(µs) AT 12MHz
000
001
010
011
100
101
110
111
2
2
4
8
12
16
20
24
28
0.167
0.333
0.667
1.000
1.333
1.667
2.000
2.333
3 (default)
4
5
6
7
8
9
Table 2. Memory Cycle Stretching (stretching of
MOVX timing as defined by MD2, MD1, and MD0
bits in CKCON register at address 8Eh).
CLK
instr_cycle
cpu_cycle
n + 1
n + 2
C1
C2
C3
C4
C1
C2
C3
C4
C1
Figure 9. Instruction Timing Cycle
24
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Furthermore, improvements were made to peripheral
features that off-load processing from the core, and the
user, to further improve efficiency. For instance, the SPI
interface uses a FIFO, which allows the SPI interface to
transmit and receive data with minimum overhead needed
from the core. Also, a 32-bit accumulator was added to
significantly reduce the processing overhead for multiple
byte data from the ADC or other sources. This allows for
32-bit addition, subtraction and shifting to be
accomplished in a few instruction cycles, compared to
hundreds of instruction cycles executed through software
implementation.
This gives the user the ability to add or subtract software
functions and to freely migrate between family members.
Thus, the MSC1211/12/13/14 can become a standard
device used across several application platforms.
Family Development Tools
The MSC1211/12/13/14 are fully compatible with the
standard 8051 instruction set. This compatibility means
that
users
can
develop
software
for
the
MSC1211/12/13/14 with their existing 8051 development
tools. Additionally, a complete, integrated development
environment is provided with each demo board, and
third-party developers also provide support.
Family Device Compatibility
Power-Down Modes
The hardware functionality and pin configuration across
the MSC1211/12/13/14 families are fully compatible. To
the user, the only differences between family members are
the memory configuration, the number of DACs, and the
availability of I2C for the MSC1211 and MSC1213. This
design makes migration between family members simple.
The MSC1211/12/13/14 can each power several of the
on-chip peripherals and put the CPU into Idle mode. This
is accomplished by shutting off the clocks to those
sections, as shown in Figure 11.
fOSC
fSYS
SYSCLK
STOP
C7
fCLK
SPICON/
SCL/SCK
I2CCON(1)
9A
fCLK
PDCON.0
PWM Clock
PWMHI
PWMLOW
A2
A3
PDCON.4
µ
s
Flash Write
Timing
FTCON
[3:0]
USEC
µ
µ
(30 s to 40 s)
FB
EF
ms
Flash Erase
Timing
FTCON
[7:4]
MSECH
MSECL
(5ms to 11ms)
FD
FC
EF
milliseconds
interrupt
MSINT
REFCLK
divide
by 4
FA
REF
CLOCK
seconds
interrupt
SEL
DC
PDCON.1
SECINT
F9
watchdog
interrupt
100ms
HMSEC
FE
WDTCON
FF
fACLK
PDCON.2
divide
by 64
ADC Output Rate
(see Figure 14)
ACLK
ADCON3
DF
Decimation Ratio
ADCON2
fDATA
F6
DE
Analog Power Down
PDCON.3
ADCON0
DC
fSAMP
fMOD
Timers 0/1/2
USART 0/1
IDLE
CPUClock
NOTE: (1) I2CCON only available on the MSC1211 and MSC1213.
Figure 11. MSC1211/12/13/14 Timing Chain and Clock Control
25
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TEMPERATURE SENSOR
OVERVIEW
On-chip diodes provide temperature sensing capability.
When the configuration register for the input MUX is set to
all 1s, the diodes are connected to the inputs of the ADC.
All other channels are open.
The MSC1211/12/13/14 ADC structure is shown in
Figure 12. The figure lists the components that make up
the ADC, along with the corresponding special function
register (SFR) associated with each component.
BURNOUT DETECT
ADC INPUT MULTIPLEXER
When the Burnout Detect (BOD) bit is set in the ADC
control configuration register (ADCON0 DCh), two current
sources are enabled. The current source on the positive
input channel sources approximately 2µA of current. The
current source on the negative input channel sinks
approximately 2µA. The current sources allow for the
detection of an open circuit (full-scale reading) or short
circuit (small differential reading) on the selected input
differential pair. The buffer should be on for sensor burnout
detection.
The input multiplexer provides for any combination of
differential inputs to be selected as the input channel, as
shown in Figure 13. For example, if AIN0 is selected as the
positive differential input channel, then any other channel
can be selected as the negative differential input channel.
With this method, it is possible to have up to eight fully
differential input channels with common connections
between them. It is also possible to switch the polarity of
the differential input pair to negate any offset voltages. In
addition, current sources are supplied that will source or
sink current to detect open or short circuits on the pins.
AVDD
REFOUT/
REFIN+
Detect
Burnout
AIN0
AIN1
AIN2
fSAMP
AIN3
AIN4
Input
Multiplexer
AIN5
In+
AIN6
AIN7
Sample
and Hold
Buffer
PGA
Σ
−
In
AINCOM
Temperature
Sensor
Burnout
Detect
Offset
DAC
−
REFIN
D7h ADMUX
REFOUT/
DCh ADC0N0
F6h ACLK
E6h ODAC
AGND
A4h AIPOL.5
A4h AIPOL.6
A6h AIE.6
fDATA
fMOD
REFIN+
A6h AIE.5
A7h AISTAT.5
A7h AISTAT.6
FAST
VIN
ADC
Result Register
SINC2
SINC3
AUTO
∆Σ
Modulator
ADC
Σ
X
Summation
Block
Offset
Gain
Calibration
Register
Calibration
Register
Σ
−
REFIN
DDh ADCON1
DEh ADCON2
DFh ADCON3
OCR
GCR
ADRES
D3h D2h D1h
D6h D5h D4h
DBh DAh D9h
SUMR
E5h E4h E3h E2h
E1h
SSCON
Figure 12. MSC1211/12/13/14 ADC Structure
26
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ADC ANALOG INPUT
When the buffer is not selected, the input impedance of the
analog input changes with ACLK clock frequency (ACLK
F6h) and gain (PGA). The relationship is:
AIN0
AIN1
1
Impedance (W) +
fSAMP @ CS
AV
DD
1 106
ACLK Frequency
7MW
PGA
Burnout Detect (2µA)
AIN2
@ ǒ Ǔ
Impedance (W) + ǒ
Ǔ
AIN
fCLK
ACLK ) 1
AIN3
where ACLK frequency (fACLK) +
In+
fACLK
64
Buffer
AIN4
and modclk + fMOD
+
.
In−
NOTE:The input impedance for PGA = 128 is the same as
7MW
64
AIN5
that for PGA = 64 (that is,
).
Burnout Detect (2µA)
Figure 14 shows the basic input structure of the
MSC1211/12/13/14. The sampling frequency varies
according to the PGA settings, as shown in the table in
Figure 14.
Temperature Sensor
AIN6
AV
DD
AV
DD
AGND
80 • I
I
AIN7
AINCOM
RSWITCH
(3k typical)
High
Impedance
AIN
Ω
> 1G
CS
(9pF typical)
Figure 13. Input Multiplexer Configuration
ADC INPUT BUFFER
Sampling
Frequency = fSAMP
AGND
PGA
1
2
CS
9pF
18pF
4 to 128 36pF
The analog input impedance is always high, regardless of
PGA setting (when the buffer is enabled). With the buffer
enabled, the input voltage range is reduced and the analog
power-supply current is higher. If the limitation of input
voltage range is acceptable, then the buffer is always
preferred. The input impedance of the MSC1211/12/13/14
without the buffer is 7MΩ/PGA. The buffer is controlled by
the state of the BUF bit in the ADC control register (ADCON0
DCh).
BIPOLAR MODE
UNIPOLAR MODE
PGA FULL-SCALE RANGE FULL-SCALE RANGE
f
SAMP
1
2
4
V
+V
REF
f
f
f
REF
MOD
MOD
MOD
V
V
V
/2
/4
/8
/16
/32
/64
+V
+V
+V
+V
/2
/4
/8
/16
/32
/64
REF
REF
REF
REF
REF
REF
8
f
f
f
f
f
S 2
MOD
MOD
MOD
MOD
MOD
16
32
64
128
V
V
V
S 4
REF
REF
REF
REF
+V
+V
+V
S 8
REF
REF
S 16
S 16
V
/128
/128
REF
REF
:
NOTE
f
MOD
= ACLK frequency/64
Figure 14. Analog Input Structure
27
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For system calibration, the appropriate signal must be
applied to the inputs. The system offset calibration
requires a zero input signal. It then computes an offset that
will nullify offset in the system. The system gain calibration
requires a positive full-scale input signal. It then computes
a value to nullify gain errors in the system. Each of these
calibrations will take seven tDATA periods to complete.
ADC PGA
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can actually improve the effective
resolution of the ADC. For instance, with a PGA of 1 on a
2.5V full-scale range (FSR), the ADC can resolve to
1.5µV. With a PGA of 128 on a 19mV FSR, the ADC can
resolve to 75nV, as shown in Table 3.
Calibration should be performed after power on. It should
also be done after a change in temperature, decimation
ratio, buffer, Power Supply, voltage reference, or PGA.
The Offset DAC wil affect offset calibration; therefore, the
value of the Offset DAC should be zero until prior to
performing a calibration.
Table 3. Sampling Frequency versus PGA Setting
BIPOLAR MODE
FULL-SCALE
RANGE (V)
RMS
INPUT-REFERRED
(1)
ENOB
AT 10HZ
PGA
SETTING
NOISE (nV)
1
2
4
2.5V
1.25
21.7
21.5
21.4
21.2
20.8
20.4
20
1468
843
452
259
171
113
At the completion of calibration, the ADC Interrupt bit goes
high, which indicates the calibration is finished and valid
data is available.
0.625
0.313
0.156
0.0781
0.039
0.019
8
16
32
64
128
ADC DIGITAL FILTER
74.5
74.5
The Digital Filter can use either the Fast Settling, Sinc2, or
Sinc3 filter, as shown in Figure 15. In addition, the Auto
mode changes the Sinc filter after the input channel or
PGA is changed. When switching to a new channel, it will
use the Fast Settling filter for the next two conversions, the
first of which should be discarded.
19
(1)
24
ENOB = Log (FSR/RMS Noise) = Log (2 ) − Log (σ )
CODES
2
2
2
= 24 − Log (σ
)
2
CODES
ADC OFFSET DAC
The analog input to the PGA can be offset (in bipolar mode)
by up to half the full-scale input range of the PGA by using
the ODAC register (SFR E6h). The ODAC (Offset DAC)
register is an 8-bit value; the MSB is the sign and the seven
LSBs provide the magnitude of the offset. Since the ODAC
introduces an analog (instead of digital) offset to the PGA,
using the ODAC does not reduce the range of the ADC.
Adjustable Digital Filter
Sinc3
Sinc2
Modulator
Data Out
ADC MODULATOR
The modulator is a single-loop, 2nd-order system. The
modulator runs at a clock speed (fMOD) that is derived from
the CLK using the value in the Analog Clock (ACLK)
register (SFR F6h). The data output rate is:
Fast Settling
FILTER SETTLING TIME
SETTLING TIME
fMOD
(1)
FILTER
Sinc
(Conversion Cycles)
Data Rate + fDATA
+
3
3
2
1
Decimation Ratio
2
Sinc
Fast
fCLK
fACLK
64
where fMOD
+
+
NOTE: (1) MUX change may add one cycle.
(ACLK ) 1) @ 64
AUTO MODE FILTER SELECTION
CONVERSION CYCLE
and Decimation Ratio is set in [ADCON3:ADCON2].
1
2
3
4
ADC CALIBRATION
2
3
Fast
Fast
Sinc
Sinc
The offset and gain errors in the MSC1211/12/13/14, or the
complete system, can be reduced with calibration.
Calibration is controlled through the ADCON1 register
(SFR DDh), bits CAL2:CAL0. Each calibration process
takes seven tDATA periods (data conversion time) to
complete. Therefore, it takes 14 tDATA periods to complete
both an offset and gain calibration.
Figure 15. Filter Step Responses
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It will then use the Sinc2 followed by the Sinc3 filter to
improve noise performance. This combines the low-noise
advantage of the Sinc3 filter with the quick response of the
Fast Settling Time filter. The frequency response of each
filter is shown in Figure 16.
reference. The valid ranges are: VREF = 2.5 internal
(AVDD = 3.3V to 5.25V) and VREF = 1.25 internal
(AVDD = 2.7V to 5.25V). If the internal VREF is selected,
then AGND must be connected to REF IN−. The
REFOUT/REF IN+pin should also have a 0.1µF capacitor
connected to AGND as close as possible to the pin. If the
internal VREF is not used, then VREF should be disabled in
ADCON0.
VOLTAGE REFERENCE
The MSC1211/12/13/14 can use either an internal or
external voltage reference. The voltage reference
selection is controlled via ADC Control Register 0
If the external voltage reference is selected, it can be used
as either a single-ended input or differential input, for
ratiometric measures. When using an external reference,
it is important to note that the input current will increase for
(ADCON0, SFR DCh).
The default power-up
configuration for the voltage reference is 2.5V internal.
V
REF with higher PGA settings and with a higher modulator
The internal voltage reference can be selected as either
1.25V or 2.5V. The analog power supply (AVDD) must be
within the specified range for the selected internal voltage
frequency. The external voltage reference can be used
over the input range specified in the Electrical
Characteristics section.
SINC3 FILTER RESPONSE
SINC2 FILTER RESPONSE
−
•
( 3dB = 0.262 fDATA
)
−
•
( 3dB = 0.318 fDATA
)
0
20
40
60
80
0
20
40
60
80
−
−
−
−
−
−
−
−
−
−
100
120
−
−
100
120
0
1
2
3
4
5
0
1
2
3
4
5
fDATA
fDATA
FAST SETTLING FILTER RESPONSE
−
•
( 3dB = 0.469 fDATA
)
0
20
−
−
−
−
40
60
80
−
−
100
120
0
1
2
3
4
5
fDATA
NOTE: fDATA = Normalized Data Output Rate = 1/tDATA
Figure 16. Filter Frequency Responses
29
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VDAC
DAC OUTPUT AMPLIFIER
The architecture of the MSC1211/12/13/14 consists of a
string DAC followed by an output buffer amplifier.
Figure 17 shows a block diagram of the DAC architecture.
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, which provides an output
range of AGND to AVDD. It is capable of driving a load of
2kΩ in parallel with 1000pF to GND. The source and sink
capabilities of the output amplifier can be seen in the
typical curves. The slew rate is 1V/µs with a full-scale
settling time of 8µs.
The input coding to the DAC is straight binary, so the ideal
output voltage is given by:
D
65536
@ ǒ Ǔ
VDAC + VREF
DAC REFERENCE
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
Each DAC can be selected to use the REFOUT/REF IN+
pin voltage or the supply voltage AVDD as the reference for
the DAC.
DAC RESISTOR STRING
DAC LOADING
The DAC selects the voltage from a string of resistors from
the reference to AGND. It is essentially a string of resistors,
each of value R. The code loaded into the DAC register
determines at which node on the string the voltage is
tapped off to be fed into the output amplifier by closing one
of the switches connecting the string to the amplifier. It is
ensured monotonic because of the design architecture.
The DAC can be selected to be turned off with a 1kΩ,
100kΩ, or open circuit on the DAC outputs.
DAC3
DAC2
DAC1
21 AIN3/VDAC3
20 AIN2/VDAC2
31 VDAC1
Sink
19 AIN1/IDAC1
AVDD
28
30
Source
Current
Mirror
RDAC1
32
REFOUT/
REF IN+
DAC0
17 VDAC0
Sink
DAC
AIN0/IDAC0
µ
0.1 F
Sink
18
16
Connection
Source
REF
2.5V/1.25V
Current
Mirror
RDAC0
Figure 17. DAC Architecture
30
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BIPOLAR OPERATION USING THE DAC
ANALOG/DIGITAL LOW-VOLTAGE DETECT
The DAC can be used for a bipolar output range, as shown
in Figure 18; the circuit illustrates an output voltage range
of VREF. Rail-to-rail operation at the amplifier output is
achievable using an OPA703 as the output amplifier.
The MSC1211/12/13/14 contain an analog or digital
low-voltage detect. When the analog or digital supply
drops below the value programmed in LVDCON (SFR
E7h), an interrupt is generated (one for each supply).
RESET
R2
100kΩ
DThe device can be reset from the following sources:
Power-on reset
+6V
R1
100kΩ
DAC
REF
D
D
D
D
External reset
OPA703
(DAC
)
REF
VREF
VDAC
Software reset
−6V
Watchdog timer reset
Brownout reset
Figure 18. Bipolar Operation with the DAC
An external reset is accomplished by taking the RST pin
The output voltage for any input code can be calculated as
follows:
high for two t
periods, followed by taking the RST pin
OSC
low. A software reset is accomplished through the System
Reset register (SRTST, 0F7h). A watchdog timer reset is
enabled and controlled through Hardware Configuration
Register 0 (HCR0) and the Watchdog Timer register
(WDTCON, 0FFh). A brownout reset is enabled through
Hardware Configuration Register 1 (HCR1). External
reset, software reset, and watchdog timer reset complete
R )R
R
1
D
65536
1
2
@ ǒ Ǔ@
ǒ Ǔ* DAC ǒ Ǔ
+ ƪDAC
ƫ
V
@
REF
REF
O
R
R
2
1
where D represents the input code in decimal (0 to 65535).
With DACREF = 5V, R1 = R2:
17
15
after 2 clock cycles. A brownout reset completes after 2
10 @ D
65536
+ ǒ Ǔ* 5V
VO
clock cycles.
All sources of reset cause the digital pins to be pulled high
from the initiation of the reset. For an external reset, taking
the RST pin high stops device operation (crystal
oscillation, internal oscillator, or PLL circuit operation) and
causes all digital pins to be pulled high from that point.
Taking the RST pin low initiates the reset procedure.
This is an output voltage range of 5V with 0000h
corresponding to a –5V output and FFFFh corresponding
to a +5V output. Similarly, using DACREF = 2.5V, a 2.5V
output voltage can be achieved.
IDAC
A recommended external reset circuit is shown in
Figure 19. The serial 10kΩ resistor is recommended for
any external reset circuit configuration.
The IDAC can source current and sink current (through an
external transistor). The compliance specification of the
IDAC output defines the maximum output voltage to
achieve the expected current.
DVDD
ȡ4 @ V
DAC
MSC1211/12/13/14
for Source mode
RDAC
ȧ
µ
0.1 F
Ω
10k
IDACOUT
+
ȥ
13 RST
ȧRV
DAC
for Sink mode
DAC
Ȣ
Ω
1M
with VDAC < (AVDD − 2V) for maximum code.
Refer to Figure 17 for the IDAC structure.
Figure 19. Typical Reset Circuit
31
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POWER ON RESET
STOP MODE
The on-chip Power On Reset (POR) circuitry releases the
device from reset when DVDD ≈ 2.0V. The power supply
ramp rate does not affect the POR. If the power supply falls
below 1.0V for more than 200ms, then the POR will
execute. If the power supply falls below 1.0V for less than
200ms, unexpected operation may occur. If these
conditions are not met, the POR will not execute. For
example, a negative spike on the DVDD supply that does
not remain below 1.0V for at least 200ms, will not initiate
a POR.
Stop mode is entered by setting the STOP bit in the Power
Control register (PCON, 087h). In STOP mode, all internal
clocks are halted. This mode has the lowest power
consumption. The device can be returned to active mode
only via an external or power-on reset (not brownout
reset).
By configuring the device prior to entering Stop mode,
further power reductions can be achieved (while in Stop
mode). These power reductions include halting the
external clock into the device, configuring all digital I/O
pins as open drain with low output drive, disabling the ADC
buffer, disabling the internal VREF, disabling the DACs, and
setting PDCON to 0FFh to power down all peripherals.
If the Analog/Digital Brownout Reset circuit is on, the POR
has no effect.
In Stop mode, all digital pins retain their values.
BROWNOUT RESET
The Brownout Reset (BOR) is enabled through HCR1. If
the conditions for proper POR are not met, or the device
encounters a brownout condition that does not generate a
POR, the BOR can be used to ensure proper device
operation. The BOR will hold the state of the device when
the power supply drops below the threshold level
programmed in HCR1, and then generate a reset when the
supply rises above the threshold level. Note that, as the
device is released from reset and program execution
begins, the device current consumption may increase,
which can result in a power supply voltage drop, which
may initiate another brownout condition.
POWER CONSUMPTION CONSIDERATIONS
The following suggestions will reduce current
consumption in the MSC1211/12/13/14 devices:
1. Use the lowest supply voltage that will work in the
application for both AV
and DV
.
DD
DD
2. Use the lowest clock frequency that will work in the
application.
3. Use Idle mode and the system clock divider
whenever possible. Note that the system clock
divider also affects the ADC clock.
The BOR level should be chosen to match closely with the
application. That is, with a high external clock frequency,
the BOR level should match the minimum operating
voltage range for the device or improper operation may still
occur.
4. Avoid using 8051-compatible I/O mode on the I/O
ports. The internal pull-up resistors will draw current
when the outputs are low.
5. Use the delay line for Flash Memory control by
setting the FRCM bit in the FMCON register (SFR
EEh)
IDLE MODE
6. Power down peripherals when they are not needed.
Refer to SFR PDCON, LVDCON, ADCON0, and
DACCONx.
Idle mode is entered by setting the IDLE bit in the Power
Control register (PCON, 087h). In Idle mode, the CPU,
Timer0, Timer1, and USARTs are stopped, but all other
peripherals and digital pins remain active. The device can
be returned to active mode via an active internal or external
interrupt. This mode is typically used for reducing power
consumption between ADC samples.
MEMORY MAP
The MSC1211/12/13/14 contain on-chip SFR, Flash
Memory, Scratchpad SRAM Memory, Boot ROM, and
SRAM. The SFR registers are primarily used for control
and status. The standard 8051 features and additional
peripheral features of the MSC1211/12/13/14 are
controlled through the SFR. Reading from an undefined
SFR will return zero; writing to an undefined SFR is not
recommended, and will have indeterminate effects.
By configuring the device prior to entering Idle mode,
further power reductions can be achieved (while in Idle
mode). These reductions include powering down
peripherals not in use in the PDCON register (0F1h) and
reducing the system clock frequency by using the System
Clock Divider register (SYSCLK, 0C7h).
32
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Flash Memory is used for both Program Memory and Data
Memory. The user has the ability to select the partition size
of Program and Data Memory. The partition size is set
through hardware configuration bits, which are
programmed through either the parallel or serial
programming methods. Both Program and Data Flash
Memory are erasable and writable (programmable) in User
Application mode (UAM). However, program execution
can only occur from Program Memory. As an added
precaution, a lock feature can be activated through the
hardware configuration bits, which disables erase and
writes to 4kB of Program Flash Memory or the entire
Program Flash Memory in UAM.
FFFFh, as shown in Figure 20. The program and data
segments can overlap since they are accessed in different
ways. Program Memory is fetched by the microcontroller
automatically. There is one instruction (MOVC) that is
used to explicitly read the program area. This instruction
is commonly used to read lookup tables. The Data Memory
area is accessed explicitly using the MOVX instruction.
This instruction provides multiple ways of specifying the
target address. It is also used to access the 64kB of Data
Memory. The address and data range of devices with
on-chip Program and Data Memory overlap the 64kB
memory space. When on-chip memory is enabled,
accessing memory in the on-chip range will cause the
device to access internal memory. Memory accesses
beyond the internal range will be addressed externally via
Ports 0 and 2.
The MSC1211/12/13/14 include 1kB of SRAM on-chip.
SRAM starts at address 0 and is accessed through the
MOVX instruction. This SRAM can also be located to start
at 8400hand can be accessed as both Program and Data
Memory.
The MSC1211/12/13/14 have two hardware configuration
registers (HCR0 and HCR1) that are programmable only
during Flash Memory Programming mode.
FLASH MEMORY
The MSC1211/12/13/14 allow the user to partition the
Flash Memory between Program Memory and Data
Memory. For instance, the MSC1213Y5 contains 32kB of
Flash Memory on-chip. Through the hardware
configuration registers, the user can define the partition
between Program Memory (PM) and Data Memory (DM),
as shown in Table 4 and Table 5. The MSC1211/12/13/14
families offer four memory configurations.
The page size for Flash memory is 128 bytes. The
respective page must be erased before it can be written to,
regardless of whether it is mapped to Program or Data
Memory space. The MSC1211/12/13/14 use a memory
addressing scheme that separates Program Memory
(FLASH/ROM) from Data Memory (FLASH/RAM). Each
area is 64kB beginning at address 0000h and ending at
Program
Memory
Data
Memory
FFFFh
F800h
FFFFh
2k Internal Boot ROM
User
Programming Application
Flash
Mapped to Both
Memory Spaces
(von Neumann)
External
Program
Memory
External
Data
Memory
Configuration
Memory
Mode
Address(1)
Mode
Address
8800h
8400h
7FFFh, 32k (Y5)
8800h
83FFh, 33k (Y5)
807Fh
8079h
7Fh
79h
1k RAM or External
External Memory
1k RAM or External
UAM: Read Only
FPM: Read/Write
43FFh, 17k (Y4)
23FFh, 9k (Y3)
UAM: Read Only
FPM: Read Only
On−Chip
Flash
3FFFh, 16k (Y4)
1FFFh, 8k (Y3)
On−Chip
Flash
8070h
8000h
70h
00h
UAM: Read Only
FPM: Read/Write
13FFh, 5k (Y2)
03FFh, 1k
0FFFh, 4k (Y2)
0000h, 0k
NOTE: (1) Can be accessed using CADDR
or the faddr_data_read Boot ROM routine.
1k RAM or External
Figure 20. Memory Map
33
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Program Memory size (no Flash Data Memory) and Flash
Program Memory can be used as Flash Data Memory.
However, this configuration may lead to undesirable
behavior if the PC points to an area of Flash Program
Memory that is being used for data storage. Therefore, it
is recommended to use Flash partitioning when Flash
Memory is used for data storage. Flash partitioning
prohibits execution of code from Data Flash Memory.
Additionally, the Program Memory erase/write can be
disabled through hardware configuration bits (HCR0),
while still providing access (read/write/erase) to Data
Flash Memory.
Table 4. MSC1211/12/13/14 Flash Partitioning
HCR0
MSC121xY2 MSC121xY3 MSC121xY4 MSC121xY5
DFSEL
000
PM
0kB
0kB
0kB
0kB
0kB
2kB
3kB
4kB
DM
4kB
4kB
4kB
4kB
4kB
2kB
1kB
0kB
PM
0kB
0kB
0kB
0kB
4kB
6kB
7kB
8kB
DM
8kB
8kB
8kB
8kB
4kB
2kB
1kB
0kB
PM
DM
PM
DM
0kB 16kB 0kB
0kB 16kB 0kB
32kB
32kB
001
010
0kB 16kB 16kB 16kB
011
8kB
8kB
24kB 8kB
28kB 4kB
30kB 2kB
31kB 1kB
32kB 0kB
100
12kB 4kB
14kB 2kB
15kB 1kB
16kB 0kB
101
110
111 (default)
NOTE: When a 0kB Program Memory configuration is selected, program
execution is external.
The effect of memory mapping on Program and Data
Memory is straightforward. The Program Memory is
decreased in size from the top of internal Program
Memory. Therefore, for example, if the MSC1213Y5 is
partitioned with 31kB of Flash Program Memory and 1kB
of Flash Data Memory, external Program Memory
execution will begin at 7C00h (versus 8000h for 32kB).
The Flash Data Memory is added on top of the SRAM
memory. Thus, access to Data Memory (through MOVX)
will access SRAM for addresses 0000h−03FFh and
access Flash Memory for addresses 0400h−07FFh.
Table 5. MSC1211/12/13/14 Flash Memory
Partitioning
HCR0
DFSEL
000
MSC121xY2 MSC121xY3 MSC121xY4 MSC121xY5
PM
DM
PM
DM
PM
DM
PM
DM
0000
0400-
13FF
0000
0400-
23FF
0000
0400-
43FF
0000
0400-
83FF
001
010
011
100
101
110
0000
0000
0000
0000
0400-
13FF
0000
0000
0000
0400-
23FF
0000
0000
0400-
43FF
0000
0400-
83FF
0400-
13FF
0400-
23FF
0400- 0000- 0400-
43FF 3FFF 43FF
Data Memory
0400-
13FF
0400- 0000- 0400- 0000- 0400-
23FF 1FFF 23FF 5FFF 23FF
The MSC1211/12/13/14 can address 64kB of Data
Memory. Scratchpad Memory provides 256 bytes in
addition to the 64kB of Data Memory. The MOVX
instruction is used to access the Data SRAM Memory. This
includes 1024 bytes of on-chip Data SRAM Memory. The
data bus values do not appear on Port 0 (during data bus
timing) for internal memory access.
0400- 0000- 0400- 0000- 0400- 0000- 0400-
13FF 0FFF 13FF 2FFF 13FF 6FFF 13FF
0000- 0400- 0000- 0400- 0000- 0400- 0000- 0400-
07FF 0BFF 17FF 0BFF 37FF 0BFF 77FF 0BFF
0000- 0400- 0000- 0400- 0000- 0400- 0000- 0400-
0BFF
07FF
1BFF
07FF
3BFF
07FF
7BFF
07FF
111
(default)
0000-
0FFF
− −
0000-
1FFF
− −
0000-
3FFF
− −
0000-
7FFF
− −
The MSC1211/12/13/14 also have on-chip Flash Data
Memory which is readable and writable (depending on
Memory Write Select register) during normal operation (full
NOTE: Program Memory accesses above the highest listed address will
access external Program Memory.
V
DD range). This memory is mapped into the external Data
Memory space directly above the SRAM.
It is important to note that the Flash Memory is readable
and writable by the user through the MOVX instruction
when configured as either Program or Data Memory (via
the MXWS bit in the MWS SFR 8Fh). This flexibility means
that the device can be partitioned for maximum Flash
The MOVX instruction is used to write to Flash Memory.
Flash Memory must be erased before it can be written.
Flash Memory is erased in 128 byte pages.
34
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CONFIGURATION MEMORY
The MSC121x Configuration Memory consists of 128 bytes.
In UAM, all Configuration Memory is readable using the
faddr_data_read Boot ROM routine, and the CADDR and
CDATA registers. In UAM, however, none of the
Configuration Memory is writable.
255
255
128
FFh
80h
FFh
Direct
Special Function
Registers
Indirect
RAM
128
127
80h
7Fh
SFR Registers
Direct
RAM
In serial or parallel programming mode, all Configuration
Memory is readable. Most locations are also writable, except
for addresses 8070h through 8079h, which are read-only.
0
00h
Scratchpad
RAM
The two hardware configuration registers reside in
configuration memory at 807Eh (HCR1) and 807Fh (HCR0).
Figure 21 shows the configuration register mapping for
programming mode and UAM. Note that reading/writing
configuration memory in Flash Programming mode (FPM)
Figure 22. Register Map
requires
16-bit
addressing;
whereas,
reading
configuration memory in User Application mode (UAM)
requires only 8-bit addressing.
SFRs are accessed directly between 80h and FFh (128 to
255). The RAM locations between 128 and 255 can be
reached through an indirect reference to those locations.
Scratchpad RAM is available for general-purpose data
storage. It is commonly used in place of off-chip RAM
when the total data contents are small. When off-chip RAM
is needed, the Scratchpad area will still provide the fastest
general-purpose access. Within the 256 bytes of RAM,
there are several special-purpose areas.
User
Flash
Programming
Mode
Application
Mode
(Read−Only)
HCR0
HCR1
0807Fh
0807Eh
08079h
7Fh
7Fh
79h
Bit Addressable Locations
Read−Only in Both
FPM and UAM
In addition to direct register access, some individual bits
are also accessible. These are individually addressable
bits in both the RAM and SFR area. In the Scratchpad
RAM area, registers 20h to 2Fh are bit addressable. This
provides 128 (16 • 8) individual bits available to software.
A bit access is distinguished from a full-register access by
the type of instruction. In the SFR area, any register
location ending in a 0 or 8 is bit addressable. Figure 23
shows details of the on-chip RAM addressing including the
locations of individual RAM bits.
08070h
08000h
70h
00h UAM Address
NOTE: All Configuration Memory is R/W in programming mode, except
addresses 8070h−8079h, which are read−only. All Configuration
Memory is read−only in UAM.
Figure 21. Configuration Memory Mapping for
Programming Mode and UAM
Working Registers
As part of the lower 128 bytes of RAM, there are four banks
of Working Registers, as shown in Figure 23. The Working
Registers are general-purpose RAM locations that can be
addressed in a special way. They are designated R0
through R7. Since there are four banks, the currently
selected bank will be used by any instruction using
R0—R7. This design allows software to change context by
simply switching banks. Bank access is controlled via the
Program Status Word register (PSW; 0D0h) in the SFR
area described below. Registers R0 and R1 also allow
their contents to be used for indirect addressing of the
upper 128 bytes of RAM.
REGISTER MAP
Figure 22 illustrates the Register Map. It is entirely
separate from the Program and Data Memory areas
discussed previously. A separate class of instructions is
used to access the registers. There are 256 potential
register locations. In practice, the MSC1211/12/13/14
have 256 bytes of Scratchpad RAM and up to 128 SFRs.
This is possible, since the upper 128 Scratchpad RAM
locations can only be accessed indirectly. Thus, a direct
reference to one of the upper 128 locations must be an
SFR access. Direct RAM is reached at locations 0 to 7Fh
(0 to 127).
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Thus, an instruction can designate the value stored in R0
(for example) to address the upper RAM. The 16 bytes
immediately above the these registers are bit addressable.
So any of the 128 bits in this area can be directly accessed
using bit addressable instructions.
FFh
Indirect
RAM
7Fh
Stack
Direct
RAM
Another use of the Scratchpad area is for the
programmer’s stack. This area is selected using the Stack
Pointer (SP; 81h) SFR. Whenever a call or interrupt is
invoked, the return address is placed on the Stack. It also
is available to the programmer for variables, etc., since the
Stack can be moved and there is no fixed location within
the RAM designated as Stack. The Stack Pointer will
default to 07h on reset. The user can then move it as
needed. A convenient location would be the upper RAM
area (> 7Fh) since this is only available indirectly. The SP
will point to the last used value. Therefore, the next value
placed on the Stack is put at SP + 1. Each PUSH or CALL
will increment the SP by the appropriate value. Each POP
or RET will decrement as well.
2Fh
2Eh
2Dh
2Ch
2Bh
2Ah
29h
28h
27h
7F 7E 7D 7C 7B 7A 79 78
77 76 75 74 73 72 71 70
6F 6E 6D 6C 6B 6A 69 68
67 66 65 64 63 62 61 60
5F 5E 5D 5C 5B 5A 59 58
57 56 55 54 53 52 51 50
4F 4E 4D 4C 4B 4A 49 48
47 46 45 44 43 42 41 40
3F 3E 3D 3C 3B 3A 39 38
37 36 35 34 33 32 31 30
2F 2E 2D 2C 2B 2A 29 28
27 26 25 24 23 22 21 20
1F 1E 1D 1C 1B 1A 19 18
26h
25h
24h
Program Memory
After reset, the CPU begins execution from Program
Memory location 0000h. The selection of where Program
Memory execution begins is made by tying the EA pin to
DVDD for internal access, or DGND for external access.
When EA is tied to DVDD, any PC fetches outside the
internal Program Memory address occur from external
memory. If EA is tied to DGND, then all PC fetches
address external memory. Table 6 shows the standard
internal Program Memory size for MSC1211/12/13/14
family members. If enabled the Boot ROM will appear from
address F800h to FFFFh.
23h
22h
21h
17 16 15 14 13 12
11
10
0F 0E 0D 0C 0B 0A 09 08
07 06 05 04 03 02 01 00
20h
1Fh
Bank 3
18h
17h
Bank 2
Bank 1
Bank 0
10h
0Fh
Table 6. MSC1211/12/13/14 Maximum Internal
Program Memory Sizes
08h
07h
STANDARD INTERNAL
PROGRAM MEMORY SIZE (BYTES)
MODEL NUMBER
MSC121xY5
MSC121xY4
MSC121xY3
MSC121xY2
0000h
32k
16k
8k
MSB
LSB
4k
Figure 23. Scratchpad Register Addressing
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The functions of Port 0 and Port 2 are selected in HCR1.
(Hardware configuration registers can only be changed
during Flash Programming mode.) The default state is for
Port 0 and Port 2 to be used as general-purpose I/O. If an
external memory access is attempted when they are
configured as general-purpose I/O, the values of Port 0
and Port 2 will not be affected.
ACCESSING EXTERNAL MEMORY
If external memory is used, P0 and P2 must be configured
as address and data lines. If external memory is not used, P0
and P2 can be configured as general-purpose I/O lines
through the hardware configuration register (HCR0, HCR1).
To enable access to external memory, bits 0 and 1 of the
HCR1 register must be set to ‘0’. When these bits are
enabled all memory accesses for both internal and
external memory will appear on Ports 0 and 2. During the
data portion of the cycle for internal memory, Port 0 will be
zero for security purposes.
External Program Memory is accessed under two conditions:
1. Whenever signal EA is low during reset, then all future
code and data accesses are external; or
2. Whenever the Program Counter (PC) contains a
number that is outside of the internal Program Memory
address range, if the ports are enabled.
Accesses to external memory are of two types: to external
Program Memory and to external Data Memory. Accesses
to external Program Memory use signal PSEN (program
store enable) as the read strobe. Accesses to external
Data Memory use RD or WR (alternate functions of P3.7
and P3.6) to strobe the memory.
If Port 0 and Port 2 are selected for external memory, all 8
bits of Port 0 and Port 2, as well as P3.6 and P3.7, are
dedicated to an output function and may not be used for
general-purpose I/O. During external program fetches,
Port 2 outputs the high byte of the PC.
If desired, External Program Memory and external Data
Memory may be combined by applying the RD and PSEN
signals to the inputs of an AND gate and using the output
of the gate as the read strobe to the external Program/Data
Memory.
Programming Flash Memory
There are four sections of Flash Memory for programming:
1. 128 configuration bytes.
2. Reset sector (4kB) (not to be confused with the 2kB
Boot ROM).
A program fetch from external Program Memory uses a
16-bit address. Accesses to external Data Memory can
use either a 16-bit address (MOVX @DPTR) or an 8-bit
address (MOVX @RI).
3. Program Memory.
4. Data Memory.
If Port 2 is selected for external memory use (HCR1, bit 0),
it cannot be used as general-purpose I/O. This bit (or Bit
1 of HCR1) also forces bits P3.6 and P3.7 to be used for
WR and RD instead of I/O. Port 2, P3.6, and P3.7 should
all be written to ‘1.’
Boot ROM
There is a 2kB Boot ROM that controls operation during
serial or parallel programming. Additionally, the Boot ROM
routines can be accessed during the user mode if it is
enabled. When enabled, the Boot ROM routines will be
located at memory addresses F800h−FFFFh during user
mode. In program mode the Boot ROM is located in the first
2kB of Program Memory. For additional information, refer
to Application Note SBAA085, available for download from
the TI web site (www.ti.com).
If an 8-bit address is being used (MOVX @RI), the contents
of the MPAGE (92h) SFR remain at the Port 2 pins
throughout the external memory cycle, which facilitates
paging.
In any case, the low byte of the address is time-multiplexed
with the data byte on Port 0. The ADDR/DATA signals use
CMOS drivers in the Port 0, Port 2, WR, and RD output
buffers. Thus, in this application, the Port 0 pins are not
open-drain outputs, and do not require external pull-ups for
high-speed access. Signal ALE (Address Latch Enable)
should be used to capture the address byte into an external
latch. The address byte is valid at the negative transition
of ALE. Then, in a write cycle, the data byte to be written
appears on Port 0 just before WR is activated, and remains
there until after WR is deactivated. In a read cycle, the
incoming byte is accepted at Port 0 just before the read
strobe is deactivated.
The MSC1211/12/13/14 are shipped with Flash Memory
erased (all 1s). Parallel programming methods typically
involve a third-party programmer. Serial programming
methods typically involve in-system programming. UAM
allows Code Program and Data Memory programming.
The actual code for Flash programming cannot execute
from Flash. That code must execute from the Boot ROM
or internal (von Neumann) RAM.
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Flash Programming Mode
MSC1211/12/13/14
HOST
There are two programming modes: parallel and serial.
The programming mode is selected by the state of the ALE
and PSEN signals during reset (BOR, WDT, software, or
POR). Serial programming mode is selected with PSEN =
0 and ALE = 1. Parallel programming mode is selected
with PSEN = 1 and ALE = 0, as shown in Figure 24. If they
are both high, the MSC1211/12/13/14 will operate in User
Application mode. For both signals, low is a reserved
mode and is not defined. Programming mode is exited with
a reset and the normal mode selected.
PSEL
AddrHi[6:0]
AddrLo[7:0]
Data[7:0]
Cmd[2:0]
Req
P2[7]
Flash
Programmer
P2[6:0]
PSEN
NC
P1[7:0]
P0[7:0]
ALE
P3[7:5]
P3[4]
P3[3]
P3[2]
RST
Ack
Figure 25 shows the serial programming conection.
Pass
Serial programming mode works through USART0, and
has special protocols. Table 7 describes these protocols,
which are discussed at length in Application Note
SBAA076 (available for download at www.ti.com). The
serial programming mode works at a maximum baud rate
RST
CLK
XIN
determined by fOSC
.
Figure 24. Parallel Programming Configuration
MSC121x
Reset Circuit (or VDD
)
RST
DVDD
P3.1 TXD
P3.0 RXD
PSEN
Host PC
or
Serial Terminal
Serial
Port 0
RS232
Transceiver
Not Connected
Clock Source
ALE
XIN
NOTE: Serial programming is selected with PSEN = 0 and ALE = 1 or open.
Figure 25. Serial Programming Connection
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Table 7. MSC121x Boot ROM Routines
ADDRESS
ROUTINE
put_string
C DECLARATIONS
void put_string (char code *string);
char page_erase (int faddr, char fdata, char fdm);
Assembly only; DPTR = address, R5 = data
char write_flash_chk (int faddr, char fdata, char fdm);
char write_flash_byte (int faddr, char fdata, char fdm);
char faddr_data_read (char faddr);
char data_x_c_read (int faddr, char fdm);
void tx_byte (char);
DESCRIPTION
Output string
FFD5
FFD7
FFD9
FFDB
FFDD
FFDF
FFE1
FFE3
FFE5
FFE7
FFE9
FFEB
FFED
FFEF
FFF1
FFF3
FFF5
FFF7
FFF9
FFFB
FFFB
page_erase
write_flash
write_flash_chk
write_flash_byte
faddr_data_read
data_x_c_read
tx_byte
Erase flash page
Fast flash write
Write flash byte, verify
Write flash byte
Read HW config byte from addr
Read xdata or code byte
Send byte to USART0
tx_hex
void tx_hex (char);
Send hex value to USART0
Send “OK” to USART0
putok
void putok (void);
rx_byte
char rx_byte (void);
Read byte from USART0
Read and echo byte on USART0
Read and echo hex on USART0
Read int as hex and echo: USART0
Read int reversed as hex and echo: USART0
Set baud with received CR
Output 4 spaces to USART0
Output 3 spaces to USART0
Output 2 spaces to USART0
Output 1 space to USART0
Output CR, LF to USART0
See SBAA076
rx_byte_echo
rx_hex_echo
rx_hex_int_echo
rx_hex_rev_echo
autobaud
char rx_byte_echo (void);
int rx_hex_echo (void);
int rx_hex_int_echo (void);
int rx_hex_rev_echo (void);
void autobaud (void);
putspace4
void putspace4 (void);
putspace3
void putspace3 (void);
putspace2
void putspace2 (void);
putspace1
void putspace1 (void);
putcr
void putcr (void);
(1)
F97D
FD3B
cmd_parse
monitor_isr
void cmd_parser (void);
(1)
void monitor_isr ( ) interrupt 6
Push registers and call cmd_parser
(1)
These addresses only relate to version 1.0 of the MSC1211/12/13/14 Boot ROM.
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(except that nine interrupts share the Auxiliary Interrupt
(AI) at the highest priority). In addition, interrupts can be
globally enabled or disabled. The interrupt structure is
compatible with the original 8051 family. All of the standard
interrupts are available.
INTERRUPTS
The MSC1211/12/13/14 use a three-priority interrupt
system. As shown in Table 8, each interrupt source has an
independent priority bit, flag, interrupt vector, and enable
Table 8. Interrupt Summary
INTERRUPT
PRIORITY
ADDR
NUM
CONTROL
INTERRUPT/EVENT
DV Low Voltage/HW Break-
PRIORITY
FLAG
ENABLE
33h
6
High
EDLVB (AIE.0 or AIPOL.0)(1)(2)
EBP (BPCON.7)(1)
EDLVB (AIE.0)(1)
EBP (BPCON.0)(1)
N/A
DD
point
AV
Low Voltage
33h
33h
33h
33h
33h
33h
33h
03h
0Bh
13h
0Bh
23h
6
6
6
6
6
6
6
0
1
2
3
4
0
0
0
0
0
0
0
1
2
3
4
5
EALV (AIE.1 or AIPOL.1)(1)(2)
EALV (AIE.1)(1)
N/A
N/A
DD
SPI Receive / I C(3)
ESPIR/EI2C (AIE.2 or AIPOL.2)(1)(2) ESPIR/EI2C (AIE.2)(1)
2
SPI Transmit
ESPIT (AIE.3 or AIPOL.3)(1)(2)
EMSEC (AIE.4 or AIPOL.4)(1)(2)
EADC (AIE.5 or AIPOL.5)(1)(2)
ESUM (AIE.6 or AIPOL.6)(1)(2)
ESEC (AIE.7 or AIPOL.7)(1)(2)
IE0 (TCON.1)(4)
ESPIT (AIE.3)(1)
EMSEC (AIE.4)(1)
EADC (AIE.5)(1)
ESUM (AIE.6)(1)
ESEC (AIE.7)(1)
EX0 (IE.0)(6)
N/A
Milliseconds Timer
ADC
N/A
N/A
Summation Register
Seconds Timer
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port 0
N/A
N/A
PX0 (IP.0)
PT0 (IP.1)
PX1 (IP.2)
PT1 (IP.3)
PS0 (IP.4)
TF0 (TCON.5)(5)
ET1 (IE.1)(6)
IE1 (TCON.3)(4)
EX1 (IE.2)(6)
TF1 (TCON.7)(5)
ET1 (IE.3)(6)
RI_0 (SCON0.0)
TI_0 (SCON0.1)
ES0 (IE.4)(6)
Timer 2 Overflow
Serial Port 1
2Bh
3Bh
5
7
6
7
TF2 (T2CON.7)
ET2 (IE.5)(6)
ES1 (IE.6)(6)
PT2 (IP.5)
PS1 (IP.6)
RI_1 (SCON1.0)
TI_1 (SCON1.1)
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog
43h
4Bh
53h
5Bh
63h
8
8
9
IE2 (EXIF.4)(4)
IE3 (EXIF.5)(4)
IE4 (EXIF.6)(4)
IE5 (EXIF.7)(4)
WDTI (EICON.3)
EX2 (EIE.0)(6)
EX3 (EIE.1)(6)
EX4 (EIE.2)(6)
EX5 (EIE.3)(6)
EWDI (EIE.4)(6)
PX2 (EIP.0)
PX3 (EIP.1)
PX4 (EIP.2)
PX5 (EIP.3)
PWDI (EIP.4)
9
10
11
12
10
11
12
Low
(1)
(2)
These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5).
For AIPOL.RDSEL = 1, reading AIPOL register gives current value of Auxiliary interrupts before masking. Reading AIE register gives value of
AIE register contents.
For AIPOL.RDSEL = 0, Reading AIPOL register gives value of AIE register contents. Reading AIE register gives current value of Auxiliary
interrupts before masking.
(3) 2
I C is only available on the MSC1211 and MSC1213.
(4)
If edge-triggered, cleared automatically by hardware on interrupt service routine vector. For EX0 or EX1, if level-triggered, the flag follows the
state of the pin.
(5)
(6)
Cleared automatically by hardware when interrupt vector occurs.
Globally enabled by EA (IE.7).
40
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Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CADDR 7Fh
EPMA
PML
RSL
EBR
EWDR
DFSEL2
DFSEL1
DFSEL0
NOTE: HCR0 is programmable only in Flash Programming mode, but can be read in User Application mode using the
CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine.
EPMA
Enable Programming Memory Access (Security Bit).
bit 7
0: After reset in programming modes, Flash Memory can only be accessed in UAM until a mass erase is done.
1: Fully Accessible (default)
PML
Program Memory Lock (PML has priority over RSL).
0: Enable writing to Program Memory in UAM.
bit 6
1: Disable writing to Program Memory in UAM (default).
RSL
bit 5
Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming, which
allows Program Memory updates without changing the jumpers for in-circuit code updates or program development.
The code in this boot sector would then provide the monitor and programming routines with the ability to jump into
the main Flash code when programming is finished.
0: Enable Reset Sector Writing
1: Enable Read-Only Mode for Reset Sector (4kB) (default)
EBR
Enable Boot ROM. Boot ROM is 2kB of code located in ROM, not to be confused with the 4kB Boot Sector located
bit 4
in Flash Memory.
0: Disable Internal Boot ROM
1: Enable Internal Boot ROM (default)
EWDR
Enable Watchdog Reset.
bit 3
0: Disable Watchdog Reset
1: Enable Watchdog Reset (default)
DFSEL1−0 Data Flash Memory Size (see Table 3).
bits 2−0
000: Reserved
001: 32kB, 16kB, 8kB, or 4kB Data Flash Memory
010: 16kB, 8kB, or 4kB Data Flash Memory
011: 8kB or 4kB Data Flash Memory
100: 4kB Data Flash Memory
101: 2kB Data Flash Memory
110: 1kB Data Flash Memory
111: No Data Flash Memory (default)
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Hardware Configuration Register 1 (HCR1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CADDR 7Eh
DBLSEL1
DBLSEL0
ABLSEL1
ABLSEL0
DAB
DDB
EGP0
EGP23
NOTE: HCR1 is programmable only in Flash Programming mode, but can be read in User Application mode using the
CADDR and CDATA SFRs or the faddr_data_read Boot ROM routine.
DBLSEL
Digital Supply Brownout Level Select
bits 7−6
00: 4.5V
01: 4.2V
10: 2.7V
11: 2.5V (default)
ABLSEL
Analog Supply Brownout Level Select
bits 5−4
00: 4.5V
01: 4.2V
10: 2.7V
11: 2.5V (default)
DAB
Disable Analog Power-Supply Brownout Reset
0: Enable Analog Brownout Reset
bit 3
1: Disable Analog Brownout Reset (default)
DDB
Disable Digital Power-Supply Brownout Reset
0: Enable Digital Brownout Reset
bit 2
1: Disable Digital Brownout Reset (default)
EGP0
Enable General-Purpose I/O for Port 0
bit 1
0: Port 0 is Used for External Memory, P3.6 and P3.7 Used for WR and RD.
1: Port 0 is Used as General-Purpose I/O (default)
EGP23
Enable General-Purpose I/O for Ports 2 and 3
bit 0
0: Port 2 is Used for External Memory, P3.6 and P3.7. Used for WR and RD.
1: Port 2 and Port3 are Used as General-Purpose I/O (default)
Configuration Memory Programming
Hardware Configuration Memory can be changed only in Serial Flash Programming mode or Parallel Programming mode.
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Table 9. Special Function Registers
NOTE (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14).
:
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESET VALUE
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
P0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
FFh
07h
00h
00h
00h
00h
00h
30h
00h
00h
SP
DPL0
DPH0
DPL1
DPH1
DPS
0
0
0
0
0
0
0
SEL
IDLE
IT0
PCON
TCON
TMOD
SMOD
TF1
0
1
1
GF1
IE1
GF0
IT1
STOP
IE0
TR1
TF0
TR0
−−−−−−−−−−−−−−−Timer 1−−−−−−−−−−−−−−−
−−−−−−−−−−−−−−−Timer 0−−−−−−−−−−−−−−−
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
TL0
00h
00h
00h
00h
01h
00h
FFh
TL1
TH0
TH1
CKCON
MWS
P1
0
0
T2M
0
T1M
0
T0M
0
MD2
0
MD1
0
MD0
0
0
MXWS
P1.7
P1.6
P1.5
P1.4
INT2/SS
P1.3
TXD1
P1.2
RXD1
P1.1
T2EX
P1.0
T2
INT5/SCK/SCL INT4/MISO/SDA INT3/MOSI
91h
EXIF
IE5
IE4
IE3
IE2
1
0
0
0
08h
08h
00h
00h
00h
00h
92h
MPAGE
CADDR
CDATA
MCON
93h
94h
95h
96h
97h
98h
99h
v
BPSEL
0
0
RAMMAP
SCON0
SBUF0
SPICON
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00h
00h
00h
9Ah
9Bh
9Ch
SCK2
START
SCK1
STOP
SCK0
ACK
FIFO
0
ORDER
FAST
MSTR
MSTR
CPHA
SCLA
CPOL
FILEN
(1)
I2CCON
SPIDATA
I2CDATA
00h
00h
(1)
SPIRCON
(1)
RXCNT7
RXFLUSH
GCMEN
RXCNT6
RXCNT5
RXCNT4
RXCNT3
RXCNT2
RXIRQ2
RXCNT1
RXIRQ1
RXCNT0
RXIRQ0
I2CGM
9Dh
SPITCON
I2CSTAT
TXCNT7
TXFLUSH
STAT7
TXCNT6
STAT5
TXCNT5
CLK_EN
STAT5
TXCNT4
DRV_DLY
STAT4
TXCNT3
DRV_EN
STAT3
TXCNT2
TXIRQ2
0
TXCNT1
TXIRQ1
0
TXCNT0
TXIRQ0
0
00h
(1)
SCKD7/SAE SCKD6/SA6 SCKD5/SA5 SCKD4/SA4 SCKD3/SA3 SCKD2/SA2 SCKD1/SA1 SCKD0/SA0
9Eh
SPISTART
1
80h
(1)
I2CSTART
SPIEND
P2
9Fh
A0h
A1h
A2h
1
80h
FFh
00h
00h
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
PWMCON
PPOL
PWMSEL
SPDSEL
TPCNTL2
TPCNTL1
TPCNTL0
PWMLOW
TONELOW
PWM7
TDIV7
PWM6
TDIV6
PWM5
TDIV5
PWM4
TDIV4
PWM3
TDIV3
PWM2
TDIV2
PWM1
TDIV1
PWM0
TDIV0
A3h
A4h
PWMHI
TONEHI
PWM15
TDIV15
PWM14
TDIV14
PWM13
TDIV13
PWM12
TDIV12
PWM11
TDIV11
PWM10
TDIV10
PWM9
TDIV9
PWM8
TDIV8
00h
00h
AIPOL
ESEC
ESUM
EADC
EMSEC
ESPIT
ESPIR/EI2C EALV
EDLVB
RDSEL
(1) 2
I C is only available on the MSC1211 and MSC1213.
(2)
(3)
Applies to MSC1211 and MSC1213 only. See HWPC0 for MSC1212 and MSC1214.
Applies to the MSC1211 and MSC1212. See HWPC1 for MSC1213 and MSC1214.
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Table 9. Special Function Registers (continued)
NOTE (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14).
:
ADDRESS
A5h
REGISTER BIT 7
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
PAI3
ESPIT
SPIT
ET1
BIT 2
PAI2
BIT 1
PAI1
BIT 0
PAI0
RESET VALUE
PAI
0
00h
00h
00h
00h
00h
A6h
AIE
ESEC
SEC
EA
ESUM
SUM
ES1
0
EADC
ADC
ET2
0
EMSEC
MSEC
ES0
0
ESPIR/EI2C EALV
SPIR/I2CSI ALVD
EDLVB
DLVD
EX0
A7h
AISTAT
IE
A8h
EX1
ET0
A9h
BPCON
BPL
BP
0
0
PMSEL
EBP
AAh
ABh
ACh
ADh
AEh
AFh
BPH
P0DDRL
P0DDRH
P1DDRL
P1DDRH
P3
P03H
P07H
P13H
P17H
P03L
P07L
P13L
P17L
P02H
P06H
P12H
P16H
P02L
P06L
P12L
P16L
P01H
P05H
P11H
P15H
P01L
P05L
P11L
P15L
P00H
P04H
P10H
P14H
P00L
P04L
P10L
P14L
00h
00h
00h
00h
FFh
B0h
P3.7
RD
P3.6
WR
P3.5
T1
P3.4
T0
P3.3
INT1
P3.2
INT0
P3.1
TXD0
P3.0
RXD0
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
P2DDRL
P2DDRH
P3DDRL
P3DDRH
DACL
P23H
P27H
P33H
P37H
P23L
P27L
P33L
P33L
P22H
P26H
P32H
P32H
P22L
P26L
P32L
P32L
P21H
P25H
P31H
P31H
P21L
P25L
P31L
P31L
P20H
P24H
P30H
P30H
P20L
P24L
P30L
P30L
00h
00h
00h
00h
DACH
DACSEL
IP
DSEL7
DSEL6
DSEL5
DSEL4
DSEL3
DSEL2
DSEL1
DSEL0
00h
1
PS1
PT2
PS0
PT1
PX1
PT0
PX0
80h
SCON1
SBUF1
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00h
00h
EWU
EWUWDT
DIV2
EWUEX1
DIV1
EWUEX0
DIV0
00h
00h
00h
SYSCLK
T2CON
0
0
DIVMOD1
DIVMOD0
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
RCAP2L
RCAP2H
TL2
00h
00h
00h
00h
TH2
PSW
CY
AC
F0
RS1
RS0
OV
F1
P
00h
OCL
LSB
00h
(1) 2
I C is only available on the MSC1211 and MSC1213.
(2)
(3)
Applies to MSC1211 and MSC1213 only. See HWPC0 for MSC1212 and MSC1214.
Applies to the MSC1211 and MSC1212. See HWPC1 for MSC1213 and MSC1214.
44
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Table 9. Special Function Registers (continued)
NOTE (Boldface are in addition to standard 8051 registers, and unique to the MSC1211/12/13/14).
:
ADDRESS
REGISTER BIT 7
OCM
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RESET VALUE
00h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
OCH
MSB
00h
GCL
LSB
54h
GCM
ECh
5Fh
GCH
MSB
ADMUX
EICON
ADRESL
ADRESM
ADRESH
ADCON0
ADCON1
ADCON2
ADCON3
ACC
INP3
INP2
INP1
INP0
INN3
INN2
INN1
INN0
0
01h
SMOD1
1
EAI
AI
WDTI
0
0
40h
LSB
00h
00h
MSB
REFCLK
OF_UF
DR7
00h
BOD
POL
DR6
0
EVREF
SM1
DR5
0
VREFH
SM0
DR4
0
EBUF
—
PGA2
CAL2
DR2
PGA1
CAL1
DR1
PGA0
CAL0
DR0
30h
0000_0000b
1Bh
DR3
0
0
DR10
DR9
DR8
06h
00h
SSCON
SUMR0
SUMR1
SUMR2
SUMR3
ODAC
SSCON1
SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
00h
00h
00h
00h
00h
00h
LVDCON
EIE
ALVDIS
ALVD2
ALVD1
ALVD0
DLVDIS
DLVD2
DLVD1
DLVD0
00h
1
0
0
1
0
0
1
0
0
EWDI
EX5
0
EX4
1
EX3
EX2
E0h
(2)
0000_01xxb
HWPC0
HWPC1
HWVER
Reserved
Reserved
FMCON
FTCON
B
0
0
MEMORY SIZE
0
(3)
08h
1
0
0
00h
00h
02h
A5h
00h
7Fh
00h
0
PGERA
FER2
B.6
0
FRCM
FER0
B.4
0
BUSY
FWR2
B.2
SPM
FPM
FER3
B.7
0
FER1
B.5
FWR3
B.3
FWR1
B.1
FWR0
B.0
PDCON
PASEL
PDDAC
0
PDI2C
PSEN2
PDPWM
PSEN1
PDADC
PSEN0
PDWDT
0
PDST
ALE1
PDSPI
ALE0
0
ACLK
0
FREQ6
FREQ5
0
FREQ4
0
FREQ3
0
FREQ2
0
FREQ1
0
FREQ0
RSTREQ
PX2
03h
00h
E0h
7Fh
7Fh
03h
9Fh
0Fh
63h
00h
SRST
0
0
EIP
1
1
1
PWDI
PX5
PX4
PX3
SECINT
MSINT
USEC
WRT
WRT
0
SECINT6
MSINT6
0
SECINT5
MSINT5
FREQ5
SECINT4
MSINT4
FREQ4
SECINT3
MSINT3
FREQ3
SECINT2
MSINT2
FREQ2
SECINT1
MSINT1
FREQ1
SECINT0
MSINT0
FREQ0
MSECL
MSECH
HMSEC
WDTCON
EWDT
DWDT
RWDT
WDCNT4
WDCNT3
WDCNT2
WDCNT1
WDCNT0
(1) 2
I C is only available on the MSC1211 and MSC1213.
(2)
(3)
Applies to MSC1211 and MSC1213 only. See HWPC0 for MSC1212 and MSC1214.
Applies to the MSC1211 and MSC1212. See HWPC1 for MSC1213 and MSC1214.
45
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Table 10. Special Function Register Cross Reference
POWER
AND
CLOCKS
SERIAL
COMM.
TIMER
COUNTERS
FLASH
MEMORY
SFR
FUNCTIONS
ADDRESS
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
98h
99h
CPU
INTERRUPTS PORTS
PWM
ADC DAC
P0
Port 0
X
SP
Stack Pointer
X
X
X
X
X
X
DPL0
Data Pointer Low 0
Data Pointer High 0
Data Pointer Low 1
Data Pointer High 1
Data Pointer Select
Power Control
DPH0
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
X
Timer/Counter Control
Timer Mode Control
Timer0 LSB
X
X
X
X
X
X
X
X
X
TL1
Timer1 LSB
TH0
Timer0 MSB
TH1
Timer1 MSB
CKCON
MWS
Clock Control
X
X
Memory Write Select
Port 1
X
P1
X
EXIF
External Interrupt Flag
Memory Page
X
MPAGE
CADDR
CDATA
MCON
SCON0
SBUF0
SPICON
I2CCON
SPIDATA
I2CDATA
SPIRCON
I2CGM
SPITCON
I2CSTAT
SPISTART
I2CSTART
SPIEND
P2
X
X
Configuration Address
Configuration Data
Memory Control
Serial Port 0 Control
Serial Data Buffer 0
SPI Control
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
9Ah
9Bh
9Ch
9Dh
9Eh
2
I C Control
SPI Data
2
I C Data
SPI Receive Control
2
I C Gen Call/Mult Master Enable
SPI Transmit Control
2
I C Status
SPI Buffer Start Address
2
I C Start
9Fh
A0h
A1h
SPI Buffer End Address
Port 2
X
PWMCON
PWMLOW
TONELOW
PWMHI
TONEHI
AIPOL
PAI
PWM Control
X
X
X
X
X
X
PWM Low Byte
A2h
A3h
Tone Low Byte
PWM HIgh Byte
Tone Low Byte
A4h
A5h
A6h
A7h
A8h
Auxiliary Interrupt Poll
Pending Auxiliary Interrupt
Auxiliary Interrupt Enable
Auxiliary Interrupt Status
Interrupt Enable
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AIE
AISTAT
IE
46
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Table 10. Special Function Register Cross Reference (continued)
POWER
AND
CLOCKS
SERIAL
COMM.
TIMER
COUNTERS
FLASH
MEMORY
SFR
FUNCTIONS
ADDRESS
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B7h
B8h
C0h
C1h
C6h
C7h
C8h
CAh
CBh
CCh
CDh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1h
E2h
E3h
E4h
E5h
CPU INTERRUPTS
PORTS
PWM
X
ADC
DAC
BPCON
BPL
Breakpoint Control
Breakpoint Low Address
Breakpoint High Address
Port 0 Data Direction Low
Port 0 Data Direction High
Port 1 Data Direction Low
Port 1 Data Direction High
Port 3
X
X
X
X
BPH
X
P0DDRL
P0DDRH
P1DDRL
P1DDRH
P3
X
X
X
X
X
X
X
X
X
P2DDRL
P2DDRH
P3DDRL
P3DDRH
DACL
Port 2 Data Direction Low
Port 2 Data Direction High
Port 3 Data Direction Low
Port 3 Data Direction High
DAC Low Byte
X
X
X
X
DACH
DAC High Byte
DACSEL
DACCON
IP
DAC Select
DAC Control
Interrupt Priority
X
X
SCON1
SBUF1
EWU
Serial Port 1 Control
Serial Data Buffer 1
Enable Wake Up
X
X
X
X
X
SYSCLK
T2CON
RCAP2L
RCAP2H
TL2
System Clock Divider
Timer 2 Control
X
X
X
X
X
X
X
X
X
X
X
X
X
Timer 2 Capture LSB
Timer 2 Capture MSB
Timer 2 LSB
TH2
Timer 2 MSB
PSW
Program Status Word
ADC Offset Calibration Low Byte
ADC Offset Calibration Mid Byte
ADC Offset Calibration High Byte
ADC Gain Calibration Low Byte
ADC Gain Calibration Mid Byte
ADC Gain Calibration High Byte
ADC Input Multiplexer
Enable Interrupt Control
ADC Results Low Byte
ADC Results Middle Byte
ADC Results High Byte
ADC Control 0
X
OCL
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OCM
OCH
GCL
GCM
GCH
ADMUX
EICON
ADRESL
ADRESM
ADRESH
ADCON0
ADCON1
ADCON2
ADCON3
ACC
X
X
X
ADC Control 1
ADC Control 2
ADC Control 3
Accumulator
X
X
X
X
X
X
SSCON
SUMR0
SUMR1
SUMR2
SUMR3
Summation/Shifter Control
Summation 0
X
X
X
X
X
Summation 1
Summation 2
Summation 3
47
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Table 10. Special Function Register Cross Reference (continued)
POWER
AND
CLOCKS
SERIAL
COMM.
TIMER
COUNTERS
FLASH
MEMORY
SFR
FUNCTIONS
ADDRESS
E6h
E7h
E8h
E9h
EAh
EBh
EEh
EFh
F0h
CPU INTERRUPTS
PORTS
PWM
ADC
DAC
ODAC
LVDCON
EIE
Offset DAC
X
Low Voltage Detect Control
Extended Interrupt Enable
Hardware Product Code 0
Hardware Product Code 1
Hardware Version
X
X
HWPC0
HWPC1
HWVER
FMCON
FTCON
B
X
X
X
Flash Memory Control
Flash Memory Timing Control
Second Accumulator
Power Down Control
X
X
X
PDCON
PASEL
ACLK
F1h
X
X
X
X
X
X
X
X
X
F2h
PSEN/ALE Select
X
F6h
Analog Clock
SRST
F7h
System Reset
X
X
X
X
EIP
F8h
Extended Interrupt Priority
Seconds Timer Interrupt
Milliseconds Timer Interrupt
One Microsecond TImer
One Millisecond TImer Low Byte
One Millisecond Timer High Byte
One Hundred Millisecond TImer
Watchdog Timer
SECINT
MSINT
USEC
F9h
X
X
X
X
X
X
X
FAh
FBh
FCh
FDh
FEh
FFh
X
X
X
X
MSECL
MSECH
HMSEC
WDTCON
X
HCR0
HCR1
3Fh
3Eh
Hardware Configuration Reg. 0
Hardware Configuration Reg. 1
X
X
48
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Port 0 (P0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reset Value
SFR 80h
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
FFh
P0.7−0
bits 7−0
Port 0. This port functions as a multiplexed address/data bus during external memory access, and as a general-
purpose I/O port when external memory access is not needed. During external memory cycles, this port will contain
the LSB of the address when ALE is high, and Data when ALE is low. When used as a general-purpose I/O, this port
drive is selected by P0DDRL and P0DDRH (ACh, ADh). Whether Port 0 is used as general-purpose I/O or for external
memory access is determined by the Flash Configuration Register (HCR1.1) (See SFR CADDR 93h).
Stack Pointer (SP)
7
6
5
4
3
2
1
0
Reset Value
SFR 81h
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
07h
SP.7−0
bits 7−0
Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented
before every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07h
after reset.
Data Pointer Low 0 (DPL0)
7
6
5
4
3
2
1
0
Reset Value
SFR 82h
DPL0.7
DPL0.6
DPL0.5
DPL0.4
DPL0.3
DPL0.2
DPL0.1
DPL0.0
00h
DPL0.7−0 Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used
bits 7−0 to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h).
Data Pointer High 0 (DPH0)
7
6
5
4
3
2
1
0
Reset Value
SFR 83h
DPH0.7
DPH0.6
DPH0.5
DPH0.4
DPH0.3
DPH0.2
DPH0.1
DPH0.0
00h
DPH0.7−0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used
bits 7−0 to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h).
Data Pointer Low 1 (DPL1)
7
6
5
4
3
2
1
0
Reset Value
SFR 84h
DPL1.7
DPL1.6
DPL1.5
DPL1.4
DPL1.3
DPL1.2
DPL1.1
DPL1.0
00h
DPL1.7−0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) (SFR
bits 7−0 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
Data Pointer High 1 (DPH1)
7
6
5
4
3
2
1
0
Reset Value
SFR 85h
DPH1.7
DPH1.6
DPH1.5
DPH1.4
DPH1.3
DPH1.2
DPH1.1
DPH1.0
00h
DPH1.7−0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) (SFR
bits 7−0 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.
49
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Data Pointer Select (DPS)
7
6
5
4
3
2
1
0
Reset Value
SFR 86h
0
0
0
0
0
0
0
SEL
00h
SEL
bit 0
Data Pointer Select. This bit selects the active data pointer.
0: Instructions that use the DPTR will use DPL0 and DPH0.
1: Instructions that use the DPTR will use DPL1 and DPH1.
Power Control (PCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 87h
SMOD
0
1
1
GF1
GF0
STOP
IDLE
30h
SMOD
Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0.
0: Serial Port 0 baud rate will be a standard baud rate.
bit 7
1: Serial Port 0 baud rate will be double that defined by baud rate generation equation.
GF1
General-Purpose User Flag 1. This is a general-purpose flag for software control.
General-Purpose User Flag 0. This is a general-purpose flag for software control.
bit 3
GF0
bit 2
STOP
Stop Mode Select. Setting this bit halts the oscillator and blocks external clocks. This bit always reads as a 0.
bit 1
All digital pins and DACs keep their respective output values. Internal REF dies. Exit with RESET.
IDLE
bit 0
Idle Mode Select. Setting this bit freezes the CPU, Timer 0, 1, and 2, and the USARTs; other peripherals remain
active. This bit will always be read as a 0. All digital pins and DACs keep their respective output values. Internal REF
remains unchanged. Exit with AI (A6h) and EWU (C6h) interrupts.
50
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Timer/Counter Control (TCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 88h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
TF1
Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode.
bit 7
This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service
routine.
0: No Timer 1 overflow has been detected.
1: Timer 1 has overflowed its maximum count.
TR1
Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer preserves the current
bit 6
count in TH1, TL1.
0: Timer is halted.
1: Timer is enabled.
TF0
bit 5
Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode.
This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service
routine.
0: No Timer 0 overflow has been detected.
1: Timer 0 has overflowed its maximum count.
TR0
Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer preserves the current
bit 4
count in TH0, TL0.
0: Timer is halted.
1: Timer is enabled.
IE1
bit 3
Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit
will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will
inversely reflect the state of the INT1 pin.
IT1
Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge or level triggered interrupts.
bit 2
0: INT1 is level-triggered.
1: INT1 is edge-triggered.
IE0
bit 1
Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit
will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will
inversely reflect the state of the INT0 pin.
IT0
Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge or level triggered interrupts.
bit 0
0: INT0 is level-triggered.
1: INT0 is edge-triggered.
51
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Timer Mode Control (TMOD)
7
6
5
4
3
2
1
0
Reset Value
TIMER 1
TIMER 0
SFR 89h
00h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
GATE
Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment.
0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1.
1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1.
bit 7
C/T
Timer 1 Counter/Timer Select.
bit 6
0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88h) is 1.
M1, M0
Timer 1 Mode Select. These bits select the operating mode of Timer 1.
bits 5−4
M1
0
M0
0
MODE
Mode 0: 8-bit counter with 5-bit prescale.
Mode 1: 16 bits.
0
1
1
0
Mode 2: 8-bit counter with auto reload.
Mode 3: Timer 1 is halted, but holds its count.
1
1
GATE
Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment.
0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control).
1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control).
bit 3
C/T
Timer 0 Counter/Timer Select.
bit 2
0: Timer is incremented by internal clocks.
1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88h) is 1.
M1, M0
Timer 0 Mode Select. These bits select the operating mode of Timer 0.
bits 1−0
M1
0
M0
0
MODE
Mode 0: 8-bit counter with 5-bit prescale.
Mode 1: 16 bits.
0
1
1
0
Mode 2: 8-bit counter with auto reload.
Mode 3: Two 8-bit counters.
1
1
Timer 0 LSB (TL0)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Ah
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
TL0.0
00h
TL0.7−0
bits 7−0
Timer 0 LSB. This register contains the least significant byte of Timer 0.
Timer 1 LSB (TL1)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Bh
TL1.7
TL1.6
TL1.5
TL1.4
TL1.3
TL1.2
TL1.1
TL1.0
00h
TL1.7−0
Timer 1 LSB. This register contains the least significant byte of Timer 1.
bits 7−0
52
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Timer 0 MSB (TH0)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Ch
TH0.7
TH0.6
TH0.5
TH0.4
TH0.3
TH0.2
TH0.1
TH0.0
00h
TH0.7−0
Timer 0 MSB. This register contains the most significant byte of Timer 0.
bits 7−0
Timer 1 MSB (TH1)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Dh
TH1.7
TH1.6
TH1.5
TH1.4
TH1.3
TH1.2
TH1.1
TH1.0
00h
TH1.7−0
Timer 1 MSB. This register contains the most significant byte of Timer 1.
bits 7−0
Clock Control (CKCON)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Eh
0
0
T2M
T1M
T0M
MD2
MD1
MD0
01h
T2M
bit 5
Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when
the timer is in baud rate generator or clock output modes. Clearing this bit to 0 maintains 8051 compatibility. This bit
has no effect on instruction cycle timing.
0: Timer 2 uses a divide by 12 of the crystal frequency.
1: Timer 2 uses a divide by 4 of the crystal frequency.
T1M
Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0
bit 4
maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 1 uses a divide by 12 of the crystal frequency.
1: Timer 1 uses a divide by 4 of the crystal frequency.
T0M
Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0
bit 3
maintains 8051 compatibility. This bit has no effect on instruction cycle timing.
0: Timer 0 uses a divide by 12 of the crystal frequency.
1: Timer 0 uses a divide by 4 of the crystal frequency.
MD2, MD1, MD0 Stretch MOVX Select 2−0. These bits select the time by which external MOVX cycles are to be stretched. This
bits 2−0
allows slower memory or peripherals to be accessed without using ports or manual software intervention. The
width of the RD or WR strobe will be stretched by the specified interval, which will be transparent to the software
except for the increased time to execute the MOVX instruction. All internal MOVX instructions on devices
containing MOVX SRAM are performed at the 2 instruction cycle rate.
STRETCH
VALUE
RD or WR STROBE
WIDTH (SYS CLKs)
RD or WR STROBE
WIDTH (ms) at 12MHz
MD2 MD1 MD0
MOVX DURATION
2 Instruction Cycles
3 Instruction Cycles (default)
4 Instruction Cycles
5 Instruction Cycles
6 Instruction Cycles
7 Instruction Cycles
8 Instruction Cycles
9 Instruction Cycles
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2
0.167
0.333
0.667
1.000
1.333
1.667
2.000
2.333
4
8
12
16
20
24
28
53
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Memory Write Select (MWS)
7
6
5
4
3
2
1
0
Reset Value
SFR 8Fh
0
0
0
0
0
0
0
MXWS
00h
MXWS
MOVX Write Select. This allows writing to the internal Flash Program Memory.
bit 0
0: MOVX operations will access Data Memory (default).
1: MOVX operations will access Program Memory. Write operations can be inhibited by the PML or RSL bits in HCR0.
Port 1 (P1)
7
6
5
4
3
2
1
0
Reset Value
P1.7
INT5/SCK/SCL
P1.6
INT4/MISO/SDA
P1.5
INT3/MOSI
P1.4
INT2/SS
P1.3
TXD1
P1.2
RXD1
P1.1
T2EX
P1.0
T2
SFR 90h
FFh
P1.7−0
bits 7−0
General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have an
alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 1
latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate
function, set the appropriate mode in P1DDRL (SFR AEh), P1DDRH (SFR AFh).
INT5/SCK/SCL
bit 7
External Interrupt 5. A falling edge on this pin will cause an external interrupt 5 if enabled.
SPI Clock. The master clock for SPI data transfers.
Serial Clock. The serial clock for I C data transfers (MSC1211 and MSC1213 only).
2
INT4/MISO/SDA External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled.
bit 6
Master In Slave Out. For SPI data transfers, this pin receives data for the master and transmits data from the slave.
SDA. For I C data transfers, this pin is the data line (MSC1211 and MSC1213 only).
2
NT3/MOSI External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled.
bit 5
Master Out Slave In. For SPI data transfers, this pin transmits master data and receives slave data.
INT2/SS
bit 4
External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled.
Slave Select. During SPI operation, this pin provides the select signal for the slave device.
TXD1
Serial Port 1 Transmit. This pin transmits the serial Port 1 data in serial port modes 1, 2, 3, and emits the
bit 3
synchronizing clock in serial port mode 0.
RXD1
Serial Port 1 Receive. This pin receives the serial Port 1 data in serial port modes 1, 2, 3, and is a bidirectional data
bit 2
transfer pin in serial port mode 0.
T2EX
bit 1
Timer 2 Capture/Reload Trigger. A 1 to 0 transition on this pin will cause the value in the T2 registers to be
transferred into the capture registers if enabled by EXEN2 (T2CON.3, SFR C8h). When in auto-reload mode, a 1 to
0 transition on this pin will reload the Timer 2 registers with the value in RCAP2L and RCAP2H if enabled by EXEN2
(T2CON.3, SFR C8h).
T2
Timer 2 External Input. A 1 to 0 transition on this pin will cause Timer 2 to increment or decrement depending on
bit 0
the timer configuration.
54
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External Interrupt Flag (EXIF)
7
6
5
4
3
2
1
0
Reset Value
SFR 91h
IE5
IE4
IE3
IE2
1
0
0
0
08h
IE5
External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared
bit 7
manually by software. Setting this bit in software will cause an interrupt if enabled.
IE4
External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared
bit 6
manually by software. Setting this bit in software will cause an interrupt if enabled.
IE3
External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared
bit 5
manually by software. Setting this bit in software will cause an interrupt if enabled.
IE2
External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared
bit 4
manually by software. Setting this bit in software will cause an interrupt if enabled.
Memory Page (MPAGE)
7
6
5
4
3
2
1
0
Reset Value
SFR 92h
00h
MPAGE
bits 7−0
The 8051 uses Port 2 for the upper 8 bits of the external Data Memory access by MOVX A@Riand MOVX @Ri, A
instructions. The MSC1211/12/13/14 uses register MPAGE instead of Port 2. To access external Data Memory using
the MOVX A@Riand MOVX @Ri, Ainstructions, the user should preload the upper byte of the address into MPAGE
(versus preloading into P2 for the standard 8051).
Configuration Address (CADDR) (write-only)
7
6
5
4
3
2
1
0
Reset Value
SFR 93h
00h
CADDR
bits 7−0
Configuration Address. This register supplies the address for reading bytes in the 128 bytes of Flash
Configuration Memory. It is recommended that faddr_data_read be used when accessing Configuration Memory.
CAUTION:If this register is written to while executing from Flash Memory, the CDATA register will be incorrect.
Configuration Data (CDATA)
7
6
5
4
3
2
1
0
Reset Value
SFR 94h
00h
CDATA
bits 7−0
Configuration Data. This register will contain the data in the 128 bytes of Flash Configuration Memory that
is located at the last written address in the CADDR register. This is a read-only register.
Memory Control (MCON)
7
6
0
5
0
4
3
2
1
0
Reset Value
SFR 95h
BPSEL
—
—
—
—
RAMMAP
00h
BPSEL
bit 7
Breakpoint Address Selection
Write: Select one of two Breakpoint registers: 0 or 1.
0: Select breakpoint register 0.
1: Select breakpoint register 1.
Read: Provides the Breakpoint register that created the last interrupt: 0 or 1.
RAMMAP Memory Map 1kB extended SRAM.
bit 0 0: Address is: 0000h—03FFh (default) (Data Memory)
1: Address is 8400h—87FFh (Data and Program Memory)
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Serial Port 0 Control (SCON0)
7
6
5
4
3
2
1
0
Reset Value
SFR 98h
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00h
SM0−2
Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in
bits 7−5
addition to the 8 or 9 data bits.
MODE
SM0
SM1
SM2 FUNCTION
LENGTH
8 bits
PERIOD
(1)
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Synchronous
12 p
CLK
(1)
4 p
CLK
Synchronous
8 bits
(2)
1
Asynchronous
Valid Stop Required
Asynchronous
10 bits
10 bits
11 bits
Timer 1 or 2 Baud Rate Equation
(2)
1
(3)
Timer 1 Baud Rate Equation
(1)
2
64 p
32 p
(SMOD = 0)
(SMOD = 1)
CLK
CLK
(1)
(4)
(4)
(1)
(1)
2
1
0
1
Asynchronous with Multiprocessor Communication
11 bits
64 p
32 p
(SMOD = 0)
(SMOD = 1)
CLK
CLK
(2)
3
1
1
1
1
0
1
Asynchronous
11 bits
11 bits
Timer 1 or 2 Baud Rate Equation
Timer 1 or 2 Baud Rate Equation
(2)
3
Asynchronous with Multiprocessor Communication
(1)
(2)
(3)
(4)
pCLK will be equal to tCLK, except that pCLK will stop for Idle mode.
For modes 1 and 3, the selection of Timer 1 or 2 for baud rate is specified via the T2CON (C8h) register.
RI_0 will only be activated when a valid STOP is received.
RI_0 will not be activated if bit 9 = 0.
REN_0
Receive Enable. This bit enables/disables the serial Port 0 received shift register.
0: Serial Port 0 reception disabled.
bit 4
1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).
TB8_0
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3.
bit 3
RB8_0
9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes
bit 2
2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.
TI_0
bit 1
Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial
port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit.
This bit must be manually cleared by software.
RI_0
bit 0
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial
port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming
stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must
be manually cleared by software.
Serial Data Buffer 0 (SBUF0)
7
6
5
4
3
2
1
0
Reset Value
SFR 99h
00h
SBUF0
Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive
bits 7−0
buffers are separate registers, but both are addressed at this location.
56
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SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers.
7
6
5
4
3
2
1
0
Reset Value
SFR 9Ah
SCK2
SCK1
SCK0
FIFO
ORDER
MSTR
CPHA
CPOL
00h
SCK
SCK Selection. Selection of tCLK divider for generation of SCK in Master mode.
bits 7−5
SCK2
SCK1
SCK0
SCK PERIOD
tCLK/2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
tCLK/4
tCLK/8
tCLK/16
tCLK/32
tCLK/64
tCLK/128
tCLK/256
FIFO
Enable FIFO in On-Chip Indirect Memory.
0: Both transmit and receive are double buffers
1: Circular FIFO used for transmit and receive bytes
bit 4
ORDER
Set Bit Order for Transmit and Receive.
0: Most Significant Bits First
bit 3
1: Least Significant Bits First
MSTR
SPI Master Mode.
0: Slave Mode
bit 2
1: Master Mode
CPHA
Serial Clock Phase Control.
bit 1
0: Valid data starting from half SCK period before the first edge of SCK
1: Valid data starting from the first edge of SCK
CPOL
Serial Clock Polarity.
0: SCK idle at logic low
1: SCK idle at logic high
bit 0
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2
I C Control (I2CCON) (Available only on the MSC1211 and MSC1213)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Ah
START
STOP
ACK
0
FAST
MSTR
SCLS
FILEN
00h
START
Start Condition (Master mode).
Read: Current status of start condition or repeated start condition.
bit 7
Write: When operating as a master, a start condition is transmitted when the START bit is set to 1. During a data
transfer, if the START bit is set, a repeated start is transmitted after the current data transfer is complete. If no transfer
is in progress when the START and STOP bits are set simultaneously, a START will be followed by a STOP.
STOP
Stop Condition (Master mode).
bit 6
Read: Current status of stop condition.
Write: Setting STOP to logic 1 causes a stop condition to be transmitted. When a stop condition is received, hardware
clears STOP to logic 0. If both START and STOP are set during a transfer, a stop condition is transmitted followed
by a start condition.
ACK
Acknowledge. Defines the ACK/NACK generation from the master/slave receiver during the acknowledge cycle.
0: A NACK (high level on SDA) is returned during the acknowledge cycle.
bit 5
1: An ACK (low level on SDA) is returned during the acknowledge cycle.
In slave transmit mode, 0 = Current byte is last byte, 1 = More to follow.
0
Always set this value to zero.
bit 4
FAST
Fast Mode Enable.
bit 3
0: Standard Mode (100kHz)
1: Fast Mode (400kHz)
MSTR
SPI Master Mode.
0: Slave Mode
bit 2
1: Master Mode
SCLS
Clock Stretch.
bit 1
0: No effect
1: Release the clock line. For the slave mode, the clock is stretched for each data transfer. This bit releases the clock.
FILEN
Filter Enable. 50ns glitch filter.
0: Filter disabled
bit 0
1: Filter enabled
2
SPI Data (SPIDATA) / I C Data (I2CDATA)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Bh
00h
SPIDATA
SPI Data. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are
bits 7−0
separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the
transmit interrupt.
2
2
I2CDATA
I2C Data . (MSC1211 and MSC1213 only.) Data for I C is read from or written to this location. The I C transmit and
receive buffers are separate registers, but both are addressed at this location. Writing to this register
starts transmission. In Master mode, reading this register starts a Master read cycle.
bits 7−0
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SPI Receive Control (SPIRCON)
7
6
5
4
3
2
1
0
Reset Value
RXCNT7
RXFLUSH
RXCNT2
RXIRQ2
RXCNT1
RXIRQ1
RXCNT0
RXIRQ0
SFR 9Ch
RXCNT6
RXCNT5
RXCNT4
RXCNT3
00h
RXCNT
bits 7−0
Receive Counter. Read-only bits which read the number of bytes in the receive buffer (0 to 128).
RXFLUSH Flush Receive FIFO. Write-only.
bit 7
0: No Action
1: SPI Receive Buffer Set to Empty
RXIRQ
Read IRQ Level. Write-only.
bits 2−0
000
001
010
011
100
101
110
111
Generate IRQ when Receive Count = 1 or more.
Generate IRQ when Receive Count = 2 or more.
Generate IRQ when Receive Count = 4 or more.
Generate IRQ when Receive Count = 8 or more.
Generate IRQ when Receive Count = 16 or more.
Generate IRQ when Receive Count = 32 or more.
Generate IRQ when Receive Count = 64 or more.
Generate IRQ when Receive Count = 128 or more.
2
I C GM (I2CGM) (Available only on the MSC1211 and MSC1213)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Ch
GCMEN
00h
GCMEN
bit 7
General Call/Multiple Master Enable. Write-only.
Slave mode: 0 = General call ignored, 1 = General call will be detected
Master mode: 0 = Single master, 1 = Multiple master mode
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SPI Transmit Control (SPITCON)
7
6
5
4
3
2
1
0
Reset Value
TXCNT7
TXFLUSH
TXCNT5
CLK_EN
TXCNT4
DRV_DLY
TXCNT3
DRV_EN
TXCNT2
TXIRQ2
TXCNT1
TXIRQ1
TXCNT0
TXIRQ0
SFR 9Dh
TXCNT6
00h
TXCNT
bits 7−0
Transmit Counter. Read-only bits which read the number of bytes in the transmit buffer (0 to 128).
TXFLUSH Flush Transmit FIFO. This bit is write-only. When set, the SPI transmit pointer is set equal to the FIFO Output pointer.
bit 7
This bit is 0 for a read operation.
CLK_EN
SCLK Driver Enable.
bit 5
0: Disable SCLK Driver (Master Mode)
1: Enable SCLK Driver (Master Mode)
DRV_DLY Drive Delay (refer to DRV_EN bit).
bit 4
0: Drive Output Immediately
1: Drive Output After Current Byte Transfer
DRV_EN
Drive Enable.
bit 3
DRV_DLY DRV_EN MOSI or MISO OUTPUT CONTROL
0
0
1
1
0
1
0
1
Tristate immediately.
Drive immediately.
Tristate after the current byte transfer.
Drive after the current byte transfer.
TXIRQ
Transmit IRQ Level. Write-only bits.
bits 2−0
000
001
010
011
100
101
110
111
Generate IRQ when Transmit Count = 1 or less.
Generate IRQ when Transmit Count = 2 or less.
Generate IRQ when Transmit Count = 4 or less.
Generate IRQ when Transmit Count = 8 or less.
Generate IRQ when Transmit Count = 16 or less.
Generate IRQ when Transmit Count = 32 or less.
Generate IRQ when Transmit Count = 64 or less.
Generate IRQ when Transmit Count = 128 or less.
60
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2
I C Status (I2CSTAT) (Available only on the MSC1211 and MSC1213)
7
6
5
4
3
2
1
0
Reset Value
STAT7
SCKD7/SAE
STAT6
SCKD6/SA6
STAT5
STAT4
STAT3
0
0
0
SFR 9Dh
00h
SCKD5/SA5 SCKD4/SA4 SCKD3/SA3 SCKD2/SA2 SCKD1/SA1 SCKD0/SA0
STAT7−3
Status Code. Read-only. Reading this register clears the status interrupt.
bit 7−3
STATUS CODE
STATUS OF THE HARDWARE
MODE
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
0x70
0x80
0x88
0x90
0x98
0xA0
0xA8
0xB8
0xC0
0xC8
START condition transmitted.
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Repeated START condition transmitted.
Slave address + W transmitted and ACK received.
Slave address + W transmitted and NACK received.
Data byte transmitted and ACK received.
Data byte transmitted and NACK received.
Arbitration lost.
Slave address + R transmitted and ACK received.
Slave address + R transmitted and NACK received.
Data byte received and ACK transmitted.
Data byte received and NACK transmitted.
I2Cs slave address + W received and ACK transmitted.
General call received and ACK transmitted.
Slave
Previously addressed as slave, data byte received and ACK transmitted.
Previously addressed as slave, data byte received and NACK transmitted.
Previously addressed with GC, data byte received and ACK transmitted.
Previously addressed with GC, data byte received and NACK transmitted.
A STOP or repeated START received when addressed as slave or GC.
I2Cs slave address + R received and ACK transmitted.
Previously addressed as slave, data byte transmitted and ACK received.
Previously addressed as slave, data byte transmitted and NACK received.
Previously addressed as slave, last data byte transmitted.
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
SCKD7−0 Serial Clock Divisor. Write-only, master mode.
bit 7−0
The frequency of the SCL line is set equal to Sysclk/[2 • (SCKD + 1)]. The minimum value for SCKD is 3.
SAE
Slave Address Enable. Write-only, slave mode.
bit 7
In slave mode, if this is set, address recognition is enabled.
SA6−0
Slave Address. Write-only, slave mode.
bit 6−0
The address of this device is used in slave mode for address recognition.
61
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2
I C Start (I2CSTART) (Available only on the MSC1211 and MSC1213)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Eh
80h
2
2
I2CSTART I C Start. Write-only. When any value is written to this register, the I C system is reset; that is, the counters
bits 7−0 and state machines will go back to the initial state. So, in multi-master mode when arbitration is lost, then the I C
should be reset so that the counters and finite state machines (FSMs) are brought back to the idle state.
2
SPI Buffer Start Address (SPISTART)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Eh
1
80h
SPISTART SPI FIFO Start Address. Write-only. This specifies the start address of the SPI data buffer. This is a circular FIFO
bits 6−0
that is located in the 128 bytes of indirect RAM. The FIFO starts at this address and ends at the address specified
in SPIEND. Must be less than SPIEND. Writing clears SPI transmit and receive counters.
SPITP
bits 6−0
SPI Transmit Pointer. Read-only. This is the FIFO address for SPI transmissions. This is where the next byte will
be written into the byte will be written into the SPI FIFO buffer. This pointer increments after each write to the SPI Data
register unless that would make it equal to the SPI Receive pointer.
SPI Buffer End Address (SPIEND)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Fh
1
80h
SPIEND
SPI FIFO End Address. Write-only. This specifies the end address of the SPI data FIFO. This is a circular buffer that
bits 6−0
is located in the 128 bytes of indirect RAM. The buffer starts at SPISTART and ends at this address.
SPIRP
SPI Receive Pointer. Read-only. This is the FIFO address for SPI received bytes. This is the location of the nextbyte
bits 6−0
to be read from the SPI FIFO. This increments with each read from the SPI Data register until the RxCNT is zero.
Port 2 (P2)
7
6
5
4
3
2
1
0
Reset Value
SFR A0h
FFh
P2
Port 2. This port functions as an address bus during external memory access, and as a general-purpose I/O port.
bits 7−0
During external memory cycles, this port will contain the MSB of the address. Whether Port 2 is used as
general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.0).
62
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PWM Control (PWMCON)
7
6
5
4
3
2
1
0
Reset Value
SFR A1h
—
—
PPOL
PWMSEL
SPDSEL
TPCNTL2
TPCNTL1
TPCNTL0
00h
PPOL
Period Polarity. Specifies the starting level of the PWM pulse.
0: ON Period. PWM Duty register programs the ON period.
1: OFF Period. PWM Duty register programs the OFF period.
bit 5
PWMSEL
PWM Register Select. Select which 16-bit register is accessed by PWMLOW/PWMHI.
bit 4
0: Period (must be 0 for TONE mode)
1: Duty
SPDSEL
Speed Select.
bit 3
0: 1MHz (the USEC Clock)
1: SYSCLK
TPCNTL
Tone Generator/Pulse Width Modulation Control.
bits 2−0
TPCNTL2 TPCNTL1 TPCNTL0 MODE
0
0
0
1
0
0
1
1
0
1
1
1
Disable (default)
PWM
TONE—Square
TONE—Staircase
Tone Low (TONELOW) /PWM Low (PWMLOW)
7
6
5
4
3
2
1
0
Reset Value
PWM7
TDIV7
PWM6
TDIV6
PWM5
TDIV5
PWM4
TDIV4
PWM3
TDIV3
PWM2
TDIV2
PWM1
TDIV1
PWM0
TDIV0
SFR A2h
00h
PWMLOW Pulse Width Modulator Low Bits. These 8 bits are the least significant 8 bits of the PWM register.
bits 7−0
TDIV7−0
Tone Divisor. The low order bits that define the half-time period. For staircase mode the output is high impedance
bits 7−0
for the last 1/4 of this period.
Tone High (TONEHI)/PWM High (PWMHI)
7
6
5
4
3
2
1
0
Reset Value
PWM15
TDIV15
PWM14
TDIV14
PWM13
TDIV13
PWM12
TDIV12
PWM11
TDIV11
PWM10
TDIV10
PWM9
TDIV9
PWM8
TDIV8
SFR A3h
00h
PWMHI
Pulse Width Modulator High Bits. These 8 bits are the high order bits of the PWM register.
bits 7−0
TDIV15−8 Tone Divisor. The high order bits that define the half time period. For staircase mode the output is high impedance
bits 7−0 for the last 1/4 of this period.
63
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Auxiliary Interrupt Poll (AIPOL)
7
6
5
4
3
2
1
0
Reset Value
00h
RD
SFR A4h
ESEC
ESUM
EADC
EMSEC
ESPIT
ESPIR/EI2C
EALV
EDLVB
RDSEL
WR
00h
Auxiliary interrupts are enabled by EICON.4 (SFR D8h); other interrupts are enabled by the IE and EIE registers.
ESEC
Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt). Read-only.
AIPOL.RDSEL = 1: Read: Current value of Seconds Timer Interrupt before masking.
AIPOL.RDSEL = 0: Read: Value of ESEC bit.
bit 7
ESUM
Enable Summation Interrupt. Read-only.
bit 6
AIPOL.RDSEL = 1: Read: Current value of Summation Interrupt before masking.
AIPOL.RDSEL = 0: Read: Value of ESUM bit.
EADC
Enable ADC Interrupt. Read-only.
bit 5
AIPOL.RDSEL = 1: Read: Current value of ADC Interrupt before masking.
AIPOL.RDSEL = 0: Read: Value of EADC bit.
EMSEC
Enable Millisecond System Timer Interrupt. Read-only.
bit 4
AIPOL.RDSEL = 1: Read: Current value of Millisecond System Timer Interrupt before masking.
AIPOL.RDSEL = 0: Read: Value of EMSEC bit.
ESPIT
Enable SPI Transmit Interrupt. Read-only.
bit 3
AIPOL.RDSEL = 1: Read: Current value of Enable SPI Transmit Interrupt before masking.
AIPOL.RDSEL = 0: Read: Value of ESPIT bit.
2
ESPIR/EI2C Enable SPI Receive Interrupt. Enable I2C Status Interrupt (I C available only on the MSC1213). Read-only.
bit 2
AIPOL.RDSEL = 1: Read: Current value of Enable SPI Receive Interrupt or I2C Status Interrupt before masking.
AIPOL.RDSEL = 0: Read: Value of ESPIR/EI2C bit.
EALV
Enable Analog Low Voltage Interrupt. Read-only.
bit 1
AIPOL.RDSEL = 1: Read: Current value of Enable Analog Low Voltage Interrupt before masking.
AIPOL.RDSEL = 0: Read: Value of EALV bit.
EDLVB
Enable Digital Low Voltage or Breakpoint Interrupt (highest priority auxiliary interrupt). Read-only.
AIPOL.RDSEL = 1: Read: Current value of Enable Digital Low Voltage or Breakpoint Interrupt before masking.
AIPOL.RDSEL = 0: Read: Value of EDLVB bit.
bit 0
RDSEL
Read Select. Write-only.
bit 0
AIPOL.RDSEL = 1: Read state for AIE and AIPOL registers. Reading AIPOL register gives current value of
Auxiliary interrupts before masking. Reading AIE register gives value of AIE register contents.
AIPOL.RDSEL = 0: Read state for AIE and AIPOL registers. Reading AIPOL register gives value of AIE register
contents. Reading AIE register gives current value of Auxiliary interrupts before masking.
64
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Pending Auxiliary Interrupt (PAI)
7
6
5
4
3
2
1
0
Reset Value
SFR A5h
0
0
0
0
PAI3
PAI2
PAI1
PAI0
00h
PAI3−0
bits 3−0
Pending Auxiliary Interrupt. The results of this register can be used as an index to vector to the
appropriate interrupt routine. All of these interrupts vector through address 0033h.
PAI3
PAI2
PAI1
PAI0
AUXILIARY INTERRUPT STATUS
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
No Pending Auxiliary IRQ
Digital Low Voltage IRQ Pending
Analog Low Voltage IRQ Pending
2
SPI Receive IRQ Pending. I C Status Pending.
SPI Transmit IRQ Pending.
One Millisecond System Timer IRQ Pending.
Analog-to-Digital Conversion IRQ Pending.
Accumulator IRQ Pending.
One Second System Timer IRQ Pending.
65
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Auxiliary Interrupt Enable (AIE)
7
6
5
4
3
2
1
0
Reset Value
SFR A6h
ESEC
ESUM
EADC
EMSEC
ESPIT
ESPIR/EI2C
EALV
EDLVB
00h
Auxiliary interrupts are enabled by EICON.4 (SFR D8h); other interrupts are enabled by the IE and EIE registers.
ESEC
Enable Seconds Timer Interrupt (lowest priority auxiliary interrupt).
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: When AIPOL.RDSEL = 0: Current value of Seconds Timer Interrupt before masking.
When AIPOL.RDSEL = 1: Value of ESEC bit.
bit 7
ESUM
Enable Summation Interrupt.
bit 6
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: When AIPOL.RDSEL = 0: Current value of Summation Interrupt before masking.
When AIPOL.RDSEL = 1: Value of ESUM bit.
EADC
Enable ADC Interrupt.
bit 5
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: When AIPOL.RDSEL = 0: Current value of ADC Interrupt before masking.
When AIPOL.RDSEL = 1: Value of EADC bit.
EMSEC
Enable Millisecond System Timer Interrupt.
bit 4
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: When AIPOL.RDSEL = 0: Current value of Millisecond System Timer Interrupt before masking.
When AIPOL.RDSEL = 1: Value of EMSEC bit.
ESPIT
Enable SPI Transmit Interrupt.
bit 3
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: When AIPOL.RDSEL = 0: Current value of SPI Transmit Interrupt before masking.
When AIPOL.RDSEL = 1: Value of ESPIT bit.
2
2
ESPIR/EI2C Enable SPI Receive Interrupt. Enable I C Status Interrupt. (I C available only on the MSC1213.)
bit 2
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
2
Read: When AIPOL.RDSEL = 0: Current value of SPI Receive Interrupt or I C Status Interrupt before masking.
When AIPOL.RDSEL = 1: Value of ESPIR/EI2C bit.
EALV
Enable Analog Low Voltage Interrupt.
bit 1
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
Read: When AIPOL.RDSEL = 0: Current value of Analog Low Voltage Interrupt before masking.
When AIPOL.RDSEL = 1: Value of EALV bit.
EDLVB
Enable Digital Low Voltage or Breakpoint Interrupt (highest priority auxiliary interrupt).
Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled.
bit 0
Read: When AIPOL.RDSEL = 0: Current value of Digital Low Voltage or Breakpoint Interrupt before masking.
When AIPOL.RDSEL = 1: Value of EDLVB bit.
66
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Auxiliary Interrupt Status (AISTAT)
7
6
5
4
3
2
1
0
Reset Value
SFR A7h
SEC
SUM
ADC
MSEC
SPIT
SPIR/I2CSI
ALVD
DLVD
00h
SEC
Second System Timer Interrupt Status Flag (lowest priority AI).
0: SEC interrupt inactive or masked.
bit 7
1: SEC Interrupt active.
SUM
Summation Register Interrupt Status Flag.
bit 6
0: SUM interrupt inactive or masked (if active, it is set inactive by reading the lowest byte of the Summation register).
1: SUM interrupt active.
ADC
ADC Interrupt Status Flag.
bit 5
0: ADC interrupt inactive or masked (If active, it is set inactive by reading the lowest byte of the Data Output Register).
1: ADC interrupt active (If active no new data will be written to the Data Output Register).
MSEC
Millisecond System Timer Interrupt Status Flag.
0: MSEC interrupt inactive or masked.
1: MSEC interrupt active.
bit 4
SPIT
SPI Transmit Interrupt Status Flag.
0: SPI transmit interrupt inactive or masked.
1: SPI transmit interrupt active.
bit 3
2
2
SPIR/I2CSI SPI Receive Interrupt Status Flag. I C Status Interrupt. (I C available only on the MSC1213.)
bit 2
0: SPI receive or I2CSI interrupt inactive or masked.
1: SPI receive or I2CSI interrupt active.
ALVD
Analog Low Voltage Detect Interrupt Status Flag.
0: ALVD interrupt inactive or masked.
1: ALVD interrupt active.
bit 1
DLVD
Digital Low Voltage Detect or Breakpoint Interrupt Status Flag (highest priority AI).
0: DLVD interrupt inactive or masked.
bit 0
1: DLVD interrupt active.
67
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Interrupt Enable (IE)
7
6
5
4
3
2
1
0
Reset Value
SFR A8h
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
00h
EA
Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6h).
0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register.
1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled.
bit 7
ES1
Enable Serial Port 1 Interrupt. This bit controls the masking of the serial Port 1 interrupt.
0: Disable all serial Port 1 interrupts.
bit 6
1: Enable interrupt requests generated by the RI_1 (SCON1.0, SFR C0h) or TI_1 (SCON1.1, SFR C0h) flags.
ET2
Enable Timer 2 Interrupt. This bit controls the masking of the Timer 2 interrupt.
0: Disable all Timer 2 interrupts.
bit 5
1: Enable interrupt requests generated by the TF2 flag (T2CON.7, SFR C8h).
ES0
Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt.
0: Disable all serial Port 0 interrupts.
bit 4
1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98h) or TI_0 (SCON0.1, SFR 98h) flags.
ET1
Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt.
0: Disable Timer 1 interrupt.
bit 3
1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88h).
EX1
Enable External Interrupt 1. This bit controls the masking of external interrupt 1.
0: Disable external interrupt 1.
bit 2
1: Enable interrupt requests generated by the INT1 pin.
ET0
Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupts.
bit 1
1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88h).
EX0
Enable External Interrupt 0. This bit controls the masking of external interrupt 0.
0: Disable external interrupt 0.
bit 0
1: Enable interrupt requests generated by the INT0 pin.
68
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Breakpoint Control (BPCON)
7
6
5
4
3
2
1
0
Reset Value
SFR A9h
BP
0
0
0
0
0
PMSEL
EBP
00h
Writing to this register sets the breakpoint condition specified by MCON, BPL, and BPH.
BP
Breakpoint Interrupt. This bit indicates that a break condition has been recognized by a hardware breakpoint register(s).
Read: Status of Breakpoint Interrupt. Will indicate a breakpoint match for any of the breakpoint registers.
Write: 0: No effect.
bit 7
1: Clear Breakpoint 1 for breakpoint register selected by MCON (SFR 95h).
PMSEL
Program Memory Select. Write this bit to select memory for address breakpoints of register selected in
MCON (SFR 95h).
bit 1
0: Break on address in Data Memory.
1: Break on address in Program Memory.
EBP
Enable Breakpoint. This bit enables this breakpoint register. Address of breakpoint register selected by
bit 0
MCON (SFR 95h).
0: Breakpoint disabled.
1: Breakpoint enabled.
Breakpoint Low (BPL) Address for BP Register Selected in MCON (95h)
7
6
5
4
3
2
1
0
Reset Value
SFR AAh
BPL.7
BPL.6
BPL.5
BPL.4
BPL.3
BPL.2
BPL.1
BPL.0
00h
BPL.7−0
Breakpoint Low Address. The low 8 bits of the 16-bit breakpoint address.
bits 7−0
Breakpoint High Address (BPH) Address for BP Register Selected in MCON (95h)
7
6
5
4
3
2
1
0
Reset Value
SFR ABh
BPH.7
BPH.6
BPH.5
BPH.4
BPH.3
BPH.2
BPH.1
BPH.0
00h
BPH.7−0
Breakpoint High Address. The high 8 bits of the 16-bit breakpoint address.
bits 7−0
69
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Port 0 Data Direction Low (P0DDRL)
7
6
5
4
3
2
1
0
Reset Value
SFR ACh
P03H
P03L
P02H
P02L
P01H
P01L
P00H
P00L
00h
P0.3
Port 0 Bit 3 Control.
bits 7−6
P03H
P03L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P0.2
Port 0 Bit 2 Control.
bits 5−4
P02H
P02L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P0.1
Port 0 Bit 1 Control.
bits 3−2
P01H
P01L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P0.0
Port 0 Bit 0 Control.
bits 1−0
P00H
P00L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
NOTE: Port 0 also controlled by EA and Memory Access Control HCR1.EGP0.
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Port 0 Data Direction High (P0DDRH)
7
6
5
4
3
2
1
0
Reset Value
SFR ADh
P07H
P07L
P06H
P06L
P05H
P05L
P04H
P04L
00h
P0.7
Port 0 Bit 7 Control.
bits 7−6
P07H
P07L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P0.6
Port 0 Bit 6 Control.
bits 5−4
P06H
P06L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P0.5
Port 0 Bit 5 Control.
bits 3−2
P05H
P05L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P0.4
Port 0 Bit 4 Control.
bits 1−0
P04H
P04L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
NOTE: Port 0 also controlled by EA and Memory Access Control HCR1.EGP0.
71
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Port 1 Data Direction Low (P1DDRL)
7
6
5
4
3
2
1
0
Reset Value
SFR AEh
P13H
P13L
P12H
P12L
P11H
P11L
P10H
P10L
00h
P1.3
Port 1 Bit 3 Control.
bits 7−6
P13H
P13L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P1.2
Port 1 Bit 2 Control.
bits 5−4
P12H
P12L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P1.1
Port 1 Bit 1 Control.
bits 3−2
P11H
P11L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P1.0
Port 1 Bit 0 Control.
bits 1−0
P10H
P10L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
72
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Port 1 Data Direction High (P1DDRH)
7
6
5
4
3
2
1
0
Reset Value
SFR AFh
P17H
P17L
P16H
P16L
P15H
P15L
P14H
P14L
00h
P1.7
Port 1 Bit 7 Control.
bits 7−6
P17H
P17L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P1.6
Port 1 Bit 6 Control.
bits 5−4
P16H
P16L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P1.5
Port 1 Bit 5 Control.
bits 3−2
P15H
P15L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P1.4
Port 1 Bit 4 Control.
bits 1−0
P14H
P14L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
73
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Port 3 (P3)
7
6
5
4
3
2
1
0
Reset Value
P3.7
RD
P3.6
WR
P3.5
T1
P3.4
T0
P3.3
INT1
P3.2
INT0
P3.1
TXD0
P3.0
RXD0
SFR B0h
FFh
P3.7−0
bits 7−0
General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an
alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 3
latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity.
RD
External Data Memory Read Strobe. This pin provides an active low read strobe to an external memory device.
bit 7
If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a ‘1’ is
not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored.
WR
External Data Memory Write Strobe. This pin provides an active low write strobe to an external memory device.
bit 6
If Port 0 or Port 2 is selected for external memory in the HCR1 register, this function will be enabled even if a ‘1’ is
not written to this latch bit. When external memory is selected, the settings of P3DRRH are ignored.
T1
Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1.
Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0.
External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled.
External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled.
bit 5
T0
bit 4
INT1
bit 3
INT0
bit 2
TXD0
Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the
bit 1
synchronizing clock in serial port mode 0.
RXD0
Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional data
bit 0
transfer pin in serial port mode 0.
74
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Port 2 Data Direction Low (P2DDRL)
7
6
5
4
3
2
1
0
Reset Value
SFR B1h
P23H
P23L
P22H
P22L
P21H
P21L
P20H
P20L
00h
P2.3
Port 2 Bit 3 Control.
bits 7−6
P23H
P23L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P2.2
Port 2 Bit 2 Control.
bits 5−4
P22H
P22L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P2.1
Port 2 Bit 1 Control.
bits 3−2
P21H
P21L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P2.0
Port 2 Bit 0 Control.
bits 1−0
P20H
P20L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.EGP23.
75
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Port 2 Data Direction High (P2DDRH)
7
6
5
4
3
2
1
0
Reset Value
SFR B2h
P27H
P27L
P26H
P26L
P25H
P25L
P24H
P24L
00h
P2.7
Port 2 Bit 7 Control.
bits 7−6
P27H
P27L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P2.6
Port 2 Bit 6 Control.
bits 5−4
P26H
P26L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P2.5
Port 2 Bit 5 Control.
bits 3−2
P25H
P25L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P2.4
Port 2 Bit 4 Control.
bits 1−0
P24H
P24L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
NOTE: Port 2 also controlled by EA and Memory Access Control HCR1.EGP23.
76
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Port 3 Data Direction Low (P3DDRL)
7
6
5
4
3
2
1
0
Reset Value
SFR B3h
P33H
P33L
P32H
P32L
P31H
P31L
P30H
P30L
00h
P3.3
Port 3 Bit 3 Control.
bits 7−6
P33H
P33L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P3.2
Port 3 Bit 2 Control.
bits 5−4
P32H
P32L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P3.1
Port 3 Bit 1 Control.
bits 3−2
P31H
P31L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P3.0
Port 3 Bit 0 Control.
bits 1−0
P30H
P30L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
77
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Port 3 Data Direction High (P3DDRH)
7
6
5
4
3
2
1
0
Reset Value
SFR B4h
P37H
P37L
P36H
P36L
P35H
P35L
P34H
P34L
00h
P3.7
bits 7−6
Port 3 Bit 7 Control.
P37H
P37L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1.
P3.6
Port 3 Bit 6 Control.
bits 5−4
P36H
P36L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
NOTE: Port 3.6 also controlled by EA and Memory Access Control HCR1.1.
P3.5
Port 3 Bit 5 Control.
bits 3−2
P35H
P35L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
P3.4
Port 3 Bit 4 Control.
bits 1−0
P34H
P34L
0
0
1
1
0
1
0
1
Standard 8051 (Pull-Up)
CMOS Output
Open Drain Output
Input
78
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DAC Low Byte (DACL)
7
6
5
4
3
2
1
0
Reset Value
SFR B5h
00h
DACL7−0 Least Significant Byte Register for DAC0−3, DAC Control (0 and 2), and DAC Load Control .
bits 7−0
NOTE: DAC2 and DAC3 available only on the MSC1211 and MSC1212.
DAC High Byte (DACH)
7
6
5
4
3
2
1
0
Reset Value
SFR B6h
00h
DACH7−0 Most Significant Byte Register for DAC0−3 and DAC Control (1 and 3).
bits 7−0
NOTE: DAC2 and DAC3 available only on the MSC1211 and MSC1212.
DAC Select (DACSEL)
7
6
5
4
3
2
1
0
Reset Value
SFR B7h
DSEL7
DSEL6
DSEL5
DSEL4
DSEL3
DSEL2
DSEL1
DSEL0
00h
DSEL7−0
DAC Select and DAC Control Select. The DACSEL register selects which DAC output register or which DAC
bits 7−0
control register is accessed by the DACL and DACH registers.
DACSEL (B7h)
DACL (B5h)
RESET VALUE
DACH (B6h)
00h
01h
02h
03h
04h
05h
06h
07h
DAC0 (high)
DAC1 (high)
DAC0 (low)
DAC1 (low)
0000h
0000h
0000h
0000h
6363h
0303h
−−00h
—
(1)
(1)
DAC2 (high)
DAC2 (low)
(1)
(1)
DAC3 (high)
DAC3 (low)
DACCON1
DACCON0
(1)
(1)
DACCON3
DACCON2
—
—
LOADCON
—
(1)
DAC2 and DAC3 available only on the MSC1211 and MSC1212.
79
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
DAC0 Control (DACCON0)
DACSEL = 04h
7
6
5
4
3
2
1
0
Reset Value
SFR B5h
COR0
EOD0
IDAC0DIS
IDAC0SINK
0
SELREF0
DOM0_1
DOM0_0
63h
COR0
Current Over Range on DAC0
bit 7
Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range condition exists.
1 = NOP
Read: 0 = No current over range for DAC0.
0 = NOP
1 = IDAC overcurrent for three consecutive ticks on ms clock USEC (EOD0 = 1) or Current Over Range raw
signal (EOD0 = 0).
EOD0
Enable Over-Current Detection
bit 6
0 = Disable over-current detection.
1 = Enable over-current detection (default). After three consecutive ticks on MSEC clock of overcurrent, the DAC is
disabled; however, the register values are preserved. Writing to COR0 releases the high-impedance state.
IDAC0DIS IDAC0 Disable (for DOM0 = 00)
bit 5
0 = IDAC on mode for DAC0.
1 = IDAC off mode for DAC0 (default).
IDAC0SINK ENABLE CURRENT SINK
bit 4
0 = DAC0 is sourcing current.
1 = DAC0 is sinking current using external device.
Not Used
bit 3
SELREF0 Select the Reference Voltage for DAC0 Voltage Reference.
bit 2
0 = DAC0 V
1 = DAC0 V
= AV
(default).
REF
REF
DD
= voltage on REF IN+/REFOUT pin.
DOM0_1−0 DAC Output Mode DAC0.
bits 1−0
DOM0
OUTPUT MODE for DAC0
00
01
10
11
Normal VDAC output; IDAC controlled by IDAC0DIS bit.
Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off high impedance, IDAC off (default).
80
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DAC1 Control (DACCON1)
DACSEL = 04h
7
6
5
4
3
2
1
0
Reset Value
SFR B6h
COR1
EOD1
IDAC1DIS
IDAC1SINK
0
SELREF1
DOM1_1
DOM1_0
63h
COR1
Current Over Range on DAC1
bit 7
Write: 0 = Clear to release from high-impedance state back to normal mode unless an over-range condition exists.
1 = No effect.
Read: 0 = No current over range for DAC1.
0 = No effect.
1 = IDAC overcurrent for three consecutive ticks on ms clock USEC (EOD1 = 1) or Current Over Range raw
signal (EOD0 = 0).
EOD1
Enable Over-Current Detection
bit 6
0 = Disable over-current detection.
1 = Enable over-current detection (default). After three consecutive ticks on MSEC clock of overcurrent, the DAC is
disabled; however, the register values are preserved. Writing to COR1 releases the high-impedance state.
IDAC1DIS IDAC1 Disable (for DOM1 = 00)
bit 5
0 = IDAC on mode for DAC1.
1 = IDAC off mode for DAC1 (default).
IDAC1SINK ENABLE CURRENT SINK
bit 4
0 = DAC1 is sourcing current.
1 = DAC1 is sinking current using external device.
Not Used
bit 3
SELREF1 Select the Reference Voltage for DAC1 Voltage Reference.
bit 2
0 = DAC1 V
1 = DAC1 V
= AV
(default).
REF
REF
DD
= voltage on V
IN pins.
REF
DOM1_1−0 DAC Output Mode DAC1.
bits 1−0
DOM1
OUTPUT MODE for DAC1
00
01
10
11
Normal VDAC output; IDAC controlled by IDAC1DIS bit.
Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off high impedance, IDAC off (default).
81
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
DAC2 Control (DACCON2) (Available only on the MSC1211 and MSC1212)
DACSEL = 05h
7
6
5
4
3
2
1
0
Reset Value
SFR B5h
0
0
0
0
0
SELREF2
DOM2_1
DOM2_0
03h
SELREF2 Select the Reference Voltage for DAC2 Voltage Reference.
bit 2
0 = DAC2 V
1 = DAC2 V
= AV
(default).
REF
REF
DD
= internal V
.
REF
DOM2_1−0 DAC Output Mode DAC2.
bits 1−0
DOM2
OUTPUT MODE for DAC2
00
01
10
11
Normal VDAC output.
Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off high impedance, IDAC off (default).
DAC3 Control (DACCON3) (Available only on the MSC1211 and MSC1212)
DACSEL = 05h
7
6
5
4
3
2
1
0
Reset Value
SFR B6h
0
0
0
0
0
SELREF3
DOM3_1
DOM3_0
03h
SELREF3 Select the Reference Voltage for DAC3 Voltage Reference.
bit 2
0 = DAC3 V
1 = DAC3 V
= AV
(default).
REF
REF
DD
= internal V
.
REF
DOM3_1−0 DAC Output Mode DAC3.
bits 1−0
DOM2
OUTPUT MODE for DAC3
00
01
10
11
Normal VDAC output.
Power-Down mode—VDAC output off 1kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off 100kΩ to AGND, IDAC off.
Power-Down mode—VDAC output off high impedance, IDAC off (default).
82
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
DAC Load Control (LOADCON)
DACSEL = 06h
7
6
5
4
3
2
1
0
Reset Value
SFR B5h
D3LOAD1
D3LOAD0
D2LOAD1
D2LOAD0
D1LOAD1
D1LOAD0
D0LOAD1
D0LOAD0
00h
D3LOAD1−0 (Available only on MSC1211 and MSC1212)
bit 7−6 The DAC load options are listed below:
DxLOAD
OUTPUT MODE for
00
01
10
11
Direct load: write to DACxL directly loads the DAC buffer and the DAC output (write to DACxH does not load DAC output).
Delay load: the values last written to DACxL/DACxH will be transferred to the DAC output on the next MSEC timer tick.
Delay load: the values last written to DACxL/DACxH will be transferred to the DAC output on the next HMSEC timer tick.
Sync load: the values contained in the DACxL/DACxH registers will be transferred to the DAC output immediately after
11b is written to this register.
D2LOAD1−0 (Available only on MSC1211 and MSC1212)
bit 5−4
D1LOAD1−0
bit 3−2
D0LOAD1−0
bit 1−0
Interrupt Priority (IP)
7
6
5
4
3
2
1
0
Reset Value
SFR B8h
1
PS1
PT2
PS0
PT1
PX1
PT0
PX0
80h
PS1
Serial Port 1 Interrupt. This bit controls the priority of the serial Port 1 interrupt.
0 = Serial Port 1 priority is determined by the natural priority order.
1 = Serial Port 1 is a high-priority interrupt.
bit 6
PT2
Timer 2 Interrupt. This bit controls the priority of the Timer 2 interrupt.
0 = Timer 2 priority is determined by the natural priority order.
1 = Timer 2 priority is a high-priority interrupt.
bit 5
PS0
Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt.
0 = Serial Port 0 priority is determined by the natural priority order.
1 = Serial Port 0 is a high-priority interrupt.
bit 4
PT1
Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt.
0 = Timer 1 priority is determined by the natural priority order.
1 = Timer 1 priority is a high-priority interrupt.
bit 3
PX1
External Interrupt 1. This bit controls the priority of external interrupt 1.
0 = External interrupt 1 priority is determined by the natural priority order.
1 = External interrupt 1 is a high-priority interrupt.
bit 2
PT0
Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt.
0 = Timer 0 priority is determined by the natural priority order.
1 = Timer 0 priority is a high-priority interrupt.
bit 1
PX0
External Interrupt 0. This bit controls the priority of external interrupt 0.
0 = External interrupt 0 priority is determined by the natural priority order.
1 = External interrupt 0 is a high-priority interrupt.
bit 0
83
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Serial Port 1 Control (SCON1)
7
6
5
4
3
2
1
0
Reset Value
SFR C0h
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00h
SM0−2
Serial Port 1 Mode. These bits control the mode of serial Port 1. Modes 1, 2, and 3 have 1 start and 1 stop bit in
bits 7−5
addition to the 8 or 9 data bits.
MODE
SM0 SM1 SM2 FUNCTION
LENGTH
PERIOD
(1)
0
0
0
0
0
0
0
1
Synchronous
Synchronous
8 bits
8 bits
12 p
4 p
CLK
(1)
CLK
(2)
(2)
1
1
0
0
1
1
0
1
Asynchronous
10 bits
10 bits
Timer 1 Baud Rate Equation
Timer 1 Baud Rate Equation
(3)
Valid Stop Required
(1)
(1)
2
2
1
0
0
Asynchronous
11 bits
64 p
32 p
(SMOD = 0)
(SMOD = 1)
CLK
CLK
(4)
(4)
(1)
(1)
1
0
1
Asynchronous with Multiprocessor Communication
11 bits
64 p
32 p
(SMOD = 0)
(SMOD = 1)
CLK
CLK
(2)
(2)
3
3
1
1
1
1
0
1
Asynchronous
11 bits
11 bits
Timer 1 Baud Rate Equation
Timer 1 Baud Rate Equation
Asynchronous with Multiprocessor Communication
(1) pCLK will be equal to tCLK, except that pCLK will stop for Idle mode.
(2) For modes 1 and 3, the selection of Timer 1 for baud rate is specified via the T2CON (C8h) register.
(3) RI_0 will only be activated when a valid STOP is received.
(4) RI_0 will not be activated if bit 9 = 0.
REN_1
Receive Enable. This bit enables/disables the serial Port 1 received shift register.
bit 4
0 = Serial Port 1 reception disabled.
1 = Serial Port 1 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).
TB8_1
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 1 modes 2 and 3.
bit 3
RB8_1
9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 1 modes
bit 2
2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit. RB8_1 is not used in mode 0.
TI_1
bit 1
Transmitter Interrupt Flag. This bit indicates that data in the serial Port 1 buffer has been completely shifted out.
In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last
data bit. This bit must be cleared by software to transmit the next byte.
RI_1
bit 0
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 1 buffer. In serial
port mode 0, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1 is set after the last sample of the incoming
stop bit subject to the state of SM2_1. In modes 2 and 3, RI_1 is set after the last sample of RB8_1. This bit must
be cleared by software to receive the next byte.
Serial Data Buffer 1 (SBUF1)
7
6
5
4
3
2
1
0
Reset Value
SFR C1h
00h
SBUF1.7−0 Serial Data Buffer 1. Data for serial Port 1 is read from or written to this location. The serial transmit and receive
bits 7−0
buffers are separate registers, but both are addressed at this location.
84
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Enable Wake Up (EWU) Waking Up from Idle Mode
7
6
5
4
3
2
1
0
Reset Value
SFR C6h
—
—
—
—
—
EWUWDT
EWUEX1
EWUEX0
00h
Auxiliary interrupts will wake up from Idle mode. They are enabled with EAI (EICON.5).
EWUWDT Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt.
bit 2
0 = Don’t wake up on watchdog timer interrupt.
1 = Wake up on watchdog timer interrupt.
EWUEX1
Enable Wake Up External 1. Wake using external interrupt source 1.
0 = Don’t wake up on external interrupt source 1.
bit 1
1 = Wake up on external interrupt source 1.
EWUEX0
Enable Wake Up External 0. Wake using external interrupt source 0.
0 = Don’t wake up on external interrupt source 0.
bit 0
1 = Wake up on external interrupt source 0.
System Clock Divider (SYSCLK)
7
6
5
4
3
2
1
0
Reset Value
SFR C7h
0
0
DIVMOD1
DIVMOD0
0
DIV2
DIV1
DIV0
00h
NOTE: Changing SYSCLK registers affects all internal clocks, including the ADC clock.
DIVMOD1−0 Clock Divide Mode
bits 5−4
Write:
DIVMOD
DIVIDE MODE
00
01
10
Normal mode (default, no divide).
Immediate mode: start divide immediately; return to Normal mode on Idle mode wakeup condition or by direct write to SFR.
Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is
enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not
enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the
MSINT counter overflows, which follows a wakeup condition. Can exit by directly writing to SFR.
11
Manual mode: start divide immediately; exit mode only by directly writing to SFR. Same as immediate mode, but cannot
return to Normal mode on Idle mode wakeup condition; only by directly writing to SFR.
Read:
DIVMOD
DIVISION MODE STATUS
00
01
10
11
No divide
Divider is in Immediate mode
Divider is in Delay mode
Medium mode
DIV2−0
Divide Mode
bit 2−0
DIV
DIVISOR
f
FREQUENCY
CLK
000
001
010
011
100
101
110
111
Divide by 2 (default)
Divide by 4
f
f
f
f
f
f
f
f
= f
SYS
= f
SYS
= f
SYS
= f
SYS
= f
SYS
= f
SYS
= f
SYS
= f
SYS
/2
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
/4
Divide by 8
/8
Divide by 16
/16
Divide by 32
/32
Divide by 1024
Divide by 2048
Divide by 4096
/1024
/2048
/4096
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Timer 2 Control (T2CON)
7
6
5
4
3
2
1
0
Reset Value
SFR C8h
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
00h
TF2
Timer 2 Overflow Flag. This flag will be set when Timer 2 overflows from FFFFh. It must be cleared by software.
bit 7
TF2 will only be set if RCLK and TCLK are both cleared to ‘0’. Writing a ‘1’ to TF2 forces a Timer 2 interrupt if enabled.
EXF2
bit 6
Timer 2 External Flag. A negative transition on the T2EX pin (P1.1) will cause this flag to be set based on the EXEN2
(T2CON.3) bit. If set by a negative transition, this flag must be cleared to ‘0’ by software. Setting this bit in software
will force a timer interrupt if enabled.
RCLK
Receive Clock Flag. This bit determines the serial Port 0 timebase when receiving data in serial modes 1 or 3.
0 = Timer 1 overflow is used to determine receiver baud rate for USART0.
bit 5
1 = Timer 2 overflow is used to determine receiver baud rate for USART0.
Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of the
external clock.
TCLK
Transmit Clock Flag. This bit determines the serial Port 0 timebase when transmitting data in serial modes 1 or 3.
0 = Timer 1 overflow is used to determine transmitter baud rate for USART0.
bit 4
1 = Timer 2 overflow is used to determine transmitter baud rate for USART0.
Setting this bit will force Timer 2 into baud rate generation mode. The timer will operate from a divide by 2 of the
external clock.
EXEN2
Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if Timer 2 is not generating
bit 3
baud rates for the serial port.
0 = Timer 2 will ignore all external events at T2EX.
1 = Timer 2 will capture or reload a value if a negative transition is detected on the T2EX pin.
TR2
Timer 2 Run Control. This bit enables/disables the operation of Timer 2. Halting this timer will preserve the current
bit 2
count in TH2, TL2.
0 = Timer 2 is halted.
1 = Timer 2 is enabled.
C/T2
Counter/Timer Select. This bit determines whether Timer 2 will function as a timer or counter. Independent of this
bit 1
bit, Timer 2 runs at 2 clocks per tick when used in baud rate generator mode.
0 = Timer 2 functions as a timer. The speed of Timer 2 is determined by the T2M bit (CKCON.5).
1 = Timer 2 will count negative transitions on the T2 pin (P1.0).
CP/RL2
bit 0
Capture/Reload Select. This bit determines whether the capture or reload function will be used for Timer 2. If either
RCLK or TCLK is set, this bit will not function and the timer will function in an auto-reload mode following each
overflow.
0 = Auto-reloads will occur when Timer 2 overflows or a falling edge is detected on T2EX if EXEN2 = 1.
1 = Timer 2 captures will occur when a falling edge is detected on T2EX if EXEN2 = 1.
Timer 2 Capture LSB (RCAP2L)
7
6
5
4
3
2
1
0
Reset Value
SFR CAh
00h
RCAP2L
Timer 2 Capture LSB. This register is used to capture the TL2 value when Timer 2 is configured in capture mode.
bits 7−0
RCAP2L is also used as the LSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode.
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Timer 2 Capture MSB (RCAP2H)
7
6
5
4
3
2
1
0
Reset Value
SFR CBh
00h
RCAP2H
bits 7−0
Timer 2 Capture MSB. This register is used to capture the TH2 value when Timer 2 is configured in capture mode.
RCAP2H is also used as the MSB of a 16-bit reload value when Timer 2 is configured in auto-reload mode.
Timer 2 LSB (TL2)
7
6
5
4
3
2
1
0
Reset Value
SFR CCh
00h
TL2
bits 7−0
Timer 2 LSB. This register contains the least significant byte of Timer 2.
Timer 2 MSB (TH2)
7
6
5
4
3
2
1
0
Reset Value
SFR CDh
00h
TH2
Timer 2 MSB. This register contains the most significant byte of Timer 2.
bits 7−0
Program Status Word (PSW)
7
6
5
4
3
2
1
0
Reset Value
SFR D0h
CY
AC
F0
RS1
RS0
OV
F1
P
00h
CY
Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during
bit 7
subtraction). Otherwise, it is cleared to ‘0’ by all arithmetic operations.
AC
Auxiliary Carry Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry into (during addition), or
bit 6
a borrow (during subtraction) from the high order nibble. Otherwise, it is cleared to ‘0’ by all arithmetic operations.
F0
User Flag 0. This is a bit-addressable, general-purpose flag for software control.
bit 5
RS1, RS0
Register Bank Select 1−0. These bits select which register bank is addressed during register accesses.
bits 4−3
RS1
RS0
REGISTER BANK
ADDRESS
0
0
1
1
0
1
0
1
0
1
2
3
00h − 07h
08h − 0Fh
10h − 17h
18h − 1Fh
OV
Overflow Flag. This bit is set to ‘1’ if the last arithmetic operation resulted in a carry (addition), borrow (subtraction),
bit 2
or overflow (multiply or divide). Otherwise, it is cleared to ‘0’ by all arithmetic operations.
F1
User Flag 1. This is a bit-addressable, general-purpose flag for software control.
bit 1
P
Parity Flag. This bit is set to ‘1’ if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity), and cleared to
bit 0
‘0’ on even parity.
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ADC Offset Calibration Low Byte (OCL)
7
6
5
4
3
2
1
0
Reset Value
SFR D1h
00h
OCL
bits 7−0
ADC Offset Calibration Low Byte. This is the low byte of the 24-bit word that contains the ADC offset
calibration. A value that is written to this location will set the ADC offset calibration value.
ADC Offset Calibration Middle Byte (OCM)
7
6
5
4
3
2
1
0
Reset Value
SFR D2h
00h
OCM
bits 7−0
ADC Offset Calibration Middle Byte. This is the middle byte of the 24-bit word that contains the ADC offset
calibration. A value that is written to this location will set the ADC offset calibration value.
ADC Offset Calibration High Byte (OCH)
7
6
5
4
3
2
1
0
Reset Value
SFR D3h
00h
OCH
bits 7−0
ADC Offset Calibration High Byte. This is the high byte of the 24-bit word that contains the ADC offset
calibration. A value that is written to this location will set the ADC offset calibration value.
ADC Gain Calibration Low Byte (GCL)
7
6
5
4
3
2
1
0
Reset Value
SFR D4h
5Ah
GCL
bits 7−0
ADC Gain Calibration Low Byte. This is the low byte of the 24-bit word that contains the ADC gain
calibration. A value that is written to this location will set the ADC gain calibration value.
ADC Gain Calibration Middle Byte (GCM)
7
6
5
4
3
2
1
0
Reset Value
SFR D5h
ECh
GCM
bits 7−0
ADC Gain Calibration Middle Byte. This is the middle byte of the 24-bit word that contains the ADC gain
calibration. A value that is written to this location will set the ADC gain calibration value.
ADC Gain Calibration High Byte (GCH)
7
6
5
4
3
2
1
0
Reset Value
SFR D6h
5Fh
GCH
ADC Gain Calibration High Byte. This is the high byte of the 24-bit word that contains the ADC gain
bits 7−0
calibration. A value that is written to this location will set the ADC gain calibration value.
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ADC Input Multiplexer (ADMUX)
7
6
5
4
3
2
1
0
Reset Value
SFR D7h
INP3
INP2
INP1
INP0
INN3
INN2
INN1
INN0
01h
INP3−0
Input Multiplexer Positive Input. This selects the positive signal input.
bits 7−4
INP3 INP2 INP1 INP0 POSITIVE INPUT
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0 (default)
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AINCOM
Temperature Sensor (requires ADMUX = FFh)
INN3−0
Input Multiplexer Negative Input. This selects the negative signal input.
bits 3−0
INN3 INN2 INN1 INN0 NEGATIVE INPUT
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1 (default)
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AINCOM
Temperature Sensor (requires ADMUX = FFh)
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Enable Interrupt Control (EICON)
7
6
5
4
3
2
1
0
Reset Value
SFR D8h
SMOD1
1
EAI
AI
WDTI
0
0
0
40h
SMOD1
Serial Port 1 Mode. When this bit is set the serial baud rate for Port 1 will be doubled.
0 = Standard baud rate for Port 1 (default).
bit 7
1 = Double baud rate for Port 1.
EAI
Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and
bit 5
identified by SFR registers PAI (SFR A5h), AIE (SFR A6h), and AISTAT (SFR A7h).
0 = Auxiliary Interrupt disabled (default).
1 = Auxiliary Interrupt enabled.
AI
bit 4
Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, after the source
of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary
Interrupt, if enabled.
0 = No Auxiliary Interrupt detected (default).
1 = Auxiliary Interrupt detected.
WDTI
Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine.
bit 3
Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The
Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabled in
HCR0.
0 = No Watchdog Timer Interrupt Detected (default).
1 = Watchdog Timer Interrupt Detected.
ADC Results Low Byte (ADRESL)
7
6
5
4
3
2
1
0
Reset Value
SFR D9h
00h
ADRESL
bits 7−0
The ADC Results Low Byte. This is the low byte of the 24-bit word that contains the ADC results.
Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared.
ADC Results Middle Byte (ADRESM)
7
6
5
4
3
2
1
0
Reset Value
SFR DAh
00h
ADRESM
The ADC Results Middle Byte. This is the middle byte of the 24-bit word that contains the A/D conversion results.
bits 7−0
ADC Results High Byte (ADRESH)
7
6
5
4
3
2
1
0
Reset Value
SFR DBh
00h
ADRESH
The ADC Results High Byte. This is the high byte of the 24-bit word that contains the A/D conversion results.
bits 7−0
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ADC Control 0 (ADCON0)
7
6
5
4
3
2
1
0
Reset Value
SFR DCh
REFCLK
BOD
EVREF
VREFH
EBUF
PGA2
PGA1
PGA0
30h
REFCLK
Reference Clock. The reference is specified with a 250kHz clock. The REFCLK should be selected by choosing
bit 7
the appropriate source so that it does not exceed 250kHz.
tCLK
0 +
(ACLK ) 1) * 4
USEC
1 +
4
BOD
bit 6
Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative
current source to the negative channel. If the channel is open circuit then the ADC results will be full-scale. Used with
Buffer ON.
0 = Burnout Current Sources Off (default).
1 = Burnout Current Sources On.
EVREF
Enable Internal Voltage Reference. If the internal voltage reference is not used, it should be turned off to savepower
bit 5
and reduce noise.
0 = Internal Voltage Reference Off.
1 = Internal Voltage Reference On (default). REF IN− should be connected to AGND in this mode. REF IN+ should
have a 0.1µF capacitor.
VREFH
Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V.
0 = REFOUT/REF IN+ is 1.25V.
bit 4
1 = REFOUT/REF IN+ is 2.5V (default).
EBUF
Enable Buffer. Enable the input buffer to provide higher input impedance but limits the input voltage range and
bit 3
dissipates more power.
0 = Buffer disabled (default).
1 = Buffer enabled.
PGA2−0
Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128.
bits 2−0
PGA2
PGA1
PGA0
GAIN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 (default)
2
4
8
16
32
64
128
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ADC Control 1 (ADCON1)
7
6
5
4
3
2
1
0
Reset Value
SFR DDh
OF_UF
POL
SM1
SM0
—
CAL2
CAL1
CAL0
0000 0000b
OF_UF
Overflow/Underflow. If this bit is set, the data in the summation register is invalid. Either an overflow or underflow
bit 7
occurred. The bit is cleared by writing a ‘0’ to it.
POL
Polarity. Polarity of the ADC result and Summation register.
0 = Bipolar.
bit 6
1 = Unipolar. The LSB size is 1/2 the size of bipolar (twice the resolution).
POL
0
ANALOG INPUT
DIGITAL OUTPUT
+FSR
ZERO
−FSR
7FFFFFh
000000h
800000h
+FSR
ZERO
−FSR
FFFFFFh
000000h
000000h
1
SM1−0
Settling Mode. Selects the type of filter or auto-select which defines the digital filter settling characteristics.
bits 5−4
SM1
SM0
SETTLING MODE
0
0
1
1
0
1
0
1
Auto
Fast Settling Filter
2
Sinc Filter
3
Sinc Filter
CAL2−0
Calibration Mode Control Bits.
bits 2−0
Writing to these bits initiates the ADC calibration.
CAL2
CAL1
CAL0 CALIBRATION MODE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Calibration (default)
Self-Calibration, Offset and Gain
Self-Calibration, Offset only
Self-Calibration, Gain only
System Calibration, Offset only
System Calibration, Gain only
Reserved
Reserved
:
NOTE Read Value—000b.
ADC Control 2 (ADCON2)
7
6
5
4
3
2
1
0
Reset Value
SFR DEh
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1Bh
DR7−0
bits 7−0
Decimation Ratio LSB.
ADC Control 3 (ADCON3)
7
6
5
4
3
2
1
0
Reset Value
SFR DFh
—
—
—
—
—
DR10
DR9
DR8
06h
DR10−8
Decimation Ratio Most Significant 3 Bits. The ADC output data rate = (ACLK + 1)/64/Decimation Ratio.
bits 2−0
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Accumulator (A or ACC)
7
6
5
4
3
2
1
0
Reset Value
SFR E0h
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
00h
ACC.7−0
bits 7−0
Accumulator. This register serves as the accumulator for arithmetic and logic operations.
Summation/Shifter Control (SSCON)
7
6
5
4
3
2
1
0
Reset Value
SFR E1h
SSCON1
SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
00h
The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register, the 32-bit
SUMR3−0 registers will be cleared. The Summation registers will do sign-extend if Bipolar mode is selected in ADCON1.
SSCON1−0 Summation/Shift Count.
bits 7−6
SSCON1 SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
DESCRIPTION
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
Clear Summation Register
0
1
0
0
0
0
CPU Summation on Write to SUMR0 (sum count/shift ignored)
CPU Subtraction on Write to SUMR0 (sum count/shift ignored)
CPU Shift only
1
0
0
0
0
0
x
x
x
Note (1)
x
Note (1)
x
Note (1)
x
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
ADC Summation only
Note (1)
Note (1)
Note (1)
ADC Summation completes, then shift completes
(1)
Refer to register bit definition.
SCNT2−0
Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the
bits 5−3
SUMR0 register clears the interrupt.
SCNT2
SCNT1
SCNT0 SUMMATION COUNT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
SHF2−0
Shift Count.
bits 2−0
SHF2
SHF1
SHF0
SHIFT
DIVIDE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
2
4
8
16
32
64
128
256
93
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Summation 0 (SUMR0)
7
6
5
4
3
2
1
0
Reset Value
SFR E2h
00h
SUMR0
bits 7−0
Summation 0. This is the least significant byte of the 32-bit summation register, or bits 0 to 7.
Write: values in SUMR3−0 are added to the summation register.
Read: clears the Summation Count Interrupt; however, AI in EICON (SFR D8) must also be cleared.
Summation 1 (SUMR1)
7
6
5
4
3
2
1
0
Reset Value
SFR E3h
00h
SUMR1
Summation 1. This is the most significant byte of the lowest 16 bits of the summation register, or bits 8−15.
bits 7−0
Summation 2 (SUMR2)
7
6
5
4
3
2
1
0
Reset Value
SFR E4h
00h
SUMR2
Summation 2. This is the most significant byte of the lowest 24 bits of the summation register, or bits 16−23.
bits 7−0
Summation 3 (SUMR3)
7
6
5
4
3
2
1
0
Reset Value
SFR E5h
00h
SUMR3
Summation 3. This is the most significant byte of the 32-bit summation register, or bits 24−31.
bits 7−0
Offset DAC (ODAC)
7
6
5
4
3
2
1
0
Reset Value
SFR E6h
00h
ODAC
bits 7−0
Offset DAC. This register will shift the input by up to half of the ADC full-scale input range. The Offset DAC
value is summed into the ADC prior to conversion. Writing 00h or 80h to ODAC turns off the Offset DAC.. The offset
DAC should be cleared prior to calibration, since the offset DAC analog output is applied directly to the ADC input.
bit 7
Offset DAC Sign bit.
0 = Positive
1 = Negative
ƪ
ƫ
ODAC 6 : 0
*VREF
2 @ PGA
bit7
(
)
@ ǒ Ǔ@ * 1
bit 6−0
Offset +
127
NOTE: ODAC cannot be used to offset the analog inputs so that the buffer can be used for signals within 50mV of AGND.
94
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Low Voltage Detect Control (LVDCON)
7
6
5
4
3
2
1
0
Reset Value
SFR E7h
ALVDIS
ALVD2
ALVD1
ALVD0
DLVDIS
DLVD2
DLVD1
DLVD0
00h
ALVDIS
Analog Low Voltage Detect Disable.
bit 7
0 = Enable Detection of Low Analog Supply Voltage.
1 = Disable Detection of Low Analog Supply Voltage.
ALVD2−0
Analog Voltage Detection Level.
bits 6−4
ALVD2
ALVD1
ALVD0
VOLTAGE LEVEL
AV 2.7V (default)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DD
AV
3.0V
3.3V
4.0V
4.2V
4.5V
4.7V
DD
DD
DD
DD
DD
DD
AV
AV
AV
AV
AV
External Voltage AIN7 compared to 1.2V
DLVDIS
Digital Low Voltage Detect Disable.
bit 3
0 = Enable Detection of Low Digital Supply Voltage.
1 = Disable Detection of Low Digital Supply Voltage.
DLVD2−0
Digital Voltage Detection Level.
bits 2−0
DLVD2
DLVD1
DLVD0
VOLTAGE LEVEL
DV 2.7V (default)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DD
DV
3.0V
3.3V
4.0V
4.2V
4.5V
4.7V
DD
DD
DD
DD
DD
DD
DV
DV
DV
DV
DV
External Voltage AIN6 compared to 1.2V
95
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Extended Interrupt Enable (EIE)
7
6
5
4
3
2
1
0
Reset Value
SFR E8h
1
1
1
EWDI
EX5
EX4
EX3
EX2
E0h
EWDI
Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by
bit 4
(SFR FFh) and PDCON (SFR F1h) registers.
0 = Disable the Watchdog Interrupt
1 = Enable Interrupt Request Generated by the Watchdog Timer
EX5
External Interrupt 5 Enable. This bit enables/disables external interrupt 5.
0 = Disable External Interrupt 5
bit 3
1 = Enable External Interrupt 5
EX4
External Interrupt 4 Enable. This bit enables/disables external interrupt 4.
0 = Disable External Interrupt 4
bit 2
1 = Enable External Interrupt 4
EX3
External Interrupt 3 Enable. This bit enables/disables external interrupt 3.
0 = Disable External Interrupt 3
bit 1
1 = Enable External Interrupt 3
EX2
External Interrupt 2 Enable. This bit enables/disables external interrupt 2.
0 = Disable External Interrupt 2
bit 0
1 = Enable External Interrupt 2
Hardware Product Code 0 (HWPC0)
7
6
5
4
3
2
1
0
Reset Value
(1)
SFR E9h
0
0
0
0
0
1
MEMORY SIZE
0000_01xxb
(1)
Applies to MSC1211 and MSC1213 only. Reset value for MSC1212 and MSC1214 is 0000_00xxb.
HWPC0.7−0 Hardware Product Code LSB. Read-only.
bits 7−0
MEMORY SIZE
MODEL
FLASH MEMORY
0
0
1
1
0
0
0
1
MSC121xY2
MSC121xY3
MSC121xY4
MSC121xY5
4kB
8kB
16kB
32kB
Hardware Product Code 1 (HWPC1)
7
6
5
4
3
2
1
0
Reset Value
(1)
08h
SFR EAh
0
0
0
0
1
0
0
0
(1)
Applies to MSC1211 and MSC1212 only. Reset value for MSC1213 and MSC1214 is 18h.
HWPC1.7−0 Hardware Product Code MSB. Read-only.
bits 7−0
96
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Hardware Version (HDWVER)
7
6
5
4
3
2
1
0
Reset Value
SFR EBh
Flash Memory Control (FMCON)
7
6
5
4
3
2
1
0
Reset Value
SFR EEh
0
PGERA
0
FRCM
0
BUSY
SPM
FPM
02h
PGERA
Page Erase. Available in both user and program modes.
bit 6
0 = Disable Page Erase Mode
1 = Enable Page Erase Mode (automatically set by page_erase Boot ROM routine).
FRCM
Frequency Control Mode.
bit 4
0 = Bypass (default)
1 = Use Delay Line. Recommended for saving power.
BUSY
Write/Erase BUSY Signal.
0 = Idle or Available
1 = Busy
bit 2
SPM
Serial/Parallel Programming Mode. Read-only.
bit 1
0 = Indicates the device is in parallel programming mode.
1 = Indicates the device is in serial programming mode (if FPM also = 1).
FPM
Flash Programming Mode. Read-only.
bit 0
0 = Indicates the device is operating in UAM.
1 = Indicates the device is operating in programming mode.
Flash Memory Timing Control (FTCON)
7
6
5
4
3
2
1
0
Reset Value
SFR EFh
FER3
FER2
FER1
FER0
FWR3
FWR2
FWR1
FWR0
A5h
Refer to Flash Memory Characteristics
FER3−0
bits 7−4
Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • t
. This can be broken into multiple shorter erase times.
For more Information, see Application Report SBAA137, Incremental Flash Memory Page Erase, available for
CLK
download from www.ti.com.
Industrial temperature range: 10ms
Commercial temperature range: 4ms
FWR3−0
bits 3−0
Set Write. Set Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • tCLK. Total writing time will be longer. For more
Information, see Application Report SBAA087, In-Application Flash Programming, available for download from
www.ti.com.
Range: 30µs to 40µs.
B Register (B)
7
6
5
4
3
2
1
0
Reset Value
SFR F0h
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
00h
B.7−0
B Register. This register serves as a second accumulator for certain arithmetic operations.
bits 7−0
97
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Power-Down Control (PDCON)
7
6
5
4
3
2
1
0
Reset Value
SFR F1h
0
PDDAC
PDI2C
PDPWM
PDADC
PDWDT
PDST
PDSPI
7Fh
Turning peripheral modules off puts the MSC1211/12/13/14 in the lowest power mode.
PDDAC
DAC Module Control.
0 = DACs On
bit 6
1 = DACs Power Down
PDI2C
I2C Control (MSC1211 and MSC1213 only).
2
bit 5
0 = I C On (the state is undefined if PDSPI is also = 0)
2
1 = I C Power Down
PDPWM
Pulse Width Module Control.
0 = PWM On
bit 4
1 = PWM Power Down
PDADC
ADC Control.
bit 3
0 = ADC On
1 = ADC, VREF, and Summation registers are powered down.
PDWDT
Watchdog Timer Control.
0 = Watchdog Timer On
bit 2
1 = Watchdog Timer Power Down
PDST
System Timer Control.
0 = System Timer On
bit 1
1 = System Timer Power Down
PDSPI
SPI System Control.
bit 0
0 = SPI System On (the state is undefined if PDI2C is also = 0)
1 = SPI System Power Down
PSEN/ALE Select (PASEL)
7
6
5
4
3
2
1
0
Reset Value
SFR F2h
0
0
PSEN2
PSEN1
PSEN0
0
ALE1
ALE0
00h
PSEN2−0
PSEN Mode Select.
bits 5−3
PSEN2
PSEN1
PSEN0
0
0
1
1
1
0
1
0
1
1
X
X
X
0
PSEN
CLK
ADC MODCLK
Low
1
High
ALE1−0
ALE Mode Select.
bits 1−0
ALE1
ALE0
0
1
1
X
0
1
ALE
Low
High
:
NOTE X = don’t care.
98
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Analog Clock (ACLK)
7
6
5
4
3
2
1
0
Reset Value
SFR F6h
0
FREQ6
FREQ5
FREQ4
FREQ3
FREQ2
FREQ1
FREQ0
03h
FREQ6−0 Clock Frequency Selection. This value + 1 divides the system clock to create the ACLK frequency.
fCLK
FREQ ) 1
bit 6−0
ACLK frequency +
fCLK
fMOD
+
(
)
ACLK ) 1 * 64
fMOD
Decimation
Data Rate +
System Reset (SRST)
7
6
5
4
3
2
1
0
Reset Value
SFR F7h
0
0
0
0
0
0
0
RSTREQ
00h
RSTREQ
bit 0
Reset Request. Setting this bit to ‘1’ and then clearing to ‘0’ will generate a system reset.
Extended Interrupt Priority (EIP)
7
6
5
4
3
2
1
0
Reset Value
SFR F8h
1
1
1
PWDI
PX5
PX4
PX3
PX2
E0h
PWDI
Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt.
0 = The watchdog interrupt is low priority.
bit 4
1 = The watchdog interrupt is high priority.
PX5
External Interrupt 5 Priority. This bit controls the priority of external interrupt 5.
0 = External interrupt 5 is low priority.
bit 3
1 = External interrupt 5 is high priority.
PX4
External Interrupt 4 Priority. This bit controls the priority of external interrupt 4.
0 = External interrupt 4 is low priority.
bit 2
1 = External interrupt 4 is high priority.
PX3
External Interrupt 3 Priority. This bit controls the priority of external interrupt 3.
0 = External interrupt 3 is low priority.
bit 1
1 = External interrupt 3 is high priority.
PX2
External Interrupt 2 Priority. This bit controls the priority of external interrupt 2.
0 = External interrupt 2 is low priority.
bit 0
1 = External interrupt 2 is high priority.
99
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
Seconds Timer Interrupt (SECINT)
7
6
5
4
3
2
1
0
Reset Value
SFR F9h
WRT
SECINT6
SECINT5
SECINT4
SECINT3
SECINT2
SECINT1
SECINT0
7Fh
This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, that 1ms timer tick is divided by the
register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate
an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt; however, AI
in EICON (SFR D8h) must also be cleared. This Interrupt can be monitored in the AIE or AIPOL registers.
WRT
Write Control. Determines whether to write the value immediately or wait until the current count is finished.
Read = 0.
bit 7
0 = Delay Write Operation. The SEC value is loaded when the current count expires.
1 = Write Immediately. The counter is loaded once the CPU completes the write operation.
SECINT6−0 Seconds Count. Normal operation would use 100ms as the clock interval.
bits 6−0 Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • t
.
CLK
Milliseconds Timer Interrupt (MSINT)
7
6
5
4
3
2
1
0
Reset Value
SFR FAh
WRT
MSINT6
MSINT5
MSINT4
MSINT3
MSINT2
MSINT1
MSINT0
7Fh
The clock used for this timer is the 1ms clock, which results from dividing the system clock by the values in registers
MSECH:MSECL. Reading this register is necessary for clearing the interrupt; however, AI in EICON (SFR D8h) must also
be cleared.
WRT
Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0.
0 = Delay Write Operation. The MSINT value is loaded when the current count expires.
bit 7
1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.
MSINT6−0 Milliseconds Count. Normal operation would use 1ms as the clock interval.
bits 6−0 MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • t
CLK
One Microsecond Timer (USEC)
7
6
5
4
3
2
1
0
Reset Value
SFR FBh
0
0
FREQ5
FREQ4
FREQ3
FREQ2
FREQ1
FREQ0
03h
FREQ5−0 Clock Frequency − 1. This value + 1 divides the system clock to create a 1µs Clock.
bits 5−0 USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh).
One Millisecond Timer Low Byte (MSECL)
7
6
5
4
3
2
1
0
Reset Value
SFR FCh
MSECL7
MSECL6
MSECL5
MSECL4
MSECL3
MSECL2
MSECL1
MSECL0
9Fh
MSECL7−0 One Millisecond Timer Low Byte. This value in combination with the next register is used to create a 1ms clock.
bits 7−0
1ms = (MSECH • 256 + MSECL + 1) • t
. This clock is used to set Flash erase time. See FTCON (SFR EFh).
CLK
100
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SBAS323D − JUNE 2004 − REVISED SEPTEMBER 2005
One Millisecond Timer High Byte (MSECH)
7
6
5
4
3
2
1
0
Reset Value
SFR FDh
MSECH7
MSECH6
MSECH5
MSECH4
MSECH3
MSECH2
MSECH1
MSECH0
0Fh
MSECH7−0 One Millisecond Timer High Byte. This value in combination with the previous register is used to create a 1ms clock.
bits 7−0 1ms = (MSECH • 256 + MSECL + 1) • t
.
CLK
One Hundred Millisecond Timer (HMSEC)
7
6
5
4
3
2
1
0
Reset Value
SFR FEh
WRT
HMSEC6
HMSEC5
HMSEC4
HMSEC3
HMSEC2
HMSEC1
HMSEC0
63h
WRT
bit 7
Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0.
0 = Delay Write Operation. The MSINT value is loaded when the current count expires.
1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.
HMSEC6−0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock.
bits 6−0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • t
.
CLK
Watchdog Timer (WDTCON)
7
6
5
4
3
2
1
0
Reset Value
SFR FFh
EWDT
DWDT
RWDT
WDCNT4
WDCNT3
WDCNT2
WDCNT1
WDCNT0
00h
EWDT
Enable Watchdog (R/W).
bit 7
Write 1/Write 0 sequence sets the Watchdog Enable Counting bit.
DWDT
Disable Watchdog (R/W).
bit 6
Write 1/Write 0 sequence clears the Watchdog Enable Counting bit.
RWDT
Reset Watchdog (R/W).
bit 5
Write 1/Write 0 sequence restarts the Watchdog Counter.
WDCNT4−0 Watchdog Count (R/W).
bits 4−0
Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is
an uncertainty of 1 count.
101
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
Drawing
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
PAG
MSC1211Y2PAGR
MSC1211Y2PAGT
MSC1211Y3PAGR
MSC1211Y3PAGT
MSC1211Y4PAGR
MSC1211Y4PAGT
MSC1211Y5PAGR
MSC1211Y5PAGT
MSC1212Y2PAGR
MSC1212Y2PAGT
MSC1212Y3PAGR
MSC1212Y3PAGT
MSC1212Y4PAGR
MSC1212Y4PAGT
MSC1212Y5PAGR
MSC1212Y5PAGT
MSC1213Y2PAGR
MSC1213Y2PAGT
MSC1213Y3PAGR
MSC1213Y3PAGT
MSC1213Y4PAGR
MSC1213Y4PAGT
MSC1213Y5PAGR
MSC1213Y5PAGT
MSC1214Y2PAGR
MSC1214Y2PAGT
MSC1214Y3PAGR
MSC1214Y3PAGT
MSC1214Y4PAGR
MSC1214Y4PAGT
MSC1214Y5PAGR
MSC1214Y5PAGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
1500
250
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
CU NIPDAU Level-3-235C-168 HR
1500
250
1500
250
1500
250
1500
250
1500
250
1500
250
2000
250
1500
250
1500
250
1500
250
1500
250
1500
250
1500
250
1500
250
2000
250
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jul-2005
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Following are URLs where you can obtain information on other Texas Instruments products and application
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Applications
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Amplifiers
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www.ti.com/audio
Data Converters
dataconverter.ti.com
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dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
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Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
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