LV595A [TI]
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS; 8位移位寄存器具有三态输出寄存器型号: | LV595A |
厂家: | TEXAS INSTRUMENTS |
描述: | 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS |
文件: | 总22页 (文件大小:755K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢂ ꢇꢈ ꢀꢁꢉ ꢃꢄꢅ ꢂꢆ ꢂꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏꢍ ꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ ꢍꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖ ꢗꢎ ꢘꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
D
D
D
D
D
D
2-V to 5.5-V V
Operation
D
I
Supports Partial-Power-Down Mode
CC
off
Operation
Max t of 7.1 ns at 5 V
pd
D
Shift Register Has Direct Clear
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
A
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
A
Support Mixed-Mode Voltage Operation on
All Ports
− 1000-V Charged-Device Model (C101)
8-Bit Serial-In, Parallel-Out Shift
SN74LV595A . . . RGY PACKAGE
(TOP VIEW)
SN54LV595A . . . FK PACKAGE
(TOP VIEW)
SN54LV595A . . . J OR W PACKAGE
SN74LV595A . . . D, DB, NS,
OR PW PACKAGE
(TOP VIEW)
1
16
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
3
2
1 20 19
18
B
SER
OE
Q
4
5
6
7
8
Q
Q
Q
15
14
13
12
11
10
2
3
4
5
6
7
D
Q
SER
OE
RCLK
SRCLK
SRCLR
C
D
A
Q
C
D
A
Q
17
16
E
Q
SER
OE
NC
NC
E
Q
E
15 RCLK
14
9 10 11 12 13
Q
F
Q
G
Q
Q
F
Q
12 RCLK
F
SRCLK
G
11
10
9
Q
SRCLK
SRCLR
G
Q
H
Q
H
8
9
GND
Q
H′
NC − No internal connection
description/ordering information
The ’LV595A devices are 8-bit shift registers designed for 2-V to 5.5-V V
operation.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − D
Reel of 1000
Tube of 40
SN74LV595ARGYR
SN74LV595AD
LV595A
LV595A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV595ADR
SN74LV595ANSR
SN74LV595ADBR
SN74LV595APW
SN74LV595APWR
SN74LV595APWT
SNJ54LV595AJ
SOP − NS
74LV595A
LV595A
−40°C to 85°C
SSOP − DB
Reel of 2000
Reel of 250
Tube of 25
TSSOP − PW
LV595A
CDIP − J
CFP − W
LCCC − FK
SNJ54LV595AJ
SNJ54LV595AW
SNJ54LV595AFK
−55°C to 125°C
Tube of 150
Tube of 55
SNJ54LV595AW
SNJ54LV595AFK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢗ ꢁ ꢄꢒꢀꢀ ꢖ ꢎꢏ ꢒꢑꢔ ꢍꢀ ꢒ ꢁ ꢖꢎꢒꢙ ꢚꢛ ꢜꢝ ꢞꢟꢠ ꢡꢢꢣ ꢤꢚ ꢠꢟ ꢤꢚꢥ ꢜꢤꢝ ꢘꢑ ꢖ ꢙ ꢗ ꢦꢎ ꢍꢖ ꢁ
ꢚ
ꢙ
ꢇ
ꢎ
ꢇ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢡ
ꢨ
ꢨ
ꢣ
ꢤ
ꢚ
ꢥ
ꢝ
ꢟ
ꢧ
ꢩ
ꢡ
ꢪ
ꢫ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢞ
ꢥ
ꢣ
ꢬ
ꢘ
ꢨ
ꢟ
ꢞ
ꢡ
ꢠ
ꢚ
ꢝ
ꢠ
ꢟ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢚ
ꢟ
ꢝ
ꢩ
ꢣ
ꢠ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢩ
ꢣ
ꢨ
ꢚ
ꢛ
ꢣ
ꢚ
ꢣ
ꢨ
ꢢ
ꢝ
ꢟ
ꢧ
ꢎ
ꢣ
ꢭ
ꢥ
ꢝ
ꢍ
ꢤ
ꢝ
ꢚ
ꢨ
ꢡ
ꢢ
ꢣ
ꢤ
ꢚ
ꢝ
ꢝ
ꢚ
ꢥ
ꢤ
ꢞ
ꢥ
ꢨ
ꢞ
ꢮ
ꢥ
ꢨ
ꢨ
ꢥ
ꢤ
ꢚ
ꢯ
ꢬ
ꢘ
ꢨ
ꢟ
ꢞ
ꢡ
ꢠ
ꢚ
ꢜ
ꢟ
ꢤ
ꢩꢥ ꢨ ꢥ ꢢ ꢣ ꢚ ꢣ ꢨ ꢝ ꢬ
ꢩ
ꢨ
ꢟ
ꢠ
ꢣ
ꢝ
ꢝ
ꢜ
ꢤ
ꢰ
ꢞ
ꢟ
ꢣ
ꢝ
ꢤ
ꢟ
ꢚ
ꢤ
ꢣ
ꢠ
ꢣ
ꢝ
ꢝ
ꢥ
ꢨ
ꢜ
ꢫ
ꢯ
ꢜ
ꢤ
ꢠ
ꢫ
ꢡ
ꢞ
ꢣ
ꢚ
ꢣ
ꢝ
ꢚ
ꢜ
ꢤ
ꢰ
ꢟ
ꢧ
ꢥ
ꢫ
ꢫ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢂꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢂ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖꢗꢎ ꢘ ꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.
The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage
register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output
for cascading. When the output-enable (OE) input is high, all outputs except Q are in the high-impedance
H′
state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both
clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK
OE
H
X
X
X
X
X
X
X
X
L
X
X
X
Outputs Q −Q are disabled.
A H
L
Outputs Q −Q are enabled.
A H
X
Shift register is cleared.
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
H
X
↑
H
X
X
X
X
X
↑
Shift-register data is stored in the storage register.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢂ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂꢆ ꢂꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏ ꢍꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ
ꢍ
ꢎ
ꢏ
ꢕ
ꢋ
ꢀ
ꢎ
ꢇ
ꢎ
ꢒ
ꢖ
ꢗ
ꢎ
ꢘ
ꢗ
ꢎ
ꢑ
ꢒ
ꢓ
ꢍꢀ
ꢎ
ꢒ
ꢑ
ꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
logic diagram (positive logic)
13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
SER
Q
Q
1D
C1
R
3D
C3
15
Q
Q
Q
Q
A
B
2D
C2
3D
C3
1
2
3
R
2D
C2
R
3D
C3
Q
Q
Q
Q
Q
Q
C
D
2D
C2
3D
C3
R
2D
C2
R
3D
C3
Q
Q
Q
4
5
6
Q
Q
Q
Q
Q
Q
E
F
2D
C2
R
3D
C3
2D
C2
3D
C3
G
R
2D
C2
R
3D
C3
Q
7
9
Q
Q
Q
H
H′
Pin numbers shown are for the D, DB, J, NS, PW, RGY, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢂꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢂ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖꢗꢎ ꢘ ꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H′
NOTE:
implies that the output is in 3-State mode.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢂ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂꢆ ꢂꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏ ꢍꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ ꢍꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖ ꢗꢎ ꢘꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range applied in the high or low state, V (see Notes 1 and 2) . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢂꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢂ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖꢗꢎ ꢘ ꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV595A
SN74LV595A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
V
V
V
V
V
V
V
= 2 V
1.5
1.5
CC
CC
CC
CC
CC
CC
CC
CC
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
V
V
V
× 0.3
× 0.3
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
V
V
Input voltage
0
0
0
5.5
0
0
0
5.5
I
High or low state
3-state
V
V
CC
5.5
CC
5.5
Output voltage
V
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−8
−16
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−8
mA
−16
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
8
8
mA
16
16
200
100
20
85
200
100
20
∆t/∆v Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
ꢘ
ꢑ
ꢖ
ꢙ
ꢗ
ꢦ
ꢎ
ꢘ
ꢑ
ꢒ
ꢅ
ꢍ
ꢒ
ꢔ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢠ
ꢞ ꢣ ꢝ ꢜ ꢰ ꢤ ꢩꢛ ꢥ ꢝ ꢣ ꢟꢧ ꢞꢣ ꢱ ꢣ ꢫ ꢟꢩ ꢢꢣ ꢤ ꢚꢬ ꢦ ꢛꢥ ꢨꢥ ꢠꢚ ꢣꢨ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢨ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢨ
ꢝ
ꢩ
ꢣ
ꢠ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢨ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢰ
ꢤ
ꢰ
ꢟ
ꢥ
ꢫ
ꢝ
ꢬ
ꢎ
ꢣ
ꢭ
ꢥ
ꢝ
ꢍ
ꢤ
ꢝ
ꢚ
ꢨ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛ ꢥ ꢤ ꢰꢣ ꢟꢨ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡ ꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢩꢨ ꢟ ꢞꢡꢠ ꢚꢝ ꢮ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢬ
ꢚ
ꢝ
ꢨ
ꢣ
ꢝ
ꢣ
ꢨ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢚ
ꢟ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢂ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂꢆ ꢂꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏ ꢍꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ ꢍꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖ ꢗꢎ ꢘꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV595A
SN74LV595A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
I
I
I
I
= −50 µA
2 V to 5.5 V
2.3 V
V
CC
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
= −2 mA
= −6 mA
= −8 mA
= −12 mA
= −16 mA
= 50 µA
= 2 mA
Q
2.48
2.48
H′
V
3 V
V
OH
Q −Q
A
2.48
3.8
2.48
3.8
H
Q
H′
4.5 V
Q −Q
A
3.8
3.8
H
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.44
0.55
0.55
1
0.1
0.4
0.44
0.44
0.55
0.55
1
Q
= 6 mA
H′
V
OL
3 V
V
Q −Q
A
= 8 mA
H
Q
= 12 mA
= 16 mA
H′
4.5 V
Q −Q
A
H
I
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
5.5 V
0
µA
µA
µA
µA
pF
I
I
V
= V
or GND,
or GND,
Q −Q
H
5
5
OZ
CC
off
O
CC
A
V = V
CC
I
O
= 0
20
20
I
V or V = 0 to 5.5 V
5
5
I
O
C
V = V
or GND
3.3 V
3.5
3.5
i
I
CC
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV595A SN74LV595A
A
UNIT
MIN
7
MAX
MIN
7.5
7.5
6.5
5.5
9
MAX
MIN
7.5
7.5
6.5
5.5
9
MAX
SRCLK high or low
RCLK high or low
SRCLR low
7
t
w
Pulse duration
ns
6
SER before SRCLK↑
SRCLK↑ before RCLK↑
5.5
8
†
Setup time
Hold time
t
t
ns
ns
su
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
SER after SRCLK↑
8.5
4
9.5
4
9.5
4
1.5
1.5
1.5
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
ꢘ
ꢑ
ꢖ
ꢙ
ꢗ
ꢦ
ꢎ
ꢘ
ꢑ
ꢒ
ꢅ
ꢍ
ꢒ
ꢔ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢞꢣ ꢝ ꢜ ꢰꢤ ꢩꢛ ꢥ ꢝ ꢣ ꢟꢧ ꢞꢣ ꢱ ꢣ ꢫꢟ ꢩꢢꢣ ꢤꢚꢬ ꢦ ꢛꢥ ꢨꢥ ꢠꢚ ꢣꢨ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢨ
ꢠ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢨ
ꢝ
ꢩ
ꢣ
ꢠ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢨ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢰ
ꢤ
ꢰ
ꢟ
ꢥ
ꢫ
ꢝ
ꢬ
ꢎ
ꢣ
ꢭ
ꢥ
ꢝ
ꢍ
ꢤ
ꢝ
ꢚ
ꢨ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛꢥ ꢤ ꢰꢣ ꢟꢨ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢩꢨ ꢟꢞ ꢡꢠꢚ ꢝ ꢮ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢬ
ꢚ
ꢝ
ꢨ
ꢣ
ꢝ
ꢣ
ꢨ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢚ
ꢟ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢂꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢂ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖꢗꢎ ꢘ ꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV595A SN74LV595A
A
UNIT
MIN
5.5
5.5
5
MAX
MIN
5.5
5.5
5
MAX
MIN
5.5
5.5
5
MAX
SRCLK high or low
RCLK high or low
SRCLR low
t
w
Pulse duration
ns
SER before SRCLK↑
SRCLK↑ before RCLK↑
3.5
8
3.5
8.5
9
3.5
8.5
9
†
Setup time
Hold time
t
t
ns
ns
su
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
SER after SRCLK↑
8
3
3
3
1.5
1.5
1.5
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV595A SN74LV595A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
SRCLK high or low
RCLK high or low
SRCLR low
5
5
5
t
Pulse duration
ns
w
5.2
3
5.2
3
5.2
3
SER before SRCLK↑
SRCLK↑ before RCLK↑
†
5
5
5
Setup time
Hold time
t
t
ns
ns
su
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
SER after SRCLK↑
5
5
5
2.5
2
2.5
2
2.5
2
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
ꢘ
ꢑ
ꢖ
ꢙ
ꢗ
ꢦ
ꢎ
ꢘ
ꢑ
ꢒ
ꢅ
ꢍ
ꢒ
ꢔ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢠ
ꢞ ꢣ ꢝ ꢜ ꢰ ꢤ ꢩꢛ ꢥ ꢝ ꢣ ꢟꢧ ꢞꢣ ꢱ ꢣ ꢫ ꢟꢩ ꢢꢣ ꢤ ꢚꢬ ꢦ ꢛꢥ ꢨꢥ ꢠꢚ ꢣꢨ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢨ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢨ
ꢝ
ꢩ
ꢣ
ꢠ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢨ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢰ
ꢤ
ꢰ
ꢟ
ꢥ
ꢫ
ꢝ
ꢬ
ꢎ
ꢣ
ꢭ
ꢥ
ꢝ
ꢍ
ꢤ
ꢝ
ꢚ
ꢨ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛ ꢥ ꢤ ꢰꢣ ꢟꢨ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡ ꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢩꢨ ꢟ ꢞꢡꢠ ꢚꢝ ꢮ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢬ
ꢚ
ꢝ
ꢨ
ꢣ
ꢝ
ꢣ
ꢨ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢚ
ꢟ
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢂ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂꢆ ꢂꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏ ꢍꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ ꢍꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖ ꢗꢎ ꢘꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
80*
SN54LV595A SN74LV595A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
65*
60
MAX
MIN
45*
40
MAX
MIN
45
40
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
70
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
8.4* 14.2*
8.4* 14.2*
9.4* 19.6*
9.4* 19.6*
8.7* 14.6*
8.2* 13.9*
10.9* 18.1*
8.3* 13.7*
9.2* 15.2*
1* 15.8*
1* 15.8*
1* 22.2*
1* 22.2*
1* 16.3*
15.8
15.8
22.2
22.2
16.3
15
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
RCLK
Q −Q
A
H
1
1
SRCLK
SRCLR
Q
H′
1
1
Q
C
= 15 pF
ns
H′
L
1*
15*
1
OE
OE
Q −Q
A
H
H
H
1* 20.3*
1* 15.6*
1* 16.7*
1
20.3
15.6
16.7
19.3
19.3
25.5
25.5
21.1
18.3
23
1
Q −Q
A
1
11.2
11.2
13.1
13.1
12.4
10.8
13.4
12.2
14
17.2
17.2
22.5
22.5
18.8
17
1
1
1
1
1
1
1
1
1
19.3
19.3
25.5
25.5
21.1
18.3
23
1
RCLK
Q −Q
A
1
1
SRCLK
SRCLR
Q
H′
1
C
= 50 pF
1
ns
Q
L
H′
1
OE
OE
Q −Q
A
H
21
1
18.3
20.9
19.5
22.6
1
19.5
22.6
Q −Q
A
H
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢘ
ꢑ
ꢖ
ꢙ
ꢗ
ꢦ
ꢎ
ꢘ
ꢑ
ꢒ
ꢅ
ꢍ
ꢒ
ꢔ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢞꢣ ꢝ ꢜ ꢰꢤ ꢩꢛ ꢥ ꢝ ꢣ ꢟꢧ ꢞꢣ ꢱ ꢣ ꢫꢟ ꢩꢢꢣ ꢤꢚꢬ ꢦ ꢛꢥ ꢨꢥ ꢠꢚ ꢣꢨ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢨ
ꢠ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢨ
ꢝ
ꢩ
ꢣ
ꢠ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢨ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢰ
ꢤ
ꢰ
ꢟ
ꢥ
ꢫ
ꢝ
ꢬ
ꢎ
ꢣ
ꢭ
ꢥ
ꢝ
ꢍ
ꢤ
ꢝ
ꢚ
ꢨ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛꢥ ꢤ ꢰꢣ ꢟꢨ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢩꢨ ꢟꢞ ꢡꢠꢚ ꢝ ꢮ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢬ
ꢚ
ꢝ
ꢨ
ꢣ
ꢝ
ꢣ
ꢨ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢚ
ꢟ
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢂꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢂ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖꢗꢎ ꢘ ꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV595A SN74LV595A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
80*
55
MAX
MIN
70*
50
MAX
MIN
70
50
1
MAX
C
C
= 15 pF
= 50 pF
120*
105
L
L
f
MHz
max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
6* 11.9*
6* 11.9*
1* 13.5*
1* 13.5*
13.5
13.5
15
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
RCLK
Q −Q
A
H
1
6.6*
6.6*
13*
13*
1*
1*
15*
15*
1
SRCLK
SRCLR
Q
H′
1
15
6.2* 12.8*
6* 11.5*
1* 13.7*
1* 13.5*
1* 13.5*
1* 15.2*
1* 15.2*
1
13.7
13.5
13.5
15.2
15.2
17
Q
C
= 15 pF
ns
H′
L
1
OE
OE
Q −Q
A
H
H
H
7.8* 11.5*
6.1* 14.7*
6.3* 14.7*
1
1
Q −Q
A
1
7.9
7.9
9.2
9.2
9
15.4
15.4
16.5
16.5
16.3
15
1
1
1
1
1
1
1
1
1
17
17
1
RCLK
Q −Q
A
1
17
18.5
18.5
17.2
17
1
18.5
18.5
17.2
17
SRCLK
SRCLR
Q
H′
1
C
= 50 pF
1
ns
Q
L
H′
7.8
9.6
8.1
9.3
1
OE
OE
Q −Q
A
H
15
17
1
17
15.7
15.7
16.2
16.2
1
16.2
16.2
Q −Q
A
H
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢘ
ꢑ
ꢖ
ꢙ
ꢗ
ꢦ
ꢎ
ꢘ
ꢑ
ꢒ
ꢅ
ꢍ
ꢒ
ꢔ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢠ
ꢞ ꢣ ꢝ ꢜ ꢰ ꢤ ꢩꢛ ꢥ ꢝ ꢣ ꢟꢧ ꢞꢣ ꢱ ꢣ ꢫ ꢟꢩ ꢢꢣ ꢤ ꢚꢬ ꢦ ꢛꢥ ꢨꢥ ꢠꢚ ꢣꢨ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢨ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢨ
ꢝ
ꢩ
ꢣ
ꢠ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢨ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢰ
ꢤ
ꢰ
ꢟ
ꢥ
ꢫ
ꢝ
ꢬ
ꢎ
ꢣ
ꢭ
ꢥ
ꢝ
ꢍ
ꢤ
ꢝ
ꢚ
ꢨ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛ ꢥ ꢤ ꢰꢣ ꢟꢨ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡ ꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢩꢨ ꢟ ꢞꢡꢠ ꢚꢝ ꢮ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢬ
ꢚ
ꢝ
ꢨ
ꢣ
ꢝ
ꢣ
ꢨ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢚ
ꢟ
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢂ ꢆ ꢂ ꢇꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂꢆ ꢂꢇ
ꢊ ꢋꢌꢍ ꢎ ꢀꢏ ꢍꢐ ꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
ꢔ ꢍꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖ ꢗꢎ ꢘꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑ ꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
170*
140
4.3*
4.3*
4.5*
4.5*
4.5*
4.3*
5.4*
2.4*
2.7*
5.6
SN54LV595A SN74LV595A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
135*
120
MAX
MIN
115*
95
1*
1*
1*
1*
1*
1*
1*
1*
1*
1
MAX
MIN
115
95
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
7.4*
7.4*
8.2*
8.2*
8*
8.5*
8.5*
9.4*
9.4*
9.1*
10*
10*
7.1*
7.2*
10.5
10.5
11.4
11.4
11.1
12
8.5
8.5
9.4
9.4
9.1
10
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
RCLK
Q −Q
A
H
1
1
SRCLK
SRCLR
Q
H′
1
1
Q
C
= 15 pF
ns
H′
L
8.6*
8.6*
6*
1
OE
OE
Q −Q
A
H
H
H
1
10
1
7.1
7.2
10.5
10.5
11.4
11.4
11.1
12
Q −Q
A
5.1*
9.4
1
1
RCLK
Q −Q
A
5.6
9.4
1
1
6.4
10.2
10.2
10
1
1
SRCLK
SRCLR
Q
H′
6.4
1
1
C
= 50 pF
6.4
1
1
ns
Q
L
H′
5.7
10.6
10.6
10.3
10.3
1
1
OE
OE
Q −Q
A
H
6.8
1
12
1
12
3.5
1
11
1
11
Q −Q
A
H
3.4
1
11
1
11
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 6)
CC
L
A
SN74LV595A
PARAMETER
UNIT
MIN
TYP
0.3
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.2
2.8
OL
OH
2.31
0.99
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
111
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
114
ꢘ
ꢑ
ꢖ
ꢙ
ꢗ
ꢦ
ꢎ
ꢘ
ꢑ
ꢒ
ꢅ
ꢍ
ꢒ
ꢔ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢞꢣ ꢝ ꢜ ꢰꢤ ꢩꢛ ꢥ ꢝ ꢣ ꢟꢧ ꢞꢣ ꢱ ꢣ ꢫꢟ ꢩꢢꢣ ꢤꢚꢬ ꢦ ꢛꢥ ꢨꢥ ꢠꢚ ꢣꢨ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢨ
ꢠ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢨ
ꢝ
ꢩ
ꢣ
ꢠ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢨ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢰ
ꢤ
ꢰ
ꢟ
ꢥ
ꢫ
ꢝ
ꢬ
ꢎ
ꢣ
ꢭ
ꢥ
ꢝ
ꢍ
ꢤ
ꢝ
ꢚ
ꢨ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛꢥ ꢤ ꢰꢣ ꢟꢨ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢩꢨ ꢟꢞ ꢡꢠꢚ ꢝ ꢮ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢬ
ꢚ
ꢝ
ꢨ
ꢣ
ꢝ
ꢣ
ꢨ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢚ
ꢟ
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢆ ꢂꢇ ꢈ ꢀꢁ ꢉꢃ ꢄꢅ ꢂ ꢆꢂ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢀꢏ ꢍ ꢐ ꢎ ꢑ ꢒ ꢓꢍ ꢀ ꢎꢒ ꢑꢀ
ꢔꢍ ꢎ ꢏ ꢕ ꢋꢀꢎꢇꢎ ꢒ ꢖꢗꢎ ꢘ ꢗꢎ ꢑꢒ ꢓ ꢍꢀ ꢎꢒ ꢑꢀ
SCLS414N − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
CC
CC
0 V
0 V
t
t
t
t
t
PLH
PHL
PZL
PLZ
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
V
+ 0.3 V
S1 at V
(see Note B)
OL
CC
V
OL
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN74LV595AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV595ADBR
SN74LV595ADBRE4
SN74LV595ADE4
SSOP
SSOP
SOIC
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV595ADR
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV595ADRE4
SN74LV595ANSR
SN74LV595ANSRE4
SN74LV595APWR
SN74LV595APWRE4
SN74LV595APWRG4
SN74LV595APWT
SN74LV595APWTE4
SN74LV595APWTG4
SN74LV595ARGYR
SN74LV595ARGYRG4
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
PW
PW
PW
PW
PW
PW
RGY
RGY
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to
discontinue any product or service without notice. Customers should obtain the latest relevant information
before placing orders and should verify that such information is current and complete. All products are sold
subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent
TI deems necessary to support this warranty. Except where mandated by government requirements, testing
of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible
for their products and applications using TI components. To minimize the risks associated with customer
products and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent
right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine,
or process in which TI products or services are used. Information published by TI regarding third-party
products or services does not constitute a license from TI to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or
other intellectual property of the third party, or a license from TI under the patents or other intellectual
property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not
responsible or liable for such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service
and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Amplifiers
Data Converters
DSP
Interface
Applications
Audio
Automotive
Broadband
Digital Control
Military
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Logic
Power Mgmt
Microcontrollers
Low Power Wireless
power.ti.com
microcontroller.ti.com
www.ti.com/lpw
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
相关型号:
LV63M10K0BP343550
Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 63V, 20% +Tol, 20% -Tol, 10000uF, Through Hole Mount, ROHS COMPLIANT
YAGEO
LV63M1200BPF-2030
Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 63V, 20% +Tol, 20% -Tol, 1200uF, Through Hole Mount, ROHS COMPLIANT
YAGEO
LV63M1500BP4-2035
Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 63V, 20% +Tol, 20% -Tol, 1500uF, Through Hole Mount, ROHS COMPLIANT
YAGEO
LV63M1500BPF42035
Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 63V, 20% +Tol, 20% -Tol, 1500uF, Through Hole Mount, ROHS COMPLIANT
YAGEO
LV63M1500BPF42230
Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 63V, 20% +Tol, 20% -Tol, 1500uF, Through Hole Mount, ROHS COMPLIANT
YAGEO
©2020 ICPDF网 联系我们和版权申明