LP8866QDCPRQ1_技术文档

LP8866-Q1

ZHCSKL3B –DECEMBER 2019 –REVISED OCTOBER 2020

具有六个200mA 通道的LP8866-Q1 汽车显示LED 背光驱动器

1 特性

2 应用

• 符合面向汽车应用的AEC-Q100 标准：

• 为以下应用提供背光：

– 器件温度等级1：

– 汽车信息娱乐系统

– 汽车仪表组

– 智能车镜

–40°C 至+125°C，T_A

– 器件HBM ESD 分类等级2

– 器件CDM ESD 分类等级C4B

• 输入电压工作范围：3V 至48V

• 六路高精度电流阱

– 抬头显示屏(HUD)

3 说明

LP8866-Q1 是一款具有升压控制器的汽车类高效 LED

驱动器。六路高精度电流阱支持根据使用的通道数自动

调整相移。可通过 I²C 接口或 PWM 输入对 LED 亮度

进行全局控制。

– 各电流阱直流电流高达200mA

– 电流匹配度为1%（典型值）

– 使用152Hz LED 输出PWM 频率时，调光比为

32000:1

– 使用I2C 或PWM 输入时，最高16 位LED 调

光分辨率

– 可配置8 个LED 灯串

升压控制器具有基于 LED 电流阱余量电压的自适应输

出电压控制。该特性可在所有条件下将升压电压调节到

能够满足需要的最低水平，从而更大限度降低功耗。凭

借宽范围可调频率，LP8866-Q1 可避免 AM 无线电频

段的干扰。

• 自动移相PWM 调光

• 12 位模拟调光

• 最高48V V_OUT升压或SEPIC 直流/直流控制器

LP8866-Q1 支持内置混合 PWM 调光和模拟电流调

光，从而可降低 EMI、延长 LED 使用寿命并提高总光

学效率。

– 开关频率为100kHz 至2.2MHz

– 升压扩频功能可降低EMI

– 升压同步输入，可通过外部时钟设置升压开关频

率

器件信息

器件型号⁽¹⁾

LP8866-Q1

封装尺寸（标称值）

9.70mm × 4.40mm

5mm × 5mm

封装

HTSSOP (38)

QFN (32)⁽²⁾

– 禁用升压时，输出电压自动放电

• 多种故障诊断功能

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

(2) 产品预览。

L

95

90

85

R_ISENSE

V_IN

V_OUT

R_SD

C_IN

C_OUT

R_G

SD

R_FB1

R_FB3

VSENSE_N

VSENSE_P

GD

PGND

ISNS

R_UVLO1

R_UVLO2

R_FB2

R_SENSE

UVLO

ISNSGND

FB

VDD

LP8866(S)-Q1

VDD

C1N

C_VDD

DISCHARGE

LED_GND

C_2x

C1P

C_PUMP

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

CPUMP

80

V_OUT= 29 V

V_OUT= 36 V

V_OUT= 42 V

V_OUT= 46 V

SGND

EN

HOST

I2C

PWM

INT

R_{BST_FSET}

R_{PWM_FSET}

R_{LED_SET}

BST_FSET

PWM_FSET

75

SDA

SCL

0

10

20

30

40

50

60

Brightness (%)

70

80 90 100

LED_SET

ISET

VDD

BST_SYNC

MODE

D007

R_ISET

R_MODE

系统效率

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNVSBA5

LP8866-Q1

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ZHCSKL3B –DECEMBER 2019 –REVISED OCTOBER 2020

Table of Contents

7.5 Programming............................................................ 40

7.6 Register Maps...........................................................43

8 Application and Implementation..................................58

8.1 Application Information............................................. 58

8.2 Typical Applications.................................................. 58

9 Power Supply Recommendations................................71

10 Layout...........................................................................72

10.1 Layout Guidelines................................................... 72

10.2 Layout Example...................................................... 73

11 Device and Documentation Support..........................75

11.1 Device Support........................................................75

11.2 接收文档更新通知................................................... 75

11.3 支持资源..................................................................75

11.4 Trademarks............................................................. 75

11.5 静电放电警告...........................................................75

11.6 术语表..................................................................... 75

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings ....................................... 6

6.2 ESD Ratings .............................................................. 6

6.3 Recommended Operating Conditions ........................6

6.4 Thermal Information ...................................................7

6.5 Electrical Characteristics ............................................7

6.6 Logic Interface Characteristics .................................10

6.7 Timing Requirements for I2C Interface .................... 10

6.8 Typical Characteristics.............................................. 11

7 Detailed Description......................................................12

7.1 Overview...................................................................12

7.2 Functional Block Diagram.........................................13

7.3 Feature Description...................................................13

7.4 Device Functional Modes..........................................39

Information.................................................................... 76

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (August 2020) to Revision B (October 2020)

Page

• 向“器件信息”表添加了QFN 封装选项............................................................................................................ 1

• Added QFN package pinout drawing and Pin Functions table........................................................................... 3

Changes from Revision * (December 2019) to Revision A (August 2020)

Page

• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1

2

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5 Pin Configuration and Functions

1

2

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

SD

VDD

EN

VSENSE_N

3

VSENSE_P

UVLO

C1N

C1P

4

5

DGND

CPUMP

6

MODE

CPUMP

GD

7

BST_FSET

PWM_FSET

LED_SET

SGND

PGND

8

9

Thermal Pad

(LED_GND)

ISNS

ISNSGND

ISET

10

11

12

13

14

PWM

BST_SYNC

FB

SCL

NC

SDA

INT

DISCHARGE

15

16

17

NC

OUT6

OUT5

OUT1

OUT2

OUT3

18

19

OUT4

图5-1. DCP Package 38-Pin HTSSOP Top View

32 31 30 29 28 27 26 25

1

2

3

4

5

6

24

23

22

OUT6

OUT5

C1N

EN

OUT4

VDD

LED_GND

OUT3

21 SD

DAP

20 VSENSE_N

19 VSENSE_P

OUT2

18

17

OUT1

UVLO

MODE

7

8

INT

9

10 11 12 13 14 15 16

Product preview

图5-2. RHB Package 32-PIN QFN Top View

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表5-1. HTTSOP Pin Functions

NAME

TYPE

DESCRIPTION

NO.

Power supply input for internal analog and digital circuit. Connect a 10-uF capacitor between

the VDD pin to GND.

1

VDD

Power

2

3

4

EN

Analog

Enable input.

C1N

C1P

Negative input for charge pump flying capacitor. If feature not used leave this pin floating.

Positive input for charge pump flying capacitor. If feature not used leave this pin floating.

Charge pump output pin. Connect to VDD if charge pump is not used. A 4.7 µF decoupling

capacitor is recommended on CPUMP pin.

5

CPUMP

Power

6

CPUMP

GD

Power

Analog

GND

Charge pump output pin. Always connects with pin 5.

Gate driver output for external N-FET.

7

8

PGND

ISNS

Power ground.

9

GND

Power ground.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

Analog

GND

Boost current sense pin.

ISNSGND

ISET

Current sense resistor GND.

Analog

N/A

LED full-scale current setup through external resistor.

Boost feedback input.

FB

NC

No connect - Leave floating.

DISCHARGE

NC

Analog

N/A

Boost output voltage discharge pin. Connect to Boost output.

No connect - Leave floating.

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

NC

Analog

N/A

LED current sink output. If unused tie to ground..

LED current sink output. If unused tie to ground.

No connect - Leave floating.

INT

Analog

Device fault interrupt output, open drain. A 10-kΩpullup resistor is recommended.

SDA for I2C interface. A 10-kΩpullup resistor is recommended.

SCL for I2C interface. A 10-kΩpullup resistor is recommended.

SDA

SCL

Input for synchronizing boost. When synchronization is not used, connect this pin to ground

to disable spread spectrum or to VDD to enable spread spectrum.

27

BST_SYNC

Analog

28

29

30

31

32

33

34

35

36

PWM

SGND

Analog

GND

PWM input for brightness control. Tie to GND if unused.

Signal ground.

LED_SET

PWM_FSET

BST_FSET

MODE

Analog

GND

LED string configuration through external resistor. Do not leave floating.

LED dimming frequency setup through external resistor. Do not leave floating.

Boost switching frequency setup through external resistor. Do not leave floating.

Dimming mode setup through external resistor. Do not leave floating.

Digital ground.

DGND

UVLO

Analog

Input voltage sense for programming input UVLO threshold through external resistor to VIN.

Pin for input voltage detection for OVP protection and positive input for input current sense.

VSENSE_P

Negative input for input current sense. If input current sense is not used, please tie to

VSENSE_P pin.

37

VSENSE_N

Analog

38

SD

Analog

GND

Power line FET control. Open Drain output. If unused, leave this pin floating.

LED ground connection.

DAP

LED_GND

4

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表5-2. QFN Pin Functions

TYPE

DESCRIPTION

NO.

1

NAME

OUT6

OUT5

OUT4

LED_GND

OUT3

OUT2

OUT1

INT

Analog

GND

LED current sink output. If unused tie to ground..

2

LED current sink output. If unused tie to ground..

LED current sink output. If unused tie to ground.

LED ground connection.

3

4

5

Analog

LED current sink output. If unused tie to ground.

Device fault interrupt output, open drain. A 10-kΩpullup resistor is recommended.

SDA for I2C interface. A 10-kΩpullup resistor is recommended.

SCL for I2C interface. A 10-kΩpullup resistor is recommended.

6

7

8

9

SDA

10

SCL

Input for synchronizing boost. When synchronization is not used, connect this pin to ground

to disable spread spectrum or to VDD to enable spread spectrum.

11

BST_SYNC

Analog

12

13

14

15

16

17

18

19

PWM

SGND

Analog

GND

PWM input for brightness control. Tie to GND if unused.

Signal ground.

LED_SET

PWM_FSET

BST_FSET

MODE

Analog

LED string configuration through external resistor. Do not leave floating.

LED dimming frequency setup through external resistor. Do not leave floating.

Boost switching frequency setup through external resistor. Do not leave floating.

Dimming mode setup through external resistor. Do not leave floating.

Input voltage sense for programming input UVLO threshold through external resistor to VIN.

Pin for input voltage detection for OVP protection and positive input for input current sense.

UVLO

VSENSE_P

Negative input for input current sense. If input current sense is not used, please tie to

VSENSE_P pin.

20

21

22

VSENSE_N

SD

Analog

Power

Power line FET control. Open Drain output. If unused, leave this pin floating.

Power supply input for internal analog and digital circuit. Connect a 10-uF capacitor between

the VDD pin to GND

VDD

23

24

25

EN

Analog

Enable input.

C1N

C1P

Negative input for charge pump flying capacitor. If feature not used leave this pin floating.

Positive input for charge pump flying capacitor. If feature not used leave this pin floating.

Charge pump output pin. Connect to VDD if charge pump is not used. A 4.7-µF decoupling

capacitor is recommended on CPUMP pin.

26

CPUMP

Power

27

GD

PGND

ISNS

Analog

GND

Gate driver output for external N-FET.

Power ground.

28

29

Analog

GND

Boost current sense pin.

30

ISNSGND

ISET

Current sense resistor GND.

LED full-scale current setup through external resistor.

Boost feedback input.

31

Analog

GND

32

FB

DAP

LED_GND

LED ground connection.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

-0.3

MAX

UNIT

VSENSE

_P + 0.3

Voltage on pins

VSENSE_N, SD, UVLO

V

VSENSE_P, FB, DISCHARGE, OUT1 to OUT6

52

6

–0.3

C1N, C1P, VDD, EN, ISNS, ISNS_GND, INT, MODE, PWM_FSET, BST_FSET,

LED_SET, ISET, GD and CPUMP

VDD +

0.3

PWM, BST_SYNC, SDA, SCL

Continuous power dissipation⁽³⁾

-0.3

V

Internally

Limited

W

Ambient temperature, TA⁽⁴⁾

Junction temperature, TJ⁽⁴⁾

Lead temperature (soldering)

Storage temperature, Tstg

125

150

260

150

–40

°C

Thermal

–65

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltages are with respect to the potential at the GND pins.

(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 165°C (typical)

and disengages at T_J= 150°C (typical).

(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature

may have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature

(T_J-MAX= 150°C), the power dissipation of the device in the application (P), the junction-to-board thermal resistance and the

temperature difference between the system board and the ambient (Δt_BA), which is given by the following equation: T_A-MAX= T_J-MAX

(Θ_JB× P) - Δt_BA

–

6.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Electrostatic

V_(ESD)

Corner pins (1, 19, 20 and 38)

Other pins

V

Charged device model (CDM), per AEC

Q100-011

discharge

±500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

NOM

MAX

48

UNIT

VSENSE_P, VSENSE_N, SD, UVLO

FB, OUT1 to OUT6

3

12

0

48

ISNS, ISNSGND

0

5.5

125

Voltage on

pins

V

EN, PWM, INT, SDA, SCL, BST_SYNC

VDD

3.3

3.3/5

5

3

C1N, C1P, CPUMP,GD

Ambient temperature, T_A

0

Thermal

°C

–40

(1) All voltages are with respect to the potential at the GND pins.

6

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6.4 Thermal Information

Device

THERMAL METRIC⁽¹⁾

HTTSOP

38-PIN

32.4

19.5

8.8

UNIT

R_θJA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJC(top)

R_θJB

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

Ψ_JT

8.9

Ψ_JB

R_θJC(bot)

2.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

6.5 Electrical Characteristics

Limits apply over the full operation temperature range –40°C ≤T_A≤+125°C , unless otherwise speicified_.V_IN= 12 V_,VDD

= 3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

General Electrical Characteristics

I_Q

Shutdown mode current, VDD pin

EN = L

1

5

µA

FSW = 303kHz, PWM = H, BOOST-FET

IPD25N06S4L-30, Charge Pump

Disabled

I_Q

Active mode current, VDD pin⁽¹⁾

15

65

mA

FSW = 2200kHz, PWM = H, BOOST-FET

IPD25N06S4L-30, Charge Pump

Disabled

I_Q

40

75

mA

FSW = 303kHz, PWM = H, BOOST-FET

IPD25N06S4L-30, Charge Pump Enabled

I_Q

Active mode current, VDD pin⁽¹⁾

20

65

91

mA

FSW = 2200kHz, PWM = H, BOOST-FET

IPD25N06S4L-30, Charge Pump Enabled

104

CPUMP and LDO Electrical Characteristics

V_CPUMPVoltage accuracy

V_DD= 3.0 to 3.6V; I_LOAD= 1 to 50mA

4.8

5

5.2

V

f_CP

CP switching frequency

387

417

447

kHz

V_{CPUMP_}

VCPUMP UVLO threshold

V_CPUMPfalling edge

V_CPUMPrising edge

3.95

4.15

0.1

4.2

4.4

4.6

V

UVLO

V_{CPUMP_}

VCPUMP UVLO threshold

VCPUMP UVLO hysteresis

Charge pump startup time

UVLO

V_{CPUMP_}

0.2

V

HYS

T_{START_U}

C_CPUMP= 10µF

1000

2000

µs

P

Protection Electrical Characteristics

VDD_UVLO

V_DDUVLO threshold

V_DDfalling

V_DDrising

2.68

2.8

0.1

2.92

3.0

V

_F

VDD_UVLO

V_DDUVLO threshold

_R

VDD_UVLO

V_DDUVLO hysteresis

_H

VIN_{UVLO_}

UVLO pin threshold

V_UVLOfalling

0.753

0.777

0.801

V

TH

I_UVLO

UVLO pin bias current

V_UVLO= V_{UVLO_TH}+ 50mV

µA

–5

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6.5 Electrical Characteristics (continued)

Limits apply over the full operation temperature range –40°C ≤T_A≤+125°C , unless otherwise speicified_.V_IN= 12 V_,VDD

= 3.3 V

PARAMETER

OVP threshold

TEST CONDITIONS

VSENSE_P rising

MIN

TYP

MAX

UNIT

VIN_{OVP_T}

40.8

43

45.2

V

H

VIN_{OVP_H}

OVP hysteresis

1.7

V

YS

VIN_{OCP_T}

Input OCP threshold

187

150

220

253

180

mV

R_ISENSE= 20mΩ

H

T_SD

Thermal shutdown threshold⁽¹⁾

Thermal shutdown hysteresis⁽¹⁾

Temperature rising

165

20

°C

I_{SD_LEAKA}

SD leakage current

SD pull down current

V_SD= 48V

1

µA

GE

I_SD

250

325

1.423

1.76

400

µA

V

R_SD= 20kΩ

V_{FB_OVPL}FB pin - Boost OVP low threshold

V_{FB_OVPH}FB pin - Boost OVP high threshold

V_{FB_UVP}FB pin - Boost OCP threshold

V

0.886

V

V_{BST_OVP}

Discharge pin - Boost OVP high threshold

48.5

100

50

1

51.8

V

H

Input PWM Electrical Characteristics

I_{PWM_LEA}

PWM leakage current

V_PWM= 5V

µA

Hz

ns

KAGE

f_{PWM_IN}

PWM input frequency

20000

200

t_{PWM_MIN}

PWM input minimum on-time

Direct PWM mode

_ON

t_{PWM_MIN}

Phase Shift PWM mode, Hybrid mode,

Current Dimming mode

PWM input minimum on-time

PWM input resolution

200

16

220

ns

bit

_ON

PWM_IN

f_{PWM_IN}= 100 Hz

f_{PWM_IN}= 20 kHz

RES

PWM_IN

PWM input resolution

10

RES

LED Current Sink and LED PWM Electrical Characteristics

I_LEAKAGELeakage current on OUTx OUTx = V_OUT= 45V, EN= L

0.1

1.21

200

2.5

µA

V

V_ISET

I_MAX

ISET voltage

1.17

1.25

Maximum LED sink current

OUTx

mA

V_{ISET_UVL}

ISET pin undervoltage

ISET Resistor range

0.97

15.6

1

1.03

104

V

O

R_ISET

I_OUT= 30mA to 200mA

kΩ

mA

LED current limit when ISET pin short to

GND

I_{LED_LIMIT}

280

R_ISET= 15.6kΩ, I_OUT= 150mA, PWM =

I_ACC

LED sink current accuracy

LED sink current matching

-4

4

%

100%

R_ISET= 15.6kΩ, I_OUT= 150mA, PWM =

100%

I_MATCH

1

3.5

8

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6.5 Electrical Characteristics (continued)

Limits apply over the full operation temperature range –40°C ≤T_A≤+125°C , unless otherwise speicified_.V_IN= 12 V_,VDD

= 3.3 V

PARAMETER

LED dimming frequency

Dimming ratio

TEST CONDITIONS

PWM_FSET =3.92 kΩ

MIN

141

TYP

152

MAX

163

UNIT

f_DIM

DIM

283

305

327

PWM_FSET =4.75 kΩ

PWM_FSET =5.76 kΩ

PWM_FSET =7.87 kΩ

PWM_FSET =11 kΩ

PWM_FSET =17.8 kΩ

PWM_FSET =42.4 kΩ

PWM_FSET =124 kΩ

f_{PWM_OUT}= 152Hz

567

610

653

1135

2270

4541

9082

18163

1221

1307

2612

5225

10450

20899

Hz

2441

4883

9766

19531

32000:1

1000:1

Dimming ratio

f_{PWM_OUT}= 4.88kHz

V_HEADRO

LED sink headroom

0.7

0.8

5.4

V

OM

V_HEADRO

LED sink headroom hysteresis

LED internal short threshold

LED short to ground threshold

OM_HYS

V_LEDSHO

RT

V_SHORTG

0.24

200

V

ND

t_{PWM_OUT}LED output minimum pulse

ns

Boost Converter Electrical Characteristics

f_SW

V_ISNS

Switching Frequency

External FET current limit

93

186

100

200

107

214

kHz

mV

BST_FSET =7.87 kΩ

BST_FSET =4.75 kΩ

BST_FSET =5.76 kΩ

BST_FSET =3.92 kΩ

BST_FSET =11 kΩ

281

303

325

372

400

428

465

500

535

1690

1860

2066

180

1818

2000

2222

200

1946

2140

2378

220

BST_FSET =17.8 kΩ

BST_FSET =42.4 kΩ

BST_FSET =124 kΩ

V_ISNSthreshold, R_SENSE= 15 to 50 mΩ

V_DD= 3.3 V

I_{SEL_MAX}IDAC maximum current

36.4

38.7

40.2

µA

V_GD/(R_{DS_ON}+ total resistance to gate

input of SW FET) must not be higher than

2.5 A

R_{DS_ONH}R_DSONof high-side FET to gate driver

1.4

Ω

V_GD/(R_{DS_ON}+ total resistance to gate

input of SW FET) must not be higher than

2.5 A

R_{DS_ONL}R_DSONof low-side FET to gate driver

0.75

50

Ω

Delay from beginning of boost Soft-start

to when LED drivers can begin

t_STARUP

Start-up time

ms

T_ON

Minimum switch on-time

Minimum switch off time

150

ns

T_OFF

(1) This specification is not ensured by ATE

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6.6 Logic Interface Characteristics

Limits apply over the full operation temperature range –40°C ≤T_A≤+125°C , unless otherwise speicified_.V_IN= 12 V_,VDD

= 5 V, V_EN= 3.3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC INPUT EN

VEN_IL

VEN_IH

R_ENPD

EN logic low threshold

0.4

V

EN logic high threshold

1.2

EN pin internal pull down resistance

1

MΩ

LOGIC INPUT SDA, SCL, BST_SYNC and PWM

V_IL

V_IH

Logic low threshold

Logic high threshold

V_DD= 3.3V and 5V

0.4

V

V_DD= 3.3V and 5V

1.2

LOGIC OUTPUT SDA, INT

V_OLOutput level low

I_LEAKAGEOutput leakage current

I = 3mA

0.2

0.4

1

V

V = 3.3V

µA

6.7 Timing Requirements for I2C Interface

Limits apply over the full operation temperature range –40°C ≤T_A≤+125°C , unless otherwise speicified_.V_IN= 12 V_,VDD

= 5 V_,V_EN= 3.3 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

kHz

µs

f_SCLK

1

Clock frequency

400

Hold time (repeated) START condition

Clock low time

0.6

1.3

600

50

2

µs

3

Clock high time

ns

4

Set-up time for a repeated START condition

Data hold time

ns

5

ns

6

Data setup time

100

ns

7

Rise time of SDA and SCL

Fall time of SDA and SCL

Set-up time for STOP condition

Bus free time between a STOP and a START condition

300

ns

8

ns

9

600

1.3

ns

10

µs

SDA

10

8

7

6

1

7

2

8

4

9

SCL

1

5

3

图6-1. I2C Timing Diagram

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6.8 Typical Characteristics

Unless otherwise specified: C_IN= C_OUT= 2 × 10-μF ceramic and 2 × 33-μF electrolytic, V_DD= 3.3 V, charge

pump enabled, T_A= 25°C

100

95

90

85

80

75

100

95

90

85

80

75

70

65

60

V_IN= 9 V

V_IN= 12 V

V_IN= 16 V

V_IN= 24 V

V_IN= 12 V

V_IN= 16 V

V_IN= 24 V

0

10

20

30

40

Brightness (%)

50

60

70

80

90 100

0

10

20

30

40

Brightness (%)

50

60

70

80

90 100

D001

D002

8 LEDs/string

6 strings

150 mA/string

8 LEDs/string

6 strings

150 mA/string

ƒ_SW= 303 kHz

ƒ_SW= 2.2 MHz

L1 = 22 µH

L1 = 10 µH

图6-2. Boost Efficiency

图6-3. Boost Efficiency

90

85

80

75

70

65

60

55

85

80

75

70

65

60

55

50

V_IN= 6 V

V_IN= 12 V

V_IN= 17 V

V_IN= 6 V

V_IN= 12 V

V_IN= 17 V

0

10

20

30

40

Brightness (%)

50

60

70

80

90 100

0

10

20

30

40

Brightness (%)

50

60

70

80

90 100

D003

D004

2 LEDs/string

150 mA/string

6 strings

2 LEDs/string

150 mA/string

6 strings

ƒ_SW= 303 kHz

L1 = 10 µH, L2 = 15 µH

ƒ_SW= 2.2 MHz

L1 = L2 = 4.7 µH

图6-4. SEPIC Efficiency

图6-5. SEPIC Efficiency

150

120

90

60

30

0

2.5

2.0

1.5

1.0

0.5

0.0

15 mA

25 mA

50 mA

80 mA

120 mA

150 mA

0

8192 16384 24576 32768 40960 49152 57344 65536

Brightness Code

0

8192 16384 24576 32768 40960 49152 57344 65536

Brightness Code

D005

D006

图6-6. Current Linearity

图6-7. Current Matching

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7 Detailed Description

7.1 Overview

The LP8866-Q1 device is a high-voltage LED driver for automotive infotainment, clusters, HUD and other

automotive display LED backlight applications. PWM input is used for brightness control by default. Alternatively,

the brightness can also be controlled by I2C Interface.

The boost frequency, LED PWM frequency, and LED string current are configured with external resistors through

the BST_FSET, PWM_FSET, and ISET pins. The INT pin is used to report faults to the system. Fault interrupt

status can be cleared with the I2C interface, or is cleared on the falling edge of the EN pin.

The LP8866-Q1 supports pure PWM dimming. The six LED current drivers provide up to 200 mA per output and

can be tied together to support higher current LEDs. The maximum output current of the LED drivers is set with

the ISET resistor and can be optionally scaled by the LEDx_CURRENT[11:0] register bits with I2C interface. The

LED output PWM frequency is set with a PWM_FSET resistor. The number of connected LED strings is

configured by the LED_SET resistor, and the device automatically selects the corresponding phase shift mode.

For example, if the device is set to 4-strings mode, each LED output is phase shifted by 90 degrees with each

other(= 360 / 4). Unused outputs, which must be connected to GND, will be disabled and excluded from adaptive

voltage and won't generate any LED faults.

A resistor divider connected from V_OUTto the FB pin sets the maximum voltage of the boost. For best efficiency,

the boost voltage is adapted automatically to the minimum necessary level needed to drive the LED strings by

monitoring all the LED output voltages continuously. The switching frequency of the boost regulator can be set

between 100 kHz and 2.2 MHz by the BST_FSET resistor. The boost has a start-up feature that reduces the

peak current from the power-line during start-up. The LP8866-Q1 can also control a power-line FET to reduce

battery leakage when disabled and provide isolation and protection in the event of a fault.

Fault detection features of LP8866-Q1 include:

• Open-string and shorted LED detection

– LED fault detection prevents system overheating in case of open or short in some of the LED strings

• LED short-to-ground detection

• ISET/BST_FSET/PWM_FSET/LED_SET/MODE resistor out-of-range detection

• Boost overcurrent

• Boost overvoltage

• Device undervoltage protection (VDD UVLO)

– Threshold sensing from VDD pin

• V_INinput overvoltage protection (V_INOVP)

– Threshold sensing from VSENSE_P pin

• V_INinput undervoltage protection (V_INUVLO)

– Threshold sensing from UVLO pin

• V_INinput overcurrent protection (V_INOCP)

– Threshold sensing across voltage between VSENSE_P pin and VSENSE_N pin

• Thermal shutdown in case of die overtemperature

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7.2 Functional Block Diagram

SD

VSENSE_N

VSENSE_P

GD

Powerline

FET

Control

PGND

ISNS

+

Boost

Controller

UVLO

œ

ISNSGND

VDD

C1N

FB

Charge

Pump

C1P

Discharge

DISCHARGE

CPUMP

PWM_FSET

BST_FSET

OSC

20 MHz

OTP

OUT1

OUT2

MODE

ADC

OUT3

OUT4

LED_SET

EN

BOOST

CONTROL

OUT5

OUT6

PWM

BST_SYNC

LED_GND

INT

SDA

SCL

LED

Current

Setting

ISET

I2C

Analog Blocks

VREF, TSD

SGND

7.3 Feature Description

7.3.1 Control Interface

Device control interface includes:

• EN is the enable input for the LP8866-Q1 device.

• PWM is the default input to control the brightness of all current sinks by duty cycle.

• INT is an open-drain fault output indicating fault condition detection.

• SDA and SCL are data and clock line for I2C interface to control the brightness of all current sinks and read

back the fault conditions for diagnosis.

• BST_SYNC is used to input an external clock for the boost switching frequency and control the internal boost

clock mode.

– The external clock is auto detected at start-up and, if missing, the internal clock is used.

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– Optionally, the BST_SYNC can be tied to VDD to enable the boost spread spectrum function or tied to

GND to disable it.

• ISET pin to set the maximum LED current level per string.

7.3.2 Function Setting

Device parameter setting includes:

• BST_FSET pin is used to set the boost switching frequency through a resistor to signal ground.

• PWM_FSET pin is used to set the LED output PWM dimming frequency through a resistor to signal ground.

• MODE pin is used to set the dimming mode via an external resistor to signal ground.

• LED_SET pin is used to set the LED configuration through a resistor to signal ground.

• ISET pin is used to set the maximum LED current level per OUTx pin.

7.3.3 Device Supply (VDD)

All internal analog and digital blocks of LP8866-Q1 are biased from external supply from VDD pin. Either a

typical 5-V or 3.3-V supply rail is able to supply VDD from previous linear regulator or DC/DC converter with at

least 200-mA current capability.

7.3.4 Enable (EN)

The LP8866-Q1 only turns on when the input voltage of EN pin is above the voltage threshold (VEN_IH) and turns

off when the voltage of EN pin is below the threshold (VEN_IL). All analog and digital blocks start operating once

the LP8866-Q1 is enabled by asserting EN pin. The SD pin is floating, I2C interface and Fault detection are not

active if the EN pin is de-asserted.

7.3.5 Charge Pump

An integrated regulated charge pump can be used to supply the gate drive for the external FET of the boost

controller. The charge pump is enabled or disabled by automatically detecting whether VDD and CPUMP pin are

connected together. If VDD is < 4.5 V then use the charge pump to generate a 5-V gate voltage to drive the

external boost switching FET. To use the charge pump, a 2.2-µF capacitor is placed between C1N and C1P. If

the charge pump is not required, C1N and C1P could be left unconnected and CPUMP pins tied to VDD. A 4.7-

µF CPUMP capacitor is used to store energy for the gate driver. The CPUMP capacitor is required to be used in

both charge pump enabled and disabled conditions and must be placed as close as possible to the CPUMP

pins. 图7-1and 图7-2 show required connections for both use cases.

V_IN

3 to 48V

L

V_OUT

C_IN

C_OUT

SD

GD

PGND

ISNS

VSENSE_N

VSENSE_P

V_DD

3.3V

ISNSGND

FB

VDD

C_VDD

C1N

C_FLY

C1P

CPUMP

C_PUMP

图7-1. Charge Pump Enabled Circuit

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V_IN

L

V_OUT

3 to 48V

C_IN

C_OUT

SD

GD

VSENSE_N

VSENSE_P

PGND

ISNS

V_DD

5V

ISNSGND

FB

VDD

C_VDD

C1N

C1P

CPUMP

C_PUMP

图7-2. Charge Pump Disabled Circuit

If the charge pump is enabled, the CPCAP_STATUS bit shows whether a fly capacitor was detected and the

CP_STATUS bit shows status of any charge pump faults and generates an INT signal. The CP_INT_EN bit can

be used to prevent the charge-pump fault from causing an interrupt on the INT pin.

7.3.6 Boost Controller

The LP8866-Q1 current-mode-controlled boost DC/DC controller generates the anode voltage for the LEDs. The

boost is a current-mode-controlled topology with a cycle by cycle current limit. The boost converter senses the

switch current and across the external sense resistor connected between ISNS and ISNSGND. A 20-mΩ sense

resistor results in a 10-A cycle by cycle current limit. The sense resistor value could vary from 15 mΩ to 50 mΩ

depending on the application. Maximum boost voltage is configured with external FB-pin resistor divider

connected between V_OUTand FB. The FB-divider equation is described in 节7.3.6.3.

V_OUT

V_IN

C_OUT

C_IN

CPUMP

Adaptive

voltage

control

R1

R2

+

GM

œ

VREF

FB

GD

+

COMP

œ

R

S

Q

PGND

OVP

OCP

TSD

BOOST OSCILLATOR

ADC

BST_FSET

CURRENT RAMP

GENERATOR

OFF/BLANK TIME

PULSE GENERATOR

ISNS

+

MUX

GM

œ

ꢀ

BST_SYNC

ISNSGND

图7-3. Boost Controller Block Diagram

The boost switching frequency is adjustable from 100 kHz to 2.2 MHz via an external resistor at BST_FSET (see

表7-1). Resistor with 1% accuracy is needed to ensure proper operation.

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表7-1. Boost Frequency Selection

BOOST FREQUENCY (kHz)

R_BST_FSET (kΩ)

3.92

4.75

5.76

7.87

11

400

200

303

100

500

17.8

42.2

124

1818

2000

2222

7.3.6.1 Boost Cycle-by-Cycle Current Limit

The voltage between ISNS and ISNSGND is used for both boost DC/DC controller's current sensing and cycle-

by-cycle current limit settings. When the cycle-by-cycle current limit is reached, the controller will turn off the

switching MOSFET immediately and turn on it again in next siwtching cycle. This cycle-by-cycle current limit

could be used as a common protection for all related DC/DC components (inductor, schottky diode and switching

MOSFET) to avoid current running over their max limit. Cycle-by-Cycle current limit won't trigger any faults of the

device.

V

ISNS

I_{CYCLE_LIMIT}

=

R_SENSE

(1)

where

• V_ISNS= 200 mV

7.3.6.2 Controller Min On/Off time

The device boost DC/DC controller has minimum on/off time as below table. Minimum off time should be

specially taken care in system design. The SW node rising time plus falling time should be higher than minimum

off time to avoid controller not turning off the MOSFET.

表7-2. Controller Minimum On/Off Time

Frequency (kHz)

100 to 500

Minimum Switch OFF time (ns)

Minimum Switch ON time (ns)

150

40

150

110

1818 to 2222

7.3.6.3 Boost Adaptive Voltage Control

The LP8866-Q1 boost DC/DC converter generates the anode voltage for the LEDs. During normal operation,

boost output voltage is adjusted automatically based on the LED current sink headroom voltages. This is called

adaptive boost control. The number of used LED outputs is set by LED_SET pin and only the active LED outputs

are monitored to control the adaptive boost voltage. Any LED strings with open or short faults are also removed

from the adaptive voltage control loop. The LED driver pin voltages are periodically monitored by the control loop

and the boost voltage is raised if any of the LED outputs falls below the V_HEADROOMthreshold. The boost voltage

is lowered until any of the LED outputs touch the V_HEADROOMthreshold. See 图 7-4 for how the boost voltage

automatically scales based on the OUTx-pin voltage, V_HEADROOMand V_{HEADROOM_HYS}

.

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Boost

Increases

voltage

Boost

decreases voltage

No actions

OUT1~6 PIN

VOLTAGE

The lowest channel

voltage touches

V_HEADROOMthreshold

No output is close to

V_HEADROOMthreshold

One output is lower than

V_HEADROOMthreshold

V_LEDSHORT

V_HEADROOM+V_{HEADROOM_HYS}

V_HEADROOM

Normal

Conditions

Dynamic

Conditions

图7-4. Adaptive Boost Voltage Control Loop Function

The resistive divider (R₁, R₂) defines both the minimum and maximum adaptive boost voltage levels. The

feedback circuit operates the same in boost and SEPIC topologies. Choose maximum boost voltage based on

the maximum LED string voltage specification. Before the LED drivers are active, the boost starts up to the initial

boost level. The initial boost voltage is approximately in the 88% point of minimum to maximum boost voltage.

Once the LED driver channels are active, the boost output voltage is adjusted automatically based on OUTx pin

voltages. The FB pin resistor divider also scales the boost OVP, OCP levels and the LED short level in HUD

application.

7.3.6.3.1 FB Divider Using Two-Resistor Method

A typical FB-pin circuit uses a two-resistor divider circuit between the boost output voltage and ground.

V_OUT

V_IN

C_OUT

C_IN

CPUMP

R1

+

VREF

GD

GM

œ

+

COMP

œ

R

S

Q

FB

PGND

R2

+

BSTOVPH

BSTOVPL

BSTOCP

OVP

OCP

TSD

VOVPH

VOVPL

œ

+

œ

VUVP

+

CURRENT RAMP

GENERATOR

ISNS

+

Pulse

Generator

ISEL[10:0]

GM

œ

ꢀ

ISNSGND

图7-5. Two-Resistor FB Divider Circuit

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Maximum boost voltage can be calculated with Equation 2. The maximum boost voltage can be reached during

OPEN string detection or if all LED strings are left disconnected.

≈

∆

«

’

R₁

R₂

V_{BOOST _MAX}=I_{SEL _MAX}ìR +

+1 ì V

÷

1

REF

◊

(2)

where

• V_REF= 1.21 V

• I_{SEL_MAX}= 38.7 µA

• R₁/ R₂normal recommended range is 7~15

The minimum boost voltage must be less than the minimum LED string voltage. Minimum boost voltage is

calculated with Equation 3:

≈

∆

«

’

R

V_{BOOST_MIN}

=

¹+1 ì V

÷

REF

R₂

◊

(3)

where

• V_REF= 1.21 V

When the boost OVP_LOW level is reached, the boost controller stops switching the boost FET and the

BSTOVPL_STATUS bit is set. The LED drivers are still active during this condition, and the boost resumes

normal switching operation once the boost output level falls. The boost OVP low voltage threshold changes

dynamically with current boost voltage. It is calculated in Equation 4:

≈

∆

«

’

R

V_{BOOST_OVPL}= V_BOOST

+

¹+1 ì(V

- V_REF

)

÷

FB_OVPL

R₂

◊

(4)

where

• V_{FB_OVPL}= 1.423 V

• V_REF= 1.21 V

When the boost OVP_HIGH level is reached the boost controller enters fault recovery mode, and the

BSTOVPH_STATUS bit is set. The boost OVP high-voltage threshold also changes dynamically with current

boost voltage and is calculated in Equation 5:

≈

∆

«

’

R

V_{BOOST_OVPH}= V_BOOST

+

¹+1 ì(V_{FB_OVPH}- V_REF

)

÷

R₂

◊

(5)

where

• V_{FB_OVPH}= 1.76 V

• V_REF= 1.21 V

When the boost UVP level is reached the boost controller starts a 110-ms OCP counter. The LP8866-Q1 device

enters the fault recovery mode and sets the BSTOCP_STATUS bit if the boost voltage does not rise above the

UVP threshold before the timer expires. The boost UVP voltage threshold also changes dynamically with current

boost voltage and is calculated in Equation 6:

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≈

∆

«

’

R

V_{BOOST_UVP}= V_BOOST

-

¹+1 ì(V_REF- V_UVP

)

÷

R₂

◊

(6)

where

• V_UVP= 0.886 V

• V_REF= 1.21 V

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7.3.6.3.2 FB Divider Using Three-Resistor Method

A FB-pin circuit using a three-resistor divider circuit can be used for applications where less than 200-kΩ

resistors are required.

V_OUT

V_IN

C_OUT

C_IN

CPUMP

R1

+

GM

VREF

R3

GD

+

COMP

œ

R

S

Q

FB

PGND

R2

+

BSTOVPH

BSTOVPL

BSTOCP

OVP

OCP

TSD

VOVPH

VOVPL

œ

+

œ

VUVP

+

CURRENT RAMP

GENERATOR

ISNS

+

Pulse

Generator

ISEL[10:0]

GM

œ

ꢀ

ISNSGND

图7-6. Three-Resistor FB Divider Circuit

Maximum boost voltage can be calculated with Equation 7. The maximum boost voltage can be reached during

OPEN string detection or if all LED strings are left disconnected.

≈

∆

«

’

≈

∆

«

’

R₁ìR

R₂

R

V_{BOOST_MAX}

=

³+R +R ìI

+

¹+1 ìV

÷

1

3

SEL_MAX

REF

R₂

◊

(7)

where

• V_REF= 1.21 V

• I_{SEL_MAX}= 38.7 µA

• R₁/ R₂normal recommended range is 7 to 15

The minimum boost voltage must be less than the minimum LED string voltage. Minimum boost voltage is

calculated in Equation 8:

≈

∆

«

’

R

V_{BOOST_MIN}

=

¹+1 ì V

÷

REF

R₂

◊

(8)

When the boost OVP_LOW level is reached the boost controller stops switching the boost FET, and the

BSTOVPL_STATUS bit is set. The LED drivers are still active during this condition, and the boost resumes

normal switching operation once the boost output level falls. The boost OVP low voltage threshold changes

dynamically with current boost voltage. It is calculated in Equation 9:

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≈

∆

«

’

R

V_{BOOST_OVPL}= V_BOOST

+

¹+1 ì(V

- V_REF

)

÷

FB_OVPL

R₂

◊

(9)

where

• V_{FB_OVPL}= 1.423 V

• V_REF= 1.21 V

When the boost OVP_LOW level is reached the boost controller enters fault recovery mode, and the

BSTOVPH_STATUS bit is set. The boost OVP high-voltage threshold also changes dynamically with current

boost voltage and is calculated in Equation 10:

≈

∆

«

’

R

V_{BOOST_OVPH}= V_BOOST

+

¹+1 ì(V_{FB_OVPH}- V_REF

)

÷

R₂

◊

(10)

where

• V_{FB_OVPH}= 1.76 V

• V_REF= 1.21 V

When the boost UVP level is reached the boost controller starts a 110-ms OCP counter. The LP8866-Q1 device

enters the fault recovery mode and sets the BSTOCP_STATUS bit if the boost voltage does not rise above the

UVP threshold before the timer expires. The boost UVP voltage threshold also changes dynamically with current

boost voltage and is calculated in Equation 11:

≈

∆

«

’

R

V_{BOOST_UVP}= V_BOOST

-

¹+1 ì(V_REF- V_UVP

)

÷

R₂

◊

(11)

where

• V_UVP= 0.886 V

• V_REF= 1.21 V

7.3.6.3.3 FB Divider Using External Compensation

The device has internal compensation network to keep the DC-DC control loop in good stability in most cases.

However, an additional external compensation network could also be added on FB-pin to offer more flexibility in

loop design or solving some extreme use-cases.

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V_OUT

V_IN

C_OUT

C_IN

CPUMP

R1

+

GM

VREF

R4

R3

GD

+

COMP

œ

R

S

Q

FB

PGND

R2

C_COMP

+

BSTOVPH

BSTOVPL

BSTOCP

OVP

OCP

TSD

VOVPH

VOVPL

œ

+

œ

VUVP

+

CURRENT RAMP

GENERATOR

ISNS

+

Pulse

Generator

ISEL[10:0]

GM

œ

ꢀ

ISNSGND

图7-7. External compensation network

This network will create one additional pole and one additional zero in the loop.

1

f_{POLE_COMP}

=

2p

(R ||R ) +R C

[

]

1

2

4

COMP

(12)

(13)

1

f_{ZERO_COMP}

=

2pR₄C_COMP

It could be noted that R₃doesn't take part in the compensation. So this external compensation network could be

both used in two-divider netwrok and T-divider network with no equation change.

In real application, for example, when DC-DC loop has stability concern, putting the additional pole in 1 kHz and

the additional zero in 2 kHz will suppress the loop gain by approximately 6 dB after 2 kHz. This will benefit gain

margin and phase margin a lot.

7.3.6.4 Boost Sync and Spread Spectrum

Spread spectrum function could be enabled when BST_SYNC pin is high and disabled when BST_SYNC pin is

low.

If an external CLK signal is on the BST_SYNC pin, the boost controller can be clocked by this signal. If the clock

disappears later, the boost continues operation at the frequency defined by RBST_FSET resistor, and the

spread spectrum function will be enabled or disabled depending on the final pin level of BST_SYNC.

表7-3. Boost Synchronization Mode

BST_SYNC PIN LEVEL

Low (GND)

BOOST CLOCK MODE

Spread spectrum disabled

Spread spectrum enabled

High (VDDIO)

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表7-3. Boost Synchronization Mode (continued)

BST_SYNC PIN LEVEL

BOOST CLOCK MODE

100-kHz to 2222-kHz clock frequency

Spread spectrum disabled, external synchronization mode

If using the external BST_SYNC input, the R_{BST_SET}resistor should be chosen the closest boost frequency

options with the external frequency.

The spread spectrum function helps to reduce EMI noise around the switching frequency and its harmonic

frequencies. The internal spread spectrum function modulates the boost frequency ±3.3% to 7.2% from the

central frequency with a 200-Hz to 1.2-kHz modulation frequency. The switching frequency variation is

programmable by SPREAD_RANGE register, and the modulation frequency is programmable by

SPREAD_MOD_FREQ register. The spread-spectrum function cannot be used when an external

synchronization clock is used.

表7-4. Spread Spectrum Frequency Range

SPREAD_RANGE (Binary)

SWITCHING FREQUENCY VARIATION

00

±3.3%

±4.3%

±5.3%

±7.2%

01

10 (Default)

11

表7-5. Spread Spectrum Modulation Frequency

SPREAD_MOD_FREQ (Binary)

MODULATION FREQUENCY

00 (Default)

200 Hz

500 Hz

800 Hz

1200 Hz

01

10

11

7.3.6.5 Boost Output Discharge

When the EN pin is pulled low, the device stops the boost controller and LED current sinks, turns off the power-

line FET, and starts to discharge the boost output. The discharge pin typically sinks 30-mA current. The

discharge duration is 400 ms. After 400 ms, the device shuts down. The DISCHARGE pin must be connected

with boost output for normal operation.

There is one internal comparator to monitor the voltage of DISCHARGE pin. As soon as the voltage of

DISCHARGE pin is higher than V_{BST_OVPH}(typically 50 V), the device enters into fault recovery mode, and

BST_OVPH fault is reported. This provides further protection if boost voltage is out of control because of system

failure.

Discharge function is only available in HTSSOP package. It's not available in QFN package.

7.3.6.6 Light Load Mode

The DC-DC controller will enter into light load mode in below condition:

• V_INvoltage is very close to V_OUT

• Loading current is very low

• PWM pulse width is very short

When DC-DC converter enters into light load mode, it stops switching occasionally to make sure output voltage

won't rise up too much. It could also be called as PFM mode, since the DC-DC converter switching frequency

will change in this mode.

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7.3.7 LED Current Sinks

7.3.7.1 LED Output Current Setting

The maximum output LED current is set by an external resistor value. For the application only using external

resistor R_ISETto set the maximum LED current for each string, the Equation 14 is used to calculate the current

setting of all strings:

1.21V

I_LED

=

ì2580

R_ISET

(14)

The LEDx_CURRENT[11:0] registers can also be used to adjust strings current down from this maximum. The

default value for LEDx_CURRENT[11:0] registers is the maximum 0xFFF(4095). Equation 15 is used to calculate

the current setting of an individual string:

≈

∆

«

’

1.21V

R_ISET

LED_CURRENT[11:0]

4095

≈

’

I_LED

=

ì2580 ì

÷

∆

«

÷

◊

(15)

For high accuracy of LED current, the ILED current is recommended to set in range from 30 mA to 200 mA. So

the R_ISETvalue is in the range from 15.6 kΩto 104 kΩ.

OUT1

OUT1 Current Sink

V_REF

VDD

Current Gain

EXTERNAL

CURRENT

SENSING

EA

R

ISET

RISET

OUT2

OUT3

OUT4

OUT5

OUT6

OUT2 Current Sink

OUT3 Current Sink

OUT4 Current Sink

OUT5 Current Sink

OUT6 Current Sink

LED_CURRENT[11:0]

图7-8. LED Driver Current Setting Circuit

7.3.7.2 LED Output String Configuration

The Six LED driver channels of the LP8866-Q1 device is configured by the LED_SET resistor, which supports

applications using one to Six LED strings. Resistor with 1% accuracy is needed to ensure proper operation. The

driver channels can also be tied together in groups of one, two or three. This allows the LP8866-Q1 device to

drive three 400-mA LED strings, two 600-mA LED strings, or one 1200-mA LED string. The LED strings are

always appropriately phase shifted for their string configuration. This reduces the ripple seen at the boost output,

which allows smaller output capacitors and reduces audible ringing in the capacitors. Phase shift increases the

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load frequency, which can move potential capacitor noise above the audible band while still keeping PWM

frequency low to support a higher dimming ratio.

When the LP8866-Q1 device is firstly powered on, the string configuration is configured by the LED_SET resistor

and the phases of each channel are automatically configured. The LED string configuration must not be changed

unless the LP8866-Q1 is powered off in shutdown state. The unused LEDx pins should be tied to ground.

表7-6. LED Output String Configuration

AUTOMATIC

CONFIGURATION

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

PHASE

SHIFT

R_LED_SET (kΩ)

3.92

4.75

6 Channels

5 Channels

200 mA 200 mA

200 mA

60°

72°

(Tied to GND)

(Tied to

GND)

5.76

7.87

11

4 Channels

3 Channels

2 Channels

200 mA 200 mA

200 mA

(Tied to GND)

90°

(Tied to

GND)

(Tied to

GND)

120°

180°

(Tied to

GND)

(Tied to

GND)

200 mA 200 mA (Tied to GND)

400 mA 400 mA

17.8

42.2

124

3 Channels

2 Channels

1 Channels

400 mA

600 mA

120°

180°

None

600 mA

1200 mA

7.3.7.3 LED Output PWM Clock Generation

The LED PWM frequency is asynchronous from the input PWM frequency. The LED PWM frequency is

generated from the internal 20-MHz oscillator and can be set to eight discrete frequencies from 152 Hz to 19.531

kHz. The PWM dimming resolution is highest when the lowest PWM frequency is used. The PWM_FSET resistor

determines the LED PWM frequency based on 表7-8. PWM resolution in 表7-8 is with PWM dither disabled.

7.3.8 Brightness Control

The LP8866-Q1 supports global brightness control for all LED strings through either duty cycle input on PWM pin

or register by I2C bus. An internal 20-MHz clock is used for generating PWM outputs.

7.3.8.1 Brightness Control Signal Path

The BRT_MODE register selects whether the input to the display brightness path is the PWM input pin or

DISP_BRT register. PWM input control will be the default setup after power on. The brightness control signal

path diagram is shown in 图7-9

The display brightness path has sloper function that can be enabled. By default the sloper function is enabled.

The sloper and dither function also can be programmable by I2C control. The sloper function is described in 节

7.3.8.7, and the dither function is described in 节7.3.8.9.

MODE Resistor

OUT1

DITHER_SELECT[3:0]

OUT2

MODE Resistor

OUT3

OUT4

OUT5

OUT6

PWM

Detector

LED

DRIVER

MUX

PWM

BRT_MODE[1:0]

MUX

PWM

GENERATOR

PHASE

SHIFT

Dither

HYBIRD

DIMMING

SLOPER

REGISTERS

PWM_FSET Resistor

I²C

ADV_SLOPE_EN

SLOPE_SELECT[2:0]

DISPLAY

BRIGHTNESS

AUTO_LED_STRING_CFG[3:0]

PWM_FSET Resistor

CURRENT

MULTIPLIER

LED_

CURRENT

ISET Resistor

图7-9. LP8866-Q1 Brightness Path Diagram

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7.3.8.2 Dimming Mode

Dimming mode can be adjusted via an external resistor to MODE pin (see 表 7-7). Resistor with 1% accuracy is

needed to ensure proper operation.

表7-7. Dimming Mode Configuration

MODE

I2C Address

0x2B

R_MODE (kΩ)

3.92

4.75

5.76

7.87

11

Phase-shift PWM Mode

Hybrid Mode

0x2B

Current Dimming Mode

Direct PWM Mode

Phase-shift PWM Mode

Hybrid Mode

0x2B

0x2A

17.8

42.2

124

0x2A

Current Dimming Mode

Direct PWM Mode

0x2A

7.3.8.3 LED Dimming Frequency

The LED dimming frequency is asynchronous from the input PWM frequency for phase-shift PWM mode and

hybrid dimming mode. The LED dimming frequency is generated from the internal 20-MHz oscillator and can be

set to eight discrete frequencies from 152 Hz to 19.531 kHz. The PWM dimming resolution is highest when the

lowest PWM frequency is used. The PWM_FSET resistor determines the LED Dimming frequency based on 表

7-8. Resistor with 1% accuracy is needed to ensure proper operation. PWM resolution in 表 7-8 is with PWM

dither disabled.

表7-8. LED PWM Frequency Selection

LED PWM FREQUENCY (Hz)

PWM DIMMING RESOLUTION (bits)

R_PWM_FSET (kΩ)

3.92

4.75

5.76

7.87

11

152

305

16

15

14

13

12

11

10

610

1221

2441

4883

9766

19531

17.8

42.2

124

7.3.8.4 Phase-Shift PWM Mode

In Phase-Shift PWM mode, all current active channels are turned on and off at LED dimming frequency with a

constant delay. However, the number of used channels or channel groups determine the phase delay time

between two neighboring channels as shown in 图7-10.

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DISPLAY_BRT

0xFFFF

0xBFFF

0x7FFF

0x3FFF

0x1FFF

0x0FFF

0x07FF

D=100%

D=75%

D=50%

D=25%

D=12.5%

D=6.25%

D=3.125%

PWM

Input

T_ON

T_PWM

LED Dimming Frequency

I_LED1

I_LED2

I_LED3

I_LED4

I_LED5

I_LED6

Phase-shift Mode

图7-10. Phase-shift Dimming Diagram

7.3.8.5 Hybrid Mode

In addition to phase-shift PWM dimming, LP8866-Q1 supports a hybrid-dimming mode. Hybrid dimming

combines PWM and current modes for brightness control for the display brightness path. By using hybrid

dimming, dimming ratio could be increased by another 8 times. In hybrid mode, PWM dimming is used for low

brightness range of brightness, and current dimming is used for high brightness levels as shown in 图 7-11.

Current dimming control enables improved optical efficiency due to increased LED efficiency at lower currents.

PWM dimming control at low brightness levels ensures linear and accurate control. Hybrid mode can be selected

through resistor value at MODE pin as 表 7-7. The PWM and current modes transition threshold can be set at

12.5% or at 0% brightness. The latter selection allows for pure current dimming control mode.

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DISPLAY_BRT

0xFFFF

0xBFFF

0x7FFF

0x3FFF

0x1FFF

0x0FFF

0x07FF

D=100%

D=75%

D=50%

D=25%

D=12.5%

D=6.25%

D=3.125%

PWM

Input

T_ON

T_PWM

100% I_LED

75%

50%

I_LED

D=50%

D=25%

25%

LED Dimming Frequency

12.5%

0A

12.5% Hybird Mode

图7-11. Hybrid Dimming Diagram

7.3.8.6 Direct PWM Mode

In direct PWM mode, all active channels are turned on and off and are synchronized with the input PWM signal.

D=100%

D=80%

D=60%

D=50%

D=25%

D=12.5%

D=6.25%

PWM

Input

T_ON

T_PWM

100% I_LED

I_LED

0A

Direct PWM Mode

图7-12. Direct PWM Dimming Diagram

7.3.8.7 Sloper

An optional sloper function makes the transition from one brightness value to another optically smooth. By

default the advanced sloper is enabled with a 200-ms linear sloper duration. Transition time between two

brightness values is programmed with the SLOPE_SELECT[2:0] bits (when 000, sloper is disabled). With

advanced sloper enabled the brightness changes are further smoothed to be more pleasing to the human eye.

Advanced slope is enabled with ADV_SLOPE_ENABLE register bit.

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Brightness

Sloper Input

Time

Brightness

Sloper Output

Advanced Slope

Linear Slope

Slope Time

Time

图7-13. Brightness Sloper

7.3.8.8 PWM Detector Hysteresis

PWM detector has an internal hysteresis function. It means when PWM input is used (except direct PWM mode),

PWM output duty cycle will change only when PWM input on-time changes by more than 6.4us. This is to avoid

the PWM duty cycle sampling error due to the onboard PWM signal's rising/falling time.

7.3.8.9 Dither

The number of brightness steps when using LED output PWM dimming is equal to the 20-MHz oscillator

frequency divided by the LED PWM frequency (set by PWM_FSET resistor). The PWM duty cycle dither is a

function the LP8866-Q1 uses to increase the number of brightness dimming steps beyond this oscillator clock

limitation. The dither function modulates the LED driver output duty cycle over time to create more possible

average brightness levels. The DITHER_SELECT[3:0] register bits control the level of dither, disabled, 1, 2, 3 or

4 bits using the I2C interface. By default the dither is disabled.

When the 1-bit dither is selected, to support higher brightness resolution, the width of every second PWM pulse

could be increased by one LSB (one 20-MHz clock period). When the 3-bit dither is selected, within a sequence

of 8 PWM periods the number of pulses with increased length varies depending on the dither value: dither value

000 - all 8 pulses at default length; 001 - one of the 8 pulses is longer; 010 - two of the 8 pulses are longer, and

so forth, until at 111 - seven of the 8 pulses have increased length. 图 7-14 shows one example of PWM output

dither.

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50.00225%

100 Hz

Input PWM

1.2 kHz LED

PWM

Without Dither

50%

1.2 kHz LED

PWM

With 3bit Dither

50.006%

图7-14. PWM Dither Example

The dither block also helps in low brightness scenario when dimming ratio is limited by LED PWM output

frequency and the LED output pulse is less than the minimum pulse width (200 ns). In such scenario, the dither

block will skip some of the PWM pulses to reduce the brightness further, enabling high dimming ratio. The end

result is that the LED PWM frequency is reduced as more and more minimum pulses are skipped or dithered

out. At the same time, dither block will also guarantee that the minimum LED PWM frequency is not less than

152 Hz to ensure no brightness flickering. 图7-15 shows how the dither works in low brightness scenario.

100 Hz

Input PWM

300 ns = 0.003%

200 ns

No

Pulse

200 ns

No

Pulse

305 Hz LED PWM

With Minimum Pulse

Dither

3.2 ms

Average Brightness = 0.003%

图7-15. Minimum Brightness Dither Example

7.3.9 Protection and Fault Detections

The LP8866-Q1 device includes fault detections for LED open, short and short-to-GND conditions, boost input

undervoltage, overvoltage and overcurrent, boost output overvoltage and overcurrent, VDD undervoltage, die

overtemperature and external components. The host can monitor the status of the faults in registers

SUPPLY_FAULT_STATUS, BOOST_FAULT_STATUS and LED_STATUS.

7.3.9.1 Supply Faults

7.3.9.1.1 V_INUndervoltage Faults (VINUVLO)

The LP8866-Q1 device supports V_INundervoltage and overvoltage protection. The undervoltage threshold is

programmable through external resistor divider on UVLO pin. If during operation of the LP8866-Q1 device, the

UVLO pin voltage falls below the UVLO falling level (0.787 V typical), the boost, LED outputs, and power-line

FET will be turned off, and the device will enter STANDBY mode. The VINUVLO_STATUS bit is also set in the

SUPPLY_FAULT_STATUS register, and the INT pin is triggered. When the UVLO voltage rises above the rising

threshold level the LP8866-Q1 exits STANDBY and begins the start-up sequence.

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V_IN

L

V_OUT

3 to 48V

C_IN

C_OUT

SD

VSENSE_N

VSENSE_P

GD

PGND

ISNS

R4

R5

UVLO

3.3V/5V

ISNSGND

FB

VDD

SGND

图7-16. V_INUVLO Setting Circuit

The following equation is used to calculate the UVLO threshold for VIN rising edge:

R₄

VIN_{UVLO_RISING}= (

+1)ìVIN_{UVLO_TH}

R₅

(16)

where

• VIN_{UVLO_TH}= 0.787 V

The hysteresis of UVLO threshold can be designed and calculated with the following equation.

VIN_HYST= R₄ìI_UVLO

(17)

where

• I_UVLO= 5 µA

So the following equation can be used for UVLO threshold for VIN falling edge:

VIN_{UVLO_FALLING}= VIN_{UVLO_RISING}-VIN_HYST

(18)

The bottom resistors, R₅of voltage divider is able to be disconnected to the GND through an additional external

N-type of FET as 图 7-17. This design is to minimize the current leakage from VIN in shutdown mode to extend

the battery life.

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V_IN

3 to 48V

L

V_OUT

C_IN

C_OUT

SD

VSENSE_N

GD

VSENSE_P

PGND

ISNS

R4

R5

UVLO

3.3V/5V

EN

ISNSGND

FB

VDD

SGND

图7-17. V_INUVLO Setting Circuit Without Current Leakage Path

7.3.9.1.2 V_INOvervoltage Faults (VINOVP)

The overvoltage threshold for V_INrising edge is internal fixed at typical 43 V. If during LP8866-Q1 operation,

VSENSE_P pin voltage rises above the OVP rising threshold, boost, LED outputs, and power-line FET will be

turned off, and the device will enter STANDBY mode. The VINOVP_STATUS bit will also be set in the

SUPPLY_FAULT_STATUS register, and the INT pin will be triggered. When the VSENSE_P pin voltage falls

below the falling threshold level, the LP8866-Q1 exits STANDBY and begins the start-up sequence.

7.3.9.1.3 V_DDUndervoltage Faults (VDDUVLO)

If during LP8866-Q1 device operation VDD falls below VDDUVLO falling level, boost, power-line FET, and LED

outputs are turned off, and the device enters STANDBY mode. The VDDUVLO_STATUS fault bit will be set in

the SUPPLY_FAULT_STATUS register, and the INT pin will be triggered. The LP8866-Q1 restarts automatically

to ACTIVE mode when V_DDrises above VDDUVLO rising threshold.

7.3.9.1.4 V_INOCP Faults (VINOCP)

If during LP8866-Q1 device operation voltage drop on RISENSE resistor rises above 220 mV, boost, power-line

FET, and LED outputs are turned off, and the device enters Fault Recovery mode and then attempt to restart 100

ms after fault occurs. The VINOCP_STATUS fault bit are set in the SUPPLY_FAULT_STATUS register, and the

INT pin is triggered.

VIN_{OCP_ TH}

I_{VIN_OCP}

=

R_ISENSE

(19)

where

• VIN_{OCP_TH}= 220 mV

7.3.9.1.4.1 VIN OCP Current Limit vs. Boost Cycle-by-Cycle Current Limit

VIN OCP current limit is totally different from boost cycle-by-cycle current limit.

Boost cycle-by-cycle current limit is to protect the DC/DC components (inductor, schottky diode and switching

MOSFET) in normal scenario, avoiding current running over their max limit. The normal scenario means when

loading has sharp change or input voltage has sharp change. It won't trigger any device fault.

VIN OCP current limit is to protect system from ciritical system hazard (e.g, inductor short, switching MOSFET

short). It will trigger the device to shutdown all the LED channels and enter into fault recovery state.

VIN OCP current limit should be always greater than boost cycle-by-cycle current limit. This means R_ISENSE

should be always no smaller than R_SENSE

.

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7.3.9.1.5 Charge Pump Faults (CPCAP, CP)

If during LP8866-Q1 device operation voltage of CPUMP pin falls below typical 4.2-V, boost, power-line FET, and

LED outputs are turned off, and the device enters Fault Recovery mode and then attempt to restart 100 ms after

fault occurs. The CP_STATUS fault bit will beset in the SUPPLY_FAULT_STATUS register, and the INT pin are

triggered.

If during LP8866-Q1 device initialization, the charge pump fly capacitor is disconnected or shorted, charge pump

are turned off. In result, boost, power-line FET, and LED outputs are turned off, and the device enters Fault

Recovery mode and then attempt to restart 100 ms after fault occurs. Both CPCAP_STATUS and CP_STATUS

fault bits are set in the SUPPLY_FAULT_STATUS register, and the INT pin are triggered.

7.3.9.1.6 CRC Error Faults (CRCERR)

If during LP8866-Q1 device initialization, the factory default configuration for registers, options and trim bits are

not corrected loaded from memory, LP8866-Q1 keeps operating normally, unless other fault criteria is triggered.

The CRCERR_STATUS fault bit are set in the SUPPLY_FAULT_STATUS register and the INT pin are triggered.

7.3.9.2 Boost Faults

7.3.9.2.1 Boost Overvoltage Faults (BSTOVPL, BSTOVPH)

Boost overvoltage is detected if the FB pin voltage exceeds the V_{FB_OVPL}threshold. When boost overvoltage is

detected, BSTOVPL_STATUS bit will be set in the BOOST_FAULT_STATUS register. The boost FET stops

switching, and the output voltage will be automatically limited. If the BSTOVPL_STATUS bit is continually set

(that is, reappears after clearing), it may indicate an loop issue in the application. Boost overvoltage low is

monitored during device Boost Softstart and Normal mode.

A second boost overvoltage high fault is detected if the FB pin voltage exceeds the V_{FB_OVPH}threshold or the

DISCHARGE pin voltage exceeds the V_{BST_OVPH}. The LP8866-Q1 device enters the fault recovery state to

protect system damage from a high boost voltage. When boost overvoltage is detected, BSTOVPH_STATUS bit

is set in the BOOST_FAULT_STATUS register. A fault interrupt is also generated. The device enters Fault

Recovery mode and then attempt to restart after 100 ms. Boost overvoltage high is monitored during Boost

Softstart and Normal mode.

7.3.9.2.2 Boost Overcurrent Faults (BSTOCP)

Boost overcurrent is detected if the FB pin voltage drops below the V_UVPthreshold for 110 ms. If the boost

overcurrent timer expires before the output voltage recovers, the BSTOCP_STATUS bit is set in the

BOOST_FAULT_STATUS register. The fault recovery state is entered, and a fault interrupt is generated. The

device will enter Fault Recovery mode and then attempt to restart after 100 ms. If the BSTOCP_STATUS bit is

permanently set, it may indicate an issue in the application. Boost overcurrent is monitored from the boost start,

and fault may trigger during boost start-up.

7.3.9.2.3 LEDSET Resistor Missing Faults (LEDSET)

The LEDSET resistor missing or invalid is detected if the resistor is not assembled or not valid value as

requested during the initialization. The LP8866-Q1 device defaults to 6-channel/200-mA configuration if the

LEDSET resistor is missing or invalid. The LEDSET_STATUS fault bit is set in the BOOST_FAULT_STATUS

register. The LEDSET resistor missing or invalid fault will not be monitored after initialization, so that the LP8866-

Q1 is operating in the configuration determined during initialization even though the LEDSET resistor is missing

or invalid after initialization.

7.3.9.2.4 MODE Resistor Missing Faults (MODESEL)

The MODE resistor missing or invalid is detected if the resistor is not assembled or not valid value as requested

during the initialization. LP8866-Q1 defaults to phase-shift PWM mode with I2C address 0x2A if the MODE

resistor is missing or invalid. The MODESEL_STATUS fault bit will be set in the BOOST_FAULT_STATUS

register. The MODE resistor missing or invalid fault is not monitored after initialization, so that the LP8866-Q1

operates in the mode determined during initialization even though the MODE resistor is missing or invalid after

initialization.

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7.3.9.2.5 FSET Resistor Missing Faults (FSET)

The FSET resistor missing or invalid for both BOOST_FSET and PWM_FSET is detected if any one of them is

not assembled or not a valid value as requested during the initialization. LP8866-Q1 defaults the switching

frequency of boost to 400 kHz if BOOST_FSET resistor is missing or invalid, or PWM dimming frequency to 305

Hz if PWM_FSET resistor is missing or invalid. The FSET_STATUS fault bit is set in the

BOOST_FAULT_STATUS register. The FSET resistor missing or invalid fault is not monitored after initialization,

so that the LP8866-Q1 device operates at the boost switching frequency and the PWM dimming frequency

determined during initialization even though the FSET resistor is missing or invalid after initialization.

7.3.9.2.6 ISET Resistor Out of Range Faults (ISET)

If the ISET pin resistor is shorted to GND during normal operation, the maximum current for each LED channel

can be calculated in Equation 20:

LED_CURRENT[11:0]

≈

’

I_{LED_ISET_FAULT}= I_{LED_LIMIT}

ì

∆

«

÷

◊

4095

(20)

where

• I_{LED_LIMIT}= 280 mA

LED_CURRENT[11:0] register will be automatically modified to 1/4 of latest programmed data. if it is not

programmed after device enabling, the default value of LED_CURRENT[11:0] register is 0xFFF and

automatically modified to 0x3FF after the fault occurs. If ISET pin voltage returns back to above 1.1 V, the

LED_CURRENT[11:0] register data automatically returns to latest programmed data. The ISET_STATUS fault bit

will be set in the BOOST_FAULT_STATUS register and the INT pin is triggered.

7.3.9.2.7 Thermal Shutdown Faults (TSD)

If the die temperature of LP8866-Q1 reaches the thermal shutdown threshold T_SD, the boost, power-line FET,

and LED outputs on LP8866-Q1 shuts down to protect the device from damage. Fault status bit TSD_STATUS

bit will be set, and the INT pin will be triggered. The device restarts the power-line FET, the boost, and LED

outputs when temperature drops by TSD_HYS amount.

7.3.9.3 LED Faults

7.3.9.3.1 Open LED Faults (OPEN_LED)

During normal boost operation, boost voltage is raised if any of the used LED outputs falls below the

LED_DRV_HEADROOM threshold level. Open LED fault is detected if boost output voltage has reached the

maximum and at least one LED output is still below the threshold. The open string is then disconnected from the

boost adaptive control loop and its output is disabled. Any LED fault sets the status bit LED_STATUS and an

interrupt is generated unless LED interrupt is disabled. The detail of open LED faults can be read from bits

OPEN_LED and LEDx_FAULT (x = 1...6). These bits maintain their value until device power-down. But the

LED_STATUS bit could be cleared by the interrupt clearing procedure. If a new LED fault is detected,

LED_STATUS is set and an interrupt generated again.

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OUT1~6 PIN

VOLTAGE

Open LED fault

when

V_BOOST= MAX

Short LED fault ( at least one

output should be between

LOW_COMP and MID COMP)

No actions

Short LED

Fault

Open LED Fault

LED Short to

GND Fault

V_LEDSHORT

V_HEADROOM+V_{HEADROOM_HYS}

V_HEADROOM

V_SHORTGND

Normal

Fault Conditions

Conditions

图7-18. LED Open and Short Detection Logic

7.3.9.3.2 Short LED Faults (SHORT_LED)

Short LED fault is detected if one or more LED outputs are above the V_LEDSHORTtypical 5.4 V and at least one

LED output is inside the normal operation window (see 图 7-18). Shorted string is disconnected from the boost

adaptive control loop and the LED PWM output is disabled. LED_STATUS status bit is set and an interrupt

generated similarly as in open LED case. Detailed shorted LED fault can be read from bits SHORT_LED and

LEDx_FAULT (x = 1...6), indicating the faulty LED) in LED_FAULT_STATUS register.

In HUD application, when output channels are connected as groups and only one or two groups are active, one

more special condition will trigger the short LED fault. This is when boost adaptive voltage comes to minimum

and one of the LED channels voltage is still higher than V_HEADROOM+ V_{HEADROOM_HYS}

.

7.3.9.3.3 LED Short to GND Faults (GND_LED)

During boost soft start and normal boost operation, if LED output is lower than V_SHORTGNDfor 20 ms, device

turns off the corresponding LED output channel and output a typical 6-mA current for 300-µs period again. After

this operation, if output voltage is still lower than V_HEADROOM, LED short to GND fault will be reported.

If LED short to GND is reported, boost, LED outputs and power-line FET is turned off, the device will enter Fault

Recovery mode. LED_STATUS bit is set and an interrupt generated similarly as in open LED case. LED short to

GND fault reason can be read from bits LED_GND and LEDx_FAULT (x = 1...6) in LED_FAULT_STATUS

register. These bits maintain their value until device powers are down while the LED_STATUS bit is cleared by

the interrupt clearing procedure.

7.3.9.3.4 Invalid LED String Faults (INVSTRING)

During device initialization, any of un-used LED outputs pins are checked whether connected to GND or not. If

they are not connected to GND as expected, the LP8866-Q1 reports invalid string fault and tries to function

normally if possible. The INVSTRING_STATUS fault bit is set in the LED_FAULT_STATUS register, and the INT

pin is triggered. The LEDSET resistor missing or invalid fault is not detected after initialization, so that the

LP8866-Q1 operates in the configuration determined during initialization even though the LEDSET resistor is

missing or invalid after initialization.

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7.3.9.3.5 I2C Timeout Faults

If chip receives I2C command without STOP signal for 500 ms, I2C communication block auto resets and waits

for the next command. I2C_ERROR_STATUS fault bit is set in the LED_FAULT_STATUS register, and the INT

pin is triggered.

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7.4 Device Functional Modes

7.4.1 State Diagram

SHUTDOWN

VDD > VDD_UVLO

EN = High

DEVICE INIT

15 ms

STANDBY

100ms

FAULT

PL FET

SOFTSTART

FAULT RECOVERY

25 ms

FAULT

BOOST

SOFTSTART

50 ms

FAULT

All LED channel have been disabled

due to open or short faults

NORMAL

LATCH FAULT

EN = 0

DISCHARGE DONE

And EN = 0

EN = 0

DISCHARGE

图7-19. State Machine Diagram

7.4.2 Shutdown

When EN is pulled low, boost, power-line FET, and LED outputs are turned off, and the device tries to discharge

the boost output for 400 ms. After this, the device is totally turned off.

7.4.3 Device Initialization

After POR is released device initialization begins. During this state the LDO is started up, EEPROM default and

trim configurations are loaded, LEDSET, MODE, BOOST_FSET and PWM_FSET resistors are detected.

7.4.4 Standby Mode

Starting from Standby mode, the device can be accessed with I2C to change any configuration registers.

Standby Mode is immediately switched to Power-line FET Soft Start mode if there's no fault.

7.4.5 Power-line FET Soft Start

Power-line FET is gradually enabled during this 25ms long state. Boost input and output capacitors are charged

to V_INlevel. V_INfaults for OCP, OVP, and UVP and fault for LED short to GND are enabled.

7.4.6 Boost Start-Up

Boost voltage is ramped to initial boost voltage level with reduced current limit for 50 ms. All boost faults are now

enabled.

7.4.7 Normal Mode

LED drivers are enabled when brightness is greater than zero. All LED faults are active.

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7.4.8 Fault Recovery

Some critical faults can trigger fault recover state. LED drivers, boost converter, and power-line FET are disabled

for 100 ms, and the device attempts to restart from standby mode if EN is still high and brightness is greater than

zero.

7.4.9 Latch Fault

If all LED strings are disabled due to faults then the LP8866-Q1 enters the latch fault mode. This state can be

exited only by pulling the EN pin low.

7.4.10 Start-Up Sequence

PL FET

DEVICE

NORMAL

SHUTDOWN

STANDBY

BOOST SOFTSTART

INIT

SOFTSTART

VIN

EN

VDD

PWM

INPUT

V_INIT

BOOST

VOUT

V_IN

LEDx

图7-20. Start-Up Sequence Diagram

7.5 Programming

7.5.1 I2C-Compatible Interface

The LP8866-Q1 device supports I2C interface to access and change the configuration. The 7-bit base slave

address is 0x2A or 0x2B. The address could be configured through the resistor settings of MODE pin.

Write I2C transactions are made up of 4 bytes. The first byte includes the 7-bit slave address and Write bit. The

7-bit slave address selects the LP8866-Q1 slave device. The second byte is eight bits register address. The last

two bytes are the 16-bit register value.

Read I2C transactions are made up of 5 bytes. The first byte includes the 7-bit slave address and Write bit. The

7-bit slave address selects the LP8866-Q1 slave device. The second byte is eight bits register address. The third

byte includes the 7-bit slave address and Read bit. The last two bytes are the 16-bit register value returned from

the slave.

where

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• W bit = 1

图7-21. I2C Write

where

• R bit = 0

• W bit = 1

图7-22. I2C Read

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7.5.2 Programming Examples

7.5.2.1 General Configuration Registers

The LP8866-Q1 does not require any serial interface configuration. It can be simply controlled with the EN pin

and PWM pin. Most of the device configuration is accomplished using external resistor values. If I2C interface is

available then extended configuration is possible. The configuration registers can be written from standby state

to normal state as shown in 表7-10.

表7-10. Configuration Registers

REGISTER NAME

ADV_SLOPE_ENABLE

FUNCTION

Enables advance sloper S-shape smoothing function.

DITHER_SELECT

SLOPE_SELECT

BRT_MODE

Selects up to 3 bits of PWM dither for added dimming resolution.

Selects duration for linear brightness sloper.

Selects PWM pin or DISPLAY_BRT register for brightness control.

Selects up to 2 bits boost switching frequency spread spectrum range.

Selects up to 2 bits boost switching frequency spread spectrum modulation frequency.

Enables pseudo random modulation for boost switching spread spectrum frequency.

SPREAD_RANGE

SPREAD_MOD_FREQ

SPREAD_PSEUDO_EN

7.5.2.2 Clearing Fault Interrupts

The LP8866-Q1 has an INT pin to alert the host when a fault occurs. If I2C interface is available, the Interrupt

Fault Status registers can be read back to learn which fault(s) have been detected. These status bits are located

in the SUPPLY_STATUS, BOOST_STATUS and LED_STATUS registers. Each interrupt status has a STATUS bit

and a CLEAR bit. To clear a fault interrupt status a 1 must be written to both the STATUS bit and CLEAR bit at

the same time.

7.5.2.3 Disabling Fault Interrupts

By default, most of the LP8866-Q1 faults trigger the INT pin. Each fault has two INT_EN bits. These bits are

located in the SUPPLY_INT_EN, BOOST_INT_EN, and LED_INT_EN registers. If the INT_EN bit is read and

returns 2b'10, the INT pin is triggered when that fault occurs. The fault interrupt can be disabled by writing 2b'01

to its INT_EN bits, or it can be enabled by writing 2b'11 to its INT_EN bits. There is also a GLOBAL fault interrupt

that can be disabled to prevent any faults from triggering the INT pin.

7.5.2.4 Diagnostic Registers

The LP8866-Q1 contains several diagnostic registers than can be read with the serial interface for debugging or

additional device information. 表7-11 is a summary of the available registers.

表7-11. Diagnostic Registers

REGISTER NAME

FSM_LIVE_STATUS

FUNCTION

Current state of the functional state machine

PWM_INPUT_STATUS

LED_PWM_STATUS

Measured 16-bit duty cycle of the PWM pin input

16-bit LED PWM duty cycle from state machine

12-bit LED current DAC value from state machine

LED_CURRENT_STATUS

10-bit value for adaptive boost voltage target —value is linear between

VBOOST_MIN and VBOOST_MAX calculations

VBOOST_STATUS

MODE_SEL_CFG

LED_STRING_CFG

BOOST_FREQ_SEL

PWM_FREQ_SEL

Dimming mode configuration from MODE detection

LED string phase configuration from LEDSET detection

Boost switching frequency value from BST_FSET detection

LED PWM frequency value from PWM_FSET detection

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7.6 Register Maps

7.6.1 FullMap Registers

表 7-12 lists the memory-mapped registers for the FullMap registers. All register offset addresses not listed in 表

7-12 should be considered as reserved locations and the register contents should not be modified.

表7-12. FULLMAP Registers

Offset

00h

02h

04h

06h

08h

0Ah

0Ch

0Eh

10h

12h

14h

16h

18h

1Ah

1Ch

1Eh

Acronym

Register Name

Section

Go

BRT_CONTROL

Display Brightness

LED Current

LED_CURR_CONFIG

USER_CONFIG1

Go

User Config 1

Go

USER_CONFIG2

User Config 2

Go

SUPPLY_INT_EN

Supply Interrupt Enable

Boost Interrupt Enable

LED Interrupt Enable

Supply Fault Status

Boost Fault Status

Go

BOOST_INT_EN

Go

LED_INT_EN

Go

SUPPLY_STATUS

Go

BOOST_STATUS

Go

LED_STATUS

LED Fault Status

Go

FSM_DIAGNOSTICS

PWM_INPUT_DIAGNOSTICS

PWM_OUTPUT_DIAGNOSTICS

LED_CURR_DIAGNOSTICS

ADAPT_BOOST_DIAGNOSTICS

AUTO_DETECT_DIAGNOSTICS

Device State Diagnostics

PWM Input Diagnostics

PWM Output Diagnostics

LED Current Diagnostics

Adaptive Boost Diagnostics

Auto Detect Diagnostics

Go

Complex bit access types are encoded to fit into small table cells. 表 7-13 shows the codes that are used for

access types in this section.

表7-13. FullMap Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

Value after reset or the default

value

–n

7.6.1.1 BRT_CONTROL Register (Offset = 00h) [reset = 0h]

BRT_CONTROL is shown in 图7-23 and described in 表7-14.

Return to Summary Table.

图7-23. BRT_CONTROL Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DISPLAY_BRT

R/W-0h

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表7-14. BRT_CONTROL Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

DISPLAY_BRT

R/W

0h

Display Brightness Register

7.6.1.2 LED_CURR_CONFIG Register (Offset = 02h) [reset = 0FFFh]

LED_CURR_CONFIG is shown in 图7-24 and described in 表7-15.

Return to Summary Table.

图7-24. LED_CURR_CONFIG Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

R/W-0h

LED_CURRENT

R/W-FFFh

表7-15. LED_CURR_CONFIG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15-12

11-0

RESERVED

LED_CURRENT

0h

These bits are reserved.

FFFh

LED current control for all LED outputs

7.6.1.3 USER_CONFIG1 Register (Offset = 04h) [reset = 8A3h]

USER_CONFIG1 is shown in 图7-25 and described in 表7-16.

Return to Summary Table.

图7-25. GROUPING1 Register

15

14

13

12

11

10

9

1

8

0

RESERVED

BRT_MODE

R/W-0h

SPREAD_PSE

UDO_EN

SPREAD_MOD_FREQ

SPREAD_RANGE

R/W-0h

7

R/W-0h

R/W-2h

6

5

4

3

2

SLOPE_SELECT

DITHER_SELECT

ADV_SLOPE_E

NABLE

RESERVED

R/W-5h

R/W-0h

R/W-1h

表7-16. USER_CONFIG1 Register Field Descriptions

Bit

15

14

Field

Type

Reset

Description

RESERVED

R/W

0h

This bit is reserved.

SPREAD_PSEUDO_EN

R/W

0h

0h = Pseudo Random SS disabled

1h = Pseudo Random SS enabled

13-12

SPREAD_MOD_FREQ

SPREAD_RANGE

R/W

0h

Boost spread spectrum modulation frequency

0h = 200 Hz

1h = 500 Hz

2h = 800 Hz

3h = 1.2 kHz

11-10

R/W

2h

OSC_BST spread spectrum range

0h = 3.3%

1h = 4.3%

2h = 5.3%

3h = 7.2%

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表7-16. USER_CONFIG1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

9-8

BRT_MODE

R/W

0h

Select PWM pin or DISPLAY_BRT register for brightness controll

0h = Brightness controlled by PWM input

1h = Reserved

2h = Brightness controlled by DISPLAY_BRT register

3h = Reserved

7-5

SLOPE_SELECT

R/W

5h

Select duration for linear brightness sloper

0h = Disabled

1h = 1 ms

2h = 2 ms

3h = 50 ms

4h = 100 ms

5h = 200 ms

6h = 300 ms

7h = 500 ms

Times are for linear slope mode. Advanced sloper will increase

durations while adding additional smoothing to brightness transitions.

1 ms and 2 ms sloper times are intended to be used only in linear

mode. 50 ms to 500 ms sloper durations may be used with or without

advanced sloper function.

4-2

DITHER_SELECT

R/W

0h

Dither mode select

0h = Dither Disabled

1h = 1-bit Dither

2h = 2-bit Dither

3h = 3-bit Dither

4h = 4-bit Dither

1

0

ADV_SLOPE_ENABLE

RESERVED

R/W

1h

0h = Linear Sloping

1h = Advanced Sloping

This bit is reserved.

7.6.1.4 USER_CONFIG2 Register (Offset = 06h) [reset = 100h]

USER_CONFIG2 is shown in 图7-26 and described in 表7-17.

Return to Summary Table.

图7-26. USER_CONFIG2 Register

15

14

13

12

11

10

2

9

1

8

RESERVED

EN_LED_GND_

DETECT

R/W-0h

4

R/W-1h

0

7

6

5

3

RESERVED

R/W-0h

LED6_SHORT_ LED5_SHORT_ LED4_SHORT_ LED3_SHORT_ LED2_SHORT_ LED1_SHORT_

DISABLE

R/W-0h

表7-17. USER_CONFIG2 Register Field Descriptions

Bit

15-9

Field

Type

Reset

Description

RESERVED

R/W

0h

These bits are reserved.

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表7-17. USER_CONFIG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

8

EN_LED_GND_DETECT R/W

1h

Enable LED short to ground detection during Boost_SS and normal

stage

0h = Disable

1h = Enable

7-6

5

RESERVED

R/W

0h

These bits must write 0 for normal operation.

LED6_SHORT_DISABLE R/W

LED5_SHORT_DISABLE R/W

LED4_SHORT_DISABLE R/W

LED3_SHORT_DISABLE R/W

LED2_SHORT_DISABLE R/W

LED1_SHORT_DISABLE R/W

Disable LED string6 internal short fault.

0h = Enable

1h = Disable

4

3

2

1

0

0h

Disable LED string5 internal short fault.

0h = Enable

1h = Disable

Disable LED string4 internal short fault.

0h = Enable

1h = Disable

Disable LED string3 internal short fault.

0h = Enable

1h = Disable

Disable LED string2 internal short fault.

0h = Enable

1h = Disable

Disable LED string1 internal short fault.

0h = Enable

1h = Disable

7.6.1.5 SUPPLY_INT_EN Register (Offset = 08h) [reset = 2AAAh]

SUPPLY_INT_EN is shown in 图7-27 and described in 表7-18.

Return to Summary Table.

图7-27. SUPPLY_INT_EN Register

15

14

13

12

11

10

2

9

8

RESERVED

R/W-0h

CP_INT_EN

R/W-2h

CPCAP_INT_EN

R/W-2h

BSTSYNC_INT_EN

R/W-2h

7

6

5

4

3

1

0

VINOCP_INT_EN

R/W-2h

VDDUVLO_INT_EN

R/W-2h

VINOVP_INT_EN

R/W-2h

VINUVLO_INT_EN

R/W-2h

表7-18. SUPPLY_INT_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

R/W

0h

15-14

13-12

These bits are reserved.

BSTSYNC_INT_EN

R/W

2h

Missing boost sync interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

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表7-18. SUPPLY_INT_EN Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

11-10

CP_INT_EN

R/W

2h

Charge pump interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

9-8

7-6

5-4

3-2

1-0

CPCAP_INT_EN

VINOCP_INT_EN

VDDUVLO_INT_EN

VINOVP_INT_EN

VINUVLO_INT_EN

R/W

2h

Charge pump cap missing interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

V_INover-current interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

V_DDunder-voltage interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

V_INover-voltage interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

V_INunder-voltage interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

7.6.1.6 BOOST_INT_EN Register (Offset = 0Ah) [reset = A028h]

BOOST_INT_EN is shown in 图7-28 and described in 表7-19.

Return to Summary Table.

图7-28. BOOST_INT_EN Register

15

14

13

12

11

10

9

8

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图7-28. BOOST_INT_EN Register (continued)

TSD_INT_EN

R/W-2h

ISET_INT_EN

LEDSET_INT_EN

MODE_INT_EN

R/W-2h

7

6

5

4

3

2

1

0

FSET_INT_EN

R/W-2h

BSTOCP_INT_EN

R/W-2h

BSTOVPH_INT_EN

R/W-2h

Reserved

R/W-0h

表7-19. BOOST_INT_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

13-12

11-10

9-8

TSD_INT_EN

R/W

2h

Thermal shutdown interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

ISET_INT_EN

R/W

2h

0h

2h

ISET resistor short to ground interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

LEDSET_INT_EN

MODE_INT_EN

FSET_INT_EN

BSTOCP_INT_EN

Missing LEDSET resistor interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

Missing MODE resistor interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

7-6

Missing FSET resistor interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

5-4

Boost over-current interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

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表7-19. BOOST_INT_EN Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-2

BSTOVPH_INT_EN

R/W

2h

Boost over-voltage high interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

1-0

Reserved

R/W

0h

These bits are reserved.

7.6.1.7 LED_INT_EN Register (Offset = 0Ch) [reset = AAh]

LED_INT_EN is shown in 图7-29 and described in 表7-20.

Return to Summary Table.

图7-29. LED_INT_EN Register

15

14

13

12

11

10

2

9

1

8

0

RESERVED

R/W-0h

7

6

5

4

3

GLOBAL_INT_EN

I2C_ERROR_INT_EN

R/W-2h

INVSTRING_INT_EN

R/W-2h

VINUVP_INT_EN

R/W-2h

表7-20. LED_INT_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

15-8

RESERVED

R/W

0h

These bits are reserved.

7-6

5-4

3-2

GLOBAL_INT_EN

R/W

2h

Global interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

I2C_ERROR_INT_EN

I2C time out interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

INVSTRING_INT_EN

Invalid LED string configuration interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

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表7-20. LED_INT_EN Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1-0

LED_INT_EN

R/W

2h

LED open/internal short/short to GND interrupt enable

Read:

0h = Interrupt is currently disabled

2h = Interrupt is currently enabled

Write:

1h = Disable interrupt

3h = Enable interrupt

7.6.1.8 SUPPLY_STATUS Register (Offset = 0Eh) [reset = 0h]

SUPPLY_STATUS is shown in 图7-30 and described in 表7-21.

Return to Summary Table.

图7-30. SUPPLY_STATUS Register

15

14

13

12

11

10

9

8

CP_STATUS

CP_CLEAR

CPCAP_STATU CPCAP_CLEA

CRCERR_STAT CRCERR_CLE BSTSYNC_STA BSTSYNC_CLE

S

R

US

AR

TUS

AR

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

3

R/W-0h

2

R/W-0h

1

R/W-0h

0

VINOCP_STAT VINOCP_CLEA VDDUVLO_ST VDDUVLO_CL VINOVP_STAT VINOVP_CLEA VINUVLO_STA VINUVLO_CLE

US

R

ATUS

EAR

US

R

TUS

AR

R/W-0h

表7-21. SUPPLY_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

15

CRCERR_STATUS

CRCERR_CLEAR

BSTSYNC_STATUS

BSTSYNC_CLEAR

CP_STATUS

R/W

0h

CRC error fault status

0h = No fault

1h = Fault

14

13

12

11

10

9

R/W

0h

CRC error fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

Missing boost sync fault status

0h = No fault

1h = Fault

Missing boost sync fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

Charge pump fault status

0h = No fault

1h = Fault

CP_CLEAR

Charge pump fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

CPCAP_STATUS

Missing charge pump fault status

0h = No fault

1h = Fault

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表7-21. SUPPLY_STATUS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

8

CPCAP_CLEAR

R/W

0h

Missing charge pump fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

7

6

5

4

3

2

1

0

VINOCP_STATUS

VINOCP_CLEAR

VDDUVLO_STATUS

VDDUVLO_CLEAR

VINOVP_STATUS

VINOVP_CLEAR

VINUVLO_STATUS

VINUVLO_CLEAR

R/W

0h

V_INover-current fault status

0h = No fault

1h = Fault

V_INover-current fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

V_DDunder-voltage fault status

0h = No fault

1h = Fault

V_DDunder-voltage fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

V_INover-voltage fault status

0h = No fault

1h = Fault

V_INover-voltage fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

V_INunder-voltage fault status

0h = No fault

1h = Fault

V_INunder-voltage fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

7.6.1.9 BOOST_STATUS Register (Offset = 10h) [reset = 0h]

BOOST_STATUS is shown in 图7-31 and described in 表7-22.

Return to Summary Table.

图7-31. BOOST_STATUS Register

15

14

13

12

11

10

9

8

TSD_STATUS

TSD_CLEAR

ISET_STATUS ISET_CLEAR LEDSET_STAT LEDSET_CLEA MODESEL_ST MODESEL_CL

US

R/W-0h

3

R

R/W-0h

2

ATUS

R/W-0h

1

EAR

R/W-0h

0

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

FSET_STATUS FSET_CLEAR BSTOCP_STAT BSTOCP_CLE BSTOVPH_STA BSTOVPH_CL BSTOVPL_STA BSTOVPL_CLE

US

AR

TUS

EAR

TUS

AR

R/W-0h

表7-22. BOOST_STATUS Register Field Descriptions

Bit

Field

TSD_STATUS

Type

Reset

Description

15

R/W

0h

Thermal shutdown fault status

0h = No fault

1h = Fault

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表7-22. BOOST_STATUS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

14

TSD_CLEAR

R/W

0h

Thermal shutdown fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

13

12

11

10

9

ISET_STATUS

R/W

0h

ISET resistor short to ground fault status

0h = No fault

1h = Fault

ISET_CLEAR

ISET resistor short to ground fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

LEDSET_STATUS

LEDSET_CLEAR

MODESEL_STATUS

MODESEL_CLEAR

FSET_STATUS

Missing LED resistor fault status

0h = No fault

1h = Fault

Missing LED resistor fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

Missing MODE SEL resistor fault status

0h = No fault

1h = Fault

8

Missing MODE SEL resistor fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

7

Missing boost FSET resistor fault status

0h = No fault

1h = Fault

6

FSET_CLEAR

Missing boost FSET resistor fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

5

BSTOCP_STATUS

BSTOCP_CLEAR

BSTOVPH_STATUS

BSTOVPH_CLEAR

BSTOVPL_STATUS

BSTOVPL_CLEAR

Boost over-current fault status

0h = No fault

1h = Fault

4

Boost over-current fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

3

Boost OVP high fault status

0h = No fault

1h = Fault

2

Boost OVP high fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

1

Boost OVP low fault status

0h = No fault

1h = Fault

0

Boost OVP low fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status

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7.6.1.10 LED_STATUS Register (Offset = 12h) [reset = 0h]

LED_STATUS is shown in 图7-32 and described in 表7-23.

Return to Summary Table.

图7-32. LED_STATUS Register

15

14

13

12

11

10

9

8

RESERVED

I2C_ERROR_S I2C_ERROR_C INVSTRING_S INVSTRING_C LED_STATUS

LED_CLEAR

GND_LED

TATUS

R/W-0h

6

LEAR

R/W-0h

5

TATUS

R/W-0h

4

LEAR

R/W-0h

3

R/W-0h

7

R/W-0h

2

R/W-0h

1

R-0h

0

SHORT_LED

R-0h

OPEN_LED

R-0h

LED6_FAULT

R-0h

LED5_FAULT

R-0h

LED4_FAULT

R-0h

LED3_FAULT

R-0h

LED2_FAULT

R-0h

LED1_FAULT

R-0h

表7-23. LED_STATUS Register Field Descriptions

Bit

15

14

Field

RESERVED

Type

R/W

Reset

Description

0h

This bit is reserved

I2C_ERROR_STATUS

I2C_ERROR_CLEAR

INVSTRING_STATUS

INVSTRING_CLEAR

LED_STATUS

0h

I2C time out fault status

0h = No fault

1h = Fault

13

12

11

10

9

R/W

R

0h

I2C time out fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

Invalid string configuration fault status

0h = No fault

1h = Fault

Invalid string configuration fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

LED open/internal short/short to GND fault status

0h = No fault

1h = Fault

LED_CLEAR

LED open/internal short/short to GND fault clear

Write "1" to both Status bit and Clear bit at the same time to clear

interrupt register status and interrupt pin status

8

GND_LED

LED short to GND fault status

0h = No fault

1h = Fault

7

SHORT_LED

R

LED internal short Status

0h = No Fault

1h = Fault

Status is cleared with LED_STATUS bit

6

5

OPEN_LED

R

0h

LED open fault status

0h = No fault

1h = Fault

Status is cleared with LED_STATUS bit

LED6_FAULT

LED 6 Status

0h = No Fault

1h = Fault

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表7-23. LED_STATUS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

4

LED5_FAULT

R

0h

LED 5 Status

0h = No Fault

1h = Fault

3

2

1

0

LED4_FAULT

LED3_FAULT

LED2_FAULT

LED1_FAULT

R

0h

LED 4 Status

0h = No Fault

1h = Fault

LED 3 Status

0h = No Fault

1h = Fault

LED 2 Status

0h = No Fault

1h = Fault

LED 1 Status

0h = No Fault

1h = Fault

7.6.1.11 FSM_DIAGNOSTICS Register (Offset = 14h) [reset = 0h]

FSM_DIAGNOSTICS is shown in 图7-33 and described in 表7-24.

Return to Summary Table.

图7-33. FSM_DIAGNOSTICS Register

15

7

14

13

5

12

11

10

9

1

8

0

RESERVED

R-0h

6

4

3

2

RESERVED

R-0h

FSM_LIVE_STATUS

R-0h

表7-24. FSM_DIAGNOSTICS Register Field Descriptions

Bit

Field

Type

Reset

Description

15-5

4-0

RESERVED

R

0h

These bits are reserved

FSM_LIVE_STATUS

R

0h

Current state of the functional state machine

0h = DISABLED

1h = LDO_STARTUP

2h = OTP_READ

3h = STANDBY

4h-Fh = BOOST_STARTUP

10h = NORMAL

11h = SHUTDOWN

12h = FAULT_RECOVERY

13h = ALL_LED_FAULT

7.6.1.12 PWM_INPUT_DIAGNOSTICS Register (Offset = 16h) [reset = 0h]

PWM_INPUT_DIAGNOSTICS is shown in 图7-34 and described in 表7-25.

Return to Summary Table.

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图7-34. PWM_INPUT_DIAGNOSTICS Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PWM_INPUT_STATUS

R-0h

表7-25. PWM_INPUT_DIAGNOSTICS Register Field Descriptions

Bit

15-0

Field

Type

Reset

Description

PWM_INPUT_STATUS

R

0h

16-bit value for detected duty cycle of PWM input signal.

7.6.1.13 PWM_OUTPUT_DIAGNOSTICS Register (Offset = 18h) [reset = 0h]

PWM_OUTPUT_DIAGNOSTICS is shown in 图7-35 and described in 表7-26.

Return to Summary Table.

图7-35. PWM_OUTPUT_DIAGNOSTICS Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PWM_OUTPUT_STATUS

R-0h

表7-26. PWM_OUTPUT_DIAGNOSTICS Register Field Descriptions

Bit

15-0

Field

Type

Reset

Description

PWM_OUTPUT_STATUS

R

0h

16-bit value for configured duty cycle of PWM output signal.

7.6.1.14 LED_CURR_DIAGNOSTICS Register (Offset = 1Ah) [reset = 0h]

LED_CURR_DIAGNOSTICS is shown in 图7-36 and described in 表7-27.

Return to Summary Table.

图7-36. LED_CURR_DIAGNOSTICS Register

15

7

14

6

13

12

11

10

9

8

0

RESERVED

R-0h

LED_CURRENT_STATUS

R-0h

5

4

3

2

1

LED_CURRENT_STATUS

R-0h

表7-27. LED_CURR_DIAGNOSTICS Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

15-12

11-0

R

0h

These bits are reserved.

LED_CURRENT_STATUS R

0h

12-bit Current DAC Code that Brightness path is driving to OUT1-6

output.

7.6.1.15 ADAPT_BOOST_DIAGNOSTICS Register (Offset = 1Ch) [reset = 0h]

ADAPT_BOOST_DIAGNOSTICS is shown in 图7-37 and described in 表7-28.

Return to Summary Table.

图7-37. ADAPT_BOOST_DIAGNOSTICS Register

15

14

13

12

11

10

9

8

RESERVED

VBOOST_STATUS

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图7-37. ADAPT_BOOST_DIAGNOSTICS Register (continued)

R-0h

1

7

6

5

4

3

2

0

VBOOST_STATUS

R-0h

表7-28. ADAPT_BOOST_DIAGNOSTICS Register Field Descriptions

Bit

Field

Type

Reset

Description

15-11

10-0

RESERVED

R

0h

These bits are reserved.

VBOOST_STATUS

R

0h

11-bit Boost Voltage Code that Adaptive Voltage Control Loop

sending to Analog Boost Block.

In two-resistor method, Boost Output Voltage =((1+R1/R2)*1.21V)+

(R1*18.9nA*VBOOST_STATUS)

7.6.1.16 AUTO_DETECT_DIAGNOSTICS Register (Offset = 1Eh) [reset = 0h]

AUTO_DETECT_DIAGNOSTICS is shown in 图7-38 and described in 表7-29.

Return to Summary Table.

图7-38. AUTO_DETECT_DIAGNOSTICS Register

15

RESERVED

R-0h

14

6

13

12

11

RESERVED

R-0h

10

9

8

0

AUTO_PWM_FREQ_SEL

AUTO_LED_STRING_CFG

R-0h

5

R-0h

1

7

4

3

2

RESERVED

AUTO_BOOST_FREQ_SEL

R-0h

MODE_SEL

R-0h

表7-29. AUTO_DETECT_DIAGNOSTICS Register Field Descriptions

Bit

15

Field

Type

Reset

Description

RESERVED

R

0h

This bit is reserved

14-12

AUTO_PWM_FREQ_SEL

R

0h

LED PWM frequency value from PWM_SEL resistor detection

0h = 152 Hz

1h = 305 Hz

2h = 610 Hz

3h = 1221 Hz

4h = 2441 Hz

5h = 4883 Hz

6h = 9766 Hz

7h = 19531 Hz

11

RESERVED

R

0h

This bit is reserved

10-8

AUTO_LED_STRING_CF

G

LED string configuration from LED_SET resistor detection

0h = 6 separate strings

1h = 5 separate strings

2h = 4 separate strings

3h = 3 separate strings

4h = 2 separate strings

5h = 6 channel outputs connected in 3 groups to drive 3 strings

6h = 6 channel outputs connected in 2 groups to drive 2 strings

7h = 6 channel outputs connected together to drive 1 string

7-6

RESERVED

R

0h

These bits are reserved

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表7-29. AUTO_DETECT_DIAGNOSTICS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-3

AUTO_BOOST_FREQ_S

EL

R

0h

Boost switching frequency value from PWM_FSET resistor detection

0h = 100 kHz

1h = 200 kHz

2h = 303 kHz

3h = 400 kHz

4h = 500 kHz

5h = 1818 kHz

6h = 2000 kHz

7h = 2222 kHz

2-0

MODE_SEL

R

0h

LED dimming MODE value from MODE detection

0h = PWM mode, I2C address 0x2B

1h = 12.5% hybrid dimming mode, I2C address 0x2B

2h = Constant current mode, I2C address 0x2B

3h = Direct PWM, I2C address 0x2B

4h = PWM mode, I2C address 0x2A

5h = 12.5% hybrid dimming mode, I2C address 0x2A

6h = Constant current mode, I2C address 0x2A

7h = Direct PWM, I2C address 0x2A

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8 Application and Implementation

Note

以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适

用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The LP8866-Q1 device is designed for automotive applications, and an input voltage V_INis intended to be

connected to the vehicle battery. Depending on the input voltage, the device may be used in either boost mode

or SEPIC mode. The device is internally powered from the VDD pin, and voltage must be in 2.7-V to 5.5-V

range. The device has flexible configurability through external components or by an I2C interface. If the VDD

voltage is not high enough to drive an external nMOSFET gate, an internal charge pump must be used to power

the gate driver (GD pin).

8.2 Typical Applications

8.2.1 Full Feature Application for Display Backlight

图 8-1 shows a full application for the LP8866-Q1 device in a boost topology. It supports 6 LED strings in display

mode, each at 150 mA, with an automatic 60° phase shift. Brightness control register is used for LED dimming

method through I2C communication. The charge pump is enabled for a 400-kHz boost switching frequency with

spread spectrum.

L

R_ISENSE

V_IN

V_OUT

R_SD

C_IN

C_OUT

R_G

SD

R_FB1

R_FB3

VSENSE_N

VSENSE_P

GD

PGND

ISNS

R_UVLO1

R_UVLO2

R_FB2

R_SENSE

UVLO

ISNSGND

FB

VDD

LP8866(S)-Q1

VDD

C1N

C_VDD

DISCHARGE

LED_GND

C_2x

C1P

C_PUMP

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

CPUMP

SGND

EN

HOST

I2C

PWM

INT

R_{BST_FSET}

R_{PWM_FSET}

R_{LED_SET}

BST_FSET

PWM_FSET

SDA

SCL

LED_SET

ISET

VDD

BST_SYNC

MODE

R_ISET

R_MODE

图8-1. Full Feature Application for Display Backlight

8.2.1.1 Design Requirements

This typical LED-driver application is designed to meet the parameters listed in 表8-1:

表8-1. LP8866-Q1 Full-Feature Design Parameters

DESIGN PARAMETER

VIN voltage range

VALUE

5 V to 20 V (Quiescent Voltage)

VDD voltage

3.3 V

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表8-1. LP8866-Q1 Full-Feature Design Parameters (continued)

DESIGN PARAMETER

VALUE

LED strings configuration

6 strings, 7 LEDs in series

Charge pump

Enabled

I2C

Brightness control

Output configuration

LED string current

Boost frequency

Inductor

OUT1 to OUT6 are in phase shift mode (60°)

150 mA

400 kHz

22 µH at 6.5-A saturation current

R_ISENSE

20 mΩ

Power-line FET

R_SENSE

Enabled

30 mΩ

Input/Output capacitors

Spread spectrum

Discharge function

C_INand C_OUT: 1 × 33-µF electrolytic + 1 × 10-µF ceramic

Enabled

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Inductor Selection

There are a few things to consider when choosing an inductor: inductance, current rating, and DC resistance

(DCR). 表 8-2 shows recommended inductor values for each operating frequency. The LP8866-Q1 device

automatically sets internal boost compensation controls depending on the selected switching frequency.

表8-2. Inductance Values for Boost Switching Frequencies

SW FREQUENCY (kHz)

INDUCTANCE (µH)

100

200

47

33

22

10

303

400

500

1818

2000

2222

The current rating of inductor must be at least 25% higher than maximum boost switching current I_SW(max), which

can be calculated with Equation 21. TI recommends to use an inductor with low DCR to achieve good efficiency.

Efficiency varies with load condition, switching frequency, and components. 80% can be used as a typical

estimation. 65% efficiency needs to take into account in extreme condition.

I_OUT(max)

DI_L

2

I_SW(max)

=

+

1- D

(21)

where

• ΔI_L= V_IN(min)× D / ƒ_SW× L

• D = 1 –V_IN(min)× η/ V_OUT

• I_SW(max): Maximum switching current

• ΔI_L: Inductor ripple current

• I_OUT(max): Maximum output current

• D: Boost duty cycle

• V_IN(min): Minimum input voltage

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• ƒ_SW: Minimum switching frequency of the converter

• L: Inductance

• V_OUT: Output voltage

• η: Efficiency of boost converter

8.2.1.2.2 Output Capacitor Selection

Recommended voltage rating for output capacitors is 50% higher than maximum output voltage level.

Capacitance value determines voltage ripple and boost stability. The DC-bias effect can reduce the effective

capacitance significantly, by up to 80%, a consideration for capacitance value selection. The conservative target

effective capacitance is 50 µF to achieve good phase and gain margin levels. A design table in product webpage

could be refered for the target effective capacitance in a certain application. TI recommends using 33-µF Al-

polymer electrolytic capacitor together with 10-µF ceramic capacitors in parallel to reduce ripple, increase

stability, and reduce ESR effect.

8.2.1.2.3 Input Capacitor Selection

Recommended input capacitance is the same as output capacitance although input capacitors are not as critical

to boost operation. Input capacitance can be reduced but must ensure enough filtering for input power.

8.2.1.2.4 Charge Pump Output Capacitor

TI recommends a ceramic capacitor with at least 10-V voltage rating for the output capacitor of the charge pump.

A 10-μF capacitor can be used for most applications.

8.2.1.2.5 Charge Pump Flying Capacitor

TI recommends a ceramic capacitor with at least 10-V voltage rating for the flying capacitor of the charge pump.

One 2.2-μF capacitor connecting C1P and C1N pins can be used for most applications.

8.2.1.2.6 Output Diode

A Schottky diode must be used for the boost output diode. Current rating must be at least 25% higher than the

maximum output current. Schottky diodes with a low forward drop and fast switching speeds are ideal for

increasing efficiency. At maximum current, the forward voltage must be as low as possible; less than 0.5 V is

recommended. Reverse breakdown voltage of the Schottky diode must be significantly larger than the output

voltage, 25% higher voltage rating is recommended. Do not use ordinary rectifier diodes, because slow switching

speeds and long recovery times cause efficiency and load regulation to suffer.

8.2.1.2.7 Switching FET

Gate-drive voltage for the FET is 5V. Switching FET is a critical component for determining power efficiency of

the boost converter. Several aspects need to be considered when selecting switching FET such as voltage and

current rating, R_DSON, power dissipation, thermal resistance and rise/fall times. An N type MOSFET with at least

25% higher voltage rating than maximum output voltage must be used. Current rating of switching FET should

be same or higher than inductor rating. R_DSONmust be as low as possible, less than 20 mΩ is recommended.

Thermal resistance (R_θJA) must also be low to dissipate heat from power loss on switching FET. In most cases,

a resistance is recommended between GD pin and Switching FET's gate terminal. It could be used to control the

rising/falling time of the switching FET. This gate resistance could offer the flexibility of balancing between EMC

performance and efficiency.

8.2.1.2.8 Boost Sense Resistor

The R_SENSEresistor determines the boost overcurrent limit and is sensed every boost switching cycle. A high-

power 20-mΩ resistor can be used for sensing the boost SW current and setting maximum current limit at 10 A

(typical). R_SENSEcan be increased to lower this limit and can be calculated with Equation 22. In typical condition,

to avoid too much efficiency loss on R_SENSEresistor, boost overcurrent limit is recommended to be set above 4A,

therefore R_SENSEdoesn't exceed 50 mΩ. Power rating can be calculated from the inductor current and sense

resistor resistance value.

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200 mV

R_SENSE

=

I_{BOOST _OCP}

(22)

where

• R_SENSE: boost sense resistor (mΩ)

• I_{BOOST_OCP}: boost overcurrent limit

8.2.1.2.9 Power-Line FET

A power line FET can be used to disconnect input power from boost input to protect the LP8866-Q1 device and

boost components in case an overcurrent event occurs. A P type MOSFET is used for the power-line FET.

Voltage rating must be at least 25% higher than maximum input voltage level. Low R_DSONis important to reduce

power loss on the FET — less than 20 mΩ is recommended. Current rating for the FET must be at least 25%

higher than input peak current. Minimum Gate-to-Source voltage (V_GS) to turn on transistor fully must be less

than minimum input voltage; use a 20-kΩresistor between the pFET gate and source.

8.2.1.2.10 Input Current Sense Resistor

A high-power resistor can be used for sensing the boost input current. Overcurrent condition is detected when

the voltage across R_ISENSEreaches 220 mV. Typical 20-mΩsense resistor is used to set 11-A input current limit.

Sense resistor value can be increased to lower overcurrent limit for application as needed. Power rating can be

calculated from the input current and resistance value.

8.2.1.2.11 Feedback Resistor Divider

Feedback resistors R_FB1and R_FB2determine the maximum boost output level. Output voltage can be calculated

as in Equation 23:

≈

∆

«

’

V_BG

V_{OUT_MAX}

=

+ I_{SEL_MAX}ì R_FB1+ V_BG

÷

R_FB2

◊

(23)

where

• V_BG= 1.21 V

• I_{SEL_MAX}= 38.7 µA

• R_FB1/ R_FB2normal recommended range is 7~15

8.2.1.2.12 Critical Components for Design

图8-2 shows the critical part of circuitry: boost components, the LP8866-Q1 internal charge pump for gate-driver

powering, and powering/grounding of LP8866-Q1 . Schematic example is shown in 图8-2.

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L

R_ISENSE

V_IN

V_OUT

R_SD

C_IN

C_OUT

R_G

SD

R_FB1

R_FB3

VSENSE_N

VSENSE_P

GD

PGND

ISNS

R_UVLO1

R_UVLO2

R_FB2

R_SENSE

UVLO

ISNSGND

FB

VDD

LP8866(S)-Q1

VDD

C1N

C_VDD

DISCHARGE

LED_GND

C_2x

C1P

C_PUMP

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

CPUMP

SGND

EN

HOST

I2C

PWM

INT

R_{BST_FSET}

R_{PWM_FSET}

R_{LED_SET}

BST_FSET

PWM_FSET

SDA

SCL

LED_SET

ISET

VDD

BST_SYNC

MODE

R_ISET

R_MODE

图8-2. Critical Components for Full Feature Design

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表8-3. Recommended Component Values for Full Feature Design Example

REFERENCE DESIGNATOR

DESCRIPTION

20 mΩ, 3 W

20 kΩ, 0.1 W

30 mΩ, 3 W

NOTE

R_ISENSE

R_SD

Input current sensing resistor

Power-line FET gate pullup resistor

Boost current sensing resistor

R_SENSE

Gate resistor to control the rising/falling time

of nMOSFET for EMC

R_G

15 Ω, 0.1 W

These UVLO resistor settings set the

VIN_UVLO rising voltage at 3.75 V,

VIN_UVLO falling voltage at 3.35 V

R_UVLO1

R_UVLO2

76.8 kΩ, 0.1 W

20.5 kΩ, 0.1 W

Not needed unless 100-kΩrestrictions on

resistors

R_FB3

0 Ω, 0.1 W

R_FB2

R_FB1

Bottom feedback divider resistor

Top feedback divider resistor

100 kΩ, 0.1 W

910 kΩ, 0.1 W

3.92 kΩ, 0.1 W

20.8 kΩ, 0.1 W

R_{BST_FSET}

R_ISET

Boost frequency set resistor (400 kHz)

Current set resistor (150 mA per channel)

Output PWM frequency set resistor (4.88kHz

PWM frequency to avoid audible noise)

R_{PWM_FSET}

R_MODE

17.8 kΩ, 0.1 W

3.92 kΩ, 0.1 W

Mode resistor (Phase-Shift PWM mode with

0x2B I2C address)

R_{LED_SET}

C_PUMP

C_2X

LED_SET resistor (6channels configuration)

Charge-pump output capacitor

Flying capacitor

3.92 kΩ, 0.1 W

10-µF, 10-V ceramic

2.2-µF, 10-V ceramic

C_VDD

C_IN

4.7-µF + 0.1-µF, 10-V ceramic

1 × 33-µF, 50-V electrolytic + 1 × 10-µF, 50-V ceramic

22-μH saturation current 6.5 A

50 V, 6.5-A Schottky diode

VDD bypass capacitor

Boost input capacitor

Boost output capacitor

Boost inductor

C_OUT

L1

D1

Boost Schottky diode

Boost nMOSFET

Q1

60-V, 15-A nMOSFET

Q2

60-V, 15-A pMOSFET

Power-line FET

8.2.1.3 Application Curves

F_{LED_PWM}= 305 Hz

Phase Shift 60°

6 Strings

图8-3. LED String Currents Showing Phase Shift

PWM Operation

150 mA/String

ƒ_SW= 400 kHz

C_IN= C_OUT= 1 × 33 μF (electrolytic) + 1 × 10 μF (ceramic)

图8-4. Typical Start-Up

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8.2.2 Application With Basic/Minimal Operation

The LP8866-Q1 needs only a few external components for basic functionality if material cost and PCB area for a

solution need to be minimized. In this example LP8866-Q1 is configured with external components and no I2C

communication. The power-line FET is removed, as is input current sensing. Internal charge pump is not used,

and all external synchronization functions and special features are disabled. The 33-µF Al-polymer electrolytic

capacitor is removed for PCB area and height limitation. And boost external compensation is used to

compensate the removal of the 33-µF Al-polymer electrolytic capacitor.

L

V_IN

V_OUT

C_IN

C_OUT

R_G

SD

VSENSE_N

VSENSE_P

GD

PGND

ISNS

R_FB1

R_FB4

R_FB2

C_COMP

R_SENSE

UVLO

C_VDD

ISNSGND

FB

VDD

LP8866(S)-Q1

VDD

C1N

DISCHARGE

LED_GND

C1P

C_PUMP

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

CPUMP

SGND

EN

Remote

HOST

PWM

INT

BST_FSET

PWM_FSET

SDA

SCL

VDD

LED_SET

ISET

BST_SYNC

MODE

R_ISET

图8-5. Minimal Solution/Minimum Components Application

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8.2.2.1 Design Requirements

This typical LED-driver application is designed to meet the parameters listed in 表8-4:

表8-4. LP8866-Q1 Minimal Solution Design Parameters

DESIGN PARAMETER

VIN voltage range

VALUE

3 V to 20 V (Quiescent Voltage)

VDD voltage

5 V

LED strings configuration

Charge pump

6 strings, 7 LEDs in series

Disabled

Brightness control

Output configuration

LED string current

Boost frequency

Inductor

PWM

OUT1 to OUT6 are in phase shift mode (60°)

120 mA

400 kHz

22 µH at 6.5-A saturation current

R_ISENSE

20 mΩ

Power-line FET

R_SENSE

Enabled

30 mΩ

Input/Output capacitors

Spread spectrum

Discharge function

C_INand C_OUT: 3 × 10-µF ceramic

Enabled

8.2.2.2 Detailed Design Procedure

See Detailed Design Procedure.

8.2.2.3 Application Curves

See Application Curves.

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8.2.3 SEPIC Mode Application

When LED string voltage can be above and below the input voltage level, use the SEPIC configuration. In

SEPIC mode, the SW pin detects a maximum voltage equal to the sum of the input and output voltages, a

consideration when selecting components.

CS2

RS

L

V_OUT

R_ISENSE

V_IN

CS1

R_SD

C_OUT

C_IN

L2

R_G

SD

R_FB1

VSENSE_N

VSENSE_P

GD

PGND

ISNS

R_UVLO1

R_UVLO2

R_FB2

R_SENSE

UVLO

ISNSGND

FB

VDD

LP8866(S)-Q1

VDD

C1N

C_VDD

DISCHARGE

LED_GND

C_2x

C1P

C_PUMP

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

CPUMP

SGND

EN

HOST

I2C

PWM

R_{BST_FSET}

R_{PWM_FSET}

R_{LED_SET}

INT

BST_FSET

PWM_FSET

SDA

SCL

LED_SET

ISET

VDD

BST_SYNC

MODE

R_ISET

R_MODE

图8-6. SEPIC Mode with Three LEDs in Series

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8.2.3.1 Design Requirements

This typical LED-driver application is designed to meet the parameters listed in 表8-5:

表8-5. LP8866-Q1 SEPIC Mode Design Parameters

DESIGN PARAMETER

V_INvoltage range

VALUE

4.5 V to 20 V (quiescent voltage)

V_DDvoltage

3.3 V

LED strings configuration

Charge pump

5 strings, 3 LEDs in series

Enabled

Brightness control

Output configuration

LED string current

Boost frequency

Inductor

I2C

OUT1 to OUT5 are in phase shift PWM mode

80 mA

2.2 MHz

10 µH at 4-A saturation current

R_ISENSE

20 mΩ

Power-line FET

R_SENSE

Enabled

50 mΩ

Input/Output capacitors

Spread spectrum

Discharge function

C_INand C_OUT: 1 × 33-µF electrolytic + 1 × 10-µF ceramic

Enabled

.

8.2.3.2 Detailed Design Procedure

8.2.3.2.1 Inductor Selection

Inductance for both inductors can be selected from 表8-6, depending on operating frequency for the application.

Current rating is recommended to be at least 25% higher than maximum inductor peak current. Peak-to-peak

ripple current can be estimated to be approximately 40% of the maximum input current and and inductor peak

current can be calculated with Equation 24, Equation 25, and Equation 26:

表8-6. Inductance Values for SEPIC Switching

Frequencies

SW FREQUENCY (kHz)

INDUCTANCE (µH)

100

200

22

15

303

10

400

10

500

10

1818

2000

2222

4.7

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V_OUT+ V_D

40%

2

≈

’

I_L1(peak)= I_OUT

ì

1+

∆

«

÷

◊

V

IN(min)

(24)

where

• I_L1(peak): Peak current for inductor 1

• I_OUT: Maximum output current

• V_OUT: Output voltage

• V_D: Diode forward voltage drop

• V_IN(min): Minimum input voltage

40%

≈

’

I_L2(peak)= I_OUT

ì

1+

∆

«

÷

◊

2

(25)

where

• I_L2(peak): Peak current for inductor 2

• I_OUT: Maximum output current

V_OUT

DI_L= I ì 40% = I_OUT

ì

ì 40%

IN

V

IN(min)

(26)

where

• ΔI_L: Inductor ripple current

• I_IN: Input current

• V_OUT: Output voltage

• V_IN(min): Minimum input voltage

8.2.3.2.2 Coupling Capacitor Selection

The coupling capacitors Cs isolate the input from the output and provide protection against a shorted load. The

selection of SEPIC capacitors, Cs, depends mostly on the RMS current, which can be calculated with Equation

27. The capacitors must be rated for a large RMS current relative to the output power; TI recommends at least

25% higher rating for I_RMS. When using uncoupled inductors, use one 10-µF ceramic capacitor in parallel with

one 33-µF electrolytic capacitor and series 2-Ω resistor. If coupled inductors are used, then use only one 10-µF

ceramic capacitor.

V_OUT+ V_D

I_Cs(rms)= I_OUT

ì

V

IN(min)

(27)

where

• I_Cs(rms): RMS current of Cs capacitor

• I_OUT: Output current

• V_OUT: Output voltage

• V_D: Diode forward voltage drop

• V_IN(min): Minimum input voltage

8.2.3.2.3 Output Capacitor Selection

See Detailed Design Procedure.

8.2.3.2.4 Input Capacitor Selection

See Detailed Design Procedure.

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8.2.3.2.5 Charge Pump Output Capacitor

See Detailed Design Procedure.

8.2.3.2.6 Charge Pump Flying Capacitor

See Detailed Design Procedure.

8.2.3.2.7 Switching FET

Gate-drive voltage for the FET is 5V. Use an N-type MOSFET for the switching FET. The switching FET for

SEPIC mode sees a maximum voltage of V_IN(max)+ V_OUT, 25% higher rating is recommended. Current rating is

also recommended to be 25% higher than peak current, which can be calculated with Equation 28. R_DSONmust

be as low as possible — less than 20 mΩ is recommended. Thermal resistance (R_θJA) must also be low to

dissipate heat from power loss on switching FET. Typical rise/fall time values recommended are less than 10 ns.

I_Q1(peak)= I_L1(peak)+ I_L2(peak)

(28)

where

• I_Q1(peak): Peak current for switching FET

• I_L1(peak): Peak current for inductor 1

• I_IL2(peak):: Peak current for inductor 2 BOOST_OCP

8.2.3.2.8 Output Diode

A Schottky diode must be used for the SEPIC output diode. Current rating must be at least 25% higher than the

maximum current, which is the same as switch peak current. Schottky diodes with a low forward drop and fast

switching speeds are ideal for increasing efficiency. At maximum current, the forward voltage must be as low as

possible; TI recommends less than 0.5 V. Reverse breakdown voltage of the Schottky diode must be able to

withstand V_IN(max)+ V_OUT(max); at least 25% higher voltage rating is recommended. Do not use ordinary rectifier

diodes, because slow switching speeds and long recovery times cause efficiency and load regulation to suffer.

8.2.3.2.9 Switching Sense Resistor

See Detailed Design Procedure.

8.2.3.2.10 Power-Line FET

See Detailed Design Procedure.

8.2.3.2.11 Input Current Sense Resistor

See Detailed Design Procedure.

8.2.3.2.12 Feedback Resistor Divider

Feedback resistors R_FB1and R_FB2determine the maximum boost output level. Output voltage can be calculated

as follows:

≈

∆

«

’

V_BG

V_{OUT _MAX}

=

+ I_{SEL_MAX}ì R_FB1+ V_BG

÷

R_FB2

◊

(29)

where

• V_BG= 1.21 V

• I_{SEL_MAX}= 38.7 µA

• R_FB1/ R_FB2normal recommended range is 5~15 (recommended for SEPIC Mode)

8.2.3.2.13 Critical Components for Design

图 8-7 shows the critical part of circuitry: SEPIC components, the LP8866-Q1 internal charge pump for gate-

driver powering, and powering/grounding of LP8866-Q1. Schematic example is shown below.

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CS2

RS

L

V_OUT

R_ISENSE

V_IN

CS1

R_SD

C_OUT

C_IN

L2

R_G

SD

R_FB1

VSENSE_N

VSENSE_P

GD

PGND

ISNS

R_UVLO1

R_UVLO2

R_FB2

R_SENSE

UVLO

ISNSGND

FB

VDD

LP8866(S)-Q1

VDD

C1N

C_VDD

DISCHARGE

LED_GND

C_2x

C1P

C_PUMP

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

CPUMP

SGND

EN

HOST

I2C

PWM

R_{BST_FSET}

R_{PWM_FSET}

R_{LED_SET}

INT

BST_FSET

PWM_FSET

SDA

SCL

LED_SET

ISET

VDD

BST_SYNC

MODE

R_ISET

R_MODE

图8-7. SEPIC Mode with Three LEDs in Series

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表8-7. Recommended Components for SEPIC Design Example

REFERENCE DESIGNATOR

DESCRIPTION

20 mΩ, 1 W

20 kΩ, 0.1 W

50 mΩ, 1 W

NOTE

R_ISENSE

R_SD

Input current sensing resistor

Power-line FET gate pullup resistor

Boost current sensing resistor

R_SENSE

Gate resistor to control the rising/falling time

of nMOSFET for EMC

R_G

15 Ω, 0.1 W

These UVLO resistor settings set the

VIN_UVLO rising voltage at 3.75 V,

VIN_UVLO falling voltage at 3.35 V

R_UVLO1

R_UVLO2

76.8 kΩ, 0.1 W

20.5 kΩ, 0.1 W

R_FB2

R_FB1

Bottom feedback divider resistor

Top feedback divider resistor

60 kΩ, 0.1 W

330 kΩ, 0.1 W

124 kΩ, 0.1 W

38.7 kΩ, 0.1 W

R_{BST_FSET}

R_ISET

Boost frequency set resistor (2200 kHz)

Current set resistor (80 mA per channel)

Output PWM frequency set resistor (305-Hz

PWM frequency)

R_{PWM_FSET}

R_MODE

4.75 kΩ, 0.1 W

3.92 kΩ, 0.1 W

Mode resistor (Phase-Shift PWM mode with

0x2B I2C address)

R_{LED_SET}

C_PUMP

C_2X

LED_SET resistor (5 channels configuration)

Charge-pump output capacitor

Flying capacitor

4.75 kΩ, 0.1 W

10-µF, 10-V ceramic

2.2-µF, 10-V ceramic

C_VDD

C_IN

4.7-µF + 0.1-µF, 10-V ceramic

1 × 33-µF, 50-V electrolytic + 1 × 10-µF, 50-V ceramic

10-µF, 50-V ceramic

VDD bypass capacitor

Boost input capacitor

Boost output capacitor

SEPIC coupling capacitor

SEPIC resistor

C_OUT

C_S1

C_S2

33-µF, 50-V electrolytic

RS

2 Ω, 0.125 W

L1

4.7-µH saturation current 3 A

50-V 10-A Schottky diode

SEPIC inductor

L2

SEPIC inductor

D1

SEPIC Schottky diode

SEPIC nMOSFET

Q1

60-V, 25-A nMOSFET

Q2

60-V, 30-A pMOSFET

Power-line FET

8.2.3.3 Application Curves

See Application Curves.

9 Power Supply Recommendations

The LP8866-Q1 is designed to operate from a car battery. The V_INinput must be protected from reverse voltage

and voltage dump condition over 48 V. The impedance of the input supply rail must be low enough that the input

current transient does not cause drop below VIN UVLO level. If the input supply is connected with long wires,

additional bulk capacitance may be required in addition to normal input capacitor.

The voltage range for V_DDis 3 V to 5.5 V. A ceramic capacitor must be placed as close as possible to the VDD

pin. The boost gate driver is powered from the CPUMP pins. A ceramic capacitor must be placed as close to the

CPUMP pins as possible.

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10 Layout

10.1 Layout Guidelines

图 10-1 shows a layout recommendation for the LP8866-Q1 used to illustrate the principles of good layout. This

layout can be adapted to the actual application layout if and where possible. It is important that all boost

components are close to each other and to the chip; the high-current traces must be wide enough. VDD must be

as noise-free as possible. Place a V_DDbypass capacitor near the VDD and GND pins. A charge-pump capacitor,

boost input capacitors, and boost output capacitors must have closest VIAs to GND. Place the charge-pump

capacitors close to the device. The main points to guide the PCB layout design:

• Current loops need to be minimized:

– For low frequency the minimal current loop can be achieved by placing the boost components as close as

possible to each other. Input and output capacitor grounds need to be close to each other to minimize

current loop size.

– Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact

under the current traces. High frequency return currents follow the route with minimum impedance, which

is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when

return current flows just under the positive current route in the ground plane, if the ground plane is intact

under the route.

– For high frequency the copper area capacitance must be taken into account. For example, the copper

area for the drain of boost N-MOSFET is a tradeoff between capacitance and the cooling capacity of the

components.

• GND plane must be intact under the high-current-boost traces to provide shortest possible return path and

smallest possible current loops for high frequencies.

• Route boost output voltage (V_OUT) to LEDs, FB pin & Discharge pin after output capacitors not straight from

the diode cathode.

• FB network should be placed as close as possible to the FB pin, not near boost output

• A small bypass capacitor (TI recommends a 39-pF capacitor) could be placed close to the FB pin and GND to

suppress high frequency noise

• VDD line must be separated from the high current supply path to the boost converter to prevent high

frequency ripple affecting the chip behavior.

• Capacitor connected to charge pump output CPUMP is recommended to have 10-µF capacitance. This

capacitor must be as close as possible to CPUMP pin. This capacitor provides a greater peak current for gate

driver and must be used even if the charge pump is disabled. If the charge pump is disabled, the VDD and

CPUMP pins must be tied together.

• Input and output capacitors need low-impedance grounding (wide traces with many vias to GND plane).

• Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost

to become unstable under certain load conditions. DC bias characteristics should be obtained from the

component manufacturer; DC bias is not taken into account on component tolerance.

72

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ZHCSKL3B –DECEMBER 2019 –REVISED OCTOBER 2020

10.2 Layout Example

pMOSFET

Input Sense Resistor

V_BAT

Boost Inductor

R_GS

C_IN

GND

1

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

SD

VDD

EN

VSENSE_N

2

3

VSENSE_P

UVLO

C1N

C1P

R_UVLO1

4

Schottky Diode

nMOSFET

R_UVLO2

5

DGND

CPUMP

GND

6

MODE

CPUMP

GD

R_G

7

BST_FSET

PWM_FSET

LED_SET

PGND

8

9

GND

ISNS

SGND

10

11

12

13

14

Sense Resistor

PWM

ISNSGND

R_ISET

GND

C_OUT

BST_SYNC

ISET

FB

SCL

R_FB2

R_FB1

NC

SDA

INT

DISCHARGE

15

16

17

NC

OUT6

OUT5

GND

OUT1

OUT2

OUT3

18

19

OUT4

Submit Document Feedback

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ZHCSKL3B –DECEMBER 2019 –REVISED OCTOBER 2020

pMOSFET

Input Sense Resistor

V_BAT

Boost Inductor

R_GS

C_IN

GND

R_UVLO1

GND

Schottky Diode

nMOSFET

C1P

CPUMP

BST_FSET

GND

PWM_FSET

LED_SET

R_G

GD

PGND

ISNS

SGND

PWM

GND

ISNSGND

ISET

BST_SYNC

SCL

Sense Resistor

R_ISET

GND

C_OUT

R_FB2

FB

SDA

R_FB1

GND

图10-1. LP8866-Q1 Layout Guidelines

74

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ZHCSKL3B –DECEMBER 2019 –REVISED OCTOBER 2020

11 Device and Documentation Support

11.1 Device Support

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Submit Document Feedback

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ZHCSKL3B –DECEMBER 2019 –REVISED OCTOBER 2020

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

76

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GENERIC PACKAGE VIEW

DCP 38

4.4 x 9.7, 0.5 mm pitch

PowerPAD TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224560/B

www.ti.com

PACKAGE OUTLINE

DCP0038A

PowerPAD^TMTSSOP - 1.2 mm max height

S

C

A

L

E

2

.

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX

AREA

SEATING

PLANE

36X 0.5

38

1

2X

9

9.8

9.6

NOTE 3

19

20

0.27

0.17

0.08

38X

4.5

4.3

B

C A B

SEE DETAIL A

(0.15) TYP

2X 0.95 MAX

NOTE 5

19

20

2X 0.95 MAX

NOTE 5

0.25

GAGE PLANE

1.2 MAX

39

4.70

3.94

THERMAL

PAD

0.15

0.05

0.75

0.50

0 -8

A

20

DETAIL A

TYPICAL

1

38

2.90

2.43

4218816/A 10/2018

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-153.

5. Features may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DCP0038A

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(3.4)

NOTE 9

METAL COVERED

BY SOLDER MASK

(2.9)

SYMM

38X (1.5)

38X (0.3)

SEE DETAILS

38

1

(R0.05) TYP

36X (0.5)

3X (1.2)

SYMM

39

(4.7)

(9.7)

NOTE 9

(0.6) TYP

SOLDER MASK

DEFINED PAD

(

0.2) TYP

VIA

20

19

(1.2)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 8X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

SOLDER MASK DETAILS

4218816/A 10/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Size of metal pad may vary due to creepage requirement.

10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DCP0038A

PowerPAD^TMTSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

(2.9)

BASED ON

0.125 THICK

STENCIL

38X (1.5)

38X (0.3)

METAL COVERED

BY SOLDER MASK

1

38

(R0.05) TYP

36X (0.5)

(4.7)

SYMM

39

BASED ON

0.125 THICK

STENCIL

19

20

SYMM

(5.8)

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 8X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

3.24 X 5.25

2.90 X 4.70 (SHOWN)

2.65 X 4.29

0.125

0.15

0.175

2.45 X 3.97

4218816/A 10/2018

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

www.ti.com

PACKAGE OUTLINE

RHB0032T

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

5.15

4.85

B

A

PIN 1 INDEX AREA

5.15

4.85

0.13 MIN

(0.15)

SECTION A-A

A

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

3.45 0.1

9

EXPOSED

THERMAL PAD

16

28X 0.5

8

(0.16) TYP

17

A

2X

SYMM

33

3.5

0.3

0.2

32X

24

0.1

C A B

C

1

0.05

32

25

PIN 1 ID

(OPTIONAL)

SYMM

0.52

0.32

(0.355)

TYP

32X

4224744/A 01/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHB0032T

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.45)

SYMM

32

25

32X (0.62)

1

24

32X (0.25)

(1.475)

28X (0.5)

33

SYMM

(4.78)

(

0.2) TYP

VIA

8

17

(R0.05)

TYP

9

16

(1.475)

(4.78)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL EDGE

EXPOSED METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224744/A 01/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHB0032T

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)

(0.845)

(R0.05) TYP

32

25

32X (0.62)

1

24

32X (0.25)

28X (0.5)

(0.845)

SYMM

33

(4.78)

17

8

METAL

TYP

16

9

SYMM

(4.78)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4224744/A 01/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LP8866QDCPRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 6 个 200mA 通道的汽车显示 LED 背光驱动器 \| DCP \| 38 \| -40 to 125 驱动驱动器
文件：	总85页 (文件大小：3517K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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