LP87524J-Q1 [TI]
适用于 AWR 和 IWR MMIC 的多相 4MHz、4A/1.0V + 2.5A/1.8V + 1.5A/3.3V + 1.5A/1.2V 降压转换器;型号: | LP87524J-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 适用于 AWR 和 IWR MMIC 的多相 4MHz、4A/1.0V + 2.5A/1.8V + 1.5A/3.3V + 1.5A/1.2V 降压转换器 转换器 |
文件: | 总79页 (文件大小:2130K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
LP87524B/J/P-Q1 适用于 AWR 和 IWR MMIC 的四 4MHz 降压转换器
1 特性
3 说明
1
•
符合汽车应用 要求
LP87524B/J/P-Q1 专为满足各种汽车电源应用中最新
处理器和平台的电源管理要求而 设计。该器件包含四
个降压直流/直流转换器内核,这些内核配置为 4 个单
相输出。该器件由 I2C 兼容串行接口和使能信号进行控
制。
•
具有符合 AEC-Q100 标准的下列结果:
–
器件温度 1 级:-40℃ 至 +125℃ 的环境运行温
度范围
•
•
•
输入电压:2.8V 至 5.5V
输出电压:0.6V 至 3.36V
自动 PFM/PWM(AUTO 模式)操作可在较宽输出电
流范围内最大限度地提高效率。LP87524B/J/P-Q1 支
持远程电压感应,可补偿稳压器输出与负载点 (POL)
之间的 IR 压降,从而提高输出电压的精度。此外,可
以强制开关时钟进入 PWM 模式以及将其与外部时钟
同步,从而最大限度地降低干扰。
四个高效降压直流/直流转换器内核:
–
–
总输出电流高达 10A
输出电压转换率 3.8mV/µs
•
•
•
•
4MHz 开关频率
扩频模式和相位交错
可配置通用 I/O (GPIO)
I2C 兼容接口,支持标准 (100kHz)、快速
(400kHz)、快速+ (1MHz) 和高速 (3.4MHz) 四种模
式
LP87524B/J/P-Q1 器件支持在不添加外部电流感应电
阻器的情况下进行负载电流测量。此
外,LP87524B/J/P-Q1 还支持与使能信号同步的可编
程启动和关断延迟与时序。这些序列可能还包括用于控
制外部稳压器、负载开关和处理器复位的 GPIO 信
号。在启动和电压变化期间,器件会对输出转换率进行
控制,从而最大限度地减小输出电压过冲和浪涌电流。
•
•
•
•
•
具有可编程屏蔽的中断功能
可编程电源正常信号 (PGOOD)
输出短路和过载保护
过热警告和保护
过压保护 (OVP) 和欠压锁定 (UVLO)
器件信息(1)
器件型号
LP87524B-Q1
LP87524J-Q1
LP87524P-Q1
封装
封装尺寸(标称值)
2 应用
汽车信息娱乐系统、仪表组、雷达和摄像头电源 应
用
VQFN-HR (26)
4.50mm × 4.00mm
空白
空白
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
简化原理图
效率与输出电流间的关系
VOUT1
VOUT2
VOUT3
VOUT4
100
SW_B0
FB_B0
VIN
LOAD
LOAD
LOAD
LOAD
VIN_B0
VIN_B1
VIN_B2
VIN_B3
VANA
90
80
70
SW_B1
FB_B1
NRST
SDA
SCL
60
1PH, VOUT = 1V, AUTO
1PH, VOUT = 1.8V, AUTO
SW_B2
FB_B2
nINT
1PH, VOUT = 2.5V, AUTO
50
0.001
CLKIN
0.01
0.1
1
5
Output Current (A)
EN1 (GPIO1)
EN2 (GPIO2)
EN3 (GPIO3)
D922
SW_B3
FB_B3
PGOOD
GNDs
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNVSAW2
LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
www.ti.com.cn
目录
7.5 Programming........................................................... 32
7.6 Register Maps......................................................... 35
Application and Implementation ........................ 57
8.1 Application Information............................................ 57
8.2 Typical Application .................................................. 57
Power Supply Recommendations...................... 63
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 I2C Serial Bus Timing Requirements...................... 11
6.7 Typical Characteristics............................................ 13
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Descriptions............................................... 15
7.4 Device Functional Modes........................................ 30
8
9
10 Layout................................................................... 64
10.1 Layout Guidelines ................................................. 64
10.2 Layout Example .................................................... 65
11 器件和文档支持 ..................................................... 66
11.1 器件支持................................................................ 66
11.2 接收文档更新通知 ................................................. 66
11.3 社区资源................................................................ 66
11.4 商标....................................................................... 66
11.5 静电放电警告......................................................... 66
11.6 术语表 ................................................................... 66
12 机械、封装和可订购信息....................................... 67
7
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision A (December 2017) to Revision B
Page
•
已添加 在 SNVSAW2 数据表中添加了 LP87524P-Q1 GPN................................................................................................... 1
Changes from Original (April 2017) to Revision A
Page
•
已添加 在 SNVSAW2 数据表中添加了 LP87524J-Q1 GPN ................................................................................................... 1
2
版权 © 2017–2018, Texas Instruments Incorporated
LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
www.ti.com.cn
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
5 Pin Configuration and Functions
RNF Package
26-Pin VQFN With Thermal Pad
Top View
26
25
24
23
22
FB_B2
FB_B3
1
21
EN3
NRST
nINT
2
3
4
5
6
7
20
19
18
17
16
15
CLKIN
AGND
SCL
VANA
AGND
PGOOD
EN2
AGND
SDA
EN1
FB_B0
FB_B1
8
14
9
10
11
12
13
Copyright © 2017–2018, Texas Instruments Incorporated
3
LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
www.ti.com.cn
Pin Functions
PIN
TYPE
DESCRIPTION
NUMBER
NAME
1
FB_B2
A
D/I/O
D/I
Output voltage feedback (positive) for Buck2.
Programmable enable signal for buck regulators (can be also configured to select between two
buck output voltage levels). Alternative function is GPIO3.
2
3
EN3
CLKIN
AGND
External clock input. Connect to ground if external clock is not used.
4, 17,
Thermal Pad
G
Ground
5
6
SCL
SDA
D/I
Serial interface clock input for I2C access. Connect a pullup resistor.
D/I/O Serial interface data input and output for I2C access. Connect a pullup resistor.
Programmable Enable signal for buck regulators (can be also configured to select between two
buck output voltage levels). Alternative function is GPIO1.
7
8
9
EN1
D/I/O
FB_B0
VIN_B0
A
P
Output voltage feedback (positive) for Buck0
Input for Buck0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
10
11
12
SW_B0
PGND_B01
SW_B1
A
G
A
Buck0 switch node
Power ground for Buck0 and Buck1
Buck1 switch node
Input for Buck1. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
13
14
15
VIN_B1
FB_B1
EN2
P
A
Output voltage feedback (positive) for Buck1.
Programmable enable signal for Buck regulators (can be also configured to select between two
buck output voltage levels). Alternative function is GPIO2.
D/I/O
16
18
19
20
21
PGOOD
VANA
nINT
D/O
P
Power Good indication signal
Supply voltage for analog and digital blocks. Must be connected to same node as with VIN_Bx.
Open-drain interrupt output, active LOW
D/O
D/I
A
NRST
FB_B3
Reset signal for the device.
Output voltage feedback (positive) for Buck3.
Input for Buck3. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
22
VIN_B3
P
23
24
25
SW_B3
PGND_B23
SW_B2
A
G
A
Buck3 switch node
Power Ground for Buck2 and Buck3
Buck2 switch node
Input for Buck2. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
26
VIN_B2
P
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
4
Copyright © 2017–2018, Texas Instruments Incorporated
LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
www.ti.com.cn
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
(2)
MIN
MAX
UNIT
Voltage on power connections
Voltage on buck switch nodes
VIN_Bx, VANA
SW_Bx
–0.3
6
V
(VIN_Bx + 0.3 V) with 6 V
maximum
–0.3
V
(VANA + 0.3 V) with 6 V
maximum
Voltage on buck voltage sense nodes
Voltage on NRST input
FB_Bx
–0.3
–0.3
–0.3
V
V
V
NRST
6
Voltage on logic pins
(input or output pins)
SDA, SCL, nINT, CLKIN
6
Voltage on logic pins
(input or output pins)
EN1 (GPIO1), EN2 (GPIO2), EN3
(GPIO3), PGOOD
(VANA + 0.3 V) with 6 V
maximum
–0.3
V
Junction temperature, TJ-MAX
Storage temperature, Tstg
−40
150
150
260
°C
°C
°C
–65
Maximum lead temperature (soldering, 10 sec.)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
All pins
V
Corner pins (1, 8, 14 and 21)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
INPUT VOLTAGE
Voltage on power connections
Voltage on NRST
VIN_Bx, VANA
NRST
2.8
5.5
V
V
V
V
1.65
VANA with 5.5 V
maximum
Voltage on logic pins
nINT, CLKIN
ENx, PGOOD
1.65
0
5.5
Voltage on logic pins
(input or output pins)
VANA with 5.5 V
maximum
Voltage on I2C interface, standard (100
kHz), fast (400 khz), fast+ (1 MHz), and
high-speed (3.4 MHz) modes
1.65
3.1
1.95
V
V
SCL, SDA
Voltage on I2C interface, standard (100
kHz), fast (400 kHz), and fast+ (1 MHz)
modes
VANA with 3.6 V
maximum
TEMPERATURE
Junction temperature, TJ
Ambient temperature, TA
−40
−40
140
125
°C
°C
Copyright © 2017–2018, Texas Instruments Incorporated
5
LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
www.ti.com.cn
6.4 Thermal Information
LP875xx-Q1
RNF (VQFN)
26 PINS
34.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
16.5
4.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJB
4.7
RθJC(bot)
1.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST
,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
(2)
unless otherwise noted.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
EXTERNAL COMPONENTS
Input filtering
capacitance
CIN
Connected from VIN_Bx to PGND_Bx
Capacitance per phase
1.9
10
10
22
22
µF
µF
µF
Output filtering
COUT
Capacitance, local
Point-of-Load (POL)
capacitance
CPOL
Optional POL capacitance per phase
Total output capacitance, 1-phase output
[1-10] MHz
COUT-
TOTAL
Output capacitance,
total (local and POL)
100
10
µF
Input and output
capacitor ESR
ESRC
2
mΩ
0.47
µH
L
Inductor
Inductance of the inductor
–30%
30%
DCRL
Inductor DCR
25
mΩ
BUCK REGULATOR
VVIN_Bx
Input voltage range
2.8
0.6
3.7
5.5
V
Programmable voltage range, 2.8 V ≤
3.36
V
VIN_Bx ≤ 4 V
Programmable voltage range, 2.8 V ≤
VIN_Bx ≤ 5.5 V
V
1.0
3.36
V
VVOUT_Bx
Output voltage
Step size, 0.6 V ≤ VOUT < 0.73 V
Step size, 0.73 V ≤ VOUT < 1.4 V
Step size, 1.4 V ≤ VOUT ≤ 3.36 V
Buck0, Buck1
10
5
mV
20
1.5(3)
4(3)
Buck2: VIN ≥ 3 V
Output current,
LP87524B/J
IOUT
A
A
Buck2: 2.8 V ≤ VIN < 3 V
Buck3
3(3)
2.5(3)
3(3)
1.5(3)
2.5(3)
Buck0, Buck2
Output current,
LP87524P
IOUT
Buck1
Buck3
(1) All voltage values are with respect to network ground.
(2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but
do represent the most likely norm.
(3) The maximum output current can be limited by the forward current limit ILIM FWD and by the junction temperature. The power dissipation
inside the die depends on the length of the current pulse and efficiency and the junction temperature may increase to thermal shutdown
level if the board and ambient temperatures are high.
6
Copyright © 2017–2018, Texas Instruments Incorporated
LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
www.ti.com.cn
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST
,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input and output
voltage difference
Minimum voltage between VIN_x and
VOUT to fulfill the electrical characteristics
0.5
V
DC output voltage
accuracy, includes
voltage reference, DC
load and line
regulations, process
and temperature
VOUT < 1 V, PWM mode
–20
–2%
–20
20
2%
40
mV
mV
V
OUT ≥ 1 V, PWM mode
VOUT < 1 V, PFM mode
OUT ≥ 1 V, PFM mode
VVOUT_DC
V
–2%
2% + 20 mV
PWM mode, ESRC < 2 mΩ, L = 0.47 µH
PFM mode, L = 0.47 µH
IOUT = IOUT(max)
4
14
Ripple voltage
mVp-p
%/V
DCLNR
DCLDR
DC line regulation
0.1
DC load regulation in
PWM mode
VOUT = 1 V, IOUT from 0 to IOUT(max)
0.8%
IOUT = 0 A to 2 A, TR = TF = 10 µs, PWM
mode, COUT = 22 µF, L = 0.47 µH, CPOL
22 µF
=
–3%
3%
Transient load step
response
TLDSR
mV
mV
IOUT = 0.1 A to 2 A, TR = TF = 1 µs, PWM
mode, COUT = 22 µF, L = 0.47 µH, CPOL
22 µF
=
±40
±5
VVIN_Bx stepping 3 V ↔ 3.5 V, TR = TF = 10
µs, IOUT = IOUT(max)
TLNSR
Transient line response
Buck0, Buck1: VVIN_Bx ≥ 3 V
Buck0, Buck1: 2.8 V ≤ VVIN_Bx < 3 V
Buck2: VVIN_Bx ≥ 3 V
2.3
2.0
4.7
4.0
4.2
3.6
3.8
3.2
2.3
2.0
4.2
3.6
2.7
2.7
5.4
5.4
4.8
4.8
4.3
4.3
2.7
2.7
4.8
4.8
3.0
3.0
6.0
6.0
5.4
5.4
4.8
4.8
3.0
3.0
5.4
5.4
Forward current limit
(peak for every
switching cycle),
LP87524B/J
ILIM FWD
A
Buck2: 2.8 V ≤ VVIN_Bx < 3 V
Buck3: VVIN_Bx ≥ 3 V
Buck3: 2.8 V ≤ VVIN_Bx < 3 V
Buck0, Buck2: VVIN_Bx ≥ 3 V
Buck0, Buck2: 2.8 V ≤ VVIN_Bx < 3 V
Buck1: VVIN_Bx ≥ 3 V
Forward current limit
(peak for every
switching cycle),
LP87524P
ILIM FWD
A
A
Buck1: 2.8 V ≤ VVIN_Bx < 3 V
Buck3: VVIN_Bx ≥ 3 V
Buck3: 2.8 V ≤ VVIN_Bx < 3 V
Negative current limit /
phase (peak for every
switching cycle)
ILIM NEG
1.6
2
2.4
RDS(ON) HS On-resistance, high-
Each phase, between VIN_Bx and SW_Bx
pins (I = 1 A)
29
17
65
35
mΩ
mΩ
side FET
FET
RDS(ON) LS On-resistance, low-side Each phase, between SW_Bx and
FET
PGND_Bx pins (I = 1 A)
FET
VOUT > 0.8
3.6
2.7
1.8
4
3
2
4.4
3.3
2.2
Switching frequency,
PWM mode
fSW
0.6 < VOUT ≤ 0.8
VOUT = 0.6
MHz
µs
From ENx to VOUT = 0.35 V (slew-rate
control begins), COUT_TOTAL = 44 µF / phase
Start-up time (soft start)
200
3.8
Output voltage slew-
rate(4)
3.23
4.4 mV/µs
(4) Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.
Copyright © 2017–2018, Texas Instruments Incorporated
7
LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1) (2)
,
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PFM-to-PWM - current
threshold(5)
IPFM-PWM
IPWM-PFM
600
mA
PWM-to-PFM - current
threshold(5)
200
230
50
mA
Output pulldown
resistance
Regulator disabled
Overvoltage monitoring (compared to DC
160
39
–53
4
300
64
Ω
output voltage level, VVOUT_DC
)
mV
Undervoltage monitoring (compared to DC
output voltage level, VVOUT_DC
–40
–29
10
)
Output voltage
monitoring for PGOOD
pin
Debounce time during regulator enable
PGOOD_SET_DELAY = 0
µs
ms
µs
Debounce time during regulator enable
PGOOD_SET_DELAY = 1
10
4
11
13
Deglitch time during operation and after
voltage change
10
Powergood threshold
for interrupt
BUCKx_PG_INT,
difference from final
voltage
Rising ramp voltage, enable or voltage
change
–20
–14
14
–8
mV
mV
Falling ramp voltage, voltage change
8
20
–8
Powergood threshold
for status bit
BUCKx_PG_STAT
During operation, status signal is forced to
'0' during voltage change
–20
–14
1
EXTERNAL CLOCK AND PLL
Nominal frequency
1
24
MHz
External input clock
Nominal frequency step size
Required accuracy from nominal frequency
Delay for missing clock detection
Delay and debounce for clock detection
–30%
10%
1.8
20
External clock
detection
µs
µs
Clock change delay
(internal to external)
Delay from valid clock detection to use of
external clock
600
300
PLL output clock jitter
Cycle to cycle
ps, p-p
PROTECTION FUNCTIONS
Temperature rising, TDIE_WARN_LEVEL =
0
115
127
125
137
135
147
Thermal warning
Temperature rising, TDIE_WARN_LEVEL =
1
°C
°C
Hysteresis
20
150
20
Temperature rising
Hysteresis
140
160
Thermal shutdown
Voltage rising
Voltage falling
Hysteresis
5.6
5.45
40
5.8
6.1
V
mV
V
VANAOVP VANA overvoltage
5.73
5.96
Voltage rising
Voltage falling
2.51
2.5
2.63
2.6
2.75
2.7
VANA undervoltage
VANAUVLO
lockout
LOAD CURRENT MEASUREMENT
(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and
the inductor current level.
8
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST
,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1) (2)
PARAMETER
TEST CONDITIONS
Output current for maximum code
LSB
MIN
TYP
MAX UNIT
Current measurement
range
20.47
A
Resolution
20
mA
Measurement accuracy IOUT > 1 A
PFM mode (automatically changing to PWM
<10%
45
4
mode for the measurement)
Measurement time
µs
PWM mode
CURRENT CONSUMPTION
Shutdown current
consumption
From VANA and VIN_Bx pins: NRST = 0 V,
VANA = VIN_Bx = 3.7 V
1.4
6.7
µA
µA
Standby current
consumption,
regulators disabled
From VANA and VIN_Bx pins: NRST = 1.8
V, VANA = VIN_Bx = 3.7 V
Active current
From VANA and VIN_Bx pins: NRST = 1.8
V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not
switching
consumption in PFM
mode, one regulator
enabled, internal RC
oscillator, PGOOD
monitoring enabled
57
Active current
consumption during
PWM operation, per
phase
19
2
mA
mA
Additional current consumption when
internal RC oscillator, clock detector and
PLL are enabled
PLL and clock detector
current consumption
DIGITAL INPUT SIGNALS NRST, EN1, EN2, EN3, EN4, SCL, SDA, GPIO1, GPIO2, GPIO3, CLKIN
VIL
VIH
Input low level
Input high level
0.4
V
1.2
10
Hysteresis of Schmitt
Trigger inputs
VHYS
77
500
200
mV
ENx pulldown
resistance
ENx_PD = 1
kΩ
NRST pulldown
resistance
Always present
650
1150
1700
0.4
DIGITAL OUTPUT SIGNALS nINT
VOL
RP
Output low level
ISOURCE = 2 mA
V
External pullup resistor To VIO supply
10
kΩ
DIGITAL OUTPUT SIGNALS SDA
VOL Output low level
DIGITAL OUTPUT SIGNALS PGOOD, GPIO1, GPIO2, GPIO3
ISOURCE = 10 mA
0.4
V
VOL
Output low level
ISOURCE = 2 mA
0.4
V
V
Output high level,
configured to push-pull
VOH
ISINK = 2 mA
VVANA – 0.4
VVANA
Supply voltage for
external pull-up
resistor, configured to
open-drain
VPU
VVANA
V
External pullup resistor,
configured to open-
drain
RPU
10
kΩ
ALL DIGITAL INPUTS
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1) (2)
,
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
All logic inputs over pin voltage range
(except NRST)
ILEAK
Input current
−1
1
µA
10
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6.6 I2C Serial Bus Timing Requirements
These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V.
MIN
MAX
100
400
1
UNIT
Standard mode
Fast mode
kHz
ƒSCL
Serial clock frequency
Fast mode+
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
3.4
1.7
MHz
4.7
1.3
0.5
160
320
4
Fast mode
µs
ns
µs
ns
tLOW
SCL low time
Fast mode+
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
Fast mode
0.6
0.26
60
tHIGH
SCL high time
Data setup time
Data hold time
Fast mode+
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
120
250
100
50
Fast mode
tSU;DAT
tHD;DAT
tSU;STA
ns
Fast mode+
High-speed mode
Standard mode
10
10
3450
900
Fast mode
10
ns
ns
Fast mode+
10
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
10
70
10
150
4.7
0.6
0.26
160
4.0
0.6
0.26
160
4.7
1.3
0.5
4
Fast mode
µs
ns
µs
ns
µs
Setup time for a start or a
repeated start condition
Fast mode+
High-speed mode
Standard mode
Fast mode
Hold time for a start or a
repeated start condition
tHD;STA
Fast mode+
High-speed mode
Standard mode
Bus free time between a stop
and start condition
tBUF
Fast mode
Fast mode+
Standard mode
Fast mode
0.6
0.26
160
µs
ns
Setup time for a stop
condition
tSU;STO
Fast mode+
High-speed mode
Standard mode
1000
300
120
80
Fast mode
20
trDA
Rise time of SDA signal
Fast mode+
ns
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
10
20
160
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I2C Serial Bus Timing Requirements (continued)
These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V.
MIN
MAX
300
UNIT
Standard mode
Fast mode
20 × (VDD
/
300
5.5 V)
tfDA
Fall time of SDA signal
20 × (VDD
/
120
ns
Fast mode+
5.5 V)
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
10
80
160
1000
300
120
40
30
Fast mode
20
trCL
Rise time of SCL signal
Fast mode+
ns
ns
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
10
20
10
80
Rise time of SCL signal after High-speed mode, Cb = 100 pF
a repeated start condition
80
trCL1
High-speed mode, Cb = 400 pF
and after an acknowledge bit
20
160
300
Standard mode
20 × (VDD
/
Fast mode
300
120
5.5 V)
tfCL
Fall time of a SCL signal
Fast mode+
20 × (VDD
/
ns
5.5 V)
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
10
40
80
20
Capacitive load for each bus
line (SCL and SDA)
Cb
400
50
pF
ns
Pulse width of spike
suppressed (SCL and SDA
spikes that are less than the
indicated width are
Standard mode, fast mode and fast mode+
tSP
High-speed mode
10
suppressed)
tBUF
SDA
SCL
tHD;STA
trCL
tfDA
trDA
tLOW
tfCL
tSP
tHD;STA
tSU;STA
tSU;STO
tHIGH
tHD;DAT
S
tSU;DAT
S
RS
P
START
REPEATED
START
STOP
START
图 1. I2C Timing
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6.7 Typical Characteristics
Unless otherwise specified: TA = 25°C, VIN = 3.7 V, VOUT = 1 V, V(NRST) = 1.8 V, ƒSW = 4 MHz, L = 0.47 µH (TOKO
DFE252012PD-R47M), COUT = 22 µF / phase, CPOL = 22 µF / phase.
4
3.5
3
10
9
8
7
6
5
4
3
2
1
0
2.5
2
1.5
1
0.5
0
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D045
D046
V(NRST) = 0 V
V(NRST) = 1.8 V
Regulators disabled
图 2. Shutdown Current Consumption vs Input Voltage
图 3. Standby Current Consumption vs Input Voltage
90
85
80
75
70
65
60
55
50
45
40
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
D051
V(NRST) = 1.8 V
Load = 0 mA
图 4. PFM Mode Current Consumption vs Input Voltage, One Regulator Enabled
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7 Detailed Description
7.1 Overview
The LP87524B/J/P-Q1 is a high-efficiency, high-performance power supply device with four step-down DC-DC
converter cores for automotive applications. 表 1 lists the output characteristics of the regulators.
表 1. Supply Specification
OUTPUT
SUPPLY
VOUT RANGE (V)
RESOLUTION (mV)
IMAX MAXIMUM OUTPUT CURRENT (A)
0.6 to 3.36 (VIN = 2.8 V - 4 V)
1.0 to 3.36 (VIN = 2.8 V - 5.5 V)
10 (0.6 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
Buck0
Buck1
Buck2
Buck3
0.6 to 3.36 (VIN = 2.8 V - 4 V)
1.0 to 3.36 (VIN = 2.8 V - 5.5 V)
10 (0.6 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
10 A total
0.6 to 3.36 (VIN = 2.8 V - 4 V)
1.0 to 3.36 (VIN = 2.8 V - 5.5 V)
10 (0.6 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
0.6 to 3.36 (VIN = 2.8 V - 4 V)
1.0 to 3.36 (VIN = 2.8 V - 5.5 V)
10 (0.6 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
LP87524B-Q1 default settings:
VOUT (V)
3.3 V
1.2 V
1.8 V
2.3 V
VOUT (V)
3.3 V
1.2 V
1 V
IMAX MAXIMUM OUTPUT CURRENT (A)
AWR / IWR Rail
IO
Buck0
1.5 A
Buck1
1.5 A
Digital
Buck2
4 A
RF, with external LDO
RF, with external LDO
AWR / IWR Rail
IO
Buck3
2.5 A
LP87524J-Q1 default settings:
IMAX MAXIMUM OUTPUT CURRENT (A)
Buck0
1.5 A
Buck1
1.5 A
Digital
Buck2
4 A
RF, with ferrite filter
RF, with ferrite filter
AWR / IWR Rail
RF, with ferrite filter
Digital
Buck3
1.8 V
VOUT (V)
1 V
2.5 A
LP87524P-Q1 default settings:
IMAX MAXIMUM OUTPUT CURRENT (A)
Buck0
Buck1
Buck2
Buck3
3 A
1.5 A
3 A
1.2 V
1 V
RF, with ferrite filter
RF, with ferrite filter
1.8 V
2.5 A
The LP87524B/J/P-Q1 also supports switching clock synchronization to an external clock. The nominal frequency
of the external clock can be from 1 MHz to 24 MHz with 1-MHz steps.
Additional features include:
•
•
Soft start
Input voltage protection:
–
–
Undervoltage lockout
Overvoltage protection
•
Output voltage monitoring and protection:
–
–
–
Overvoltage monitoring
Undervoltage monitoring
Overload protection
•
•
Thermal warning
Thermal shutdown
Three enable signals can be multiplexed to general purpose I/O (GPIO) signals. The direction and output type
(open-drain or push-pull) are programmable for the GPIOs.
14
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7.2 Functional Block Diagram
VANA
BUCK0
ILIM Detection
nINT
Power-Good Detection
Interrupts
Overload and Short-Circuit
Detection
GPIO1 (EN1)
GPIO2 (EN2)
GPIO3 (EN3)
ILOAD ADC
Enable,
Roof and Floor,
or Slew-Rate
Control
BUCK1
ILIM Detection
Power-Good Detection
SDA
SCL
Overload and Short-Circuit
Detection
I2C
ILOAD ADC
PGOOD
BUCK2
Registers
OTP EPROM
ILIM Detection
Power-Good Detection
Digital
Logic
Overload and Short-Circuit
Detection
UVLO
Thermal
Monitor
ILOAD ADC
NRST
BUCK3
ILIM Detection
SW
Reset
Power-Good Detection
Reference
and Bias
Oscillator
Overload and Short-Circuit
Detection
CLKIN
ILOAD ADC
7.3 Feature Descriptions
7.3.1 DC-DC Converters
7.3.1.1 Overview
The LP87524B/J/P-Q1 includes four step-down DC-DC converter cores configured for four single-phase outputs.
The cores are designed for flexibility; most of the functions are programmable, thus giving a possibility to
optimize the regulator operation for each application.
The LP87524B/J/P-Q1 has the following features:
•
•
•
•
•
•
•
•
•
•
•
•
DVS support
Automatic mode control based on the loading (PFM or PWM mode)
Forced-PWM mode operation
Optional external clock input to minimize crosstalk
Optional spread spectrum technique to reduce EMI
Phase control for optimized EMI
Synchronous rectification
Current mode loop with PI compensator
Soft start
Power Good flag with maskable interrupt
Power Good signal (PGOOD) with selectable sources
Average output current sensing (for PFM entry and load current measurement)
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Feature Descriptions (接下页)
The following parameters can be programmed via registers:
•
•
•
Output voltage
Forced-PWM operation
Enable and disable delays for regulators and GPIOs controlled by ENx pins
There are two modes of operation for the converter, depending on the output current required: pulse-width
modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load
currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically
switch into PFM mode for reduced current consumption when forced-PWM mode is disabled.
A multi-phase synchronous buck converter offers several advantages over a single power stage converter. For
application processor power delivery, lower ripple on the input and output currents and faster transient response
to load steps are the most significant advantages. Also, because the load current is evenly shared among
multiple channels in multi-phase output configuration, the heat generated is greatly reduced for each channel due
to the fact that power loss is proportional to square of current. The physical size of the output inductor shrinks
significantly due to this heat reduction. A block diagram of a single core is shown in 图 5.
PMOS
Current
Sense
Differential to Single-
Ended
FBP
FBN
+
-
VIN
POS
Current
Limit
œ
Slave
Phase
Control
Ramp
Generator
VOUT
œ
Gate
Error
Control
Amp
SW
+
Loop
Comp
Voltage
Setting
Slew Rate
Control
NEG
Current
Limit
Power
Good
+
-
VDAC
Zero
Cross
Detect
NMOS
Current
Sense
Programmable
Parameters
Master
Interface
Control
Block
Slave
Interface
IADC
GND
Copyright © 2017, Texas Instruments Incorporated
图 5. Detailed Block Diagram Showing One Core
7.3.1.2 Transition Between PWM and PFM Modes
The LP87524B/J/P-Q1 converter operates in PWM mode at load current of about 600 mA or higher. At lighter
load-current levels the device automatically switches into PFM mode for reduced current consumption when
forced-PWM mode is disabled (AUTO-mode operation). By combining the PFM and the PWM modes a high
efficiency is achieved over a wide output-load-current range.
7.3.1.3 Buck Converter Load-Current Measurement
Buck load current can be monitored via I2C registers. The monitored buck converter is selected with the
LOAD_CURRENT_BUCK_SELECT[1:0] bits in SEL_I_LOAD register. A write to this selection register starts a
current measurement sequence. The regulator is forced to PWM mode during the measurement. The
measurement sequence is 50 µs long, maximum. LP87524B/J/P-Q1 can be configured to give out an interrupt
(I_LOAD_READY bit in INT_TOP1 register) after the load current measurement sequence is finished. Load
current measurement interrupt can be masked with I_LOAD_READY_MASK bit (TOP_MASK1 register). The
measurement result can be read from registers I_LOAD_1 and I_LOAD_2. Register I_LOAD_1 bits
BUCK_LOAD_CURRENT[7:0] give out the LSB bits and register I_LOAD_2 bits BUCK_LOAD_CURRENT[9:8]
the MSB bits. The measurement result BUCK_LOAD_CURRENT[9:0] LSB is 20 mA, and maximum value of the
measurement corresponds to 20.46 A.
16
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Feature Descriptions (接下页)
7.3.1.4 Spread-Spectrum Mode
Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband
frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add
EMI filters and shields to the boards. The LP87524B/J/P-Q1 device has register selectable spread-spectrum
mode which minimizes the need for output filters, ferrite beads, or chokes. In spread-spectrum mode, the
switching frequency varies around the center frequency, reducing the EMI emissions radiated by the converter
and associated passive components and PCB traces (see 图 6). This feature is available only when internal RC
oscillator is used (PLL_MODE[1:0] = 00 in PLL_CTRL register), and it is enabled with the EN_SPREAD_SPEC
bit (PIN_FUNCTION register), and it affects all the buck cores.
Frequency
Where a fixed-frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread-
spectrum architecture of the LP87524B/J/P-Q1 spreads that energy over a large bandwidth.
图 6. Spread-Spectrum Modulation
7.3.2 Sync Clock Functionality
The LP87524B/J/P-Q1 device contains a CLKIN input to synchronize switching clock of the buck regulator with
the external clock. The block diagram of the clocking and PLL module is shown in 图 7. Depending on the
PLL_MODE[1:0] bits (in PLL_CTRL register) and the external clock availability, the external clock is selected and
interrupt is generated as shown in 表 2. The interrupt can be masked with SYNC_CLK_MASK bit in
TOP_MASK1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits (in
PLL_CTRL register) and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside
accuracy limits (–30%/+10%) for valid clock detection.
The NO_SYNC_CLK interrupt (in INT_TOP1 register) is also generated in cases the external clock is expected
but it is not available. These cases are start-up (read OTP-to-STANDBY transition) when PLL_MODE[1:0] = 01
and regulator enable (STANDBY-to-ACTIVE transition) when PLL_MODE[1:0] = 10.
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Feature Descriptions (接下页)
24-MHz
RC
Oscillator
Internal
24-MHz
clock
CLKIN
Detector
Divider
“EXT_CLK_
FREQ“
Clock Select
Logic
CLKIN
1MHz
24MHz
PLL
“PLL_MODE“
1MHz
Divider
24
Copyright © 2017, Texas Instruments Incorporated
图 7. Clock and PLL Module
表 2. PLL Operation
DEVICE
OPERATION MODE
PLL AND CLOCK
DETECTOR STATE
INTERRUPT FOR
EXTERNAL CLOCK
PLL_MODE[1:0]
CLOCK
STANDBY
ACTIVE
00
00
Disabled
Disabled
No
No
Internal RC
Internal RC
When external clock
appears or disappears
Automatic change to external
clock when available
STANDBY
01
Enabled
When external clock
appears or disappears
Automatic change to external
clock when available
ACTIVE
STANDBY
ACTIVE
01
10
10
Enabled
Disabled
Enabled
No
Internal RC
When external clock
appears or disappears
Automatic change to external
clock when available
STANDBY
ACTIVE
11
11
Reserved
Reserved
7.3.3 Power-Up
The power-up sequence for the LP87524B/J/P-Q1 is as follows:
•
•
VANA (and VIN_Bx) reach minimum recommended level (VVANA > VANAUVLO).
NRST is set to high level (or shorted to VANA). This initiates power-on-reset (POR), OTP reading and
enables the system I/O interface. The I2C host must allow at least 1.2 ms before writing or reading data to the
LP87524B/J/P-Q1.
•
•
•
Device enters STANDBY-mode.
The host can change the default register setting by I2C if needed.
The regulator(s) can be enabled/disabled by ENx pin(s) and by I2C interface.
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7.3.4 Regulator Control
7.3.4.1 Enabling and Disabling Regulators
The regulator(s) can be enabled when the device is in STANDBY or ACTIVE state. There are two ways for
enable and disable the regulators:
•
•
Using EN_BUCKx bit in BUCKx_CTRL1 register (EN_PIN_CTRLx register bit is 0)
Using EN1/2/3 control pins (EN_BUCKx bit is 1 AND EN_PIN_CTRLx register bit is 1 in BUCKx_CTRL1
register)
If the EN1/2/3 control pins are used for enable and disable then the control pin is selected with
BUCKx_EN_PIN_SELECT[1:0] bits (in BUCKx_CTRL1 register). The delay from the control signal rising edge to
enabling of the regulator is set by BUCKx_STARTUP_DELAY[3:0] bits and the delay from control signal falling
edge to disabling of the regulator is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register.
The delays are valid only for EN1/2/3 signal control. The control with EN_BUCKx bit is immediate without the
delays.
The control of the regulator (with 0-ms delays) is shown in 表 3.
注
The control of the regulator cannot be changed from one ENx pin to a different ENx pin
because the control is ENx signal edge sensitive. The control from ENx pin to register bit
and back to the original ENx pin can be done during operation.
表 3. Regulator Control
CONTROL
METHOD
BUCKx_EN_PI EN_ROOF_FLOOR
BUCKx
OUTPUT VOLTAGE
EN_BUCKx EN_PIN_CTRLx
EN1 PIN
EN2 PIN
EN3 PIN
N_SELECT[1:0]
x
Enable/disable
control with
EN_BUCKx bit
0
1
Don't Care
0
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Disabled
Don't Care
BUCKx_VSET[7:0]
Enable/disable
control with EN1
pin
1
1
1
1
00
00
0
0
Low
Don't Care
Don't Care
Don't Care
Don't Care
Disabled
High
BUCKx_VSET[7:0]
Enable/disable
control with EN2
pin
1
1
1
1
01
01
0
0
Don't Care
Don't Care
Low
Don't Care
Don't Care
Disabled
High
BUCKx_VSET[7:0]
Enable/disable
control with EN3
pin
1
1
1
1
10
10
0
0
Don't Care
Don't Care
Don't Care
Don't Care
Low
Disabled
High
BUCKx_VSET[7:0]
Roof/floor control
with EN1 pin
1
1
1
1
1
1
1
1
1
1
1
1
00
00
01
01
10
10
1
1
1
1
1
1
Low
Don't Care
Don't Care
Low
Don't Care
Don't Care
Don't Care
Don't Care
Low
BUCKx_FLOOR_VSET[7:0]
BUCKx_VSET[7:0]
High
Roof/floor control
with EN2 pin
Don't Care
Don't Care
Don't Care
Don't Care
BUCKx_FLOOR_VSET[7:0]
BUCKx_VSET[7:0]
High
Roof/floor control
with EN3 pin
Don't Care
Don't Care
BUCKx_FLOOR_VSET[7:0]
BUCKx_VSET[7:0]
High
The regulator is enabled by the ENx pin or by I2C writing as shown in 图 8. The soft-start circuit limits the in-rush
current during start-up. When the output voltage rises to 0.35-V level, the output voltage becomes slew-rate
controlled. If there is a short circuit at the output and the output voltage does not increase above 0.35-V level in 1
ms, the regulator is disabled, and interrupt is set. When the output voltage reaches the Power-Good threshold
level the BUCKx_PG_INT interrupt flag (in INT_BUCK_x register) is set. The Power-Good interrupt flag can be
masked using BUCKx_PG_MASK bit (in BUCKx_MASK register).
The ENx input pins have integrated pulldown resistors. The pulldown resistors are enabled by default, and the
host can disable those with ENx_PD bits (in CONFIG register).
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Voltage decrease because of load
No new Powergood interrupt
BUCKx_VSET[7:0]
Powergood
Voltage
Ramp 3.8 mV/ms
0.6V
0.35V
Time
Resistive pull-down
(if enabled)
Soft start
Enable
BUCK_x_STAT(BUCKx_STAT)
BUCK_x_STAT(BUCKx_PG_STAT)
INT_BUCK_x(BUCKx_PG_INT)
nINT
0
0
0
1
0
0
1
1
0
1
0
Powergood
interrupt
Host clears
interrupt
图 8. Regulator Enable and Disable
7.3.4.2 Changing Output Voltage
The output voltage of the regulator can be changed by the ENx pin (voltage levels defined by the BUCKx_VOUT
and BUCKx_FLOOR_VOUT registers) or by writing to the BUCKx_VOUT and BUCKx_FLOOR_VOUT registers.
The voltage change is always slew-rate controlled, 3.8 mV/µs. During voltage change the forced-PWM mode is
used automatically. When the programmed output voltage is achieved, the mode becomes the one defined by
the load current and the BUCKx_FPWM bit in BUCKx_CTRL1 register.
The Power-Good interrupt is generated when the output voltage reaches the programmed voltage level, as
shown in 图 9.
20
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Voltage
BUCKx_VSET
Powergood
Ramp 3.8 mV/ms
Powergood
BUCKx_FLOOR_VSET
Time
ENx
1
1
0
BUCKx_STAT(BUCKx_STAT)
BUCKx_STAT(BUCKx_PG_STAT)
INT_BUCKx(BUCKx_PG_INT)
nINT
0
1
1
0
1
1
0
Powergood
interrupt
Host clears
interrupt
Powergood
interrupt
Host clears
interrupt
图 9. Regulator Output Voltage Change With ENx pin
7.3.5 Enable and Disable Sequences
The LP87524B/J/P-Q1 device supports start-up and shutdown sequencing with programmable delays for
different regulator outputs using single EN1/2/3 control signal. The regulator is selected for delayed control with:
•
•
•
•
•
•
EN_BUCKx = 1 (in BUCKx_CTRL1 register)
EN_PIN_CTRLx = 1 (in BUCKx_CTRL1 register)
EN_ROOF_FLOORx = 0 (in BUCKx_CTRL1 register)
BUCKx_VSET[7:0] = Required voltage when ENx is high (in BUCKx_VOUT register)
The ENABLE pin for control is selected with BUCKx_EN_PIN_SELECT[1:0] (in BUCKx_CTRL1 register)
The delay from rising edge of ENx signal to the regulator enable is set by BUCKx_STARTUP_DELAY[3:0]
bits (in BUCKx_DELAY register) and
•
The delay from falling edge of ENx signal to the regulator disable is set by BUCKx_SHUTDOWN_DELAY[3:0]
bits (in BUCKx_DELAY register)
There are four time steps available for start-up and shutdown sequences. The delay times are selected with
DOUBLE_DELAY bit in CONFIG register and HALF_DELAY bit in PGOOD_CTRL2 register as shown in 表 4.
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表 4. Start-up and Shutdown Delays
X_STARTUP_DELAY /
X_SHUTDOWN_DELAY
DOUBLE_DELAY = 0
HALF_DELAY = 1
DOUBLE_DELAY = 1
HALF_DELAY = 1
DOUBLE_DELAY = 0
HALF_DELAY = 0
DOUBLE_DELAY = 1
HALF_DELAY = 0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0 ms
0 ms
0 ms
1 ms
0 ms
0.32 ms
0.64 ms
0.96 ms
1.28 ms
1.6 ms
0.64 ms
1.28 ms
1.92 ms
2.56 ms
3.2 ms
2 ms
2 ms
4 ms
3 ms
6 ms
4 ms
8 ms
5 ms
10 ms
12 ms
14 ms
16 ms
18 ms
20 ms
22 ms
24 ms
26 ms
28 ms
30 ms
1.92 ms
2.24 ms
2.56 ms
2.88 ms
3.2 ms
3.84 ms
4.48 ms
5.12 ms
5.76 ms
6.4 ms
6 ms
7 ms
8 ms
9 ms
10 ms
11 ms
12 ms
13 ms
14 ms
15 ms
3.52 ms
3.84 ms
4.16 ms
4.48 ms
4.8 ms
7.04 ms
7.68 ms
8.32 ms
8.96 ms
9.6 ms
An example of start-up and shutdown sequences is shown in 图 10 and 图 11. The start-up and shutdown delays
for the Buck0/1 regulators are 1 ms and 4 ms and for the Buck2/3 regulators 3 ms and 1 ms. The delay settings
are used only for enable/disable control with EN1/2/3 signals, not for Roof/Floor control.
ENx
EN_BUCK01
EN_BUCK23
1 ms
4 ms
3 ms
1 ms
图 10. Typical Start-Up and Shutdown Sequencing
ENx
Start-up control
Shutdown control
EN_BUCK01
0
0
0
1
0
1
2
3
4
5
6
0
0
1
0
1
2
0
1
2
3
4
5
1 ms
4 ms
EN_BUCK23
3 ms
1 ms
图 11. Start-Up and Shutdown Sequencing With Short ENx Low and High Periods
22
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7.3.6 Device Reset Scenarios
There are three reset methods implemented on the LP87524B/J/P-Q1:
•
•
•
Software reset with SW_RESET register bit (in RESET register)
POR from rising edge of NRST signal
Undervoltage lockout (UVLO) reset from VANA supply
A SW-reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event
disables all the regulators immediately, resets all the register bits to the default values and OTP bits are loaded
(see 图 15). I2C interface is not reset during software reset. The host must wait at least 1.2 ms after writing SW
reset until making a new I2C read or write to the device.
If VANA supply voltage falls below UVLO threshold level or NRST signal is set low then all the regulators are
disabled immediately, and all the register bits are reset to the default values. When the VANA supply voltage
rises above UVLO threshold level AND NRST signal rises above threshold level an internal power-on reset
(POR) occurs. OTP bits are loaded to the registers and a start-up is initiated according to the register settings.
The host must wait at least 1.2 ms after POR until reading or writing to I2C interface.
7.3.7 Diagnosis and Protection Features
The LP87524B/J/P-Q1 is capable of providing four levels of protection features:
•
•
•
•
Information of valid regulator output voltage which sets interrupt or PGOOD signal;
Warnings for diagnosis which sets interrupt;
Protection events which are disabling the regulators affected; and
Faults which are causing the device to shutdown.
The LP87524B/J/P-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the
nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all
the pending interrupts are cleared.
When a fault is detected, it is indicated by a RESET_REG interrupt flag (in INT2_TOP register) after next start-
up.
表 5. Summary of Interrupt Signals
INTERRUPT REGISTER AND
BIT
RECOVERY/INTERRUPT
CLEAR
EVENT
RESULT
INTERRUPT MASK
STATUS BIT
Current limit triggered
(20-µs debounce)
Interrupt
INT_BUCKx = 1
BUCKx_ILIM_INT = 1
BUCKx_ILIM_MASK
BUCKx_ILIM_STAT
Write 1 to BUCKx_ILIM_INT bit
Interrupt is not cleared if
current limit is active
Short circuit (VVOUT
<
Regulator disable and
interrupt
INT_BUCKx = 1
BUCKx_SC_INT = 1
N/A
N/A
Write 1 to BUCKx_SC_INT bit
0.35 V at 1 ms after
enable) or overload
(VVOUT decreasing
below 0.35 V during
operation, 1 ms
debounce)
Thermal warning
Thermal whutdown
VANA overvoltage
Interrupt
TDIE_WARN = 1
TDIE_SD = 1
INT_OVP
TDIE_WARN_MASK
TDIE_WARN_STAT
TDIE_SD_STAT
OVP_STAT
Write 1 to TDIE_WARN bit
Interrupt is not cleared if
temperature is above thermal
warning level
All regulators disabled
and Output GPIOx set to
low and interrupt
N/A
Write 1 to TDIE_SD bit
Interrupt is not cleared if
temperature is above thermal
shutdown level
All regulators disabled
and Output GPIOx set to
low and interrupt
N/A
Write 1 to INT_OVP bit
Interrupt is not cleared if VANA
voltage is above VANA OVP
level
(VANAOVP
)
Power Good, output
voltage reaches the
programmed value
Interrupt
INT_BUCKx = 1
BUCKx_PG_INT = 1
BUCKx_PG_MASK
BUCKx_PG_STAT
Write 1 to BUCKx_PG_INT bit
GPIO
Interrupt
Interrupt
INT_GPIO
GPIO_MASK
GPIO_IN register
SYNC_CLK_STAT
Write 1 to INT_GPIO bit
External clock appears
or disappears
NO_SYNC_CLK(1)
SYNC_CLK_MASK
Write 1 to NO_SYNC_CLK bit
Load current
Interrupt
I_LOAD_READY = 1
I_LOAD_READY_MASK
N/A
Write 1 to I_LOAD_READY bit
measurement ready
(1) Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled.
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表 5. Summary of Interrupt Signals (接下页)
INTERRUPT REGISTER AND
BIT
RECOVERY/INTERRUPT
CLEAR
EVENT
RESULT
INTERRUPT MASK
STATUS BIT
Start-up (NRST rising
edge)
Device ready for
operation, registers reset
to default values and
interrupt
RESET_REG = 1
RESET_REG = 1
RESET_REG = 1
RESET_REG_MASK
N/A
N/A
N/A
Write 1 to RESET_REG bit
Write 1 to RESET_REG bit
Write 1 to RESET_REG bit
Glitch on supply voltage Immediate shutdown
RESET_REG_MASK
RESET_REG_MASK
and UVLO triggered
(VANA falling and
rising)
followed by power up,
registers reset to default
values and interrupt
Software requested
reset
Immediate shutdown
followed by power up,
registers reset to default
values and interrupt
7.3.7.1 Power-Good Information (PGOOD pin)
In addition to the interrupt based indication of current limit and Power-Good level the LP87524B/J/P-Q1 device
supports the indication with PGOOD signal. Either voltage and current monitoring or a voltage monitoring only
can be selected for PGOOD indication. This selection is individual for all buck regulators and is set by
PGx_SEL[1:0] bits (in PGOOD_CTRL1 register). When both voltage and current are monitored, PGOOD signal
active indicates that regulator output is inside the Power-Good voltage window and that load current is below ILIM
FWD. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal. When a regulator
is disabled, the monitoring is automatically masked to prevent it forcing PGOOD inactive. This allows connecting
PGOOD signals from various devices together when open-drain outputs are used. When regulator voltage is
transitioning from one target voltage to another, the voltage monitoring PGOOD signal is set inactive. The
monitoring from all the output rails are combined, and PGOOD is active only if all the sources shows active
status. The status from all the voltage rails are summarized in 表 6.
If the PGOOD signal is inactive or it changes the state to inactive, the source for the state can be read from
PGOOD_FLT register. During reading all the PGx_FLT bit are cleared that are not driving the PGOOD inactive.
When PGOOD signal goes active, the host must read the PGOOD_FLT register to clear all the bits. The PGOOD
signal follows the status of all the monitored outputs.
The PGOOD signal can be also configured so that it maintains inactive state even when the monitored outputs
are valid but there are PGx_FLT bits pending clearance in PGOOD_FLT register. This mode of operation is
selected by setting EN_PGFLT_STAT bit to 1 (in PGOOD_CTRL2 register).
The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit (in
PGOOD_CTRL2 register). If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and
overvoltage are monitored.
The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and PGOOD_OD bits in
PGOOD_CTRL2 register.
The filtering time for invalid output voltage is always typically 7 µs and for valid output voltage the filtering time is
selected with PGOOD_SET_DELAY bit (in PGOOD_CTRL2 register). The Power-Good waveforms are shown in
图 13.
24
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ILIM
Buck0
Buck1
Buck2
Buck3
MUX
Power Good
PG0_SEL[1:0]
ILIM
MUX
Power Good
PG1_SEL[1:0]
PGOOD
ILIM
MUX
Power Good
PG2_SEL[1:0]
ILIM
MUX
Power Good
PG3_SEL[1:0]
Copyright © 2017, Texas Instruments Incorporated
图 12. PGOOD Block Diagram
表 6. PGOOD Operation
STATUS / USE CASE
CONDITION
INPUT TO PGOOD SIGNAL
PGx_SEL = 00 (in PGOOD_CTRL1
register)
Buck not selected for PGOOD monitoring
Active
Active
Buck disabled
BUCK SELECTED FOR PGOOD MONITORING
Buck start-up delay
Inactive
Inactive
Inactive
Buck soft start
VOUT < 0.35 V
Buck voltage ramp-up
0.35 V < VOUT < VSET
Output voltage within window limits after
start-up
Must be inside limits longer than debounce
time
Active
Output voltage inside voltage window and Current limit active longer than debounce
Active (if only voltage monitoring selected)
Inactive (if also current monitoring selected)
current limit active
time
Output voltage spikes (overvoltage or
undervoltage)
If spikes are outside voltage window longer
than debounce time
Inactive
Inactive
Active
Voltage setting change, output voltage
ramp
Output voltage within window limits after
voltage change
Must be inside limits longer than debounce
time
Buck shutdown delay
Active
Active
Buck output voltage ramp down
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表 6. PGOOD Operation (接下页)
STATUS / USE CASE
CONDITION
INPUT TO PGOOD SIGNAL
Buck disabled by thermal shutdown and
interrupt pending
Inactive
Inactive
Inactive
Buck disabled by overvoltage and
interrupt pending
Buck disabled by short-circuit detection
and interrupt pending
Voltage
Powergood window
BUCKx_VSET (1)
Powergood
window
BUCKx_VSET (2)
Time
ENx
7us/11ms
PGOOD_SET_DELAY
PGOOD
BUCKx_VSET (1)
BUCKx_VSET (2)
BUCKx_VSET
图 13. PGOOD Waveforms (PGOOD_POL=0)
7.3.7.2 Warnings for Diagnosis (Interrupt)
7.3.7.2.1 Output Power Limit
The regulators have output peak current limits. The peak current limits are described in Specifications. If the load
current is increased so that the current limit is triggered, the regulator continues to regulate to the limit current
level (current peak regulation, peak on every switching cycle). The voltage may decrease if the load current is
higher than the average output current. If the current regulation continues for 20 µs, the LP87524B/J/P-Q1 device
sets the BUCKx_ILIM_INT bit (in INT_BUCKx register) and pulls the nINT pin low. The host processor can read
BUCKx_ILIM_STAT bits (in BUCKx_STAT register) to see if the regulator is still in peak current regulation mode.
If the load is so high that the output voltage decreases below a 350-mV level, the LP87524B/J/P-Q1 device
disables the regulator and sets the BUCKx_SC_INT bit (in INT_BUCKx register). In addition the BUCKx_STAT
bit (in BUCKx_STAT register) is set to 0. The interrupt is cleared when the host processor writes 1 to
BUCKx_SC_INT bit. The overload situation is shown in 图 14.
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Regulator
disabled by digital
New start-up if
enable is valid
Voltage
VOUTx
350 mV
Resistive
pulldown
1 ms
Time
Current
ILIMx
Time
20 ms
INT_BUCKx
(BUCKx_ILIM_INT)
0
0
1
1
0
INT_BUCK
(BUCKx_SC_INT)
1
0
0
1
BUCKx_STAT
(BUCKx_STAT)
nINT
Host clearing the interrupt by writing to flags
图 14. Overload Situation
7.3.7.2.2 Thermal Warning
The LP87524B/J/P-Q1 device includes a monitoring feature against overtemperature by setting an interrupt for
host processor. The threshold level of the thermal warning is selected with TDIE_WARN_LEVEL bit (in CONFIG
register).
If the LP87524B/J/P-Q1 device temperature increases above thermal warning level the device sets TDIE_WARN
bit (in INT_TOP1 register) and pulls nINT pin low. The status of the thermal warning can be read from
TDIE_WARN_STAT bit (in TOP_STAT register), and the interrupt is cleared by writing 1 to TDIE_WARN bit.
7.3.7.3 Protection (Regulator Disable)
If the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal
shutdown, overvoltage protection, or UVLO), the output power FETs are set to high-impedance mode, and the
output pulldown resistor is enabled (if enabled with EN_RDISx bits in BUCKx_CTRL1 register). The turnoff time
of the output voltage is defined by the output capacitance, load current, and the resistance of the integrated
pulldown resistor. The pulldown resistors are active as long as VANA voltage is above approximately a 1.2-V
level.
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7.3.7.3.1 Short-Circuit and Overload Protection
A short-circuit protection feature allows the LP87524B/J/P-Q1 to protect itself and external components against
short circuit at the output or against overload during start-up. The fault threshold is 350 mV, the protection is
triggered, and the regulator is disabled if the output voltage is below the threshold level 1 ms after the regulator
is enabled.
In a similar way the overload situation is protected during normal operation. If the voltage on the feedback pin of
the regulator falls below 0.35 V and remains below the threshold level for 1 ms, the regulator is disabled.
In the short-circuit and overload situations the BUCKx_SC_INT (in INT_BUCKx register) and the INT_BUCKx bits
(in INT_TOP1 register) are set to 1, the BUCKx_STAT bit (in BUCKx_STAT register) is set to 0, and the nINT
signal is pulled low. The host processor clears the interrupt by writing 1 to the BUCKx_SC_INT bit. Upon clearing
the interrupt the regulator makes a new start-up attempt if the regulator is in enabled state.
7.3.7.3.2 Overvoltage Protection
The LP87524B/J/P-Q1 device monitors the input voltage from the VANA pin in standby and active operation
modes. If the input voltage rises above VANAOVP voltage level, all the regulators are disabled, pulldown resistors
discharge the output voltages (if EN_RDISx = 1 in BUCKx_CTRL1 register), GPIOs that are configured to
outputs are set to logic low level, nINT signal is pulled low, INT_OVP bit (in INT_TOP1 register) is set to 1, and
BUCKx_STAT bits (in BUCK_x_STAT register) are set to 0. The host processor clears the interrupt by writing 1
to the INT_OVP bit. If the input voltage is above the overvoltage detection level the interrupt is not cleared. The
host can read the status of the overvoltage from the OVP_STAT bit (in TOP_STAT register). Regulators cannot
be enabled as long as the input voltage is above overvoltage detection level or the overvoltage interrupt is
pending.
7.3.7.3.3 Thermal Shutdown
The LP87524B/J/P-Q1 has an overtemperature protection function that operates to protect the device from short-
term misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are
disabled, the TDIE_SD bit (in INT_TOP1 register) is set to 1, the nINT signal is pulled low, and the device enters
STANDBY. nINT is cleared by writing 1 to the TDIE_SD bit. If the temperature is above thermal shutdown level
the interrupt is not cleared. The host can read the status of the thermal shutdown from the TDIE_SD_STAT bit
(in TOP_STAT register). Regulators cannot be enabled as long as the junction temperature is above thermal
shutdown level or the thermal shutdown interrupt is pending.
7.3.7.4 Fault (Power Down)
7.3.7.4.1 Undervoltage Lockout
When the input voltage falls below VANAUVLO at the VANA pin, the buck converters are disabled immediately,
and the output capacitors are discharged using the pulldown resistor, and the LP87524B/J/P-Q1 device enters
SHUTDOWN. When VANA voltage is above UVLO threshold level and NRST signal is high, the device powers
up to STANDBY state.
If the reset interrupt is unmasked by default (RESET_REG_MASK = 0 in TOP_MASK2 register) the
RESET_REG interrupt (in INT_TOP2 register) indicates that the device has been in SHUTDOWN. The host
processor must clear the interrupt by writing 1 to the RESET_REG bit. If the host processor reads the
RESET_REG flag after detecting an nINT low signal, it knows that the input supply voltage has been below
UVLO level (or the host has requested reset), and the registers are reset to default values.
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7.3.8 GPIO Signal Operation
The LP87524B/J/P-Q1 device supports up to 3 GPIO signals. The GPIO signals are multiplexed with enable
signals. The selection between enable and GPIO function is set with GPIOx_SEL bits in PIN_FUNCTION
register. The GPIOs are mapped to EN signals so that:
•
•
•
EN1 is multiplexed with GPIO1
EN2 is multiplexed with GPIO2
EN3 is multiplexed with GPIO3
When the pin is selected for GPIO function, additional bits defines how the GPIO operates:
•
•
GPIOx_DIR defines the direction of the GPIO, input or output (GPIO_CONFIG register)
GPIOx_OD defines the type of the output when the GPIO is set to output, either push-pull with VANA level or
open-drain (GPIO_CONFIG register)
When the GPIOx is defined as output, the logic level of the pin is set by GPIOx_OUT bit (in GPIO_OUT register).
When the GPIOx is defined as input, the logic level of the pin can be read from GPIOx_IN bit (in GPIO_IN
register).
The control of the GPIOs configured to outputs can be included to start-up and shutdown sequences. The GPIO
control for a sequence with ENx signal is selected by EN_PIN_CTRL_GPIOx and EN_PIN_SELECT_GPIOx bits
(in
PIN_FUNCTION
register).
The
delays
during
start-up
and
shutdown
are
set
by
GPIOx_STARTUP_DELAY[3:0] and GPIOx_SHUTDOWN_DELAY[3:0] bits (in GPIOx_DELAY register) in the
same way as control of the regulators.
The GPIOx signals have a selectable pulldown resistor. The pulldown resistors are selected by ENx_PD bits (in
CONFIG register).
注
The control of the GPIOx pin cannot be changed from one ENx pin to a different ENx pin
because the control is ENx signal edge sensitive. The control from ENx pin to register bit
and back to the original ENx pin can be done during operation.
7.3.9 Digital Signal Filtering
The digital signals have a debounce filtering. The signal/supply is sampled with a clock signal and a counter.
This results as an accuracy of one clock period for the debounce window.
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ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
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表 7. Digital Signal Filtering
FALLING EDGE DEBOUNCE
TIME
EVENT
SIGNAL/SUPPLY
RISING EDGE DEBOUNCE TIME
Enable/disable/voltage select
for Buckx
(1)
(1)
(1)
(1)
EN1
EN2
EN3
3 µs
3 µs
3 µs
3 µs
Enable/disable/voltage select
for Buckx
(1)
3 µs
Enable/disable/voltage select
for Buckx
(1)
3 µs
VANA UVLO
VANA
VANA
20 µs (VANA voltage rising)
Immediate (VANA voltage falling)
VANA overvoltage
Thermal warning
Thermal shutdown
Current limit
20 µs (VANA voltage rising)
20 µs (VANA voltage falling)
TDIE_WARN
TDIE_SD
VOUTx_ILIM
20 µs
20 µs
20 µs
20 µs
20 µs
20 µs
FB_B0, FB_B1, FB_B2,
FB_F3
Overload
1 ms
20 µs
20 µs
FB_B0, FB_B1, FB_B2,
FB_F3
Power-Good interrupt
20 µs
PGOOD pin (voltage
monitoring)
PGOOD / FB_B0, FB_B1,
FB_B2, FB_F3
4-8 µs (start-up debounce time during
start-up)
4 to 8 µs
20 µs
PGOOD pin (current
monitoring)
PGOOD
20 µs
(1) No glitch filtering, only synchronization.
7.4 Device Functional Modes
7.4.1 Modes of Operation
SHUTDOWN: The NRST voltage is below threshold level. All switch, reference, control, and bias circuitry of the
LP87524B/J/P-Q1 device are turned off.
READ OTP: The main supply voltage VANA is above VANAUVLO level and NRST voltage is above threshold
level. The regulators are disabled and the reference and bias circuitry of the LP87524B/J/P-Q1 are
enabled. The OTP bits are loaded to registers.
STANDBY: The main supply voltage VANA is above VANAUVLO level and NRST voltage is above threshold
level. The regulators are disabled and the reference, control and bias circuitry of the LP87524B/J/P-
Q1 are enabled. All registers can be read or written by the host processor via the system serial
interface. The regulators can be enabled if needed.
ACTIVE:
The main supply voltage VANA is above VANAUVLO level and NRST voltage is above threshold
level. At least one regulated DC-DC converter is enabled. All registers can be read or written by the
host processor via the system serial interface.
The operating modes and transitions between the modes are shown in 图 15.
30
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Device Functional Modes (接下页)
SHUTDOWN
NRST low
OR
VVANA < VANAUVLO
NRST high
AND
VVANA > VANAUVLO
From any state except
SHUTDOWN
READ
OTP
REGISTER
RESET
STANDBY
I2C RESET
REGULATOR
ENABLED
REGULATORS
DISABLED
ACTIVE
图 15. Device Operation Modes
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7.5 Programming
7.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the devices
connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every
device on the bus is assigned a unique address and acts as either a master or a slave depending on whether it
generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed
somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data
transfer. The LP87524B/J/P-Q1 supports standard mode (100 kHz), fast mode (400 kHz), fast mode+ (1 MHz),
and high-speed mode (3.4 MHz).
7.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
change
allowed
data
change
allowed
data
valid
data
valid
图 16. Data Validity Diagram
7.5.1.2 Start and Stop Conditions
The LP87524B/J/P-Q1 is controlled via an I2C-compatible interface. START and STOP conditions classify the
beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while
SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C
master always generates the START and STOP conditions.
SDA
SCL
S
P
START
STOP
Condition
Condition
图 17. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. 图 18 shows the SDA
and SCL signal timing for the I2C-compatible bus. See the 图 1 for timing values.
32
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Programming (接下页)
tBUF
SDA
tHD;STA
trCL
tfDA
trDA
tLOW
tfCL
tSP
SCL
tHD;STA
tHD;DAT
tSU;STA
tSU;STO
tHIGH
S
tSU;DAT
S
RS
P
START
REPEATED
START
STOP
START
图 18. I2C-Compatible Timing
7.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The
LP87524B/J/P-Q1 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The
LP87524B/J/P-Q1 generates an acknowledge after each byte has been received.
There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
注
If the NRST signal is low during I2C communication the LP87524B/J/P-Q1 device does not
drive SDA line. The ACK signal and data transfer to the master is disabled at that time.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
ACK from slave
ACK from slave
ACK from slave
START MSB Chip Address LSB
W
ACK MSB Register Address LSB ACK
MSB Data LSB
ACK STOP
SCL
SDA
START
id = 0x60
W
ACK
address = 0x40
ACK
address 0x40 data
ACK STOP
图 19. Write Cycle (w = write; SDA = 0), id = Device Address = 0x60 for LP87524B/J/P-Q1
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Programming (接下页)
ACK from slave
ACK from slave REPEATED START
ACK from slave Data from slave NACK from master
START MSB Chip Address LSB
W
MSB Register Address LSB
RS
MSB Chip Address LSB
R
MSB Data LSB
STOP
SCL
SDA
START
ACK
ACK
ACK
NACK
STOP
id = 0x60
W
address = 0x3F
RS
id = 0x60
R
address 0x3F data
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
图 20. Read Cycle ( r = read; SDA = 1), id = Device Address = 0x60 for LP87524B/J/P-Q1
7.5.1.4 I2C-Compatible Chip Address
注
The device address for the LP87524B/J/P-Q1 is 0x60
After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W).
R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address
selects the register address to which the data will be written. The third byte contains the data for the selected
register.
MSB
LSB
1
Bit 7
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
I2C Slave Address (chip address)
A. Here device address is 1100000Bin = 60Hex.
图 21. Example Device Address
7.5.1.5 Auto-Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-
bit word is sent to the device, the internal address index counter is incremented by one and the next register is
written. 表 8 below shows writing sequence to two consecutive registers. Note that auto increment feature does
not work for read.
表 8. Auto-Increment Example
DEVICE
ADDRESS
= 0x60
MASTER
ACTION
REGISTER
ADDRESS
START
WRITE
DATA
DATA
STOP
LP87524B/J/P-
Q1
ACK
ACK
ACK
ACK
34
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7.6 Register Maps
7.6.1 Register Descriptions
The LP87524B/J/P-Q1 is controlled by a set of registers through the I2C-compatible interface. The device
registers, their addresses, and their abbreviations are listed in 表 9. A more detailed description is given in the
OTP_REV to GPIO_OUT sections.
The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state.
注
This register map describes the default values read from OTP memory for a device with
orderable code of LP87524BRNFRQ1, LP87524JRNFRQ1 and LP87524PRNFRQ1. For
other LP8752x versions the default values read from OTP memory can be different.
表 9. Summary of LP87524B/J/P-Q1 Control Registers
Addr
Register
Read /
Write
D7
D6
D5
D4
D3
D2
D1
D0
0x01
0x02
OTP_REV
R
OTP_ID[7:0]
BUCK0_
CTRL1
EN_PIN_
CTRL0
BUCK0_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR0
BUCK0_
FPWM
R/W
EN_BUCK0
EN_BUCK1
EN_BUCK2
EN_BUCK3
EN_RDIS0
EN_RDIS1
EN_RDIS2
EN_RDIS3
Reserved
Reserved
Reserved
Reserved
BUCK1_
CTRL1
EN_PIN_
CTRL1
BUCK1_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR1
BUCK1_
FPWM
0x04
0x06
0x08
0x0A
R/W
R/W
R/W
R/W
BUCK2_
CTRL1
EN_PIN_
CTRL2
BUCK2_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR2
BUCK2_
FPWM
BUCK3_
CTRL1
EN_PIN_
CTRL3
BUCK3_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR3
BUCK3_
FPWM
BUCK0_
VOUT
BUCK0_VSET[7:0]
BUCK0_
FLOOR_
VOUT
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BUCK0_FLOOR_VSET[7:0]
BUCK1_VSET[7:0]
BUCK1_
VOUT
BUCK1_
FLOOR_
VOUT
BUCK1_FLOOR_VSET[7:0]
BUCK2_VSET[7:0]
BUCK2_
VOUT
BUCK2_
FLOOR_
VOUT
BUCK2_FLOOR_VSET[7:0]
BUCK3_VSET[7:0]
BUCK3_
VOUT
BUCK3_
FLOOR_
VOUT
BUCK3_FLOOR_VSET[7:0]
BUCK0_
DELAY
0x12
0x13
0x14
0x15
0x16
0x17
0x18
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK1_SHUTDOWN_DELAY[3:0]
BUCK2_SHUTDOWN_DELAY[3:0]
BUCK3_SHUTDOWN_DELAY[3:0]
GPIO2_SHUTDOWN_DELAY[3:0]
GPIO3_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
BUCK1_STARTUP_DELAY[3:0]
BUCK2_STARTUP_DELAY[3:0]
BUCK3_STARTUP_DELAY[3:0]
GPIO2_STARTUP_DELAY[3:0]
GPIO3_STARTUP_DELAY[3:0]
BUCK1_
DELAY
BUCK2_
DELAY
BUCK3_
DELAY
GPIO2_
DELAY
GPIO3_
DELAY
SW_
RESET
RESET
Reserved
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Register Maps (接下页)
表 9. Summary of LP87524B/J/P-Q1 Control Registers (接下页)
Addr
Register
Read /
Write
D7
D6
D5
D4
D3
D2
D1
D0
TDIE
_WARN
_LEVEL
DOUBLE_D
ELAY
0x19
CONFIG
R/W
CLKIN_PD
Reserved
EN3_PD
EN2_PD
EN1_PD
Reserved
INT_
BUCK23
INT_
BUCK01
NO_SYNC
_CLK
TDIE_
WARN
INT_
OVP
I_LOAD_
READY
0x1A
0x1B
0x1C
0x1D
INT_TOP1
INT_TOP2
R/W
R/W
R/W
R/W
Reserved
TDIE_SD
RESET_
REG
Reserved
INT_BUCK_
0_1
BUCK1_
PG_INT
BUCK1_
SC_INT
BUCK1_
ILIM_INT
BUCK0_
PG_INT
BUCK0_
SC_INT
BUCK0_
ILIM_INT
Reserved
Reserved
Reserved
Reserved
INT_BUCK_
2_3
BUCK3_
PG_INT
BUCK3_
SC_INT
BUCK3_
ILIM_INT
BUCK2_
PG_INT
BUCK2_
SC_INT
BUCK2_
ILIM_INT
TDIE_
WARN_
STAT
TOP_
STAT
SYNC_CLK
_STAT
TDIE_SD
_STAT
OVP_
STAT
0x1E
R
Reserved
Reserved
BUCK1_
ILIM_
STAT
BUCK0_
ILIM_
STAT
BUCK_0_1_
STAT
BUCK1_
STAT
BUCK1_
PG_STAT
BUCK0_
STAT
BUCK0_
PG_STAT
0x1F
0x20
0x21
0x22
0x23
R
Reserved
Reserved
Reserved
Reserved
Reserved
BUCK_2_3_
STAT
BUCK3_
STAT
BUCK3_
PG_STAT
BUCK3_
ILIM_STAT
BUCK2_
STAT
BUCK2_
PG_STAT
BUCK2_
ILIM_STAT
R
I_LOAD_
READY_
MASK
TOP_
MASK1
SYNC_CLK
_MASK
TDIE_WAR
N_MASK
R/W
R/W
R/W
Reserved
Reserved
Reserved
TOP_
MASK2
RESET_
REG_MASK
Reserved
BUCK1_
ILIM_
MASK
BUCK0_
ILIM_
MASK
BUCK_0_1_
MASK
BUCK1_
PG_MASK
BUCK0_
PG_MASK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BUCK3_
ILIM_
MASK
BUCK2_
ILIM_
MASK
BUCK_2_3_
MASK
BUCK3_
PG_MASK
BUCK2_
PG_MASK
0x24
0x25
R/W
R/W
SEL_I_
LOAD
LOAD_CURRENT_
BUCK_SELECT[1:0]
Reserved
Reserved
BUCK_LOAD_CURRENT[7:0]
PG2_SEL[1:0] PG1_SEL[1:0]
BUCK_LOAD_CURRENT[
9:8]
0x26
0x27
0x28
I_LOAD_2
I_LOAD_1
R
R
PGOOD
_CTRL1
R/W
PG3_SEL[1:0]
PG0_SEL[1:0]
PGOOD_SE
T_
DELAY
PGOOD
_CTRL2
HALF_DEL
AY
EN_PG0_
NINT
EN_PGFLT
_STAT
PGOOD_WI PGOOD_O
PGOOD_P
OL
0x29
R/W
Reserved
PG3_FLT
NDOW
D
PGOOD_FL
T
0x2A
0x2B
R
PG2_FLT
PG1_FLT
PG0_FLT
PLL_CTRL
R/W
PLL_MODE[1:0]
Reserved
EXT_CLK_FREQ[4:0]
EN_
SPREAD
_SPEC
EN_PIN_CT EN_PIN_SE EN_PIN_CT EN_PIN_SE
PIN_
FUNCTION
0x2C
R/W
RL
LECT
RL
LECT
GPIO3_SEL GPIO2_SEL GPIO1_SEL
GPIO3_DIR GPIO2_DIR GPIO1_DIR
_GPIO3
_GPIO3
_GPIO2
_GPIO2
GPIO_
CONFIG
0x2D
0x2E
0x2F
R/W
R
Reserved
GPIO3_OD GPIO2_OD GPIO1_OD
Reserved
GPIO_IN
Reserved
Reserved
GPIO3_IN
GPIO2_IN
GPIO1_IN
GPIO3_OU GPIO2_OU GPIO1_OU
GPIO_OUT
R/W
T
T
T
36
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ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
7.6.1.1 OTP_REV
Address: 0x01
D7
D6
D5
D4
D3
D2
D1
D0
OTP_ID[7:0]
Bits
Field
Type
Default
Description
7:0
OTP_ID[7:0]
R
0x71 for
LP87524B,
0x72 for
LP87524J, Identification code of the OTP EPROM version
0x3B for
LP87524P
*
7.6.1.2 BUCK0_CTRL1
Address: 0x02
D7
D6
D5
D4
D3
D2
D1
D0
EN_BUCK0
EN_PIN_CTRL BUCK0_EN_PIN_SELECT[1:0]
0
EN_ROOF_
FLOOR0
EN_RDIS0
BUCK0_FPWM
Reserved
Bits
Field
Type
Default
Description
7
EN_BUCK0
R/W
1 *
Enable Buck0 regulator:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled
6
EN_PIN_CTRL0
R/W
R/W
1 *
Enable EN1/2/3 pin control for Buck0:
0 - Only the EN_BUCK0 bit controls Buck0
1 - EN_BUCK0 bit AND ENx pin control Buck0
5:4
BUCK0_EN_PIN
_SELECT[1:0]
0x0*
Enable EN1/2/3 pin control for Buck0:
0x0 - EN_BUCK0 bit AND EN1 pin control Buck0
0x1 - EN_BUCK0 bit AND EN2 pin control Buck0
0x2 - EN_BUCK0 bit AND EN3 pin control Buck0
0x3 - Reserved
3
2
1
EN_ROOF_
FLOOR0
R/W
R/W
R/W
0
1
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL0 = 1:
0 - Enable/disable (1/0) control
1 - Roof/floor (1/0) control
EN_RDIS0
Enable output discharge resistor when Buck0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
BUCK0_FPWM
0 for
LP87524B,
LP87524J,
1 for
LP87524P
*
Forces the Buck0 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode).
1 - Forced to PWM operation
0
Reserved
R/W
0 *
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7.6.1.3 BUCK1_CTRL1
Address: 0x04
D7
D6
D5
D4
D3
D2
D1
D0
EN_BUCK1
EN_PIN_CTRL BUCK1_EN_PIN_SELECT[1:0]
1
EN_ROOF_
FLOOR1
EN_RDIS1
BUCK1_FPWM
Reserved
Bits
Field
Type
Default
Description
7
EN_BUCK1
R/W
1 *
Enable Buck1 regulator:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled
6
EN_PIN_CTRL1
R/W
R/W
1 *
Enable EN1/2/3 pin control for Buck1:
0 - Only EN_BUCK1 bit controls Buck1
1 - EN_BUCK1 bit AND ENx pin control Buck1
5:4
BUCK1_EN_PIN
_SELECT[1:0]
0x0*
Enable EN1/2/3 pin control for Buck1:
0x0 - EN_BUCK1 bit AND EN1 pin control Buck1
0x1 - EN_BUCK1 bit AND EN2 pin control Buck1
0x2 - EN_BUCK1 bit AND EN3 pin control Buck1
0x3 - Reserved
3
2
1
EN_ROOF_
FLOOR1
R/W
R/W
R/W
0
1
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL1 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control
EN_RDIS1
Enable output discharge resistor when Buck1 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
BUCK1_FPWM
0 for
LP87524B,
LP87524J,
1 for
LP87524P
*
Forces the Buck1 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode).
1 - Forced to PWM operation
0
Reserved
R/W
0
38
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7.6.1.4 BUCK2_CTRL1
Address: 0x06
D7
D6
D5
D4
D3
D2
D1
D0
EN_BUCK2
EN_PIN_CTRL BUCK2_EN_PIN_SELECT[1:0]
2
EN_ROOF_
FLOOR2
EN_RDIS2
BUCK2_FPWM
Reserved
Bits
Field
Type
Default
Description
7
EN_BUCK2
R/W
1 *
Enable Buck2 regulator:
0 - Buck2 regulator is disabled
1 - Buck2 regulator is enabled
6
EN_PIN_CTRL2
R/W
R/W
1 *
Enable EN1/2/3 pin control for Buck2:
0 - Only EN_BUCK2 bit controls Buck2
1 - EN_BUCK2 bit AND ENx pin control Buck2
5:4
BUCK2_EN_PIN
_SELECT[1:0]
0x0*
Enable EN1/2/3 pin control for Buck2:
0x0 - EN_BUCK2 bit AND EN1 pin control Buck2
0x1 - EN_BUCK2 bit AND EN2 pin control Buck2
0x2 - EN_BUCK2 bit AND EN3 pin control Buck2
0x3 - Reserved
3
2
1
0
EN_ROOF_
FLOOR2
R/W
R/W
R/W
R/W
0
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL2 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control
EN_RDIS2
BUCK2_FPWM
Reserved
1
Enable output discharge resistor when Buck2 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
1 *
0 *
Forces the Buck2 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation
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ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
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7.6.1.5 BUCK3_CTRL1
Address: 0x08
D7
D6
D5
D4
D3
D2
D1
D0
EN_BUCK3
EN_PIN_CTRL BUCK3_EN_PIN_SELECT[1:0]
3
EN_ROOF_
FLOOR3
EN_RDIS3
BUCK3_FPWM
Reserved
Bits
Field
Type
Default
Description
7
EN_BUCK3
R/W
1 *
Enable Buck3 regulator:
0 - Buck3 regulator is disabled
1 - Buck3 regulator is enabled
6
EN_PIN_CTRL3
R/W
R/W
1 *
Enable EN1/2/3 pin control for Buck3:
0 - Only EN_BUCK3 bit controls Buck3
1 - EN_BUCK3 bit AND ENx pin control Buck3
5:4
BUCK3_EN_PIN
_SELECT[1:0]
0x0*
Enable EN1/2/3 pin control for Buck3:
0x0 - EN_BUCK3 bit AND EN1 pin control Buck3
0x1 - EN_BUCK3 bit AND EN2 pin control Buck3
0x2 - EN_BUCK3 bit AND EN3 pin control Buck3
0x3 - Reserved
3
2
1
0
EN_ROOF_
FLOOR3
R/W
R/W
R/W
R/W
0
1
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL3 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control
EN_RDIS3
BUCK3_FPWM
Reserved
Enable output discharge resistor when Buck3 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
1 *
0
Forces the Buck3 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation
40
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LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
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ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
7.6.1.6 BUCK0_VOUT
Address: 0x0A
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_VSET[7:0]
Bits
Field
Type
Default
Description
7:0 BUCK0_VSET[7:0]
R/W
0xFC for Sets the output voltage of Buck0 regulator
LP87524B, Reserved, DO NOT USE
LP87524J, 0x00...0x09
0x4D for 0.6 V - 0.73 V, 10 mV steps
LP87524P 0x0A - 0.6 V
*
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.7 BUCK0_FLOOR_VOUT
Address: 0x0B
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_FLOOR_VSET[7:0]
Bits
Field
Type
Default
Description
7:0
BUCK0_FLOOR
_VSET[7:0]
R/W
0x00
Sets the output voltage of Buck0 regulator when floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.8 BUCK1_VOUT
Address: 0x0C
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_VSET[7:0]
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ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
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Bits
Field
Type
Default
Description
Sets the output voltage of Buck1 regulator:
7:0 BUCK1_VSET[7:0]
R/W
0x75*
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.9 BUCK1_FLOOR_VOUT
Address: 0x0D
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_FLOOR_VSET[7:0]
Bits
Field
Type
Default
Description
7:0
BUCK1_FLOOR
_VSET[7:0]
R/W
0x00
Sets the output voltage of Buck1 regulator when floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.10 BUCK2_VOUT
Address: 0x0E
D7
D6
D5
D4
D3
D2
D1
D0
BUCK2_VSET[7:0]
42
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LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
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Bits
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
Field
Type
Default
Description
7:0 BUCK2_VSET[7:0]
R/W
0xB1 for Sets the output voltage of Buck2 regulator:
LP87524B, Reserved, DO NOT USE
0x4D for 0x00...0x09
LP87524J, 0.6 V - 0.73 V, 10 mV steps
LP87524P 0x0A - 0.6V
*
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.11 BUCK2_FLOOR_VOUT
Address: 0x0F
D7
D6
D5
D4
D3
D2
D1
D0
BUCK2_FLOOR_VSET[7:0]
Bits
Field
Type
Default
Description
7:0
BUCK2_FLOOR
_VSET[7:0]
R/W
0x00
Sets the output voltage of Buck2 regulator when floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.12 BUCK3_VOUT
Address: 0x10
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_VSET[7:0]
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LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
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Bits
Field
Type
Default
Description
7:0 BUCK3_VSET[7:0]
R/W
0xCA for Sets the output voltage of Buck3 regulator:
LP87524B, Reserved, DO NOT USE
LP87524J, 0x00...0x09
0xB1 for 0.6 V - 0.73 V, 10 mV steps
LP87524P 0x0A - 0.6 V
*
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.13 BUCK3_FLOOR_VOUT
Address: 0x11
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_FLOOR_VSET[7:0]
Bits
Field
Type
Default
Description
7:0
BUCK3_FLOOR
_VSET[7:0]
R/W
0x00
Sets the output voltage of Buck3 regulator when Floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.14 BUCK0_DELAY
Address: 0x12
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
BUCK0_
SHUTDOWN_
DELAY[3:0]
R/W
0x0 for
Shutdown delay of Buck0 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
LP87524B, CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
LP87524J, delay options in 表 4):
0x1 for
0x0 - 0 ms
LP87524P 0x1 - 1 ms
*
...
0xF - 15 ms
3:0
BUCK0_
STARTUP_
DELAY[3:0]
R/W
0x5 for
Start-up delay of Buck0 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
LP87524B, CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
LP87524J, delay options in 表 4):
0x3 for
0x0 - 0 ms
LP87524P 0x1 - 1 ms
*
...
0xF - 15 ms
44
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LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
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ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
7.6.1.15 BUCK1_DELAY
Address: 0x13
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_SHUTDOWN_DELAY[3:0]
BUCK1_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
BUCK1_
SHUTDOWN_
DELAY[3:0]
R/W
0x0 for
Shutdown delay of Buck1 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
LP87524B, CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
LP87524J, delay options in 表 4):
0x1 for
0x0 - 0 ms
LP87524P 0x1 - 1 ms
*
...
0xF - 15 ms
3:0
BUCK1_
STARTUP_
DELAY[3:0]
R/W
0x5 for
start-up delay of Buck1 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
LP87524B, CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
LP87524J, delay options in 表 4):
0x7 for
0x0 - 0 ms
LP87524P 0x1 - 1 ms
*
...
0xF - 15 ms
7.6.1.16 BUCK2_DELAY
Address: 0x14
D7
D6
D5
D4
D3
D2
D1
D0
BUCK2_SHUTDOWN_DELAY[3:0]
BUCK2_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
BUCK2_
SHUTDOWN_
DELAY[3:0]
R/W
0x0 for
Shutdown delay of Buck2 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
LP87524B, CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
LP87524J, delay options in 表 4):
0x1 for
0x0 - 0 ms
LP87524P 0x1 - 1 ms
*
...
0xF - 15 ms
3:0
BUCK2_
STARTUP_
DELAY[3:0]
R/W
0x2 for
start-up delay of Buck2 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
LP87524B, CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
LP87524J, delay options in 表 4):
0x5 for
0x0 - 0 ms
LP87524P 0x1 - 1 ms
*
...
0xF - 15 ms
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LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
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7.6.1.17 BUCK3_DELAY
Address: 0x15
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_SHUTDOWN_DELAY[3:0]
BUCK3_start-up_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
BUCK3_
SHUTDOWN_
DELAY[3:0]
R/W
0x1*
Shutdown delay of Buck3 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in 表 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
3:0
BUCK3_
STARTUP_
DELAY[3:0]
R/W
0x0*
Startup delay of Buck3 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in 表 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
7.6.1.18 GPIO2_DELAY
Address: 0x16
D7
D6
D5
D4
D3
D2
D1
D0
GPIO2_SHUTDOWN_DELAY[3:0]
GPIO2_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
GPIO2_
R/W
0x0 for
Delay for GPIO2 falling edge from falling edge of ENx signal (DOUBLE_DELAY = 0 in
SHUTDOWN_
DELAY[3:0]
LP87524B, CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
LP87524J, delay options in 表 4):
0x1 for
0x0 - 0 ms
LP87524P 0x1 - 1 ms
*
...
0xF - 15 ms
3:0
GPIO2_
R/W
0x5 for
Delay for GPIO2 rising edge from rising edge of ENx signal (DOUBLE_DELAY = 0 in
STARTUP_
DELAY[3:0]
LP87524B, CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
LP87524J, delay options in 表 4):
0x9 for
0x0 - 0 ms
LP87524P 0x1 - 1 ms
*
...
0xF - 15 ms
7.6.1.19 GPIO3_DELAY
Address: 0x17
D7
D6
D5
D4
D3
D2
D1
D0
GPIO3_SHUTDOWN_DELAY[3:0]
GPIO3_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
GPIO3_
R/W
0x0 *
Delay for GPIO3 falling edge from falling edge of ENx signal (DOUBLE_DELAY = 0 in
SHUTDOWN_
DELAY[3:0]
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in 表 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
46
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LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
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Bits
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
Field
Type
Default
Description
3:0
GPIO3_
R/W
0x3 for
Delay for GPIO3 rising edge from rising edge of ENx signal (DOUBLE_DELAY = 0 in
STARTUP_
DELAY[3:0]
LP87524B, CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
LP87524J, delay options in 表 4):
0xD for
0x0 - 0 ms
LP87524P 0x1 - 1 ms
*
...
0xF - 15 ms
7.6.1.20 RESET
Address: 0x18
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
SW_RESET
Bits
7:1
0
Field
Type
R/W
R/W
Default
0x00
0
Description
Reserved
SW_RESET
Software commanded reset. When written to 1, the registers are reset to default
values, OTP memory is read, and the I2C interface is reset.
The bit is automatically cleared.
7.6.1.21 CONFIG
Address: 0x19
D7
D6
CLKIN_PD
D5
D4
D3
D2
D1
D0
DOUBLE_DEL
AY
EN4_PD
EN3_PD
TDIE_WARN_
LEVEL
EN2_PD
EN1_PD
Reserved
Bits
Field
Type
Default
Description
7
DOUBLE_DELAY
R/W
0 *
Start-up and shutdown delays from ENx signals:
0 - 0 ms - 15 ms with 1-ms steps
1 - 0 ms - 30 ms with 2-ms steps
6
CLKIN_PD
R/W
1 *
Selects the pulldown resistor on the CLKIN input pin:
0 - Pulldown resistor is disabled.
1 - Pulldown resistor is enabled.
5
4
Reserved
EN3_PD
R/W
R/W
0 *
0 *
Selects the pulldown resistor on the EN3 (GPIO3) input pin:
0 - Pulldown resistor is disabled.
1 - Pulldown resistor is enabled.
3
TDIE_WARN_
LEVEL
R/W
1 for
LP87524B,
LP87524J,
0 for
Thermal warning threshold level:
0 - 125°C
1 - 137°C.
LP87524P
*
2
1
0
EN2_PD
EN1_PD
Reserved
R/W
R/W
R/W
0 *
1 *
0
Selects the pull down resistor on the EN2 (GPIO2) input pin:
0 - Pulldown resistor is disabled.
1 - Pull-down resistor is enabled.
Selects the pull down resistor on the EN1 (GPIO1) input pin:
0 - Pulldown resistor is disabled.
1 - Pulldown resistor is enabled.
7.6.1.22 INT_TOP1
Address: 0x1A
D7
D6
INT_BUCK23
D5
D4
D3
D2
D1
D0
Reserved
INT_BUCK01
NO_SYNC_CL
K
TDIE_SD
TDIE_WARN
INT_OVP
I_LOAD_
READY
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47
LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
www.ti.com.cn
Bits
7
Field
Type
R/W
R
Default
Description
Reserved
0
0
6
INT_BUCK23
Interrupt indicating that output Buck3 and/or Buck2 have a pending interrupt. The
reason for the interrupt is indicated in INT_BUCK_2_3 register.
This bit is cleared automatically when INT_BUCK_2_3 register is cleared to 0x00.
5
INT_BUCK01
R
0
Interrupt indicating that output Buck1 and/or Buck0 have a pending interrupt. The
reason for the interrupt is indicated in INT_BUCK_0_1 register.
This bit is cleared automatically when INT_BUCK_0_1 register is cleared to 0x00.
4
3
NO_SYNC_CLK
TDIE_SD
R/W
R/W
0
0
Latched status bit indicating that the external clock is not valid.
Write 1 to clear interrupt.
Latched status bit indicating that the die junction temperature has exceeded the
thermal shutdown level. The regulators have been disabled if they were enabled. The
regulators cannot be enabled if this bit is active. The actual status of the thermal
warning is indicated by TDIE_SD_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
2
1
0
TDIE_WARN
INT_OVP
R/W
R/W
R/W
0
0
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal warning level. The actual status of the thermal warning is indicated by
TDIE_WARN_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
Latched status bit indicating that the input voltage has exceeded the overvoltage
detection level. The actual status of the overvoltage is indicated by OVP_STAT bit in
TOP_STAT register.
Write 1 to clear interrupt.
I_LOAD_READY
Latched status bit indicating that the load current measurement result is available in
I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt.
7.6.1.23 INT_TOP2
Address: 0x1B
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
RESET_REG
Bits
7:1
0
Field
Type
R/W
R/W
Default
0x00
0
Description
Reserved
RESET_REG
Latched status bit indicating that either start-up (NRST rising edge) is done, VANA
supply voltage has been below undervoltage threshold level, or the host has requested
a reset (SW_RESET bit in RESET register). The regulators have been disabled, and
registers are reset to default values and the normal start-up procedure is done.
Write 1 to clear interrupt.
7.6.1.24 INT_BUCK_0_1
Address: 0x1C
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_PG
_INT
BUCK1_SC
_INT
BUCK1_ILIM
_INT
Reserved
BUCK0_PG
_INT
BUCK0_SC
_INT
BUCK0_ILIM
_INT
Bits
Field
Type
R/W
R/W
Default
Description
7
6
Reserved
0
0
BUCK1_PG_INT
Latched status bit indicating that Buck1 output voltage has reached Power-Good-
threshold level.
Write 1 to clear.
5
BUCK1_SC_INT
R/W
0
Latched status bit indicating that the Buck1 output voltage has fallen below 0.35-V
level during operation or Buck1 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
4
3
BUCK1_ILIM_INT
Reserved
R/W
R/W
0
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
48
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LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
www.ti.com.cn
Bits
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
Field
Type
Default
Description
2
1
0
BUCK0_PG_INT
BUCK0_SC_INT
BUCK0_ILIM_INT
R/W
0
Latched status bit indicating that Buck0 output voltage has reached Power-Good-
threshold level.
Write 1 to clear.
R/W
R/W
0
0
Latched status bit indicating that the Buck0 output voltage has fallen below 0.35-V
level during operation or Buck0 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
7.6.1.25 INT_BUCK_2_3
Address: 0x1D
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_PG
_INT
BUCK3_SC
_INT
BUCK3_ILIM
_INT
Reserved
BUCK2_PG
_INT
BUCK2_SC
_INT
BUCK2_ILIM
_INT
Bits
Field
Type
R/W
R/W
Default
Description
7
6
Reserved
0
0
BUCK3_PG_INT
Latched status bit indicating that Buck3 output voltage has reached Power-Good-
threshold level.
Write 1 to clear.
5
4
BUCK3_SC_INT
BUCK3_ILIM_INT
R/W
R/W
0
0
Latched status bit indicating that the Buck3 output voltage has fallen below 0.35-V
level during operation or Buck3 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
3
2
Reserved
R/W
R/W
0
0
BUCK2_PG_INT
Latched status bit indicating that Buck2 output voltage has reached Power-Good-
threshold level.
Write 1 to clear.
1
0
BUCK2_SC_INT
BUCK2_ILIM_INT
R/W
R/W
0
0
Latched status bit indicating that the Buck2 output voltage has fallen below 0.35-V
level during operation or Buck2 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
7.6.1.26 TOP_STAT
Address: 0x1E
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
SYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_WARN
_STAT
OVP_STAT
Reserved
Bits
7:5
4
Field
Reserved
Type
R
Default
0x0
Description
SYNC_CLK_STAT
R
0
Status bit indicating the status of external clock (CLKIN):
0 - External clock frequency is valid
1 - External clock frequency is not valid
3
2
1
0
TDIE_SD_STAT
R
R
R
R
0
0
0
0
Status bit indicating the status of thermal shutdown:
0 - Die temperature below thermal shutdown level
1 - Die temperature above thermal shutdown level
TDIE_WARN
_STAT
Status bit indicating the status of thermal warning:
0 - Die temperature below thermal warning level
1 - Die temperature above thermal warning level
OVP_STAT
Reserved
Status bit indicating the status of input overvoltage monitoring:
0 - Input voltage below overvoltage threshold level
1 - Input voltage above overvoltage threshold level
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7.6.1.27 BUCK_0_1_STAT
Address: 0x1F
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_STAT
BUCK1_PG
_STAT
Reserved
BUCK1_ILIM
_STAT
BUCK0_STAT
BUCK0_PG
_STAT
Reserved
BUCK0_ILIM
_STAT
Bits
Field
Type
Default
Description
7
BUCK1_STAT
BUCK1_PG_STAT
Reserved
R
0
Status bit indicating the enable/disable status of Buck1:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled
6
R
0
Status bit indicating Buck1 output voltage validity (raw status)
0 - Buck1 output is below Power-Good-threshold level
1 - Buck1 output is above Power-Good-threshold level
5
4
R
R
0
0
BUCK1_ILIM
_STAT
Status bit indicating Buck1 current limit status (raw status)
0 - Buck1 output current is below current limit level
1 - Buck1 output current limit is active
3
2
BUCK0_STAT
BUCK0_PG_STAT
Reserved
R
R
0
0
Status bit indicating the enable/disable status of Buck0:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled
Status bit indicating Buck0 output voltage validity (raw status):
0 - Buck0 output is below Power-Good-threshold level
1 - Buck0 output is above Power-Good-threshold level
1
0
R
R
0
0
BUCK0_ILIM
_STAT
Status bit indicating Buck0 current limit status (raw status):
0 - Buck0 output current is below current limit level
1 - Buck0 output current limit is active
7.6.1.28 BUCK_2_3_STAT
Address: 0x20
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_STAT
BUCK3_PG
_STAT
Reserved
BUCK3_ILIM
_STAT
BUCK2_STAT
BUCK2_PG
_STAT
Reserved
BUCK2_ILIM
_STAT
Bits
Field
Type
Default
Description
7
BUCK3_STAT
BUCK3_PG_STAT
Reserved
R
0
Status bit indicating the enable/disable status of Buck3:
0 - Buck3 regulator is disabled
1 - Buck3 regulator is enabled
6
R
0
Status bit indicating Buck3 output voltage validity (raw status):
0 - Buck3 output is below Power-Good-threshold level
1 - Buck3 output is above Power-Good-threshold level
5
4
R
R
0
0
BUCK3_ILIM
_STAT
Status bit indicating Buck3 current limit status (raw status):
0 - Buck3 output current is below current limit level
1 - Buck3 output current limit is active
3
2
BUCK2_STAT
BUCK2_PG_STAT
Reserved
R
R
0
0
Status bit indicating the enable/disable status of Buck2:
0 - Buck2 regulator is disabled
1 - Buck2 regulator is enabled
Status bit indicating Buck2 output voltage validity (raw status):
0 - Buck2 output is below Power-Good-threshold level
1 - Buck2 output is above Power-Good-threshold level
1
0
R
R
0
0
BUCK2_ILIM
_STAT
Status bit indicating Buck2 current limit status (raw status):
0 - Buck2 output current is below current limit level
1 - Buck2 output current limit is active
50
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7.6.1.29 TOP_MASK1
Address: 0x21
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
SYNC_CLK
_MASK
Reserved
TDIE_WARN
_MASK
Reserved
I_LOAD_
READY_MASK
Bits
Field
Type
R/W
R/W
R/W
Default
1 *
Description
7
6:5
4
Reserved
Reserved
0x0
SYNC_CLK
_MASK
0 *
Masking for external clock detection interrupt (NO_SYNC_CLK in INT_TOP1 register):
0 - Interrupt generated
1 - Interrupt not generated
3
2
Reserved
R/W
R/W
0
TDIE_WARN
_MASK
0 *
Masking for thermal warning interrupt (TDIE_WARN in INT_TOP1 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect TDIE_WARN_STAT status bit in TOP_STAT register.
1
0
Reserved
I_LOAD_
R/W
R/W
0
1 *
Masking for load current measurement ready interrupt (I_LOAD_READY in INT_TOP
READY_MASK
register).
0 - Interrupt generated
1 - Interrupt not generated
7.6.1.30 TOP_MASK2
Address: 0x22
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
RESET_REG
_MASK
Bits
7:1
0
Field
Type
R/W
R/W
Default
0x00
1 *
Description
Reserved
RESET_REG
_MASK
Masking for register reset interrupt (RESET_REG in INT_TOP2 register):
0 - Interrupt generated
1 - Interrupt not generated
7.6.1.31 BUCK_0_1_MASK
Address: 0x23
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_PG
_MASK
Reserved
BUCK1_ILIM
_MASK
Reserved
BUCK0_PG
_MASK
Reserved
BUCK0_ILIM
_MASK
Bits
Field
Type
R/W
R/W
Default
Description
7
6
Reserved
0
BUCK1_PG_MASK
1 *
Masking for Buck1 Power-Good interrupt (BUCK1_PG_INT in INT_BUCK_0_1
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK1_PG_STAT status bit in BUCK_0_1_STAT register.
5
4
Reserved
R
0
BUCK1_ILIM
_MASK
R/W
1 *
Masking for Buck1 current-limit-detection interrupt (BUCK1_ILIM_INT in
INT_BUCK_0_1 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_0_1_STAT register.
3
Reserved
R/W
0
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Bits
Field
Type
Default
Description
2
BUCK0_PG_MASK
R/W
1 *
Masking for Buck0 Power-Good interrupt (BUCK0_PG_INT in INT_BUCK_0_1
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK0_PG_STAT status bit in BUCK_0_1_STAT register.
1
0
Reserved
R
0
BUCK0_ILIM
_MASK
R/W
1 *
Masking for Buck0 current-limit-detection interrupt (BUCK0_ILIM_INT in
INT_BUCK_0_1 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK0_ILIM_STAT status bit in BUCK_0_1_STAT register.
7.6.1.32 BUCK_2_3_MASK
Address: 0x24
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_PG
_MASK
Reserved
BUCK3_ILIM
_MASK
Reserved
BUCK2_PG
_MASK
Reserved
BUCK2_ILIM
_MASK
Bits
Field
Type
R/W
R/W
Default
Description
7
6
Reserved
0
BUCK3_PG_MASK
1 *
Masking for Buck3 Power-Good interrupt (BUCK3_PG_INT in INT_BUCK_2_3
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK3_PG_STAT status bit in BUCK_2_3_STAT register.
5
4
Reserved
R
0
BUCK3_ILIM
_MASK
R/W
1 *
Masking for Buck3 current-limit-detection interrupt (BUCK3_ILIM_INT in
INT_BUCK_2_3 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK3_ILIM_STAT status bit in BUCK_2_3_STAT register.
3
2
Reserved
R/W
R/W
0
BUCK2_PG_MASK
1 *
Masking for Buck2 Power-Good interrupt (BUCK2_PG_INT in INT_BUCK_2_3
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK2_PG_STAT status bit in BUCK_2_3_STAT register.
1
0
Reserved
R
0
BUCK2_ILIM
_MASK
R/W
1 *
Masking for Buck2 current limit-detection interrupt (BUCK2_ILIM_INT in
INT_BUCK_2_3 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK2_ILIM_STAT status bit in BUCK_2_3_STAT register.
7.6.1.33 SEL_I_LOAD
Address: 0x25
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
LOAD_CURRENT_BUCK
_SELECT[1:0]
Bits
Field
Type
R/W
R/W
Default
0x00
Description
7:2
Reserved
1:0 LOAD_CURRENT_
BUCK_SELECT
[1:0]
0x0
Start the current measurement on the selected regulator:
0x0 - Buck0
0x1 - Buck1
0x2 - Buck2
0x3 - Buck3
A single measurement is started when register is written.
52
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7.6.1.34 I_LOAD_2
Address: 0x26
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK_LOAD_CURRENT[9:8]
Bits
7:2
Field
Type
R
Default
0x00
Description
Reserved
1:0
BUCK_LOAD_
CURRENT[9:8]
R
0x0
This register describes 3 MSB bits of the average load current on selected regulator
with a resolution of 20 mA per LSB and max code corresponding to 20.47-A current.
7.6.1.35 I_LOAD_1
Address: 0x27
D7
D6
D5
D4
D3
D2
D1
D0
BUCK_LOAD_CURRENT[7:0]
Bits
Field
Type
Default
Description
7:0
BUCK_LOAD_
CURRENT[7:0]
R
0x00
This register describes 8 LSB bits of the average load current on selected regulator
with a resolution of 20 mA per LSB and max code corresponding to a 20.47-A current.
7.6.1.36 PGOOD_CTRL1
Address: 0x28
D7
D6
D5
D4
D3
D2
D1
D0
PG3_SEL[1:0]
PG2_SEL[1:0]
PG1_SEL[1:0]
PG0_SEL[1:0]
Bits
Field
Type
Default
Description
7:6
PG3_SEL[1:0]
R/W
0x1*
PGOOD signal source control from Buck3
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good-threshold voltage AND current limit
5:4
3:2
1:0
PG2_SEL[1:0]
PG1_SEL[1:0]
PG0_SEL[1:0]
R/W
R/W
R/W
0x1*
0x1*
0x1*
PGOOD signal source control from Buck2
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good threshold voltage AND current limit
PGOOD signal source control from Buck1
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good-threshold voltage AND current limit
PGOOD signal source control from Buck0
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good-threshold voltage AND current limit
7.6.1.37 PGOOD_CTRL2
Address: 0x29
D7
D6
D5
D4
D3
D2
D1
PGOOD_OD
D0
HALF_DELAY
EN_PG0
_NINT
PGOOD_SET
_DELAY
EN_PGFLT
_STAT
Reserved
PGOOD_
WINDOW
PGOOD_POL
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Bits
Field
Type
Default
Description
7
HALF_DELAY
R/W
0 for
Select the time step for start-up and shutdown delays:
LP87524B, 0 - Start-up and shutdown delays have 0.5-ms or 1-ms time steps, based on
LP87524J, DOUBLE_DELAY bit in CONFIG register.
1 for
1 - Start-up and shutdown delays have 0.32-ms or 0.64-ms time steps, based on
LP87524P DOUBLE_DELAY bit in CONFIG register.
*
6
5
4
EN_PG0_NINT
R/W
R/W
R/W
0 *
1 *
0 *
Combine Buck0 PGOOD signal to nINT signal:
0 - Buck0 PGOOD signal not included to nINT signal
1 - Buck0 PGOOD signal included to nINT signal. If nINT OR Buck0 PGOOD is low
then nINT signal is low.
PGOOD_SET_DEL
AY
Debounce time of output voltage monitoring for PGOOD signal (only when PGOOD
signal goes valid):
0 - 4-10 µs
1 - 11 ms
EN_PGFLT_STAT
Operation mode for PGOOD signal:
0 - Indicates live status of monitored voltage outputs.
1 - Indicates status of PGOOD_FLT register, inactive if at least one of PGx_FLT bit is
inactive.
3
2
Reserved
R/W
R/W
0
PGOOD_WINDOW
1 *
Voltage monitoring method for PGOOD signal:
0 - Only undervoltage monitoring
1 - Overvoltage and undervoltage monitoring
1
0
PGOOD_OD
PGOOD_POL
R/W
R/W
1 *
0 *
PGOOD signal type:
0 - Push-pull output (VANA level)
1 - Open-drain output
PGOOD signal polarity:
0 - PGOOD signal high when monitored outputs are valid
1 - PGOOD signal low when monitored outputs are valid
7.6.1.38 PGOOD_FLT
Address: 0x2A
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
PG3_FLT
PG2_FLT
PG1_FLT
PG0_FLT
Bits
7:4
3
Field
Type
R/W
R
Default
0x0
Description
Reserved
PG3_FLT
0
Source for PGOOD inactive signal:
0 - Buck3 has not set PGOOD signal inactive.
1 - Buck3 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck3 output is valid.
2
1
0
PG2_FLT
PG1_FLT
PG0_FLT
R
R
R
0
0
0
Source for PGOOD inactive signal:
0 - Buck2 has not set PGOOD signal inactive.
1 - Buck2 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck2 output is valid.
Source for PGOOD inactive signal:
0 - Buck1 has not set PGOOD signal inactive.
1 - Buck1 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck1 output is valid.
Source for PGOOD inactive signal:
0 - Buck0 has not set PGOOD signal inactive.
1 - Buck0 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck0 output is valid.
7.6.1.39 PLL_CTRL
Address: 0x2B
D7
D6
D5
D4
D3
D2
D1
D0
PLL_MODE[1:0]
Reserved
EXT_CLK_FREQ[4:0]
54
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Bits
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
Field
Type
Default
Description
7:6
PLL_MODE[1:0]
R/W
0x2*
Selection of external clock and PLL operation:
0x0 - Forced to internal RC oscillator — PLL disabled.
0x1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use
when available, interrupt generated if external clock appears or disappears.
0x2 - PLL is enabled only in ACTIVE mode. Automatic external clock use when
available, interrupt generated if external clock appears or disappears.
0x3 - Reserved
5
Reserved
R/W
R/W
0
4:0 EXT_CLK_FREQ[4
:0]
0x01*
Frequency of the external clock (CLKIN):
0x00 - 1 MHz
0x01 - 2 MHz
0x02 - 3 MHz
...
0x16 - 23 MHz
0x17 - 24 MHz
0x18...0x1F - Reserved
See Specifications for input clock frequency tolerance.
7.6.1.40 PIN_FUNCTION
Address: 0x2C
D7
D6
D5
D4
D3
D2
D1
D0
EN_SPREAD_ EN_PIN_CTRL EN_PIN_SELE EN_PIN_CTRL EN_PIN_SELE
GPIO3_SEL
GPIO2_SEL
GPIO1_SEL
SPEC
_GPIO3
CT_GPIO3
_GPIO2
CT_GPIO2
Bits
Field
Type
Default
Description
7
EN_SPREAD
_SPEC
R/W
0 *
Enable spread-spectrum feature:
0 - Disabled
1 - Enabled
6
5
4
3
2
1
0
EN_PIN_CTRL_GP
IO3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 *
0 *
1 *
0 *
1 *
1 *
0 *
Enable EN1/2 pin control for GPIO3 (GPIO3_SEL=1 AND GPIO3_DIR=1):
0 - Only GPIO3_OUT bit controls GPIO3.
1 - GPIO3_OUT bit AND ENx pin control GPIO3
EN_PIN_SELECT_
GPIO3
Enable EN1/2 pin control for GPIO3:
0 - GPIO3_SEL bit AND EN1 pin control GPIO3
1 - GPIO3_SEL bit AND EN2 pin control GPIO3
EN_PIN_CTRL_GP
IO2
Enable EN1/3 pin control for GPIO2 (GPIO2_SEL=1 AND GPIO2_DIR=1):
0 - Only GPIO2_OUT bit controls GPIO2.
1 - GPIO2_OUT bit AND ENx pin control GPIO2
EN_PIN_SELECT_
GPIO2
Enable EN1/3 pin control for GPIO2:
0 - GPIO2_SEL bit AND EN1 pin control GPIO2
1 - GPIO2_SEL bit AND EN3 pin control GPIO2
GPIO3_SEL
GPIO2_SEL
GPIO1_SEL
EN3 pin function:
0 - EN3
1 - GPIO3
EN2 pin function:
0 - EN2
1 - GPIO2
EN1 pin function:
0 - EN1
1 - GPIO1
7.6.1.41 GPIO_CONFIG
Address: 0x2D
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
GPIO3_OD
GPIO2_OD
GPIO1_OD
Reserved
GPIO3_DIR
GPIO2_DIR
GPIO1_DIR
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Bits
7
Field
Type
R
Default
Description
Reserved
GPIO3_OD
0
6
R/W
1 *
GPIO3 signal type when configured to output:
0 - Push-pull output (VANA level)
1 - Open-drain output
5
4
GPIO2_OD
GPIO1_OD
R/W
R/W
1 *
0 *
GPIO2 signal type when configured to output:
0 - Push-pull output (VANA level)
1 - Open-drain output
GPIO1 signal type when configured to output:
0 - Push-pull output (VANA level)
1 - Open-drain output
3
2
Reserved
R
0
GPIO3_DIR
R/W
1 *
GPIO3 signal direction:
0 - Input
1 - Output
1
0
GPIO2_DIR
GPIO1_DIR
R/W
R/W
1 *
0 *
GPIO2 signal direction:
0 - Input
1 - Output
GPIO1 signal direction:
0 - Input
1 - Output
7.6.1.42 GPIO_IN
Address: 0x2E
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
GPIO3_IN
GPIO2_IN
GPIO1_IN
Bits
7:3
2
Field
Type
R
Default
0x00
0
Description
Reserved
GPIO3_IN
R
State of GPIO3 signal:
0 - Logic low level
1 - Logic high level
1
0
GPIO2_IN
GPIO1_IN
R
R
0
0
State of GPIO2 signal:
0 - Logic low level
1 - Logic high level
State of GPIO1 signal:
0 - Logic low level
1 - Logic high level
7.6.1.43 GPIO_OUT
Address: 0x2F
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
GPIO3_OUT
GPIO2_OUT
GPIO1_OUT
Bits
7:3
2
Field
Type
R/W
R/W
Default
0x00
1 *
Description
Reserved
GPIO3_OUT
Control for GPIO3 signal when configured to GPIO Output:
0 - Logic low level
1 - Logic high level
1
0
GPIO2_OUT
GPIO1_OUT
R/W
R/W
1 *
0
Control for GPIO2 signal when configured to GPIO Output:
0 - Logic low level
1 - Logic high level
Control for GPIO1 signal when configured to GPIO Output:
0 - Logic low level
1 - Logic high level
56
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LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
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ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP87524B/J/P-Q1 is a multi-phase step-down converter with four switcher cores, which are configured to
four one-phase regulators configuration.
8.2 Typical Application
R0
VIN
C0
C1
C2
C3
L0
L1
L2
L3
VOUT0
CPOL0
VIN_B0
VIN_B1
VIN_B2
VIN_B3
VANA
SW_B0
FB_B0
LOAD
LOAD
LOAD
LOAD
CIN0 CIN1 CIN2 CIN3
COUT0
COUT1
COUT2
COUT3
R1
R2
R3
VOUT1
CPOL1
SW_B1
FB_B1
CVANA
NRST
SDA
SCL
nINT
VOUT2
CPOL2
SW_B2
FB_B2
CLKIN
PGOOD
EN1 (GPIO1)
EN2 (GPIO2)
EN3 (GPIO3)
VOUT3
CPOL3
SW_B3
FB_B3
GNDs
Copyright © 2017, Texas Instruments Incorporated
图 22. Four 1-Phase Configuration
8.2.1 Design Requirements
8.2.1.1 Inductor Selection
The inductors are L0, L1, L2, and L3 are shown in the Typical Application. The inductance and DCR of the
inductor affects the control loop of the buck regulator. TI recommends using inductors similar to those listed in 表
10. Pay attention to the saturation current and temperature rise current of the inductor. Check that the saturation
current is higher than the peak current limit and the temperature rise current is higher than the maximum
expected rms output current. Minimum effective inductance to ensure good performance is 0.22 μH at maximum
peak output current over the operating temperature range. DC resistance of the inductor must be less than 0.05
Ω for good efficiency at high-current condition. The inductor AC loss (resistance) also affects conversion
efficiency. Higher Q factor at switching frequency usually gives better efficiency at light load to middle load.
Shielded inductors are preferred as they radiate less noise.
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Typical Application (接下页)
表 10. Recommended Inductors
RATED DC CURRENT,
ISAT maximum (typical) / ITEMP
maximum (typical) (A)
DCR typical /
maximum
(mΩ)
DIMENSIONS
L × W × H (mm)
MANUFACTURER
PART NUMBER
VALUE
TOKO
Vishay
DFE252012PD-R47M 0.47 µH (20%)
IHLP1616AB-1A 0.47 µH (20%)
2.5 × 2 × 1.2
5.2 (–) / 4 (–)(1)
– (6 ) / – (6 )(1)
- / 27
4.1 × 4.5 × 1.2
19 / 21
(1) Operating temperature range is up to 125°C including self temperature rise.
8.2.1.2 Input Capacitor Selection
The input capacitors CIN0, CIN1, CIN2, and CIN3 are shown in the Typical Application. A ceramic input bypass
capacitor of 10 μF is required for each phase of the regulator. Place the input capacitor as close as possible to
the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating improves the input
voltage filtering. Use X7R type of capacitors, not Y5V or F. DC bias characteristics capacitors must be
considered, minimum effective input capacitance to ensure good performance is 1.9 μF per buck input at
maximum input voltage including tolerances and ambient temperature range, assuming that there are at least 22
μF of additional capacitance common for all the power input pins on the system power rail. See 表 11.
The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces
voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering
of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient
ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI.
表 11. Recommended Input Capacitors (X7R Dielectric)
DIMENSIONS L × W × H
(mm)
VOLTAGE
RATING (V)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
Murata
GCM21BR71A106KE22
10 µF (10%)
0805
2 × 1.25 × 1.25
10 V
8.2.1.3 Output Capacitor Selection
The output capacitors COUT0, COUT1, COUT2, and COUT3 are shown in Typical Application. A ceramic local output
capacitor of 22 μF is required per phase. Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. DC
bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out
current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes
and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently
low ESR and ESL to perform these functions. Minimum effective output capacitance to ensure good performance
is 10 μF per phase including the DC voltage roll-off, tolerances, aging and temperature effects.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for
selection process is at the switching frequency of the part. See 表 12.
POL capacitors (CPOL0, CPOL1, CPOL2, CPOL3) can be used to improve load transient performance and to decrease
the ripple voltage. A higher output capacitance improves the load step behavior and reduces the output voltage
ripple as well as decreases the PFM switching frequency. However, output capacitance higher than 100 µF per
phase is not necessarily of any benefit. Note that the output capacitor may be the limiting factor in the output
voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded.
At shutdown the output voltage is discharged to 0.6 V level using forced-PWM operation. This can increase the
input voltage if the load current is small and the output capacitor is large. Below 0.6 V level the output capacitor
is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down
as a consequence of the increased time constant.
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表 12. Recommended Output Capacitors (X7R or X7T Dielectric)
DIMENSIONS L × W × H
(mm)
VOLTAGE
RATING (V)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
Murata
GCM31CR71A226KE02
22 µF (10%)
1206
3.2 × 1.6 × 1.6
10
8.2.1.4 Snubber Components
If the input voltage for the regulators is above 4 V, snubber components are needed at the switching nodes to
decrease voltage spiking in the switching node and to improve EMI. The snubber capacitors C0, C1, C2, and C3
and the snubber resistors R0, R1, R2, and R3 are shown in 图 22. The recommended components are shown in
表 13 and these component values give good performance on LP87524B/J/P-Q1 EVM. The optimal resistance
and capacitance values finally depend on the PCB layout.
表 13. Recommended Snubber Components
DIMENSIONS L × W x
H (mm)
VOLTAGE /
POWER RATING
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
Vishay-Dale
Murata
CRCW04023R90JNED
GCM1555C1H391JA16
3.9 Ω (5%)
0402
0402
1 × 0.5 × 0.4
1 × 0.5 × 0.5
62 mW
50 V
390 pF (5%)
8.2.1.5 Supply Filtering Components
The VANA input is used to supply analog and digital circuits in the device. See 表 14 for recommended
components for VANA input supply filtering.
表 14. Recommended Supply Filtering Components
DIMENSIONS L × W × VOLTAGE RATING
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
H (mm)
(V)
16
16
Murata
Murata
GCM155R71C104KA55
GCM188R71C104KA37
100 nF (10%)
100 nF (10%)
0402
0603
1.0 × 0.5 × 0.5
1.6 × 0.8 × 0.8
8.2.2 Detailed Design Procedure
The performance of the LP87524B/J/P-Q1 device depends greatly on the care taken in designing the printed
circuit board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly
recommended, while proper grounding is crucial. Attention must be given to decoupling the power supplies.
Decoupling capacitors must be connected close to the device and between the power and ground pins to support
high peak currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and
output traces as short as possible, because trace inductance, resistance, and capacitance can easily become the
performance limiting items. The separate power pins VIN_Bx are not connected together internally. Connect the
VIN_Bx power connections together outside the package using power plane construction.
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8.2.3 Application Curves
Measurements are done using typical application set up with connections shown in 图 22 (snubber components
included when VIN > 4 V). Graphs may not reflect the OTP default settings. Unless otherwise specified: VIN = 3.7
V, VOUT = 1 V, V(NRST) = 1.8 V, TA = 25°C, ƒSW = 4 MHz, L = 0.47 µH (TOKO DFE252012PD-R47M), COUT = 22
µF / phase, and CPOL = 22 µF / phase. Measurements are done using connections in the Typical Application.
100
90
80
70
60
50
40
100
90
80
70
60
50
1PH, VIN=3.3V, AUTO
1PH, VIN=3.3V, FPWM
1PH, VIN=5.0V, AUTO
1PH, VIN=5.0V, FPWM
1PH, VOUT=1.0V, FPWM
1PH, VOUT=1.8V, FPWM
1PH, VOUT=2.5V, FPWM
0.001
0.01
0.1
Output Current (A)
1
5
0.01
0.1
Output Current (A)
1
5
D923
D924
VOUT = 1.8 V
VIN = 3.3 V
图 24. Efficiency in Forced-PWM Mode
图 23. Efficiency in PFM/PWM Mode
100
90
80
70
60
50
40
1.02
1.016
1.012
1.008
1.004
1
0.996
0.992
0.988
0.984
0.98
1PH, VOUT=1.0V, FPWM
1PH, VOUT=1.8V, FPWM
1PH, VOUT=2.5V, FPWM
1PH, Vin=3.3V, FPWM
1PH, Vin=5.0V, FPWM
0.01
0.1
1
5
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Current (A)
D925
Output Current (A)
D026
VIN = 5 V
图 25. Efficiency in Forced-PWM Mode
图 26. Output Voltage vs Load Current in Forced-PWM
Mode
1.02
1.016
1.012
1.008
1.004
1
1.02
1.016
1.012
1.008
1.004
1
0.996
0.996
0.992
0.988
0.984
0.98
0.992
1PH, BUCK0
1PH, BUCK1
1PH, BUCK2
0.988
0.984
1PH, Vin=3.3V, AUTO
1PH, Vin=5.0V, AUTO
1PH, BUCK3
3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
0.98
2.8
3
0
0.2
0.4
0.6
0.8
1
Input Voltage (V)
D028
Output Current (A)
D027
VOUT = 1 V
Load = 1 A
图 27. Output Voltage vs Load Current in PFM/PWM Mode
图 28. Output Voltage vs Input Voltage in PWM Mode
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1.02
1.016
1.012
1.008
1.004
1
VOUT(200mV/div)
V(EN1)(500mV/div)
0.996
0.992
0.988
0.984
1PH, PWM
1PH, PFM
V(SW)(2V/div)
0.98
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
D036
Time (100 µs/div)
Load = 1 A (PWM) and 0.1 A (PFM)
图 29. Output Voltage vs Temperature
IOUT = 0 A
图 30. Start-Up With EN1, Forced PWM
VOUT(200mV/div)
V(EN1)(500mV/div)
VOUT(200mV/div)
V(EN1)(500m/div)
ILOAD(500mA/div)
ILOAD(500mA/div)
V(SW)(2V/div)
V(SW)(2V/div)
Time (100 µs/div)
Time (100 µs/div)
RLOAD = 1 Ω
RLOAD = 1 Ω
图 31. Start-Up With EN1, Forced PWM
图 32. Shutdown With EN1, Forced PWM
(1-Phase Output)
(1-Phase Output)
VOUT(10mV/div)
VOUT(10mV/div)
V(SW_B0)(1V/div)
V(SW_B0)(2V/div)
Time (40 µs/div)
Time (100 ns/div)
IOUT = 10 mA
IOUT = 200 mA
图 33. Output Voltage Ripple, PFM Mode
图 34. Output Voltage Ripple, Forced-PWM Mode
(1-Phase Output)
(1-Phase Output)
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10000
1000
100
VOUT(10mV/div)
10
VIN = 3.3V 4MHz
VIN = 5V 4MHz
1
0.1
V(SW_B0)(1V/div)
Time (2 µs/div)
1
10
Frequency (MHz)
D300
VOUT = 1 V
No load RBW/VBW = 10 Hz
图 35. Output Voltage Ripple Spectrum, Forced-PWM
Mode. COUT = 22 µF, ferrite BLM18KG121TH1D, CPOL = 10
µF + 0.22 µF.
图 36. Transient from PFM-to-PWM Mode
(1-Phase Output)
VOUT(10mV/div)
VOUT(20mV/div)
I(LOAD(1A/div)
V(SW_B0)(1V/div)
Time (2 µs/div)
Time (40 µs/div)
IOUT = 0.1 A → 2 A → 0.1 A
TR = TF = 1 µs
图 37. Transient from PWM-to-PFM Mode
图 38. Transient Load Step Response, AUTO Mode
(1-Phase Output)
(1-Phase Output)
VOUT(20mV/div)
VOUT(200mV/div)
I(LOAD(1A/div)
Time (20 µs/div)
Time (40 µs/div)
IOUT = 0.1 A → 2 A → 0.1
TR = TF = 1 µs
A
图 40. VOUT Transition from 0.6 V to 1.4 V
图 39. Transient Load Step Response, Forced-PWM Mode
(1-Phase Output)
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V(EN1)(1V/div)
VOUT(200mV/div)
V(nINT)(1V/div)
VOUT(50mV/div)
IOUT(2A/div)
Time (20 µs/div)
Time (200 µs/div)
图 41. VOUT Transition from 1.4 V to 0.6 V
图 42. Start-up With Short on Output (1-Phase Output)
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.8 V and 5.5 V. This input supply
must be well regulated and able to withstand maximum input current and maintain stable voltage without voltage
drop even at load transition condition. The resistance of the input supply rail must be low enough that the input
current transient does not cause too high drop in the LP87524B/J/P-Q1 supply voltage that can cause false
UVLO fault triggering. If the input supply is located more than a few inches from the LP87524B/J/P-Q1 additional
bulk capacitance may be required in addition to the ceramic bypass capacitors.
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10 Layout
10.1 Layout Guidelines
The high frequency and large switching currents of the LP87524B/J/P-Q1 make the choice of layout important.
Good power supply results only occur when care is given to proper design and layout. Layout affects noise
pickup and generation and can cause a good design to perform with less-than-expected results. With a range of
output currents from milliamps to 10 A, good power supply layout is much more difficult than most general PCB
design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and
current regulation across its intended operating voltage and current range.
1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bxx pin. Route the VIN trace wide and thick
to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of
LP87524B/J/P-Q1, as well as the trace between the negative node of the input capacitor and power
PGND_Bxx pin(s), must be kept as short as possible. The input capacitance provides a low-impedance
voltage source for the switching converter. The inductance of the connection is the most important parameter
of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for
proper device operation. The parasitic inductance can be reduced by using a ground plane as close as
possible to top layer by using thin dielectric layer between top layer and ground plane.
2. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output
voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI
behavior. Route the traces between the LP87524B/J/P-Q1 output capacitors and the load direct and wide to
avoid losses due to the IR drop.
3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a
quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling
capacitor as close as possible to the VANA pin.
4. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the
LP87524B/J/P-Q1 device to the respective sense pins on the processor. The sense lines are susceptible to
noise. They must be kept away from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high
bandwidth signals such as the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines
short, direct, and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a
voltage or ground plane if possible. If series resistors are used for load current measurement, place them
after connection of the voltage feedback.
5. PGND_Bxx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers,
which are not able to withstand interference from noisy PGND_Bxx, VIN_Bx and SW_Bx.
6. If the input voltage is above 4 V, place snubber components (capacitor and resistor) between SW_Bx and
ground on all four phases. The components can be also placed to the other side of the board if there are
area limitations and the routing traces can be kept short.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent parameters such as thermal coupling, airflow, added heat
sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die
temperatures. Wide and thick power traces come with the ability to sink dissipated heat. This can be improved
further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA
)
and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. TI
strongly recommends to perform of a careful system-level 2D or full 3D dynamic thermal analysis at the
beginning product design process, by using a thermal modeling analysis software.
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10.2 Layout Example
Via to GND plane
Via to VIN plane
VOUT1
VOUT0
L1
L0
COUT0
COUT1
CIN1
CIN0
GND
VIN
VIN
VIN
13 12 11 10
9
CIN4
14
15
8
7
6
FB_B1
EN2
FB_B0
EN1
GND
16
17
PGOOD
AGND
SDA
SCL
5
4
AGND
GND
GND
CVANA
VIN
18
19
GND
VANA
nINT
AGND
CLKIN
3
2
1
20 NRST
FB_B3
EN3
CIN5
FB_B2
21
22 23 24 25 26
VIN
VIN
VIN
CIN3
CIN2
GND
COUT3
COUT2
L3
L2
VOUT3
VOUT2
图 43. LP87524B/J/P-Q1 Board Layout
The output voltage rails are shorted together based on the configuration as shown in Typical Application.
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11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
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PACKAGE OUTLINE
RNF0026C
VQFN-HR - 0.9 mm max height
SCALE 2.800
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
A
-
A
2
5
.
0
0
0
SECTION A-A
TYPICAL
C
0.9 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X
2
0.3
10X
8X 0.5
0.2
4X (0.35)
4X (0.4)
4X (0.575)
(0.2) TYP
9
13
4X (0.625)
8
14
1.72
1.52
10X
7
A
A
SYMM
27
2X
0.66 0.1
2.5
0.3
0.2
10X 0.5
12X
0.5
21
1
0.1
C A B
C
26
22
PIN 1 ID
THERMAL PAD
0.05
SYMM
12X
0.3
2.24 0.1
4223207/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNF0026C
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
8X (0.5)
10X (0.25)
22
12X (0.6)
26
1
21
10X (1.82)
12X (0.25)
SYMM
(3.08)
27
(0.66)
2X (3.65)
10X (0.5)
( 0.2) TYP
VIA
8
4X (0.4)
14
4X (0.825)
(R0.05)
TYP
9
13
4X (0.35)
(0.87)
(2.24)
4X (0.775)
2X (3.2)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAIL
NOT TO SCALE
4223207/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
版权 © 2017–2018, Texas Instruments Incorporated
69
LP87524B-Q1, LP87524J-Q1, LP87524P-Q1
ZHCSH29B –APRIL 2017–REVISED DECEMBER 2018
www.ti.com.cn
EXAMPLE STENCIL DESIGN
RNF0026C
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.575) TYP
10X
EXPOSED METAL
SYMM
(0.5)
TYP
12X (0.6)
26
22
1
21
12X (0.25)
(1.01) TYP
(1.775)
TYP
(1.035) TYP
10X (0.5)
SYMM
2X (0.98)
27
2X (0.66)
(0.59)
(R0.05) TYP
EXPOSED METAL
4X (0.3)
20X (0.81)
4X (0.825)
8
14
13
9
4X (0.3)
20X (0.25)
4X (0.775)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1, 8, 14 & 21: 87% - PADS 9-13 & 22-26: 88% - THERMAL PAD 27: 87%
SCALE:25X
4223207/B 04/2018
NOTES: (continued)
6. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
www.ti.com
70
版权 © 2017–2018, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
验证并测试您的应用;(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更,恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2019 德州仪器半导体技术(上海)有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
3000
250
(1)
(2)
(3)
(4/5)
(6)
LP87524BRNFRQ1
LP87524BRNFTQ1
LP87524JRNFRQ1
LP87524JRNFTQ1
LP87524PRNFRQ1
LP87524PRNFTQ1
ACTIVE
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RNF
26
26
26
26
26
26
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
LP8752
4B-Q1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RNF
RoHS-Exempt
& Green
SN
SN
SN
SN
SN
LP8752
4B-Q1
RNF
3000
250
RoHS-Exempt
& Green
LP8752
4J-Q1
RNF
RoHS-Exempt
& Green
LP8752
4J-Q1
RNF
3000
250
RoHS-Exempt
& Green
LP8752
4P-Q1
RNF
RoHS-Exempt
& Green
LP8752
4P-Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP87524BRNFRQ1
LP87524BRNFTQ1
LP87524JRNFRQ1
LP87524JRNFTQ1
LP87524PRNFRQ1
LP87524PRNFTQ1
VQFN-
HR
RNF
RNF
RNF
RNF
RNF
RNF
26
26
26
26
26
26
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
4.25
4.25
4.25
4.25
4.25
4.25
4.75
4.75
4.75
4.75
4.75
4.75
1.2
1.2
1.2
1.2
1.2
1.2
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
VQFN-
HR
VQFN-
HR
3000
250
VQFN-
HR
VQFN-
HR
3000
250
VQFN-
HR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP87524BRNFRQ1
LP87524BRNFTQ1
LP87524JRNFRQ1
LP87524JRNFTQ1
LP87524PRNFRQ1
LP87524PRNFTQ1
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
RNF
RNF
RNF
RNF
RNF
RNF
26
26
26
26
26
26
3000
250
346.0
200.0
346.0
200.0
346.0
200.0
346.0
183.0
346.0
183.0
346.0
183.0
35.0
25.0
35.0
25.0
35.0
25.0
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RNF0026B
VQFN-HR - 0.9 mm max height
SCALE 2.800
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.6
4.4
C
0.9 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X
2
0.3
0.2
10X
8X 0.5
4X (0.35)
4X (0.575)
(0.2) TYP
4X (0.4)
9
13
4X (0.625)
14
8
7
1.72
1.52
10X
SYMM
27
2X
2.5
0.66 0.1
0.3
0.2
10X 0.5
12X
0.5
21
1
0.1
C A B
C
26
22
PIN 1 ID
THERMAL PAD
0.05
SYMM
12X
0.3
2.24 0.1
4222978/C 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RNF0026B
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
8X (0.5)
10X (0.25)
22
12X (0.6)
26
1
21
10X (1.82)
12X (0.25)
SYMM
(3.08)
27
(0.66)
2X (3.65)
10X (0.5)
(
0.2) TYP
VIA
8
4X (0.4)
14
4X (0.825)
(R0.05)
TYP
9
13
4X (0.35)
(0.87)
(2.24)
4X (0.775)
2X (3.2)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED
METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAIL
NOT TO SCALE
4222978/C 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RNF0026B
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.575) TYP
(0.5)
10X
EXPOSED METAL
SYMM
TYP
12X (0.6)
26
22
1
21
12X (0.25)
(1.01) TYP
(1.775)
TYP
(1.035) TYP
10X (0.5)
SYMM
2X (0.98)
27
2X (0.66)
(0.59)
(R0.05) TYP
EXPOSED METAL
4X (0.3)
20X (0.81)
4X (0.825)
8
14
13
9
4X (0.3)
20X (0.25)
4X (0.775)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1, 8, 14 & 21: 87% - PADS 9-13 & 22-26: 88% - THERMAL PAD 27: 87%
SCALE:25X
4222978/C 04/2018
NOTES: (continued)
6. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2021 德州仪器半导体技术(上海)有限公司
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