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LP8557, LP85571

SNVSA15B –DECEMBER 2013–REVISED DECEMBER 2015

LP8557 High-Efficiency LED Backlight Driver For Tablets

1 Features

3 Description

The LP8557 and LP8557I are high-efficiency LED

1

•

High-Efficiency DC-DC Boost Converter With 28-V

Integrated Power MOSFET

drivers each featuring an integrated DC-DC inductive

boost converter and six high-precision current sinks.

LP8557 is intended for applications that exclusively

use a pulse width modulated (PWM) signal for

controlling the brightness while LP8557I is intended

for applications that can utilize an I²C master as well.

•

2.7-V to 5.5-V VDD Range for Supporting Single-

Cell Li-Ion Battery Applications

•

Six 25-mA High-Precision LED Current Sinks

Adaptive Boost Voltage and LED Current Sink

Headroom Controls for Maximum System

Efficiency

The boost converter has adaptive output voltage

control. This feature minimizes the power

consumption by adjusting the voltage to the lowest

sufficient level under all conditions.

•

LED String Count Auto-Detect for Maximum

Design Flexibility

The adaptive current sink headroom voltage control

scales the headroom voltage with the LED current for

optimal system efficiency.

Smart Phase Shift PWM Mode for Reduced

Audible Noise

PWM Input Duty Cycle Brightness Control, PWM

Output Frequency Selectable Independent of

Input Frequency

The LED string auto-detect function enables use of

the same device in systems with 1 to 6 LED strings

for the maximum design flexibility.

•

Hybrid PWM Plus Current Dimming for Higher

LED Drive Optical Efficiency

Proprietary hybrid PWM plus current mode dimming

enables additional system power savings. Phase-shift

PWM allows reduced audible noise and smaller boost

output capacitors.

Switching Frequency, PWM Output Frequency,

and LED Current can be set Through Resistors or

I²C Interface

Flexible CABC support combines brightness level

selections based on the PWM input and I²C

commands.

•

Programmable Boost SW Slew Rate Control and

Spread Spectrum Scheme for Reduced Switching

Noise and Improved EMI Performance

Device Information⁽¹⁾

•

UVLO, TSD, BST_OVP, BST_OCP, BST_UV,

LED OPEN* and LED Short Fault Coverage

PART NUMBER

LP8557

PACKAGE

BODY SIZE (MAX)

Minimum Number of External Components

DSBGA (16)

1.906 mm x 1.64 mm

LP8557I

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Tablet LCD Display LED Backlight

Simplified Schematic With PWM-Only Option

LED Efficiency With 6 LED Strings

7 V œ 28 V

90

2.7 V œ 5.5 V

L1

D1

1.1 ≤ V

OUT

/ V ≤ 11

IN

V

OUT

IN

C

T

OU

C

IN

88

86

84

VDD

SW

PWM

FB

PWM

LED1

LED2

LED3

LED4

LED5

LED6

GNDs

LP8557

R

FSET

82

FSET

ISET

6p8s

6p6s

6p4s

R

ISET

80

0

20

40

60

80

100

Brightness [%]

C001

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP8557, LP85571

SNVSA15B –DECEMBER 2013–REVISED DECEMBER 2015

www.ti.com

Table of Contents

8.2 Functional Block Diagram ....................................... 11

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 20

8.5 Programming........................................................... 20

8.6 Register Maps......................................................... 24

Application and Implementation ........................ 31

9.1 Application Information............................................ 31

9.2 Typical Applications ............................................... 34

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Device Comparison Table..................................... 3

Pin Function and Configurations......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics........................................... 5

7.6 Boost Converter Electrical Characteristics................ 5

9

10 Power Supply Recommendations ..................... 38

11 Layout................................................................... 38

11.1 Layout Guidelines ................................................. 38

11.2 Layout Example .................................................... 42

12 Device and Documentation Support ................. 43

12.1 Device Support .................................................... 43

12.2 Related Links ........................................................ 43

12.3 Community Resources.......................................... 43

12.4 Trademarks........................................................... 43

12.5 Electrostatic Discharge Caution............................ 43

12.6 Glossary................................................................ 43

7.7 LED Driver Electrical Characteristics (LED1 To LED6

Pins)........................................................................... 5

7.8 PWM Interface Characteristics (PWM Pin)............... 6

7.9 Logic Interface Characteristics

(PWM, FSET/SDA, ISET/SCL Pins) .......................... 6

7.10 I²C Serial Bus Timing Parameters (SDA, SCL)..... 7

7.11 Typical Characteristics............................................ 8

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

13 Mechanical, Packaging, and Orderable

8

Information ........................................................... 43

4 Revision History

Changes from Revision A (June 2014) to Revision B

Page

•

moved storage temperature range to Abs Max table ............................................................................................................ 4

Changed Handling Ratings table to ESD Ratings table ........................................................................................................ 4

Updated Thermal Information table ....................................................................................................................................... 4

Changed word "safety" to "fault detection"........................................................................................................................... 11

Deleted "to 25% of the brightness range" ........................................................................................................................... 16

Changed PGEN register table and descriptions .................................................................................................................. 28

Changed fixed typo "2.4.4 kHz" to "24.4 kHz" ..................................................................................................................... 28

Added note to beginning of Application and Implementation section .................................................................................. 31

Added Community Resources section ................................................................................................................................ 43

Changes from Original (December 2013) to Revision A

Page

•

Changed formatting to match new TI datasheet guidelines; added Device Information and Handling Ratings table,

Layout, and Device and Documentation Support sections; reformatted Detailed Description and Application and

Implementation sections, fix typographical errors. ................................................................................................................ 1

Changed 6 LED strings to 5 LED Strings to correct typo....................................................................................................... 8

Added PWM Input Duty Measurement subsection............................................................................................................... 13

Changed description for "0" BFSET as well as description of register table for BFSET bit ................................................ 29

•

2

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SNVSA15B –DECEMBER 2013–REVISED DECEMBER 2015

5 Device Comparison Table

ORDERABLE

PACKAGE TOP

MARK

PACKAGE TYPE

(DRAWING)

DEVICE OPTION

PINS

PACKAGE QTY.

DEVICE

LP8557AYFQT

LP8557AYFQR

LP8557IAYFQT

LP8557IAYFQR

250

3000

250

"PWM Only" - Recommended for

systems without an I²C master

D40

D41

DSBGA (YFQ)

16

"PWM and I²C" - Recommended for

systems with an I²C master

3000

6 Pin Function and Configurations

YFQ Package

16-Pin DSBGA

4

3

2

1

2

3

4

ISET

SCL

FSET

SDA

GND

SW

GND

SW

FSET

SDA

ISET

SCL

SW

A

B

C

D

SW

GND

SW

GND

SW

LED3

LED2

LED1

FB

SW

VDD

LED6

B

C

D

SW

VDD

LED6

FB

LED3

LED2

LED1

PWM

LED4

GND

PWM

LED4

LED5

BOTTOM VIEW

TOP VIEW

Pin Functions

(1)

TYPE

DESCRIPTION

NAME

NO.

FB

B3

A

Boost feedback pin. The FB and OVP circuitry monitors the voltage on this pin.

Dual function pin. When I²C is not used (for example, BRTMODE = 00b), this pin can be used to set

ƒ_SWand/or ƒ_PWMby connecting a resistor from this pin to a ground reference. When I²C is used (for

example, BRTMODE = 01, 10 or 11), connect this pin to an SDA line of an I²C bus. The LP8557

"PWM Only" device option uses this pin as an FSET pin. LP8557I "PWM and I²C" device option

uses this pin as an SDA pin.

FSET/SDA

GND

A3

C2

A4

I/O

G

I

Ground pin.

Dual function pin. When I²C is not used (for example, BRTMODE = 00b), this pin can be used to set

the full-scale LED current by connecting a resistor from the pin to a ground reference. When I²C is

used (for example, BRTMODE =01, 10, or 11), connect this pin to an SCL line of an I²C bus. The

LP8557 "PWM Only" device option uses this pin as an ISET pin. LP8557I "PWM and I²C" device

option uses this pin as an SCL pin.

ISET/SCL

LED1

LED2

LED3

LED4

LED5

LED6

PWM

SW

D4

C4

A

I

LED driver – current sink terminal. If unused, this pin may be left floating.

PWM input pin.

B4

D3

D2

D1

C3

A1, B1

A2, B2

C1

A

G

P

A connection to the drain terminal of the integrated power MOSFET.

A connection to the source terminal of the integrated power MOSFET.

Device power supply pin.

SW_GND

VDD

(1) A: Analog Pin, G: Ground Pin, P: Power Pin, I: Digital Input Pin, I/O: Digital Input/Output Pin

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SNVSA15B –DECEMBER 2013–REVISED DECEMBER 2015

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

(1)(2)

MIN

–0.3

–30

MAX

6

UNIT

V

V_DD

V_IO

V_O

Voltage range on VDD pin

Voltage range on digital IO pins

Voltage range on SW, FB, LED1 to LED6 pins

Junction temperature

6

V

31

V

T_J

125

260

150

°C

T_sldr

T_stg

Maximum lead temperature (soldering)

Storage temperature range

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the potential at the GND pin.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

(1)(2)

MIN

MAX

5.5

28

UNIT

V

V_DD

2.7

0

V (SW, FB, LED1 to LED6)

Ambient temperature, T_A

Junction temperature, T_J

V

–30

85

°C

125

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability

(2) All voltage values are with respect to the potential at the GND pin.

7.4 Thermal Information

LP8557/LP8557I

THERMAL METRIC⁽¹⁾⁽²⁾

YFQ (DSBGA)

16 PINS

75.7

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

0.5

16.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.2

ψ_JB

16.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

4

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SNVSA15B –DECEMBER 2013–REVISED DECEMBER 2015

7.5 Electrical Characteristics

Unless otherwise specified: T_A= 25°C, V_DD= 3.8 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

5.5

1

UNIT

V

V_DD

I_DDQ

I_DD

Input voltage range

Standby current

2.7

µA

Operating current

No current going through LEDs

2.2

mA

Internal oscillator frequency

accuracy

–4%

4%

ƒ_OSC

–7%⁽¹⁾

7%⁽¹⁾

T_TSD

Thermal shutdown threshold⁽²⁾

Thermal shutdown hysteresis⁽²⁾

150

20

°C

T_{TSD_hyst}

(1) Limits apply over the full operating ambient temperature range –30°C ≤ T_A≤ 85°C.

(2) Verified by design and not tested in production.

7.6 Boost Converter Electrical Characteristics

Unless otherwise specified: T_A= 25°C, V_DD= 3.8 V⁽¹⁾

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Ω

R_{DS_ON}

Switch ON resistance

Minimum output voltage

Maximum output voltage

SW pin current limit

I_SW= 0.5 A

0.2

7

V_{BOOST_MIN}

V_{BOOST_MAX}

I_{SW_CL}

6⁽²⁾

27⁽²⁾

2.1

8⁽²⁾

29⁽²⁾

2.5

V

28

2.4

V

A

I_{SW_LIM}= 2.4 A

V_IN= 3 V, V_OUT= 24 V

(3)

I_{LOAD_MAX}

ƒ_SW

Maximum continuous load current

Switching frequency

160

mA

500

1000

kHz

Overvoltage protection voltage

threshold

V_{BOOST_MAX}

+ 1.6

V_{OVP_TH}

V

V_{UVLO_TH}

V_{UVLO_hyst}

t_PULSE

UVLO threshold

UVLO hysteresis

2.5

50

80

1

mV

ns

(3)

Switch pulse minimum width

No load

(3)

t_STARTUP

Boost start-up time

ms

(1) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis.

(2) Limits apply over the full operating ambient temperature range –30°C ≤ T_A≤ 85°C.

(3) Verified by design and not tested in production.

7.7 LED Driver Electrical Characteristics (LED1 To LED6 Pins)

Unless otherwise specified: T_A= 25°C, V_DD= 3.8 V⁽¹⁾

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

µA

I_LEAKAGE

I_{LED_MAX}

Leakage current

Outputs LED1...LED6, V_OUT= 28 V

1

Maximum sink current LED1...6

25

mA

–3%

3%

I_{LED_ACC}

I_MATCH

ƒ_LED

LED current accuracy⁽²⁾

Output current set to 20 mA

–4%⁽³⁾

4%⁽³⁾

(2)

Channel to Channel Matching

LED switching frequency⁽⁴⁾

Saturation voltage⁽⁵⁾

0.5

PFREQ = 000b

PFREQ = 111b

4.9

39.1

kHz

mV

V_SAT

Output current set to 20 mA

200

(1) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis.

(2) The LED current accuracy is defined as 100 × (ILED_AVE – ILED_Target) / ILED_AVE. The channel-to-channel LED current matching

is defined as (ILED_MAX – ILED_MIN) / ILED_AVE.

(3) Limits apply over the full operating ambient temperature range –30°C ≤ T_A≤ 85°C.

(4) Verified by design and not tested in production.

(5) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.

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7.8 PWM Interface Characteristics (PWM Pin)

(1)

See

PARAMETER

PWM frequency⁽²⁾

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Hz

ƒ_PWM

75

25000

t_{MIN_ON}

t_{MIN_OFF}

Minimum pulse ON time⁽²⁾

Minimum pulse OFF time⁽²⁾

1

9

µs

Turnon delay from standby to backlight

on⁽²⁾

PWM pin goes from low to

switching.

t_ON

ms

Turnoff delay from backlight off to

standby⁽²⁾

PWM pin goes from switching to

low.

52

t_STBY

ƒ_IN< 2.4 kHz

ƒ_IN< 4.8 kHz

ƒ_IN< 9.6 kHz

ƒ_IN< 19.5 kHz

ƒ_IN< 25 kHz

12

11

10

9

PWM_RES

PWM input resolution⁽²⁾

bits

8

(1) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis.

(2) Verified by design and not tested in production.

7.9 Logic Interface Characteristics

(PWM, FSET/SDA, ISET/SCL Pins)

Limits apply over the full operating ambient temperature range –30°C ≤ T_A≤ 85°C⁽¹⁾

.

PARAMETER

Input low level

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

V_IL

V_IH

I_I

0.4

Input high level

Input current

1.44

–1

V

1

0.5

1

µA

V

V_OL

I_O

Output low level

Output leakage

I_SDA= 3 mA

V_SDA= 2.8 V

µA

(1) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis.

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SNVSA15B –DECEMBER 2013–REVISED DECEMBER 2015

7.10 I²C Serial Bus Timing Parameters (SDA, SCL)

See⁽¹⁾and Figure 1.

PARAMETER

MIN

MAX

UNIT

kHz

μs

ƒ_SCL

1

Clock Frequency

400

Hold Time (repeated) START Condition

Clock Low Time

0.6

1.3

2

μs

3

Clock High Time

600

ns

4

Setup Time for a Repeated START Condition

Data Hold Time

600

ns

5

50

ns

6

Data Setup Time

100

ns

7

Rise Time of SDA and SCL

Fall Time of SDA and SCL

Set-up Time for STOP condition

Bus Free Time between a STOP and a START Condition

20 + 0.1C_b

15 + 0.1C_b

600

300

ns

8

ns

9

ns

10

1.3

μs

Capacitive Load Parameter for Each Bus Line

Load of 1 pF corresponds to 1 ns.

C_b

10

200

ns

t_WAIT

Wait time from V_DD= 2.7 V to 1^stI²C command

150

μs

(1) Verified by design and not tested in production.

Figure 1. I²C-Compatible Timing

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7.11 Typical Characteristics

Unless otherwise specified: V_IN= V_DD= 3.8 V, L = 10 µH Cyntec PIME051E, D = Diodes PD3S130L-7, C_OUT= 2 × 4.7 µF,

LED V_ƒ= 2.85 V (typical), I_{LED_MAX}= 25 mA per string.

90

88

86

84

82

80

90

88

86

84

82

80

6p9s

6p7s

6p5s

6p8s

6p6s

6p4s

0

20

40

60

80

100

0

20

40

60

80

100

Brightness [%]

C001

Figure 3. LED Efficiency With 6 LED Strings

Figure 2. LED Efficiency With 6 LED Strings

90

88

86

84

82

80

90

88

86

84

82

80

5p9s

5p7s

5p5s

5p8s

5p6s

5p4s

20

40

60

80

100

20

40

60

80

100

Brightness [%]

C001

Figure 4. LED Efficiency With 5 LED Strings

Figure 5. LED Efficiency With 5 LED Strings

90

88

86

84

82

80

90

88

86

84

82

80

4p9s

4p7s

4p5s

4p8s

4p6s

4p4s

20

40

60

80

100

20

40

60

80

100

Brightness [%]

C001

Figure 7. LED Efficiency With 4 LED Strings

Figure 6. LED Efficiency With 4 LED Strings

8

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Typical Characteristics (continued)

Unless otherwise specified: V_IN= V_DD= 3.8 V, L = 10 µH Cyntec PIME051E, D = Diodes PD3S130L-7, C_OUT= 2 × 4.7 µF,

LED V_ƒ= 2.85 V (typical), I_{LED_MAX}= 25 mA per string.

90

88

86

84

82

80

90

88

86

84

82

80

3p9s

3p7s

3p5s

3p8s

3p6s

3p4s

0

20

40

60

80

100

0

20

40

60

80

100

Brightness [%]

C001

Figure 8. LED Efficiency With 3 LED Strings

Figure 9. LED Efficiency With 3 LED Strings

90

88

86

84

82

80

90

88

86

84

82

80

2p8s

2p6s

2p4s

2p9s

2p7s

2p5s

0

20

40

60

80

100

0

20

40

60

80

100

Brightness [%]

C001

Figure 10. LED Efficiency With 2 LED Strings

Figure 11. LED Efficiency With 2 LED Strings

90

88

86

84

82

80

90

88

86

84

82

80

1p9s

1p7s

1p5s

1p8s

1p6s

1p4s

0

20

40

60

80

100

0

20

40

60

80

100

Brightness [%]

C001

Figure 12. LED Efficiency With 1 LED String

Figure 13. LED Efficiency With 1 LED String

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Typical Characteristics (continued)

Unless otherwise specified: V_IN= V_DD= 3.8 V, L = 10 µH Cyntec PIME051E, D = Diodes PD3S130L-7, C_OUT= 2 × 4.7 µF,

LED V_ƒ= 2.85 V (typical), I_{LED_MAX}= 25 mA per string.

90

88

86

84

82

80

92

90

88

86

84

82

2.7V

3.8V

5.5V

2.7V

3.8V

5.5V

0

20

40

60

80

100

0

20

40

60

80

100

Brightness [%]

C001

6p6s Load

Figure 14. LED Efficiency as a Function of VIN/VDD

6p6s Load

Figure 15. Boost Efficiency as a Function of VIN/VDD

10

5

2.7V

3.8V

5.5V

2.7V

3.8V

5.5V

8

6

4

2

0

4

3

2

1

0

20

40

60

80

100

0

20

40

60

80

100

Brightness [%]

C001

Figure 16. LED Current Accuracy as a Function of VDD

Figure 17. LED Current Channel-Channel Matching as a

Function of VDD

6

0.5

0.4

0.3

0.2

5

4

3

2

0.1

2.7V

3.8V

5.5V

1

0

20

40

60

80

100

0

20

40

60

80

100

Brightness [%]

C001

Figure 18. Device Operating Current as a

Function of VDD

Figure 19. Current Sink Headroom Voltage as a

Function of VDD

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SNVSA15B –DECEMBER 2013–REVISED DECEMBER 2015

8 Detailed Description

8.1 Overview

The LP8557 and LP8557I are high-efficiency LED drivers each featuring an integrated DC-DC inductive boost

converter and six high-precision current sinks. LP8557 is intended for applications that exclusively use a pulse

width modulated (PWM) signal for controlling the brightness while LP8557I is intended for applications that can

utilize an I²C master as well.

The boost converter has adaptive output voltage control. This feature minimizes the power consumption by

adjusting the voltage to the lowest sufficient level under all conditions.

The adaptive current sink headroom voltage control scales the headroom voltage with the LED current for

optimal system efficiency.

The LED string auto-detect function enables use of the same device in systems with 1 to 6 LED strings for the

maximum design flexibility.

Proprietary hybrid PWM plus current mode dimming enables additional system power savings. Phase shift PWM

allows reduced audible noise and smaller boost output capacitors.

Flexible CABC support combines brightness level selections based on the PWM input and I²C commands.

The LP8557 and LP8557I feature a full set of features that ensure robust operation of the device and external

components. The set consists of input undervoltage lockout, thermal shutdown, overcurrent protection,

overvoltage protection, and LED open and short detection.

8.2 Functional Block Diagram

VIN

VOUT

VDD

SW

FB

Boost Converter

PWM Control

UVLO

Switching

Frequency

500, 1000 kHz

Reference

Voltage

Thermal

shutdown

BOOST_FREQ

Oscillator

POR

Headroom

Control

Fault Detection

(Open*/Short LED,

OCP, OVP)

LED Current Sinks

LED1

LED2

LED3

LED4

LED5

LED6

PWM

BRIGHTNESS

CONTROL

FSET / SDA

ISET /SCL

Digital Logic

EPROM

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8.3 Feature Description

8.3.1 Boost Converter Overview

8.3.1.1 Operation

The boost DC-DC converter generates a 7-V to 28-V boost output voltage from a 2.7-V to 5.5-V boost input

voltage.

The converter is a magnetic switching PWM mode DC-DC inductive boost converter with a current limit. It uses

current programmed mode control, where the inductor current is measured and controlled with the feedback.

During start-up, the soft-start function reduces the peak inductor current. Figure 20 shows the boost block

diagram.

FB

SW

Startup

+

Light

Load

OVP

R

VREF

g

-

+

m

R

S

R

-

VFB

Osc/

ramp

OCP

+

-

S

Figure 20. Boost Circuit Block Diagram

8.3.1.2 Adaptive Boost Output Voltage Control

The boost converter operates in adaptive boost control mode. In this mode, the voltage at the LED pins is

monitored by the control loop. It raises the boost voltage when the measured voltage of ANY of the LED strings

falls below the voltage threshold of its corresponding LOW comparator. If the headrooms of ALL of the LED

strings are above the voltage threshold of their corresponding MID comparator, then the boost voltage is

lowered.

V

Driver

BOOST

headroom

V

BOOST

Time

Figure 21. Adaptive Headroom Detail

8.3.2 Brightness Control

The brightness can be controlled using an external PWM signal or the Brightness registers accessible via an I²C

interface or both. Which of these two input sources is selected is set by the BRTMODE bits. The LP8557

operates exclusively in BRTMODE = 00. While the LP8557I, by default, operates in BRTMODE = 11, it can

operate in all BRTMODE settings by configuring the bits via the I²C interface. How the brightness is controlled in

each of the four possible modes is described in the following sections.

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Feature Description (continued)

8.3.2.1 PWM Input Duty Measurement

When using PWM input for brightness control the input PWM duty cycle is measured as described in following

diagram and the brightness is controlled based on the result. When changing the brightness it must be noted that

the measurement cycle is from rising edge to next rising edge and brightness change must be done accordingly

(time from rising to rising edge is constant (=cycle time) and falling edge defines the brightness).

Cycle Time

t_PWM

Cycle Time

t_PWM

t_ON

Duty =

PWM/INT

t_PWM

Change in Duty

on this Edge

On-time

t_ON1

On-time

t_ON2

Figure 22. PWM Input Duty Cycle Measurement

8.3.2.2 BRTMODE = 00b

With BRTMODE = 00b, the LED output current is controlled by the PWM input duty cycle. The PWM detector

block measures the duty cycle at the PWM pin and uses it to generate a PWM-based brightness code. Before

the output is generated, the code goes through the curve shaper block. Then the code goes into the hybrid PWM

& I Dimming block which determines the range of the PWM and Current control. The outcome of the hybrid PWM

& I dimming block is current and/or up to 6 PWM output signals.

MAXCURR

CURRENT

Hybrid

PWM&I

PWM

Input

PWM

Detector

Curve

Shaper

Dimming

PWM

Gen

PWM

THRESHOLD

Figure 23. Brightness Data Path for BRTMODE = 00b

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Feature Description (continued)

7 V œ 28 V

/ V ≤ 11

2.7 V œ 5.5 V

L1

D1

1.1 ≤ V

OUT

IN

V

OUT

IN

C

T

OU

C

IN

VDD

SW

PWM

FB

PWM

LED1

LED2

LED3

LED4

LED5

LED6

GNDs

LP8557

R

FSET

ISET

R

ISET

Figure 24. Typical Application Circuit for Devices Configured With BRTMODE = 00

8.3.2.3 BRTMODE = 01b

With BRTMODE = 01b, the LED output current is controlled by the BRTHI/BRTLO registers. Before the output is

generated the BRTHI/BRTLO registers-based brightness code goes through the Curve Shaper block. Then the

code goes into the hybrid PWM & I dimming block which determines the range of the PWM and current control.

The outcome of the Hybrid PWM&I Dimming block is Current and/or up to 6 PWM output signals.

MAXCURR

CURRENT

Hybrid

PWM&I

I²C

Input

Curve

Shaper

Brightness

Dimming

PWM

Gen

PWM

THRESHOLD

Figure 25. Brightness Data Path for BRTMODE = 01b

8.3.2.4 BRTMODE = 10b

With BRTMODE = 10b, the LED output current is controlled by the PWM input duty cycle and the BRTHI/BRTLO

registers. The PWM detector block measures the duty cycle at the PWM pin and uses it to generate PWM-based

brightness code. Before the code is multiplied with the BRTHI/BRTLO registers-based brightness code, it goes

through the curve shaper block. After the multiplication, the resulting code goes into the hybrid PWM & I dimming

block which determines the range of the PWM and Current control. The outcome of the hybrid PWM & I dimming

block is current or up to 6 PWM output signals.

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Feature Description (continued)

I²C

Input

Brightness

MAXCURR

CURRENT

Hybrid

PWM&I

Dimming

PWM

Input

PWM

Detector

Curve

Shaper

PWM

Gen

THRESHOLD

Figure 26. Brightness Data Path for BRTMODE = 10b

8.3.2.5 BRTMODE = 11b

With BRTMODE = 11b, the LED output current is controlled by the PWM input duty cycle and the BRTHI/BRTLO

registers. The PWM detector block measures the duty cycle at the PWM pin and uses it to generate PWM-based

brightness code. In this mode, the BRTHI/BRTLO registers-based brightness code goes through the curve

shaper block before it is multiplied with the PWM input duty cycle-based brightness code. After the multiplication,

the resulting code goes into the hybrid PWM & I dimming block which determines the range of the PWM and

Current control. The outcome of the hybrid PWM & I dimming block is current and/or up to 6 PWM output

signals.

I²C

Input

Curve

Shaper

Brightness

MAXCURR

CURRENT

PWM

Hybrid

PWM&I

Dimming

PWM

Input

PWM

Detector

PWM

Gen

THRESHOLD

Figure 27. Brightness Data Path for BRTMODE = 11b

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Feature Description (continued)

7 V œ 28 V

/ V ≤ 11

2.7 V œ 5.5 V

L1

D1

1.1 ≤ V

OUT

IN

V

OUT

IN

C

IN

C

OUT

VDD

SW

PWM

FB

PWM

LED1

LED2

LED3

LED4

LED5

LED6

GNDs

LP8557I

SDA

SCL

SDA

SCL

Figure 28. Typical Application Circuit for Devices Configured With BRTMODE = 01, 10, or 11

8.3.2.6 Hybrid PWM & I Dimming Control

Hybrid PWM & I dimming control combines PWM dimming and LED current-dimming control methods. With this

dimming control, better optical efficiency is possible from the LEDs compared to pure PWM control while still

achieving smooth and accurate control and low brightness levels. The switch point from current-to-PWM control

can be set to get the optimal compromise between good matching of the LEDs brightness/white point at low

brightness and good optical efficiency.

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Feature Description (continued)

PWM CONTROL

100%

25%

50%

BRIGHTNESS

HYBRID PWM & CURRENT CONTROL

PWM CONTROL

CURRENT CONTROL

100%

50%

25%

100%

25%

50%

BRIGHTNESS

PURE CURRENT CONTROL

100%

50%

25%

100%

25%

50%

BRIGHTNESS

Figure 29. Dimming Methods

8.3.2.7 Phase Shift PWM Scheme

The phase shift PWM (PSPWM) scheme allows delay of the time when each LED current sink is active. When

the LED current sinks are not activated simultaneously, the peak load current from the boost output is greatly

decreased. This reduces the ripple seen on the boost output and allows smaller output capacitors to be used.

Reduced ripple also reduces the output ceramic capacitor audible ringing. The PSPWM scheme also increases

the load frequency seen on the boost output by up to six times, therefore transferring the possible audible noise

to the frequencies outside the audible range.

The phase difference between each active driver is automatically determined as 360°/number of active drivers.

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Feature Description (continued)

Phase Delay

60 degrees

Cycle Time

1/(f_PWM

)

LED1

LED2

LED3

LED4

LED5

LED6

Figure 30. Phase Shift PWM Dimming Scheme Diagram

8.3.3 Slope and Advanced Slope

The transition time between two brightness values can be programmed with the STEP bits from 0 to 200 ms. The

same slope time is used for sloping up and down. With advanced slope the brightness changes can be made

more pleasing to a human eye. It is implemented with a digital smoothing filter. The filter strength is set with

SMOOTH bits.

Brightness (PWM)

Sloper Input

Time

Brightness (PWM)

PWM Output

Normal slope

Advanced slope

Time

Slope Time

Figure 31. Slope and Advanced Slope

8.3.4 LED String Count Auto Detection

The LP8557 and LP8557I can auto-detect the number of the LED strings attached. During the auto-detect

routine, the devices automatically remove the unused current sink(s) and adjust the phasing of the remaining

current sinks. The LED OPEN* fault condition is not supported with auto-detect function enabled. On the

LP8557I, the user may disable the function by setting CONFIG.AUTO bit to 0 via an I²C write.

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Feature Description (continued)

8.3.5 EMI Reduction Schemes

LP8557I features two EMI reduction schemes. By default, the schemes are disabled; however, the schemes can

be enabled by I²C writes to SSEN and SREN bits in COMMAND register. The schemes are unavailable on the

LP8557.

The first scheme, programmable slew rate control, uses a combination of three drivers for boost switch. Enabling

all three drivers allows boost switch on/off transition times to be the shortest. On the other hand, enabling just

one driver allows boost switch on/off transition times to be the longest. The longer the transition times, the lower

the switching noise on the SW terminal. It should also be noted that the shortest transition times bring the best

efficiency as the switching losses are the lowest. This scheme can be enabled by setting SREN=1 with an I²C

write.

The second EMI reduction scheme is the spread spectrum scheme. This scheme deliberately spreads the

frequency content of the boost switching waveform, which inherently has a narrow bandwidth, makes the

switching waveform's bandwidth wider and ultimately reduces its EMI spectral density. This scheme can be

enabled by setting SSEN = 1 with an I²C write.

Slew rate control,

programmable

Duty cycle D = 1 - V / V

IN OUT

Spread spectrum scheme,

programmable pseudo

random duty cycle changes

minimize EMI

t

= 1 / f

SW

Figure 32. EMI Reduction Schemes

8.3.6 Fault Detection

The LP8557 and LP8557I have fault detection for LED SHORT, UVLO, BST_OVP, BST_OCP, BST_UV, and

TSD. Additionally, the LP8557I can support LED OPEN* fault. Faults are recorded in the STATUS register. Each

time the STATUS register is read it is automatically cleared.

8.3.6.1 LED Short Detection

Voltages at the individual current sinks are constantly monitored for the LED SHORT fault. This fault may occur

when some LEDs in a string are electrically bypassed making that LED string shorter than the other LED strings.

The reduced forward voltage causes the current sink attached to that string to have a higher headroom voltage

than the other current sinks. When the headroom voltage is higher than the fault comparator threshold

(configured with the 0V field in the LEDEN register), that current sink is disabled, and the PWM phasing is

automatically adjusted. The fault comparator threshold is at 2 V, typical.

8.3.6.2 LED OPEN* Detection

When the auto-detect function is disabled, each current sink is also monitored for the LED OPEN* condition. The

condition is set when the headroom voltage on one or more current sinks is below the LOW comparator

threshold, and the boost voltage is at the maximum. This fault condition may be caused by one or more OPEN

LED strings or by one or more current sinks shorted to GND. The LP8557I immediately shuts down the backlight

whenever an LED OPEN* condition is detected on any enabled LED drivers. The backlight does not turn on

again (regardless of the COMMAND.ON bit) until the STATUS register is read.

8.3.6.3 Undervoltage Detection

The device continuously monitors the voltage on the VDD pin. When the VDD voltage drops below 2.5 V the

backlight is immediately shut down, and the UVLO bit is set in the STATUS register. The backlight automatically

starts again when the voltage has increased above 2.5 V + 50 mV hysteresis. Hysteresis is implemented to avoid

continuously triggering undervoltage.

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Feature Description (continued)

8.3.6.4 Thermal Shutdown

If the internal temperature reaches 150°C, the deviceimmediately shuts down the backlight to protect it from

damage. The TSD bit is also set in the STATUS register. The device re-activates the backlight again when the

internal temperature drops below 130°C.

8.3.6.5 Boost Overcurrent Protection

The device automatically limits boost current to 2.4 A . When the 2.4-A limit is reached the BST_OCP bit is set in

the STATUS register. It is normal for the device to trigger the boost current limit during the start-up or sudden

brightness changes. The STATUS register can be cleared by reading the bit. If the bit is permanently set, it may

indicate an issue in the application.

8.3.6.6 Boost Overvoltage Protection

The device automatically limits boost voltage to VBOOST_MAX + 1.6 V. When the limit is reached the BST_OVP

bit is set in the STATUS register. It is normal for the device to trigger the boost OVP limit during the start-up or

sudden brightness changes. The status register can be cleared by reading the bit. If the bit is permanently set, it

may indicate an issue in the application.

8.3.6.7 Boost Undervoltage Protection

The device can detect when the boost voltage is below VBOOST – 2.5 V for longer than 6 ms. When the

threshold is reached the BST_UV bit is set in the STATUS register.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The device is in shutdown mode when the VDD pin is low. Current consumption in this mode from VDD pin is

< 1 µA.

8.4.2 Active Mode

In active mode the backlight is enabled either with setting the ON register bit high (LP8557I) or by activating

PWM input (LP8557). The power supplying the VDD pin must be present. Brightness is controlled with I²C writes

to brightness registers or by changing PWM input duty cycle (operation without I²C control). Configuration

registers are not accessible in Active mode to prevent damage to the device by accidental writes. Current

consumption from VDD terminal in this mode is typically 2.2 mA when LEDs are not drawing any current.

8.5 Programming

8.5.1 I²C-Compatible Serial Bus Interface

8.5.1.1 Interface Bus Overview

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bi-directional communications between the devices

connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL).

These lines must be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is

idle.

The default 7-bit I²C address for the LP8557I slave is 2Ch.

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Programming (continued)

8.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the I²C session (see Figure 33). A START

condition is defined as SDA transitioning from HIGH to LOW while SCL is HIGH. A STOP condition is defined as

SDA transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP

conditions. The I²C bus is considered busy after a START condition and free after a STOP condition. During data

transmission the I²C master can generate repeated START conditions. A START and a repeated START

condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock

signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW.

{5!

{/[

{

ꢀ

{tart /ondition

{top /ondition

Figure 33. Start And Stop Conditions

After the START condition, the I²C master sends the 7-bit address followed by an eighth read or write bit (R/W).

R/W = 0 indicates a WRITE, and R/W = 1 indicates a READ. The second byte following the chip address selects

the register address to which the data is written. The third byte contains the data for the selected register.

8.5.1.3 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

Figure 34. Bit Transfer

Each data transaction is composed of a START Condition, a number of byte transfers (set by the software) and a

STOP Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

8.5.1.4 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

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Programming (continued)

Data Output

By

Transmitter

Transmitter Stays Off the

Bus During the

Acknowledgement Clock

Data Output

By Receiver

Acknowledgement Signal

from Receiver

SCL

1

2

3 - 6

7

8

9

S

Start Condition

Figure 35. Bus Acknowledge Cycle

8.5.1.5 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

8.5.1.6 Control Register Write Cycle

•

Master device generates start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master sends data byte to be written to the addressed register.

Slave sends acknowledge signal.

If master sends further data bytes the control register address is incremented by one after acknowledge

signal.

•

Write cycle ends when the master creates stop condition.

8.5.1.7 Control Register Read Cycle

•

Master device generates a start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master device generates repeated start condition.

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

Slave sends acknowledge signal if the slave address is correct.

Slave sends data byte from addressed register.

If the master device sends acknowledge signal, the control register address is incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

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Programming (continued)

Table 1. Data Read and Write Cycles

ADDRESS MODE

Data Read

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Slave Address><r/w = ‘1’>[Ack]

[Register Data]<Ack or Nack>

… additional reads from subsequent

register address possible

Data Write

<Slave Address><r/w=’0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

… additional writes to subsequent

register address possible

<> Data from master; [] Data from slave

8.5.1.8 Register Read and Write Detail

Slave Address

Control Register Add.

(8 bits)

Register Data

(8 bits)

S

'0' A

A

P

(7 bits)

Data transfered,

byte + Ack

R/W

From Slave to Master

From Master to Slave

A - ACKNOWLEDGE (SDA Low)

S - START CONDITION

P - STOP CONDITION

Register Write Format

Figure 36. Register Write Format

Slave Address

(7 bits)

Slave Address

(7 bits)

Data- Data

(8 bits)

Control Register Add.

(8 bits)

A/

NA

S

'0' A

A Sr

'1' A

P

Data transfered, byte +

Ack/NAck

R/W

Direction of the transfer

will change at this point

From Slave to Master

From Master to Slave

A

- ACKNOWLEDGE (SDA Low)

NA - ACKNOWLEDGE (SDA High)

- START CONDITION

Sr - REPEATED START CONDITION

- STOP CONDITION

S

P

Register Read Format

Figure 37. Register Read Format

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8.6 Register Maps

The register map is useful for LP8557I users intending to re-configure the register reset values. If re-

configuration is necessary, it has to be done every time the power on VDD pin is recycled.

There is a restriction on register writes. The COMMAND, BRTLO, and BRTHI registers can be written at any

time; however, the remaining registers only accept writes when the COMMAND.ON bit is low. All registers can be

read at any time.

Many registers contain empty bit locations. These blank areas are reserved for future use. When writing to a

register any empty fields must not be modified; when reading a register, these empty fields should be ignored.

8.6.1 Register Bit Descriptions

8.6.1.1 COMMAND

Address: 0x00h

Reset: 0x00h (LP8557I)

D7

D6

D5

D4

D3

D2

D1

D0

RESET

—

SREN

SSEN

ON

Bits

Field

RESET

reserved

SREN

Type

Default

0b

Description

7

6:3

2

R/W

R/O

R/W

Write 1 to reset the device. This bit is self-clearing and is always 0 when read.

0000b

0b

Enable the boost slew rate control.

0 = Slew-rate control off (Default)

1 = Slew-rate control on

1

0

SSEN

ON

R/W

0b

Enable the spread-spectrum boost clocking.

0 = Spread-spectrum off (Default)

1 = Spread-spectrum on

See Description Turn on the backlight.

0 = backlight off (Default)

1 = backlight on

The COMMAND.ON bit is used to turn on the backlight.

The COMMAND.SSEN and COMMAND.SREN bits may be updated at any time. It is not necessary for the

backlight to be off when changing COMMAND.SSEN or COMMAND.SREN.

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8.6.1.2 STATUS

Address: 0x01h

Reset: 0x00h

D7

D6

D5

D4

D3

D2

D1

D0

LED_OPEN*

LED_SHORT

–

BST_UV

BST_OVP

BST_OCP

TSD

UVLO

Bits

Field

LED_OPEN*

Type

Default

Description

7

R/O

0b

An LED_OPEN* condition was detected on one or more strings. The condition is set

when the headroom voltage on one or more current sinks is below the LOW

comparator threshold, and the boost voltage is at the maximum. This fault condition

may be caused by one or more OPEN LED strings or by one or more current sinks

shorted to GND. Once set this bit stays set until the STATUS register is read. An

LED_OPEN* condition turns off the backlight when CONFIG.AUTO is 0. When

CONFIG.AUTO is 1, the condition is never set.

6

LED_SHORT

R/O

0b

An LED SHORT condition was detected on one or more strings. The condition is set

when the headroom voltage on one or more current sinks is above the FAULT

comparator threshold and at least one driver has the headroom voltage in regulation

(between LOW and MID comparator thresholds). This fault condition may be caused

by one or more shorted LEDs on one or more (but not all) strings. Once set this bit

stays set until the STATUS register is read.

5

4

reserved

BST_UV

R/O

0b

A boost output undervoltage condition was detected. The boost voltage is 2.5 V

(typical) or more below the target. Once set this bit stays set until the STATUS

register is read.

3

BST_OVP

R/O

0b

A boost overvoltage protection condition was detected. The boost voltage is 1.6 V

(typical) above the VMAX value. Once set this bit stays set until the STATUS register

is read.

2

1

0

BST_OCP

TSD

R/O

0b

A boost overcurrent protection condition was detected. Once set this bit stays set

until the STATUS register is read.

A thermal shutdown condition was detected. Once set, this bit stays set until the

STATUS register is read. A thermal shutdown condition turns off the backlight.

UVLO

An input undervoltage lockout condition was detected. Once set, this bit stays set

until the STATUS register is read. An undervoltage lockout condition turns off the

backlight.

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8.6.1.3 BRTLO

Address: 0x03h

Reset: 0x00h

D7

D6

D5

D4

D3

D2

D1

D0

BRT[3:0]

—

Bits

Field

Type

Default

Description

7:4

BRT[3:0]

R/W

0000b

Least significant bits of the 12-bit wide brightness level. If controlling the brightness

with 8-bit resolution, writing to this register is not needed.

6:0

reserved

R/O

0000b

Reserved.

8.6.1.4 BRTHI

Address: 0x04h

Reset: 0x00h

D7

D6

D5

D4

D3

D2

D1

D0

BRT[11:4]

Bits

Field

Type

Default

Description

7:0

BRT[11:4]

R/W

00h

Most significant bits of the 12-bit wide brightness level. If controlling the brightness

with the 8-bit resolution, writing to this register is all that is needed.

The brightness level can be updated via one (8 bits) or two (16 bits) register writes. The internal brightness level

is 12 bits wide and is only updated when the BRTHI register is written. If the BRTHI register is written without a

previous write to the BRTLO register, then the lower order bits of the internal brightness is synthesized from the

BRTHI register value.

BRTLO

write 0x95

write 0x10

no write

BRTHI

Brightness

0xFC9

0xDC1

0x8C8

Comments

write 0xFC

write 0xDC

write 0x8C

write 0x0C

write 0x00

write 0xFF

BRTLO[3:0] is ignored

set to an exact 12-bit value

synthesize low order bits

0% brightness

no write

0x0C0

no write

0x000

no write

0xFFF

100% brightness

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8.6.1.5 CONFIG

Address: 0x10h

Reset: 0x07h (LP8557I)

D7

D6

D5

D4

D3

D2

D1

D0

PWMSB

—

AUTO

BRTMODE[1:0]

Bits

Field

Type

Default

Description

7

PWMSB

R/W

0b

Enables PWM standby mode

0 = COMMAND.ON alone turns the backlight on/off (Default)

1 = turn off the backlight after 52 ms of PWM pin low

6:3

2

reserved

AUTO

R/O

R/W

0000b

1b

Automatic LED string configuration0 = enable LED strings using just

LEDEN.ENABLE

1 = disable all open LED strings (Default)

1:0

BRTMODE

R/W

11b

Brightness mode

00 = PWM

01 = BRTHI/BRTLO registers

10 = PWM × unshaped BRTHI/BRTLO registers

11 = Unshaped PWM × BRTHI/BRTLO registers

The AUTO bit is set, and the LED string configuration is done automatically. The LP8557I allows users to disable

the auto-detect function by setting AUTO bit to 0b.

8.6.1.6 CURRENT

Address: 0x11h

Reset: 0x07h (LP8557I)

D7

D6

D5

D4

D3

D2

D1

D0

ISET

——

MAXCURR[2:0]

Bits

Field

Type

Default

Description

7

ISET

R/W

0b

Set full-scale LED current via the ISET pin.

0 = Full-scale current is set with MAXCURR bits. (Default)

1 = Full-scale current is set with an external, R_ISET, resistor.

6:3

2:0

reserved

R/O

R/W

0000b

111b

MAXCURR

Full-scale current (100% brightness).

000 = 5 mA

001 = 10 mA

010 = 13 mA

011 = 15 mA

100 = 18 mA

101 = 20 mA

110 = 23 mA

111 = 25 mA (Default)

The ISET bit determines how the maximum LED current is set. On the LP8557I (ISET = 0), the maximum LED

current is 25 mA. It may be re-configured via the I²C interface by overriding MAXCURR bits. Note that re-

configuration must be done every time the power on VDD pin is recycled.

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8.6.1.7 PGEN

Address: 0x12h

Reset: 0x29h (LP8557I)

D7

D6

D5

D4

D3

D2

D1

D0

PFSET

—

THRESHOLD

PRFEQ[2:0]

Bits

Field

Type

Default

Description

7

PFSET

R/W

0b

Set PWM output frequency via the FSET pin.

0 = PWM output frequency is set with PRFEQ bits. (Default)

1 = PWM output frequency is set with an external, R_FSET, resistor.

6:3

5:3

reserved

R/O

R/W

0101b

THRESHOLD

EPROM

Adaptive dimming threshold. PWM dimming is used below threshold, and current

dimming is used above threshold.

000 = 100% current diming

001 = PWM below 1.5625% (6-bit PWM)

010 = PWM below 3.125% (7-bit PWM)

011 = PWM below 6.25% (8-bit PWM)

100 = PWM below 12.5% (9-bit PWM)

101 = PWM below 25% (10-bit PWM)

110 = PWM below 50% (11-bit PWM)

111 = 100 %PWM below (12-bit PWM)

2:0

PFREQ

R/W

001b

PWM output frequency

000 = 4.9 kHz

001 = 9.8 kHz (Default)

010 = 14.6 kHz

011 = 19.5 kHz

100 = 24.4 kHz

101 = 29.3 kHz

110 = 34.2 kHz

111 = 39.1 kHz

The PFSET bit distinguishes how the PWM dimming frequency is set. On the LP8557I (PFSET = 0), the PWM

dimming frequency is 9.8 kHz by default. It may be re-configured via I²C interface by overriding PFREQ bits.

Note that re-configuration must be done every time the power on VDD pin is recycled.

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8.6.1.8 BOOST

Address: 0x13h

Reset: 0x02h (LP8557I)

D7

D6

D5

D4

D3

D2

D1

D0

BFSET

BCSET

—

BCOMP

BFREQ

Bits

Field

Type

Default

Description

7

BFSET

R/W

0b

Set boost frequency via the FSET pin.

0 = Boost frequency is set with BFREQ bits. (Default)

1 = boost frequency is set with an external, R_FSET, resistor.

6

BCSET

R/W

0b

Set boost inductor size via ISET pin.

0 = boost inductor and compensation is set with BCOMP bit. (Default)

1 = boost inductor is set with an external, R_ISET, resistor.

5:2

1

reserved

BCOMP

R/O

R/W

0000b

1b

Boost compensation options.

0 = Boost compensation option 0

1 = Boost compensation option 1 (Default).

0

BFREQ

R/W

0b

Boost frequency.

0 = 500 kHz (Default)

1 = 1 MHz

The BFSET bit distinguishes how the boost switching frequency is set. If BFSET = 0, the boost switching

frequency is set by the BFREQ bit. If BFSET = 1, the switching frequency is set with an external resistor. On the

LP8557I (BFSET = 0), the boost switching frequency is 500 kHz by default. It may be re-configured via the I²C

interface by overriding the BFREQ bit. Please note the re-configuration must be done every time the power on

the VDD pin is recycled.

The BCSET bit distinguishes how the boost inductor and compensation is set. If BCSET = 0, the boost inductor

and compensation is set by the BCOMP bit. If BCSET = 1, the boost inductor and compensation is set with an

external resistor. On the LP8557I (BCSET = 0), the boost compensation is set to option 1 by default. It may be

re-configured via I²C interface by overriding BCOMP bit. Please note the re-configuration must be done every

time the power on the VDD pin is recycled.

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8.6.1.9 LEDEN

Address: 0x14h

Reset: 0xBFh (LP8557I)

D7

D6

D5

D4

D3

D2

D1

D0

-

ENABLE[6:1]

Bits

7:6

Field

Type

Default

10b

Description

reserved

ENABLE

R/W

5:0

111111b

LED string enables.

000001 = Only 1 current sink enabled.

.

001111 = Current sinks 1-4 enabled.

011111 = Current sinks 1-5 enabled.

111111 = All 6 current sinks enabled (Default)

The ENABLE field configures the strings if the AUTO bit is 0. The LP8557I allows re-configuration of the

ENABLE bits via I²C writes. Note that re-configuration must be done every time the power on the VDD pin is

recycled.

8.6.1.10 STEP

Address: 0x15h

Reset: 0x00h (LP8557I)

D7

D6

D5

D4

D3

D2

D1

D0

SMOOTH[1:0]

—

STEP[1:0]

Bits

Field

Type

Default

Description

7:6

SMOOTH

R/W

00b

Filter strength for digital smoothing filter.

00 = no smoothing (Default)

10 = light smoothing

10 = medium smoothing

11 = heaving smoothing

5:2

1:0

reserved

STEP

R/W

0000b

00b

Ramp time for a 0% to 100% current change.

00 = 0 ms (Default)

01 = 50 ms (12.2 µs/12-bit LSB)

10 = 100 ms (24.4 µs/12-bit LSB)

11 = 200 ms (48.8 µs/12-bit LSB)

On LP8557I, it is possible to enable slope and advanced slope functions by re-configuration of the STEP and

SMOOTH bits appropriately via I²C writes. Note that re-configuration must be done every time power on the VDD

pin is recycled.

The STEP field controls the rate of brightness level changes (slope function). Brightness transitions have a fixed

step time. The time required to complete a ramp between two levels also depends upon the difference between

the starting and ending current levels. For example, when STEP is set to 10b a brightness transition from 0% to

100% takes 100 ms, while a transition from 50% to 100% takes 50 ms.

The SMOOTH field controls the digital smoothing filter (advanced slope function). This filter behaves much like

an RC filter. It can be used to remove the overshoot that appears to occur on large brightness changes. The

actual amount of smoothing is tailored for the STEP field setting. For example, medium filter strength is higher for

100-ms ramp times than for 50-ms ramp times. This gives 16 possible brightness-level ramping configurations.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Designing With LP8557

The LP8557 is intended for applications without an I²C master. It can be fully controlled with an external PWM

signal. Boost switching frequency, boost compensation, PWM dimming frequency, and the maximum LED

current can be set with external resistors.

9.1.1.1 Setting Boost Switching and PWM Dimming Frequencies

Boost switching frequency and PWM dimming frequency are set by connecting a resistor from the FSET pin to

GND. Available options are shown in Table 2.

Table 2. Setting Boost Switching and PWM Dimming Frequencies With an

External Resistor

RFSET [Ω] (TOLERANCE)

470k - 1M (±5%)

300k, 330k (±5%)

200k (±5%)

ƒ_SW(kHz)

500

ƒ_PWM(kHz)

4.9

500

9.8

500

14.6

19.5

24.4

29.3

34.2

39.1

4.9

147k, 150k, 154k, 158k (±1%)

121k (±1%)

500

100k (±1%)

500

86.6k (±1%)

500

75.0k (±1%)

500

63.4k (±1%)

1000

500

52.3k, 53.6k (±1%)

44.2k, 45.3k (±1%)

39.2k (±1%)

9.8

14.6

19.5

24.4

29.3

34.2

39.1

9.8

34.0k (±1%)

30.1k (±1%)

26.1k (±1%)

23.2k (±1%)

0 (grounded)

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9.1.1.2 Setting Boost Compensation

For stable LP8557 boost operation, appropriate boost compensation must be selected based on the selected

boost switching frequency and the boost inductance. Table 3 shows recommended boost compensation options

based on the boost switching frequency and selected boost circuit inductance.

Table 3. Recommended Boost Compensation Options Based

on the Boost Switching Frequency and Inductance

RECOMMENDED BOOST

COMPENSATION OPTION

ƒ_SW(kHz)

L (µH)

10

15

22

1

0

500

4.7

6.8

10

1

0

1000

The LP8557 boost converter compensation is set by placing an external resistor, RISET, from the ISET pin to

GND. Note that the ISET pin is shared for setting the full-scale LED current in addition to setting the boost

compensation. Setting the boost compensation and the full-scale LED current using an external resistor is shown

in Table 4.

9.1.1.3 Setting Full-Scale Led Current

The LP8557 full-scale current is set by placing an external resistor, RISET, from the ISET pin to GND. Note that

the ISET pin is shared for setting the boost compensation in addition to the full-scale LED current. Setting the

boost compensation and the full-scale LED current using an external resistor is shown in Table 4.

Table 4. Setting Full-Scale LED Current and Boost Compensation Using an

External Resistor

RISET [Ω] (TOLERANCE)

BOOST COMPENSATION

OPTION

ILED (mA)

470k - 1M (±5%)

300k, 330k (±5%)

200k (±5%)

1

0

1

5

10

13

15

18

20

23

25

5

147k, 150k, 154k, 158k (±1%)

121k (±1%)

100k (±1%)

86.6k (±1%)

75.0k (±1%)

63.4k (±1%)

52.3k, 53.6k (±1%)

44.2k, 45.3k (±1%)

39.2k (±1%)

10

13

15

18

20

23

25

20

34.0k (±1%)

30.1k (±1%)

26.1k (±1%)

23.2k (±1%)

0 (grounded)

9.1.2 Designing With LP8557I

The LP8557I is intended for applications that can utilize an I²C master to control the device. Use of an external

PWM signal is allowed for controlling the brightness levels; however, I²C commands are required to turn the

backlight on or off. Boost switching frequency, boost compensation, PWM dimming frequency, and the maximum

LED current are set to default values. Re-configuration is possible with I²C writes; however, re-programming has

to be done every time power on the VDD pin is recycled.

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9.1.2.1 Setting Boost Switching Frequency

The LP8557I boost converter switching frequency is set to 500 kHz by default. It may be re-programmed by

overriding the BFREQ bit with an I²C write. Table 5 shows the boost switching frequency options available.

Table 5. Available Boost Switching Frequencies

BFREQ

ƒ_SW[kHz]

500

0

1

1000

9.1.2.2 Setting Boost Compensation

For stable LP8557I boost operation, appropriate boost compensation must be selected based on the selected

boost switching frequency and the boost inductance. Table 6 shows recommended boost compensation options

based on the boost switching frequency and selected boost circuit inductance.

Table 6. Recommended Boost Compensation Options Based

on the Boost Switching Frequency and Inductance

RECOMMENDED BOOST

COMPENSATION OPTION

ƒ_SW(kHz)

L (µH)

10

15

22

1

0

500

4.7

6.8

10

1

0

1000

The LP8557I boost converter compensation is set to option 1 by default. It may be re-programmed by overriding

the BCOMP bit with an I²C write. Table 7 shows available boost compensation options.

Table 7. Available Boost Compensation Options

BCOMP

BOOST COMPENSATION

OPTION

0

1

0

1

9.1.2.3 Setting PWM Dimming Frequency

The LP8557I PWM dimming frequency is set to 9.8 kHz by default. It may be re-programmed by overriding the

PFREQ bits with an I²C write. Table 8 summarizes available PWM dimming frequencies.

Table 8. Available PWM Dimming Frequencies

PFREQ

000

ƒ_PWM(kHz)

4.9

001

9.8

010

14.6

011

19.5

100

24.4

101

29.3

110

34.2

111

39.1

9.1.2.4 Setting Full-Scale LED Current

The LP8557I full-scale LED current is set to 25 mA by default. It may be re-programmed by overriding

MAXCURR bits with an I²C write. Table 9 shows available full-scale LED current levels.

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Table 9. Available Full-Scale LED Currents

MAXCURR

000

ILED [mA]

5

001

10

13

15

18

20

23

25

010

011

100

101

110

111

9.2 Typical Applications

9.2.1 LP8557 PWM-Only Option

7 V œ 28 V

2.7 V œ 5.5 V

L1

D1

1.1 ≤ V

OUT

/ V ≤ 11

IN

V

OUT

IN

C

T

OU

C

IN

VDD

SW

PWM

FB

PWM

LED1

LED2

LED3

LED4

LED5

LED6

GNDs

LP8557

R

FSET

ISET

R

ISET

Figure 38. LP8557 PWM-Only Device Option

9.2.1.1 Design Requirements

Table 10. Recommended Inductance

MIN

3.29

7

TYP

MAX

UNIT

ƒsw = 1 MHz

4.7 - 10

10 - 22

µH

ƒsw = 500 kHz

Table 11. Recommended Output Capacitance⁽¹⁾

MIN

2

TYP

MAX

UNIT

ƒsw = 1 MHz

µF

ƒsw = 500 kHz

2

(1) The recommended output capacitance is the de-rated capacitance.

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9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Boost Output Capacitor Selection

The LP8557 inductive boost converter typically requires two 4.7-µF output capacitors. The voltage rating of the

capacitor must be 35 V or higher as the OVP threshold is at 29.6 V (typ). Pay careful attention to the capacitor

tolerance and DC bias response. For proper operation the degradation in capacitance due to tolerance, DC bias,

and temperature should stay above 2 µF. This might require placing more than two devices in parallel in order to

maintain the required output capacitance over the device operating temperature and output voltage range.

9.2.1.2.2 Schottky Diode Selection

The Schottky diode must have a reverse breakdown voltage greater than the LP8557’s maximum output voltage.

Additionally, the diode must have an average current rating high enough to handle the LP8557 maximum output

current; at the same time the diode's peak current rating must be high enough to handle the peak inductor

current. Schottky diodes are required due to their lower forward voltage drop (0.3V to 0.5V) and their fast

recovery time.

9.2.1.2.3 Inductor Selection

The chosen inductor must be from 10 to 22 µH (for 500-kHz operation) or 4.7 to 10 µH (for 1-MHz operation) and

must have a saturation rating equal to, or greater than, the circuit's peak operating current. I_PEAKcan be found by

the following calculation:

é

ê

ë

ù

ú

û

æ

ö

÷

ø

I_OUT´ V_OUT

V

V ´ efficiency

IN

I_PEAK

=

+

x 1-

ç

V ´ efficiency

2´ ƒ

´L

SW

V_OUT

IN

è

(1)

This assumes the device is operating in continuous conduction mode (CCM) which is typically the case when

operating near the peak current. For smaller rated inductors, and when the device is operating in discontinuous

conduction mode (DCM), the peak current can be found from:

2´I_OUT

I_PEAK

=

´(V_OUT- V ´ efficiency)

IN

ƒ_SW´L ´ efficiency

(2)

(3)

The device operates in CCM when the following is true:

æ

ö

÷

ø

I_OUT´ V_OUT

V

V ´ efficiency

IN

>

´ 1-

ç

V ´ efficiency ƒ_SW´ 2´L

V_OUT

IN

è

9.2.1.2.4 Boost Input andVDD Capacitor Selection

The LP8557 VDD pin is typically tied to the same supply as the input of the boost power stage (V_INnode). A 10-

µF input capacitor is recommended on that node. The voltage rating of the capacitor must be at least 10 V. If a

supply powering the VDD pin is different from a supply powering the boost power stage, then 10-µF input

capacitors are required on both VDD and VIN nodes.

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9.2.1.3 Application Curves

V_TX= 5 V/div

V_SW

10V/DIV

V_SW

10V/DIV

V_IN= 200 mV/div

I_L

I_IN= 1 A/div

500mA/DIV

I_LED= 1 A/div

V_FBac

100mV/DIV

1ms/DIV

Figure 39. Steady State Operation With Light Load

(200 µA/String, 6 Strings)

Figure 40. Steady State Operation With Medium Load

(5 mA/String, 6 Strings)

V_DD

5V/DIV

V_TX= 5 V/div

V_SW

V_PWM

5V/DIV

V_IN= 200 mV/div

10V/DIV

I_L

I_LED

500mA/DIV

10mA/DIV

I_IN= 1 A/div

I_LED= 1 A/div

V_FBac

100mV/DIV

V_BOOST

10V/DIV

1ms/DIV

2ms/DIV

Figure 41. Steady State Operation With Heavy Load

(25 mA/String, 6 Strings)

Figure 42. Start-Up With a 1% Input PWM Duty

V_DD

5V/DIV

V_TX= 5 V/div

V_DD

5V/DIV

V_TX= 5 V/div

V_PWM

5V/DIV

V_PWM

5V/DIV

V_IN= 200 mV/div

I_LED

20mA/DIV

I_IN= 1 A/div

I_LED= 1 A/div

V_BOOST

10V/DIV

2ms/DIV

Figure 44. Start-Up With a 99% Input PWM Duty

Figure 43. Start-Up With a 50% Input PWM Duty

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V_DD

5V/DIV

V_TX= 5 V/div

V_DD

5V/DIV

V_TX= 5 V/div

V_PWM

5V/DIV

V_IN= 200 mV/div

V_PWM

5V/DIV

V_IN= 200 mV/div

I_LED

20mA/DIV

I_LED

20mA/DIV

I_IN= 1 A/div

I_LED= 1 A/div

V_BOOST

10V/DIV

4ms/DIV

Figure 46. Shutdown Operation

Figure 45. Start-Up With a 100% Input PWM Duty

9.2.2 LP8557I PWM and I²C Device Option

7 V œ 28 V

2.7 V œ 5.5 V

L1

D1

1.1 ≤ V

OUT

/ V ≤ 11

IN

V

OUT

IN

C

IN

C

OUT

VDD

SW

PWM

FB

PWM

LED1

LED2

LED3

LED4

LED5

LED6

GNDs

LP8557I

SDA

SCL

SDA

SCL

Figure 47. Typical Application With LP8557I PWM and I²C Device Option

9.2.2.1 Design Requirements

See Design Requirements.

9.2.2.2 Detailed Design Procedure

See Detailed Design Procedure.

9.2.2.3 Application Curves

See Application Curves.

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10 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.7 V and 5.5 V. This input supply

should be well regulated and able to withstand maximum input current and maintain stable voltage without

voltage drop even at load transition condition (start-up or rapid brightness change). The resistance of the input

supply rail should be low enough that the input current transient does not cause drop high enough in the LP8557

supply voltage that can cause false UVLO fault triggering.

If the input supply is located more than a few inches from the LP8557 additional bulk capacitance may be

required in addition to the ceramic bypass capacitors. Depending on device EPROM configuration and usage

case the boost converter is configured to operate optimally with certain input voltage range. Examples are seen

in the Detailed Design Procedure. In uncertain cases, TI recommends contacting a TI sales representative for

confirmation of the compatibility of the use case, EPROM configuration, and input voltage range.

11 Layout

11.1 Layout Guidelines

Figure 50 shows an example layout which applies the required proper layout guidelines to be used as a guide for

laying out the LP8557 circuit.

Table 12. Application Circuit Component List

CURRENT/VOLTAGE

COMPONENT

MANUFACTURER

VALUE

PART NUMBER

SIZE (mm)

RATING, RESISTANCE,

TEMPERATURE

L

Cyntec

Murata

10 µH

PIME051E

5.4 × 5.2 × 1.5

2 A, 0.153 Ω

0603

(1.6 × 0.8 × 0.8)

COUT

4.7 µF (×2)

GRM188R6YA475KE15D

35 V, X5R

0603

(1.6 × 0.8 × 0.8)

CIN

TDK

10 µF

C1608X5R1A106M080AC

RB160M-40

10 V, X5R

SOD-123

(3.5 × 1.6 × 0.8)

Diode

Rohm Semiconductor

Schottky

V_R= 40 V, V_F= 0.5 V

The following guidelines apply to both LP8557 and LP8557I.

The LP8557 inductive boost converter sees a high switched voltage at the SW pin, and a step current through

the Schottky diode and output capacitor each switching cycle. The high switching voltage can create interference

into nearby nodes due to electric field coupling (I = C × dV/dt). The large step current through the diode and the

output capacitor can cause a large voltage spike at the SW and FB pins due to parasitic inductance in the step

current conducting path (V = L × di/dt). Board layout guidelines are geared towards minimizing this electric field

coupling and conducted noise. Figure 48 highlights these two noise-generating components.

38

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Voltage Spike

V_OUT+ V_FSchottky

Pulsed voltage at SW

Current through

Schottky Diode and C_OUT

I_PEAK

I_AVE= I_IN

Parasitic

PCB

Inductances

Current through

inductor

Affected Node

due to capacitive

coupling

Cp1

Lp1

L

Lp2

D1

Up to 28V

C_OUT

2.7V to 5.5V

SW

VDD

Lp3

FSET/SDA

ISET/SCL

FB

LP8557

LCD Display

ILED1

PWM/INT

ILED6

GNDs

Figure 48. LP8557 Inductive Boost Converter Showing Pulsed Voltage at SW (High dv/dt) And Current

Through the Schottky Diode and C_OUT(High di/dt)

The following list details the main (layout sensitive) areas of the LP8557’s inductive boost converter in order of

decreasing importance:

1. Output Capacitor

–

COUT+ to Schottky diode cathode connection

COUT– to GND bump of the LP8557 connection

2. Schottky Diode

–

Schottky diode anode to SW connection

Schottky diode cathode to COUT+ connection

3. Inductor

–

SW Node PCB capacitance to other traces

4. Input Capacitor

–

CIN+ to VDD bump connection

CIN– to GND connection

11.1.1 Boost Output Capacitor Placement

Because the output capacitor is in the path of the inductor current discharge path, it detects a high-current step

from 0 to I_PEAKeach time the switch turns off and the Schottky diode turns on. Any inductance along this series

path from the diodes cathode, through C_OUT, and back into the LP8557 GND pin contributes to voltage spikes

(V_SPIKE= LP_ × dI/dt) at SW and OUT. These spikes can potentially over-voltage the SW and FB pins, or feed

through to GND. To avoid this, COUT+ must be connected as close to the cathode of the Schottky diode as

possible, and COUT− must be connected as close to the LP8557 GND pins as possible. The best placement for

COUT is on the same layer as the LP8557 to avoid any vias that can add excessive series inductance.

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11.1.2 Schottky Diode Placement

In the LP8557’s boost circuit the Schottky diode is in the path of the inductor current discharge. As a result the

Schottky diode sees a high-current step from 0 to I_PEAKeach time the switch turns off, and the diode turns on.

Any inductance in series with the diode can cause a voltage spike (V_SPIKE= LP_ × dI/dt) at SW and OUT. This

can potentially over-voltage the SW pin, or feed through to VOUT and through the output capacitor, into GND.

Connecting the anode of the diode as close to the SW pin as possible, and connecting the cathode of the diode

as close to COUT+ as possible, reduces the inductance (LP_) and minimize these voltage spikes.

11.1.3 Inductor Placement

The node where the inductor connects to the LP8557 SW bump has 2 challenges. First, a large switched voltage

(0 to (V_OUT+ V_{F_SCHOTTKY})) appears on this node every switching cycle. This switched voltage can be capacitively

coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces connecting the

input supply to the inductor and connecting the inductor to the SW bump. Any resistance in this path can cause

voltage drops that can negatively affect efficiency and reduce the input operating voltage range.

To reduce the capacitive coupling of the signal on SW into nearby traces, the SW bump-to-inductor connection

must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, high-

impedance nodes that are more susceptible to electric field coupling need to be routed away from SW and not

directly adjacent or beneath. This is especially true for traces such as ISET/SCL, FSET/SDA, and PWM. A GND

plane placed directly below SW dramatically reduces the capacitance from SW into nearby traces.

Lastly, limit the trace resistance of the VBATT-to-inductor connection and from the inductor-to-SW connection, by

use of short, wide traces.

11.1.4 Boost Input and VDD Capacitor Placement

The LP8557 input capacitor filters the inductor current ripple and the internal MOSFET driver currents. The

inductor current ripple can add input voltage ripple due to any series resistance in the input power path. The

MOSFET driver currents can add voltage spikes on the input due to the inductance in series with the VIN/VDD

and the input capacitor. Close placement of the input capacitor to the VDD pin and to the GND pin is critical

because any series inductance between VIN/VDD and CIN+ or CIN– and GND can create voltage spikes that

could appear on the VIN/VDD supply line and GND.

Close placement of the input capacitor at the input side of the inductor is also critical. The source impedance

(inductance and resistance) from the input supply, along with the input capacitor of the LP8557, forms a series

RLC circuit. If the output resistance from the source (R_S, Figure 49) is low enough, the circuit is underdamped

and has a resonant frequency (typically the case). Depending on the size of LS, the resonant frequency could

occur below, close to, or above the LP8557's switching frequency. This can cause the supply current ripple to be:

1. Approximately equal to the inductor current ripple when the resonant frequency occurs well above the

LP8557 switching frequency.

2. Greater than the inductor current ripple when the resonant frequency occurs near the switching frequency.

3. Less than the inductor current ripple when the resonant frequency occurs well below the switching frequency.

Figure 49 shows the series RLC circuit formed from the output impedance of the supply and the input

capacitor.

The circuit is redrawn for the AC case where the VIN supply is replaced with a short to GND and the LP8557 +

Inductor is replaced with a current source (ΔI_L). Equation 1 is the criteria for an under-damped response.

Equation 2 is the resonant frequency. Equation 3 is the approximated supply current ripple as a function of L_S,

R_S, and C_IN.

As an example, consider a 3.8-V supply with 0.1-Ω of series resistance connected to C_IN(10 µF) through 50 nH

of connecting traces. This results in an under-damped input-filter circuit with a resonant frequency of 225 kHz.

Because both the 1-MHz and 500-kHz switching frequency options lie above the resonant frequency of the input

filter, the supply current ripple is probably smaller than the inductor current ripple. In this case, using Equation 3,

the supply current ripple can be approximated as 0.2 times the inductor current ripple (using a 500-kHz switching

frequency) and 0.051 times the inductor current ripple using a 1-MHz switching frequency.

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I_SUPPLY

R_S

DI_L

L

L_S

SW

VDD

V_IN

Supply

LP8557

C_IN

I_SUPPLY

R_S

L_S

C_IN

DI_L

2

R_S

1

1.

>

4 x L_S²

L_Sx C_IN

1

2.

3.

f_RESONANT

=

2p L_Sx C_IN

1

2p x fSW

x

C_IN

D

_Lx

I_SUPPLYRIPPLEö I

2

≈

’

÷

◊

1

2

∆

R_S+ 2p x fSW

x L_S-

∆

x

C_IN

2p

fSW

«

Figure 49. Input RLC Network

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11.2 Layout Example

VIN

L1

VOUT

D1

CIN

GND

(bottom)

COUT

GND

(top)

LP8557

LED1-6

Figure 50. LP8557 and LP8557I Layout Example

Low-pass filter near VDD input pin is recommended for noisy power condition to prevent unstable LED current.

10 Ω plus approximately 2.2 µF to 10 µF can be used as low-pass filter components.

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 13. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

LP8557

Click here

LP85571

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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MECHANICAL DATA

YFQ0016xxx

D

0.600±0.075

E

TMD16XXX (Rev A)

D: Max = 1.906 mm, Min =1.846 mm

E: Max = 1.64 mm, Min = 1.58 mm

4215081/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LP8557IAYFQT
厂家：	TEXAS INSTRUMENTS
描述：	适用于平板电脑的高效 LED 背光驱动器 \| YFQ \| 16 \| -30 to 85 驱动电脑接口集成电路驱动器
文件：	总49页 (文件大小：1247K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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