LP5024RSMR [TI]
24 通道 I2C 恒流 RGB LED 驱动器 | RSM | 32 | -40 to 85;
| 型号： | LP5024RSMR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24 通道 I2C 恒流 RGB LED 驱动器 | RSM | 32 | -40 to 85 驱动 驱动器 |
| 文件： | 总54页 (文件大小：2011K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP5018, LP5024
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
LP50xx 18/24 通道 12 位 PWM 超低静态电流 I2C RGB LED 驱动器
1 特性
2 应用
用于以下设备的 LED 照明、指示灯和闪烁光：
1
•
工作电压范围：
•
•
•
•
•
•
•
•
智能扬声器（带语音助理）
智能家用电器
可视门铃
–
–
VCC 范围：2.7V 至 5.5V
与
1.8V、3.3V 和 5V 电源轨兼容的 EN、SDA 和
SCL 引脚
电子智能锁
–
最大输出电压：6V
烟雾和热量探测器
STB 和 DVR
智能路由器
•
24 路高精度恒定电流阱
–
–
–
在整个 VCC 范围内，每个通道的最大电流为
25.5mA
手持设备
当 VCC ≥ 3.3V 时，每个通道的最大电流为
35mA
3 说明
器件间的误差为 ±7%；通道间的误差为 ±7%
在智能家居以及配备人机交互功能的其他 应用中， 高
性能 RGB LED 驱动器必不可少。LED 动画效果（如
闪烁、呼吸以及追逐）可极大地改善用户体验，同时最
大限度地降低系统噪声也至关重要。
•
•
超低静态电流：
–
–
关断模式：1µA（最大值），EN 处于低电平
省电模式：10µA（典型），EN 处于高电平，
所有 LED 关断时间大于 30ms
LP50xx 器件是一款 18 或 24 通道恒定电流阱 LED 驱
动器。LP50xx 器件包含集成色彩混合和亮度控制，预
配置特性简化了软件编码过程。为每个通道配备的集成
式 12 位、29kHz PWM 发生器可实现流畅、清晰的
LED 色彩，并消除了可闻噪声。
每个通道具有一个集成式 12 位 29kHz PWM 发生
器：
–
–
每个通道具有一个独立的色彩混合寄存器
每个 RGB LED 模块具有一个独立的亮度控制
寄存器
–
–
可选的对数或线性标度亮度控制
器件信息(1)
集成式三相 PWM 相移方案
器件型号
LP5018
LP5024
封装
封装尺寸（标称值）
•
3 个可编程组（R、G、B），可轻松对每种颜色进
行软件控制
VQFN (32)
4.00mm × 4.00mm
•
•
•
2 个外部硬件地址引脚允许连接多达 4 个器件
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
广播从地址允许同时配置多个器件
自动递增允许在一次传输期间写入或读取多个连续
的寄存器
简化原理图
高达 400kHz 的快速模式 I2C 速度
VCC
CVCC
•
VMCU
VLED
VCC
OUT0
EN
OUT1
OUT2
SDA
SCL
ADDR0
ADDR1
MCU
LP5024
OUT21
VCAP
IREF
CVCAP
RIREF
OUT22
OUT23
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEB8
LP5018, LP5024
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 17
8.5 Programming .......................................................... 18
8.6 Register Maps ........................................................ 22
Application and Implementation ........................ 38
9.1 Application Information............................................ 38
9.2 Typical Application ................................................. 38
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements................................................ 8
7.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
9
10 Power Supply Recommendations ..................... 41
11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
11.2 Layout Examples................................................... 42
12 器件和文档支持 ..................................................... 44
12.1 相关链接................................................................ 44
12.2 接收文档更新通知 ................................................. 44
12.3 社区资源................................................................ 44
12.4 商标....................................................................... 44
12.5 静电放电警告......................................................... 44
12.6 术语表 ................................................................... 44
13 机械、封装和可订购信息....................................... 45
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (October 2018) to Revision B
Page
•
•
Added % after 100 in Parameter for IERR_DD and IERR_CC under OUTPUT STAGE................................................................. 7
已更改 value of "KIREF = 100" to "KIREF = 105"...................................................................................................................... 16
Changes from Original (October 2018) to Revision A
Page
•
首次发布生产数据数据表 ........................................................................................................................................................ 1
2
版权 © 2018, Texas Instruments Incorporated
LP5018, LP5024
www.ti.com.cn
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
5 说明 （续）
LP50xx 以 12 位 PWM 分辨率和 29kHz 开关频率控制每个 LED 输出，这有助于实现平滑的调光效果和消除可闻噪
声。独立的色彩混合和亮度控制寄存器使软件编码变得非常简单。在以淡入淡出类型的呼吸效果为目标时，全局
R、G、B 组控制可显著减轻微控制器负载。LP50xx 还可以实现 PWM 相移功能，以帮助在多个 LED 同时打开时
降低输入功率预算。
LP50xx 可实现自动节能模式，以实现超低静态电流。当所有通道都关断 30ms 时，该器件的总功耗会降至 10µA，
这使得 LP50xx 器件成为电池供电终端设备的潜在选择。
Copyright © 2018, Texas Instruments Incorporated
3
LP5018, LP5024
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
www.ti.com.cn
6 Pin Configuration and Functions
LP5018 RSM Package
32-Pin VQFN With Exposed Thermal Pad
Top View
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
1
2
3
4
5
6
7
8
24
NC
23
22
21
20
19
18
17
NC
NC
NC
Exposed Thermal Pad (GND)
NC
NC
OUT17
OUT16
Not to scale
LP5024 RSM Package
32-Pin VQFN With Exposed Thermal Pad
Top View
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
1
2
3
4
5
6
7
8
24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
23
22
21
20
19
18
17
Exposed Thermal Pad
(GND)
Not to scale
4
Copyright © 2018, Texas Instruments Incorporated
LP5018, LP5024
www.ti.com.cn
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
LP5018
25
LP5024
25
ADDR0
ADDR1
EN
—
—
I
I2C slave-address selection pin. This pin must not be left floating.
I2C slave-address selection pin. This pin must not be left floating.
Chip enable input pin
26
26
30
30
IREF
31
31
—
Output current-reference global-setting pin
19, 20, 21,
22, 23, 24
NC
—
—
No internal connection
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
SCL
1
2
1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
Current sink output 0. If not used, this pin can be left floating.
Current sink output 1. If not used, this pin can be left floating.
Current sink output 2. If not used, this pin can be left floating.
Current sink output 3. If not used, this pin can be left floating.
Current sink output 4. If not used, this pin can be left floating.
Current sink output 5. If not used, this pin can be left floating.
Current sink output 6. If not used, this pin can be left floating.
Current sink output 7. If not used, this pin can be left floating.
Current sink output 8. If not used, this pin can be left floating.
Current sink output 9. If not used, this pin can be left floating.
Current sink output 10. If not used, this pin can be left floating.
Current sink output 11. If not used, this pin can be left floating.
Current sink output 12. If not used, this pin can be left floating.
Current sink output 13. If not used, this pin can be left floating.
Current sink output 14. If not used, this pin can be left floating.
Current sink output 15. If not used, this pin can be left floating.
Current sink output 16. If not used, this pin can be left floating.
Current sink output 17. If not used, this pin can be left floating.
Current sink output 18. If not used, this pin can be left floating.
Current sink output 19. If not used, this pin can be left floating.
Current sink output 20. If not used, this pin can be left floating.
Current sink output 21. If not used, this pin can be left floating.
Current sink output 22. If not used, this pin can be left floating.
Current sink output 23. If not used, this pin can be left floating.
I2C bus clock line. If not used, this pin must be connected to GND or VCC.
I2C bus data line. If not used, this pin must be connected to GND or VCC.
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
—
—
—
—
—
—
29
28
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
29
28
SDA
I/O
Internal LDO output pin, this pin must be connected to a 1-µF capacitor to
GND. Place the capacitor as close to the device as possible.
VCAP
32
32
27
—
VCC
GND
27
I
Input power.
GND
—
Exposed thermal pad also serves the ground pin for the device.
Copyright © 2018, Texas Instruments Incorporated
5
LP5018, LP5024
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
Voltage on EN, IREF, OUTx, SCL, SDA, VCC
Voltage on ADDRx
6
VCC+0.3
2
V
V
V
Voltage on VCAP
Continuous power dissipation
Junction temperature, TJ-MAX
Storage temperature, Tstg
Internally limited
–40
–65
125
150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1500
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
2.7
0
MAX
5.5
5.5
5.5
85
UNIT
V
Input voltage on VCC
Voltage on OUTx
V
Voltage on ADDRx, EN, SDA, SCL
Operating ambient temperature, TA
0
V
–40
°C
7.4 Thermal Information
LP5018 or LP5024
THERMAL METRIC(1)
RSM (QFN)
32 PINS
36.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
34.8
15.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
16
RθJC(bot)
6.3
(1) For more information about traditional and new thermal metrics, see Semiconductor and ICPackage Thermal Metrics .
6
Copyright © 2018, Texas Instruments Incorporated
LP5018, LP5024
www.ti.com.cn
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
7.5 Electrical Characteristics
over operating ambient temperature range (–40°C < TA<85°C) (unless otherwise noted)
PARAMETER
POWER SUPPLIES (VCC)
VVCC Supply voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.7
5.5
1
V
Shutdown supply current
Standby supply current
VEN = 0 V
0.2
6
µA
mA
VEN = 3.3 V, Chip_EN = 0 (bit)
10
8
Normal-mode supply current
With 10-mA LED current per OUTx
5
IVCC
VEN = 3.3 V, Chip_EN = 1 (bit),
Power_Save_EN = 1 (bit), all the
LEDs off duration > tPSM
Power-save mode supply current
6
10
µA
VUVR
Undervoltage restart
VVCC rising
VVCC falling
2.5
V
V
V
VUVF
Undervoltage shutdown
2
VUV_HYS
Undervoltage shutdown hysteresis
0.2
OUTPUT STAGE (OUTx)
Maximum sink current
VVCC in full range,
(OUT0–OUTx) (For LP5024, x = 23. Max_Current_Option = 0 (bit), PWM
25.5
35
For LP5018, x = 17.)
= 100%
IMAX
mA
Maximum sink current
(OUT0–OUTx) (For LP5024, x = 23.
For LP5018, x = 17.)
V
VCC ≥ 3.3 V, Max_Current_Option
= 1 (bit), PWM = 100%
Internal sink current limit
VVCC in full range,
(OUT0–OUTx) (For LP5024, x = 23. Max_Current_Option = 0 (bit), VIREF
35
40
55
75
80
For LP5018, x = 17.)
= 0 V
ILIM
mA
µA
Internal sink current limit
VVCC ≥ 3.3V,
(OUT0–OUTx) (For LP5024, x = 23. Max_Current_Option=1 (bit), VIREF
=
120
1
For LP5018, x = 17.)
0 V
Leakage current (OUT0–OUTx) (For
LP5024, x = 23. For LP5018, x =
17.)
Ilkg
PWM = 0%
0.1
All channels' current set to 10 mA.
PWM = 100%. Already includes the
VIREF and KIREF tolerance
Device to device current error,
IERR_DD=(IAVE-ISET)/ISET×100%
IERR_DD
–7%
–7%
7%
7%
All channels' current set to 10 mA.
PWM = 100%. Already includes the
VIREF and KIREF tolerance
Channel to channel current error,
IERR_CC=(IOUTX-IAVE)/IAVE×100%
IERR_CC
VIREF
KIREF
ƒPWM
IREF voltage
0.7
105
29
V
IREF ratio
PWM switching frequency
21
kHz
VVCC in full range,
Max_Current_Option = 0 (bit), output
current set to 20 mA, the voltage
when the LED current has dropped
5%
0.25
0.3
0.35
VSAT
Output saturation voltage
V
VVCC ≥ 3.3 V, Max_Current_Option
= 1 (bit), output current set to 20
mA, the voltage when the LED
current has dropped 5%
0.4
0.4
LOGIC INPUTS (EN, SCL, SDA, ADDRx)
VIL
Low level input voltage
High level input voltage
Input current
V
V
VIH
1.4
–1
ILOGIC
VSDA
1
µA
V
SDA output low level
IPULLUP = 5 mA
0.4
PROTECTION CIRCUITS
Thermal-shutdown junction
temperature
T(TSD)
160
°C
Copyright © 2018, Texas Instruments Incorporated
7
LP5018, LP5024
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
over operating ambient temperature range (–40°C < TA<85°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Thermal shutdown temperature
hysteresis
T(HYS)
15
°C
7.6 Timing Requirements
over operating ambient temperature range (-40°C < TA<85°C) (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
ƒOSC
tPSM
Internal oscillator frequency
Power save mode deglitch time
EN first rising edge until first I2C access
EN first falling edge until first I2C reset
I2C clock frequency
15
30
MHz
ms
µs
20
40
500
3
tEN_H
tEN_L
ƒSCL
µs
400
kHz
µs
Hold time (repeated) START condition
Clock low time
0.6
1
2
3
4
5
6
7
8
9
1.3
600
µs
Clock high time
ns
Setup time for a repeated START condition
Data hold time
600
ns
0
ns
Data setup time
100
ns
Rise time of SDA and SCL
Fall time of SDA and SCL
Setup time for STOP condition
20 + 0.1 Cb
15 + 0.1 Cb
600
300
300
ns
ns
ns
Bus free time between a STOP and a START
condition
1.3
10
µs
pF
10
Capacitive load parameter for each bus line Load
of 1 pF corresponds to one nanosecond.
Cb
200
图 1. I2C Timing Parameters
8
版权 © 2018, Texas Instruments Incorporated
LP5018, LP5024
www.ti.com.cn
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
7.7 Typical Characteristics
35
32.5
30
40
35
30
25
20
15
10
5
27.5
25
22.5
20
17.5
15
5-mA Average Current
10-mA Average Current
25-mA Average Current
35-mA Average Current
12.5
10
7.5
5
2.5
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
RIREF(kW)
Ambient Temperature (èC)
RIRE
CURR
VCC = 3.3 V
图 2. IOUT Target vs RIREF
图 3. Output Current vs Temperature
40
35
30
25
20
15
10
5
1.65
1.35
1.05
0.75
0.45
0.15
-0.15
-0.45
-0.75
-1.05
Minimum at 5 mA
Maximum at 5 mA
Minimum at 10mA
Maximum at 10 mA
Minimum at 25 mA
Maximum at 25 mA
Minimum at 35 mA
Maximum at 35 mA
5-mA Average Current
10-mA Average Current
25-mA Average Current
35-mA Average Current
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
-40
-20
0
20
40
60
80 90
Ambient Temperature (èC)
Air Temperature (èC)
CURR
C2C3
VCC = 5 V
VCC = 3.3 V
图 5. Channel-to-Channel Current Accuracy
图 4. Output Current vs Temperature
0.055
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
1.6
1.2
0.8
0.4
0
50-mA IREF
100-mA IREF
150-mA IREF
200-mA IREF
250-\sm}A IREF
300-mA IREF
350-mA IREF
Minimum at 5 mA
Maximum at 5 mA
Minimum at 10mA
Maximum at 10 mA
Minimum at 25 mA
Maximum at 25 mA
Minimum at 35 mA
Maximum at 35 mA
-0.4
-0.8
-1.2
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5
Ambient Tempeature (èC)
Output Pin Voltage (V)
C2C5
VSAT
VCC = 5 V
VCC = 3.3 V
图 7. OUT Pin Voltage vs Current
图 6. Channel-to-Channel Current Accuracy vs Temperature
版权 © 2018, Texas Instruments Incorporated
9
LP5018, LP5024
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
0.055
0.05
0.045
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
50-mA IREF
100-mA IREF
150-mA IREF
200-mA IREF
250-mA IREF
300-mA IREF
350-mA IREF
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5
Output Pin Volatge (V)
VSAT
VCC = 5 V
图 8. OUT Pin Voltage vs Output Current
10
版权 © 2018, Texas Instruments Incorporated
LP5018, LP5024
www.ti.com.cn
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
8 Detailed Description
8.1 Overview
The LP50xx device is an 18- or 24-channel constant-current-sink LED driver. The LP50xx device includes all
necessary power rails, an on-chip oscillator, and a two-wire serial I2C interface. The maximum constant-current
value of all channels is set by a single external resistor. Two hardware address pins allow up to four devices on
the same bus. An automatic power-saving mode is implemented to keep the total current consumption under 10
µA, which makes the LP50xx device a potential choice for battery-powered end-equipment.
The LP50xx device is optimized for RGB LEDs regarding to both live effects and software efforts. The LP50xx
device controls each LED output with 12-bit PWM resolution at 29-kHz switching frequency, which helps achieve
a smooth dimming effect and eliminates audible noise. The independent color-mixing and intensity-control
registers make the software coding straightforward. When targeting a fade-in, fade-out type breathing effect, the
global RGB bank control reduces the microcontroller loading significantly. The LP50xx device also implements a
PWM phase-shifting function to help reduce the input power budget when LEDs turn on simultaneously.
8.2 Functional Block Diagram
VCC
VLED
VCC
Bandgap
OUT0
OUT1
OUT2
V1P8
LDO
VCAP
12 Bits
29 kHz
PWM
Oscillator
15MHz
Generators
EN
SDA
SCL
OUT21
OUT22
OUT23
Digital
Interface
Digital Control
ADDR0
ADDR1
IREF
IREF Setting Current
Thermal Shutdown
GND
8.3 Feature Description
8.3.1 PWM Control for Each Channel
Most traditional LED drivers are designed for the single-color LEDs, in which the high-resolution PWM generator
is used for intensity control only. However, for RGB LEDs, both the color mixing and intensity control should be
addressed to achieve the target effect. With the traditional solution, the users must handle the color mixing and
intensity control simultaneously with a single PWM register. Several undesired effects occur: the limited dimming
steps, the complex software design, and the color distortion when using a logarithmic scale control.
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Feature Description (接下页)
The LP50xx device is designed with independent color mixing and intensity control, which makes the RGB LED
effects fancy and the control experience straightforward. With the inputs of the color-mixing register and the
intensity-control register, the final PWM generator output for each channel is 12-bit resolution and 29-kHz
dimming frequency, which helps achieve a smooth dimming effect and eliminates audible noise. See 图 9.
Color-Mixing
Brightness-Control
PWM Generators
OUT0
8 Bits Color
12 Bits / 29KHz PWM
OUT1
OUT2
8 Bits Color
8 Bits Color
8 Bits Brightness
12 Bits / 29KHz PWM
12 Bits / 29KHz PWM
OUT21
8 Bits Color
8 Bits Color
8 Bits Color
12 Bits / 29KHz PWM
12 Bits / 29KHz PWM
12 Bits / 29KHz PWM
8 Bits Brightness
OUT22
OUT23
图 9. PWM Control Scheme for Each Channel
8.3.1.1 Independent Color Mixing Per RGB LED Module
Each output channel has its own individual 8-bit color-setting register (OUTx_COLOR). The device allows every
RGB LED module to achieve >16 million (256 × 256 × 256) color-mixing.
8.3.1.2 Independent Intensity Control Per RGB LED Module
When color is fixed, the independent intensity-control is used to achieve accurate and flexible dimming control for
every RGB LED module.
8.3.1.2.1 Intensity-Control Register Configuration
Every three consecutive output channels are assigned to their respective intensity-control register
(LEDx_BRIGHTNESS). For example, OUT0, OUT1, and OUT2 are assigned to LED0_BRIGHTNESS, so it is
recommended to connect the RGB LEDs in the sequence as shown in 表 1. The LP50xx device allows 256-step
intensity control for each RGB LED module, which helps achieve a smooth dimming effect.
Keeping FFh (default value) in the LED0_BRIGHTNESS register results in 100% dimming duty cycle. With this
setting, users can just configure the color mixing register by channel to achieve the target dimming effect in a
single-color LED application.
8.3.1.2.2 Logarithmic- or Linear-Scale Intensity Control
For human-eye-friendly visual performance, a logarithmic-scale dimming curve is usually implemented in LED
drivers. However, for RGB LEDs, if using a single register to achieve both color mixing and intensity control,
color distortion can be observed easily when using a logarithmic scale. The LP50xx device, with independent
color-mixing and intensity-control registers, implements the logarithmic scale dimming control inside the intensity
control function, which solves the color distortion issue effectively. See 图 10. Also, the LP50xx device allows
users to configure the dimming scale either logarithmically or linearly through the global Log_Scale_EN register.
If a special dimming curve is desired, using the linear scale with software correction is the most flexible
approach. See 图 11.
12
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Feature Description (接下页)
Brightness Control
8 Bits Brightness
Linear OR Logarithmic
Log_Scale_EN
8 Bits Brightness
Linear OR Logarithmic
图 10. Logarithmic- or Linear-Scale Intensity Control
Linear Scale Dimming Curve
Logarithmic Scale Dimming Curve
100 %
80 %
60 %
40 %
20 %
0 %
100 %
80 %
60 %
40 %
20 %
0 %
0
32
64
96
128 160 192 224 255
0
32
64
96
128 160 192 224 255
LEDx_BRIGHTNESS Register Input
LEDx_BRIGHTNESS Register Input
图 11. Logarithmic vs Linear Dimming Curve
8.3.1.3 12-Bit, 29-kHz PWM Generator Per Channel
8.3.1.3.1 PWM Generator
With the inputs of the color mixing and the intensity control, the final output PWM duty cycle is defined as the
product obtained by multiplying the color-mixing register value by the related intensity-control register value. The
final output PWM duty cycle has 12 bits of control accuracy, which is achieved by a 9 bits of pure PWM
resolution and 3 bits of digital dithering control. For 3-bit dithering, every eighth pulse is made 1 LSB longer to
increase the average value by 1 / 8th. The LP50xx device allows users to enable or disable the dithering function
through the PWM_Dithering_EN register. When enabled (default), the output PWM duty-cycle accuracy is 12
bits. When disabled, the output PWM duty-cycle accuracy is 9 bits.
To eliminate the audible noise due to the PWM switching, the LP50xx device sets the PWM switching frequency
at 29-kHz, above the 20-kHz human hearing range.
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Feature Description (接下页)
8.3.1.4 PWM Phase-Shifting
A PWM phase-shifting scheme allows delaying the time when each LED driver is active. When the LED drivers
are not activated simultaneously, the peak load current from the pre-stage power supply is significantly
decreased. The scheme also reduces input-current ripple and ceramic-capacitor audible ringing. LED drivers are
grouped into three different phases.
•
•
•
Phase 1—the rising edge of the PWM pulse is fixed. The falling edge of the pulse is changed when the duty
cycle changes. Phase 1 is applied to LED0, LED3, …, LED21.
Phase 2—the middle point of the PWM pulse is fixed. The pulse spreads in both directions when the PWM
duty cycle is increased. Phase 2 is applied to LED1, LED4, …, LED22.
Phase 3—the falling edge of the PWM pulse is fixed. The rising edge of the pulse is changed when the duty
cycle changes. Phase 3 is applied to LED2, LED5, …, LED23.
Cycle Time
LED0
LED3
Phase 1
LED[3Ü (n-1)]
LED1
LED4
Phase 2
LED[3Ü (n-1)+1]
LED2
LED5
Phase 3
LED[3Ü (n-1)+2]
Phase 1
Phase 2
Phase 3
图 12. PWM Phase-Shifting
8.3.2 LED Bank Control
For most LED-animation effects, like blinking and breathing, all the RGB LEDs have the same lighting pattern.
Instead of controlling the individual LED separately, which occupies the microcontroller resources heavily, the
LP50xx device provides an easy coding approach, the LED bank control.
Each channel can be configured as either independent control or bank control through the LEDx_Bank_EN
register. When LEDx_Bank_EN = 0 (default), the LED is controlled independently by the related color-mixing and
intensity-control registers. When LEDx_Bank_EN = 1, the LP50xx device drives the LEDs in LED bank-control
mode. The LED bank has its own independent PWM control scheme, which is the same structure as the PWM
scheme of each channel. See PWM Control for Each Channel for more details. When a channel is configured in
LED bank-control mode, the related color mixing and intensity control is governed by the bank control registers
(BANK_A_COLOR, BANK_B_COLOR, BANK_C_COLOR, and BANK_BRIGHTNESS) regardless of the inputs
on its own color-mixing and intensity-control registers.
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Feature Description (接下页)
Bank Color-Mixing Bank Brightness-Control
Bank PWM Generators
Bank A:
Bank B:
Bank C:
8 Bits Color
8 Bits Color
8 Bits Color
12 Bits / 29kHz PWM
8 Bits Brightness
12 Bits / 29kHz PWM
12 Bits / 29kHz PWM
图 13. Bank PWM Control Scheme
表 1. Bank Number and LED Number Assignment
OUT NUMBER
BANK Number
Bank A
Bank B
Bank C
Bank A
Bank B
Bank C
Bank A
Bank B
Bank C
Bank A
Bank B
Bank C
Bank A
Bank B
Bank C
Bank A
Bank B
Bank C
Bank A
Bank B
Bank C
Bank A
Bank B
Bank C
RGB LED MODULE NUMBER
OUT0
OUT1
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18 (LP5024 only)
OUT19 (LP5024 only)
OUT20 (LP5024 only)
OUT21 (LP5024 only)
OUT22 (LP5024 only)
OUT23 (LP5024 only)
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With the bank control configuration, the LP50xx device enables users to achieve smooth and live LED effects
globally with an ultrasimple software effort. 图 14 shows an example using LED0 as an independent RGB
indicator and others with group breathing effect.
Bank A
CH3/6/9/12/15/18/21
Bank B
Independent
Ch0/1/2
CH4/7/10/13/16/19/22
Bank C
CH5/8/11/14/17/20/23
图 14. Bank PWM Control Example
8.3.3 Current Range Setting
The constant-current value (ISET) of all 24 channels is set by a single external resistor, RIREF. The value of RIREF
can be calculated by 公式 1.
VIREF
RIREF=KIREF
×
ISET
where:
•
•
KIREF = 105
VIREF = 0.7 V
(1)
With the IREF pin floating, the output current is close to zero. With the IREF pin shorted to GND, the LP50xx
device provides internal current-limit protection, and the output-channel maximum current is limited to ILIM
.
The LP50xx device supports two levels of maximum output current, IMAX
.
•
•
When VCC is in the range from 2.7 V to 5.5 V, and the Max_Current_Option (bit) = 0, IMAX = 25.5 mA.
When VCC is in the range from 3.3 V to 5.5 V, and the Max_Current_Option (bit) = 1, IMAX = 35 mA.
8.3.4 Automatic Power-Save Mode
When all the LED outputs are inactive, the LP50xx device is able to enter power-save mode automatically, thus
lowering idle-current consumption down to 10 μA (typical). Automatic power-save mode is enabled when register
bit Power_Save_EN = 1 (default) and all the LEDs are off for a duration of >30 ms. Almost all analog blocks are
powered down in power-save mode. If any I2C command to the device occurs, the LP50xx device returns to
NORMAL mode.
16
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8.3.5 Protection Features
8.3.5.1 Thermal Shutdown
The LP50xx device implements a thermal shutdown mechanism to protect the device from damage due to
overheating. When the junction temperature rises to 160°C (typical), the device switches into shutdown mode.
The LP50xx device releases thermal shutdown when the junction temperature of the device is reduced to 145°C
(typical).
8.3.5.2 UVLO
The LP50xx device has an internal comparator that monitors the voltage at VCC. When VCC is below VUVF, reset
is active and the LP50xx device is in the INITIALIZATION state.
8.4 Device Functional Modes
VCC Power Up
EN = L
From all states
From all states
SHUTDOWN
EN = H
RESET = FF or UVLO = H
INITIALIZATION
STANDBY
Chip_EN = 1
Chip_EN = 0
TSD=H
TSD=L
I2C Command
THERMAL
SHUTDOWN
POWER SAVE
NORMAL
Power_Save_EN =1 and
All LEDs off > 30ms
图 15. Functional Modes
•
INITIALIZATION: The device enters into INITIALIZATION mode when EN = H. In this mode, all the registers
are reset. Entry can also be from any state, if the RESET (register) = FFh or UVLO is active.
•
•
NORMAL: The device enters the NORMAL mode when Chip_EN (register) = 1. ICC is 10 mA (typ.).
POWER SAVE: The device automatically enters the POWER SAVE mode when Power_Save_EN (register) =
1 and all the LEDs are off for a duration of >30 ms. In POWER SAVE mode, analog blocks are disabled to
minimize power consumption, but the registers retain the data and keep it available via I2C. ICC is 10 µA (typ.).
In case of any I2C command to this device, it returns to the NORMAL mode.
•
•
SHUTDOWN: The device enters into SHUTDOWN mode from all states on VCC power up or when EN = L.
ICC is < 1 µA (max).
STANDBY: The device enters the STANDBY mode when Chip_EN (register) = 0. In this mode, all the OUTx
pins are shut down, but the registers retain the data and keep it available via I2C. STANDBY is the low-
power-consumption mode, when all circuit functions are disabled. ICC is 10 µA (typ.).
•
THERMAL SHUTDOWN: The device automatically enters the THERMAL SHUTDOWN mode when the
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Device Functional Modes (接下页)
junction temperature exceeds 160°C (typical). In this mode, all the OUTx outputs are shut down. If the
junction temperature decreases below 145°C (typical), the device returns to the NORMAL mode.
8.5 Programming
8.5.1 I2C Interface
The I2C-compatible two-wire serial interface provides access to the programmable functions and registers on the
device. This protocol uses a two-wire interface for bidirectional communications between the devices connected
to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL). Every device on
the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates
or receives the serial clock, SCL. The SCL and SDA lines should each have a pullup resistor placed somewhere
on the line and remain HIGH even when the bus is idle.
8.5.1.1 Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state
of the data line can only be changed when the clock signal is LOW.
图 16. Data Validity
8.5.1.2 Start and Stop Conditions
START and STOP conditions classify the beginning and the end of the data transfer session. A START condition
is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. A STOP condition is
defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates
START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP
condition. During data transmission, the bus master can generate repeated START conditions. First START and
repeated START conditions are functionally equivalent.
图 17. Start and Stop Conditions
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Programming (接下页)
8.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most-significant bit (MSB) being transferred first.
Each byte of data must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by
the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls
down the SDA line during the ninth clock pulse, signifying an acknowledge. The device generates an
acknowledge after each byte has been received.
There is one exception to the acknowledge-after-every-byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1
indicates a READ. The second byte selects the register to which the data is written. The third byte contains data
to write to the selected register.
图 18. Acknowledge and Not Acknowledge on I2C Bus
8.5.1.4 I2C Slave Addressing
The device slave address is defined by connecting GND or VCC to the ADDR0 and ADDR1 pins. A total of four
independent slave addresses can be realized by combinations when GND or VCC is connected to the ADDR0
and ADDR1 pins (see 表 2 and 表 3).
The device responds to a broadcast slave address regardless of the setting of the ADDR0 and ADDR1 pins.
Global writes to the broadcast address can be used for configuring all devices simultaneously. The device
supports global read using a broadcast address; however, the data read is only valid if all devices on the I2C bus
contain the same value in the addressed register.
表 2. Slave-Address Combinations
SLAVE ADDRESS
ADDR1
ADDR0
INDEPENDENT
010 1000
BROADCAST
GND
GND
VCC
VCC
GND
VCC
GND
VCC
010 1001
011 1100
010 1010
010 1011
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表 3. Chip Address
SLAVE ADDRESS
R/W
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ADDR1
0
Bit 1
ADDR0
0
Independent
Broadcast
0
0
1
1
0
1
1
1
0
1
1 or 0
1 or 0
8.5.1.5 Control-Register Write Cycle
•
•
•
•
•
•
•
•
The master device generates a start condition.
The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).
The slave device sends an acknowledge signal if the slave address is correct.
The master device sends the control register address (8 bits).
The slave device sends an acknowledge signal.
The master device sends the data byte to be written to the addressed register.
The slave device sends an acknowledge signal.
If the master device sends further data bytes, the control register address of the slave is incremented by 1
after the acknowledge signal. To reduce program load time, the device supports address auto incrementation.
The register address is incremented after each 8 data bits.
•
The write cycle ends when the master device creates a stop condition.
图 19. Write Cycle
8.5.1.6 Control-Register Read Cycle
•
•
•
•
•
•
•
•
•
•
The master device generates a start condition.
The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).
The slave device sends an acknowledge signal if the slave address is correct.
The master device sends the control register address (8 bits).
The slave device sends an acknowledge signal.
The master device generates a repeated-start condition.
The master device sends the slave address (7 bits) and the data direction bit (R/W = 1).
The slave device sends an acknowledge signal if the slave address is correct.
The slave device sends the data byte from the addressed register.
If the master device sends an acknowledge signal, the control-register address is incremented by 1. The
slave device sends the data byte from the addressed register. To reduce program load time, the device
supports address auto incrementation. The register address is incremented after each 8 data bits.
•
The read cycle ends when the master device does not generate an acknowledge signal after a data byte and
generates a stop condition.
图 20. Read Cycle
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8.5.1.7 Auto-Increment Feature
The auto-increment feature allows writing or reading several consecutive registers within one transmission. For
example, when an 8-bit word is sent to the device, the internal address index counter is incremented by 1, and
the next register is written. The auto-increment feature is enabled by default and can be disabled by setting the
Auto_Incr_EN bit = 0 in the DEVICE_CONFIG1 register. The auto-increment feature is applied for the full register
address from 0h to FFh.
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8.6 Register Maps
表 4 lists the memory-mapped registers of the device.
表 4. Register Maps
REGISTER
NAME
DEF-
AULT
ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
DEVICE_
CONFIG0
00h
01h
R/W
R/W
RESERVED
Chip_EN
RESERVED
00h
DEVICE_
CONFIG1
Power_Save_
PWM_
Dithering_EN
Max_Current_
Option
RESERVED
LED7_Bank_EN LED6_Bank_EN
Log_Scale_EN
Auto_Incr_EN
LED_Global Off
3Ch
00h
EN
LED_CONFIG0
02h
R/W
(Only for
LP5024)
(Only for
LP5024)
LED5_Bank_EN LED4_Bank_EN LED3_Bank_EN LED2_Bank_EN LED1_Bank_EN LED0_Bank_EN
BANK_
BRIGHTNESS
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bank_Brightness
Bank_A_Color
FFh
00h
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
BANK_A_
COLOR
BANK_B_
COLOR
Bank_B_Color
BANK_C_
COLOR
Bank_C_Color
LED0_
BRIGHTNESS
LED0_Brightness
LED1_Brightness
LED2_Brightness
LED3_Brightness
LED4_Brightness
LED5_Brightness
LED1_
BRIGHTNESS
LED2_
BRIGHTNESS
LED3_
BRIGHTNESS
LED4_
BRIGHTNESS
LED5_
BRIGHTNESS
LED6_
BRIGHTNESS
LED6_Brightness
(Only for LP5024)
LED7_
BRIGHTNESS
LED7_Brightness
(Only for LP5024)
OUT0_COLOR
OUT1_COLOR
OUT2_COLOR
OUT3_COLOR
0Fh
10h
11h
12h
R/W
R/W
R/W
R/W
OUT0_Color
OUT1_Color
OUT2_Color
OUT3_Color
00h
00h
00h
00h
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Register Maps (接下页)
表 4. Register Maps (接下页)
REGISTER
ADDR TYPE
NAME
DEF-
D7
D6
D5
D4
D3
D2
D1
D0
AULT
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
OUT4_COLOR
OUT5_COLOR
OUT6_COLOR
OUT7_COLOR
OUT8_COLOR
OUT9_COLOR
OUT10_COLOR
OUT11_COLOR
OUT12_COLOR
OUT13_COLOR
OUT14_COLOR
OUT15_COLOR
OUT16_COLOR
OUT17_COLOR
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OUT4_Color
OUT5_Color
OUT6_Color
OUT7_Color
OUT8_Color
OUT9_Color
OUT10_Color
OUT11_Color
OUT12_Color
OUT13_Color
OUT14_Color
OUT15_Color
OUT16_Color
OUT17_Color
OUT18_Color
OUT18_COLOR
OUT19_COLOR
OUT20_COLOR
OUT21_COLOR
OUT22_COLOR
21h
22h
23h
24h
25h
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
00h
(Only for LP5024)
OUT19_Color
(Only for LP5024)
OUT20_Color
(Only for LP5024)
OUT21_Color
(Only for LP5024)
OUT22_Color
(Only for LP5024)
OUT23_Color
(Only for LP5024)
OUT23_COLOR
RESET
26h
27h
R/W
W
00h
00h
Reset
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表 5. Access Type Codes
ACCESS TYPE
CODE
DESCRIPTION
Read Type
R
R
Read
Write
Write Type
W
W
Reset or Default Value
-n
Value after reset or the default
value
8.6.1 DEVICE_CONFIG0 (Address = 0h) [reset = 0h]
DEVICE_CONFIG0 is shown in 图 21 and described in 表 6.
Return to 表 4.
图 21. DEVICE_CONFIG0 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
Chip_EN
R/W-0h
RESERVED
R/W-0h
表 6. DEVICE_CONFIG0 Register Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
0h
Description
Reserved
6
Chip_EN
0h
1 = LP50xx enabled
0 = LP50xx not enabled
5–0
RESERVED
R/W
0h
Reserved
8.6.2 DEVICE_CONFIG1 (Address = 1h) [reset = 3Ch]
DEVICE_CONFIG1 is shown in 图 22 and described in 表 7.
Return to 表 4.
图 22. DEVICE_CONFIG1 Register
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
Log_Scale_EN Power_Save_E Auto_Incr_EN PWM_Dithering Optional_Headr LED_Global Off
N
_EN
oom
R/W-1h
R/W-1h
R/W-1h
R/W-1h
R/W-0h
R/W-0h
表 7. DEVICE_CONFIG1 Register Field Descriptions
Bit
7–6
5
Field
Type
R/W
R/W
Reset
0h
Description
RESERVED
Reserved
Log_Scale_EN
1h
1 = Logarithmic scale dimming curve enabled
0 = Linear scale dimming curve enabled
4
3
2
1
0
Power_Save_EN
Auto_Incr_EN
R/W
R/W
R/W
R/W
R/W
1h
1h
1h
0h
0h
1 = Automatic power-saving mode enabled
0 = Automatic power-saving mode not enabled
1 = Automatic increment mode enabled
0 = Automatic increment mode not enabled
PWM_Dithering_EN
Max_Current_Option
LED_Global Off
1 = PWM dithering mode enabled
0 = PWM dithering mode not enabled
1 = Output maximum current IMAX = 35 mA.
0 = Output maximum current IMAX = 25.5 mA.
1 = Shut down all LEDs
0 = Normal operation
24
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ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
8.6.3 LED_CONFIG0 (Address = 2h) [reset = 00h]
LED_CONFIG0 is shown in 图 23 and described in 表 8.
Return to 表 4.
图 23. LED_CONFIG0 Register
7
6
5
4
3
2
1
0
LED7_Bank_E LED6_Bank_E LED5_Bank_E LED4_Bank_E LED3_Bank_E LED2_Bank_E LED1_Bank_E LED0_Bank_E
N
N
N
N
N
N
N
N
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表 8. LED_CONFIG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LED7_Bank_EN
LED6_Bank_EN
LED5_Bank_EN
LED4_Bank_EN
LED3_Bank_EN
LED2_Bank_EN
LED1_Bank_EN
LED0_Bank_EN
R/W
0h
1 = LED7 bank control mode enabled
0 = LED7 independent control mode enabled
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
1 = LED6 bank control mode enabled
0 = LED6 independent control mode enabled
1 = LED5 bank control mode enabled
0 = LED5 independent control mode enabled
1 = LED4 bank control mode enabled
0 = LED4 independent control mode enabled
1 = LED3 bank control mode enabled
0 = LED3 Independent control mode enabled
1 = LED2 bank control mode enabled
0 = LED2 independent control mode enabled
1 = LED1 bank control mode enabled
0 = LED1 independent control mode enabled
1 = LED0 bank control mode enabled
0 = LED0 independent control mode enabled
8.6.4 BANK_BRIGHTNESS (Address = 3h) [reset = FFh]
BANK_BRIGHTNESS is shown in 图 24 and described in 表 9.
Return to 表 4.
图 24. BANK_BRIGHTNESS Register
7
6
5
4
3
2
1
0
Bank_Brightness
R/W-FFh
表 9. BANK_BRIGHTNESS Register Field Descriptions
Bit
Field
Bank_Brightness
Type
Reset
Description
7–0
R/W
FFh
FFh = 100% of full brightness
...
80h = 50% of full brightness
...
00h = 0% of full brightness
8.6.5 BANK_A_COLOR (Address = 4h) [reset = 00h]
BANK_A_COLOR is shown in 图 25 and described in 表 10.
Return to 表 4.
版权 © 2018, Texas Instruments Incorporated
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图 25. BANK_A_COLOR Register
7
6
5
4
3
2
1
0
Bank_A_Color
R/W-0h
表 10. BANK_A_COLOR Register Field Descriptions
Bit
Field
Bank_A_Color
Type
Reset
Description
7–0
R/W
0h
FFh = The color mixing percentage is 100%.
...
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.
8.6.6 BANK_B_COLOR (Address = 5h) [reset = 00h]
BANK_B_COLOR is shown in 图 26 and described in 表 11.
Return to 表 4.
图 26. BANK_B_COLOR Register
7
6
5
4
3
2
1
0
Bank_B_Color
R/W-0h
表 11. BANK_B_COLOR Register Field Descriptions
Bit
Field
Bank_B_Color
Type
Reset
Description
7–0
R/W
0h
FFh = The color mixing percentage is 100%.
...
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.
8.6.7 BANK_C_COLOR (Address = 6h) [reset = 00h]
BANK_C_COLOR is shown in 图 27 and described in 表 12.
Return to 表 4.
图 27. BANK_C_COLOR Register
7
6
5
4
3
2
1
0
Bank_C_Color
R/W-0h
表 12. BANK_C_COLOR Register Field Descriptions
Bit
Field
Bank_C_Color
Type
Reset
Description
7–0
R/W
0h
FFh = The color mixing percentage is 100%.
...
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.
8.6.8 LED0_BRIGHTNESS (Address = 7h) [reset = FFh]
LED0_BRIGHTNESS is shown in 图 28 and described in 表 13.
Return to 表 4.
26
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ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
图 28. LED0_BRIGHTNESS Register
7
6
5
4
3
2
1
0
LED0_Brightness
R/W-FFh
表 13. LED0_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
LED0_Brightness
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.9 LED1_BRIGHTNESS (Address = 8h) [reset = FFh]
LED1_BRIGHTNESS is shown in 图 29 and described in 表 14.
Return to 表 4.
图 29. LED1_BRIGHTNESS Register
7
6
5
4
3
2
1
0
LED1_Brightness
R/W-FFh
表 14. LED1_BRIGHTNESS Register Field Descriptions
Bit
Field
LED1_Brightness
Type
Reset
Description
7–0
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.10 LED2_BRIGHTNESS (Address = 9h) [reset = FFh]
LED2_BRIGHTNESS is shown in 图 30 and described in 表 15.
Return to 表 4.
图 30. LED2_BRIGHTNESS Register
7
6
5
4
3
2
1
0
LED2_Brightness
R/W-FFh
表 15. LED2_BRIGHTNESS Register Field Descriptions
Bit
Field
LED2_Brightness
Type
Reset
Description
7–0
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.11 LED3_BRIGHTNESS (Address = 0Ah) [reset = FFh]
LED3_BRIGHTNESS is shown in 图 31 and described in 表 16.
Return to 表 4.
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图 31. LED3_BRIGHTNESS Register
7
6
5
4
3
2
1
0
LED3_Brightness
R/W-FFh
表 16. LED3_BRIGHTNESS Register Field Descriptions
Bit
Field
LED3_Brightness
Type
Reset
Description
7–0
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.12 LED4_BRIGHTNESS (Address = 0Bh) [reset = FFh]
LED4_BRIGHTNESS is shown in 图 32 and described in 表 17.
Return to 表 4.
图 32. LED4_BRIGHTNESS Register
7
6
5
4
3
2
1
0
LED4_Brightness
R/W-FFh
表 17. LED4_BRIGHTNESS Register Field Descriptions
Bit
Field
LED4_Brightness
Type
Reset
Description
7–0
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.13 LED5_BRIGHTNESS (Address = 0Ch) [reset = FFh]
LED5_BRIGHTNESS is shown in 图 33 and described in 表 18.
Return to 表 4.
图 33. LED5_BRIGHTNESS Register
7
6
5
4
3
2
1
0
LED5_Brightness
R/W-FFh
表 18. LED5_BRIGHTNESS Register Field Descriptions
Bit
Field
LED5_Brightness
Type
Reset
Description
7–0
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.14 LED6_BRIGHTNESS (Address = 0Dh) [reset = FFh]
LED6_BRIGHTNESS is shown in 图 34 and described in 表 19.
Return to 表 4.
28
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ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
图 34. LED6_BRIGHTNESS Register
7
6
5
4
3
2
1
0
LED6_Brightness
R/W-FFh
表 19. LED6_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
LED6_Brightness
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.15 LED7_BRIGHTNESS (Address = 0Eh) [reset = FFh]
LED7_BRIGHTNESS is shown in 图 35 and described in 表 20.
Return to 表 4.
图 35. LED7_BRIGHTNESS Register
7
6
5
4
3
2
1
0
LED7_Brightness
R/W-FFh
表 20. LED7_BRIGHTNESS Register Field Descriptions
Bit
Field
LED7_Brightness
Type
Reset
Description
7–0
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.16 OUT0_COLOR (Address = 0Fh) [reset = 00h]
OUT0_COLOR is shown in 图 36 and described in 表 21.
Return to 表 4.
图 36. OUT0_COLOR Register
7
6
5
4
3
2
1
0
OUT0_Color
R/W-00h
表 21. OUT0_COLOR Register Field Descriptions
Bit
Field
OUT0_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.17 OUT1_COLOR (Address = 10h) [reset = 00h]
OUT1_COLOR is shown in 图 37 and described in 表 22.
Return to 表 4.
版权 © 2018, Texas Instruments Incorporated
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图 37. OUT1_COLOR Register
7
6
5
4
3
2
1
0
OUT1_Color
R/W-00h
表 22. OUT1_COLOR Register Field Descriptions
Bit
Field
OUT1_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.18 OUT2_COLOR (Address = 11h) [reset = 00h]
OUT2_COLOR is shown in 图 38 and described in 表 23.
Return to 表 4.
图 38. OUT2_COLOR Register
7
6
5
4
3
2
1
0
OUT2_Color
R/W-00h
表 23. OUT2_COLOR Register Field Descriptions
Bit
Field
OUT2_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.19 OUT3_COLOR (Address = 12h) [reset = 00h]
OUT3_COLOR is shown in 图 39 and described in 表 24.
Return to 表 4.
图 39. OUT3_COLOR Register
7
6
5
4
3
2
1
0
OUT3_Color
R/W-00h
表 24. OUT3_COLOR Register Field Descriptions
Bit
Field
OUT3_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.20 OUT4_COLOR (Address = 13h) [reset = 00h]
OUT4_COLOR is shown in 图 40 and described in 表 25.
Return to 表 4.
30
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ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
图 40. OUT4_COLOR Register
7
6
5
4
3
2
1
0
OUT4_Color
R/W-00h
表 25. OUT4_COLOR Register Field Descriptions
Bit
Field
OUT4_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.21 OUT5_COLOR (Address = 14h) [reset = 00h]
OUT5_COLOR is shown in 图 41 and described in 表 26.
Return to 表 4.
图 41. OUT5_COLOR Register
7
6
5
4
3
2
1
0
OUT5_Color
R/W-00h
表 26. OUT5_COLOR Register Field Descriptions
Bit
Field
OUT5_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.22 OUT6_COLOR (Address = 15h) [reset = 00h]
OUT6_COLOR is shown in 图 42 and described in 表 27.
Return to 表 4.
图 42. OUT6_COLOR Register
7
6
5
4
3
2
1
0
OUT6_Color
R/W-00h
表 27. OUT6_COLOR Register Field Descriptions
Bit
Field
OUT6_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.23 OUT7_COLOR (Address = 16h) [reset = 00h]
OUT7_COLOR is shown in 图 43 and described in 表 28.
Return to 表 4.
版权 © 2018, Texas Instruments Incorporated
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图 43. OUT7_COLOR Register
7
6
5
4
3
2
1
0
OUT7_Color
R/W-00h
表 28. OUT7_COLOR Register Field Descriptions
Bit
Field
OUT7_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.24 OUT8_COLOR (Address = 17h) [reset = 00h]
OUT8_COLOR is shown in 图 44 and described in 表 29.
Return to 表 4.
图 44. OUT8_COLOR Register
7
6
5
4
3
2
1
0
OUT8_Color
R/W-00h
表 29. OUT8_COLOR Register Field Descriptions
Bit
Field
OUT8_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.25 OUT9_COLOR (Address = 18h) [reset = 00h]
OUT9_COLOR is shown in 图 45 and described in 表 30.
Return to 表 4.
图 45. OUT9_COLOR Register
7
6
5
4
3
2
1
0
OUT9_Color
R/W-00h
表 30. OUT9_COLOR Register Field Descriptions
Bit
Field
OUT9_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.26 OUT10_COLOR (Address = 19h) [reset = 00h]
OUT10_COLOR is shown in 图 46 and described in 表 31.
Return to 表 4.
32
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ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
图 46. OUT10_COLOR Register
7
6
5
4
3
2
1
0
OUT10_Color
R/W-00h
表 31. OUT10_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT10_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.27 OUT11_COLOR (Address = 1Ah) [reset = 00h]
OUT11_COLOR is shown in 图 47 and described in 表 32.
Return to 表 4.
图 47. OUT11_COLOR Register
7
6
5
4
3
2
1
0
OUT11_Color
R/W-00h
表 32. OUT11_COLOR Register Field Descriptions
Bit
Field
OUT11_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.28 OUT12_COLOR (Address = 1Bh) [reset = 00h]
OUT12_COLOR is shown in 图 48 and described in 表 33.
Return to 表 4.
图 48. OUT12_COLOR Register
7
6
5
4
3
2
1
0
OUT12_Color
R/W-00h
表 33. OUT12_COLOR Register Field Descriptions
Bit
Field
OUT12_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.29 OUT13_COLOR (Address = 1Ch) [reset = 00h]
OUT13_COLOR is shown in 图 49 and described in 表 34.
Return to 表 4.
版权 © 2018, Texas Instruments Incorporated
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图 49. OUT13_COLOR Register
7
6
5
4
3
2
1
0
OUT13_Color
R/W-00h
表 34. OUT13_COLOR Register Field Descriptions
Bit
Field
OUT13_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.30 OUT14_COLOR (Address = 1Dh) [reset = 00h]
OUT14_COLOR is shown in 图 50 and described in 表 35.
Return to 表 4.
图 50. OUT14_COLOR Register
7
6
5
4
3
2
1
0
OUT14_Color
R/W-00h
表 35. OUT14_COLOR Register Field Descriptions
Bit
Field
OUT14_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.31 OUT15_COLOR (Address = 1Eh) [reset = 00h]
OUT15_COLOR is shown in 图 51 and described in 表 36.
Return to 表 4.
图 51. OUT15_COLOR Register
7
6
5
4
3
2
1
0
OUT15_Color
R/W-00h
表 36. OUT15_COLOR Register Field Descriptions
Bit
Field
OUT15_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.32 OUT16_COLOR (Address = 1Fh) [reset = 00h]
OUT16_COLOR is shown in 图 52 and described in 表 37.
Return to 表 4.
34
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ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
图 52. OUT16_COLOR Register
7
6
5
4
3
2
1
0
OUT16_Color
R/W-00h
表 37. OUT16_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT16_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.33 OUT17_COLOR (Address = 20h) [reset = 00h]
OUT17_COLOR is shown in 图 53 and described in 表 38.
Return to 表 4.
图 53. OUT17_COLOR Register
7
6
5
4
3
2
1
0
OUT17_Color
R/W-00h
表 38. OUT17_COLOR Register Field Descriptions
Bit
Field
OUT17_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.34 OUT18_COLOR (Address = 21h) [reset = 00h]
OUT18_COLOR is shown in 图 54 and described in 表 39.
Return to 表 4.
图 54. OUT18_COLOR Register
7
6
5
4
3
2
1
0
OUT18_Color
R/W-00h
表 39. OUT18_COLOR Register Field Descriptions
Bit
Field
OUT18_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.35 OUT19_COLOR (Address = 22h) [reset = 00h]
OUT19_COLOR is shown in 图 55 and described in 表 40.
Return to 表 4.
版权 © 2018, Texas Instruments Incorporated
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图 55. OUT19_COLOR Register
7
6
5
4
3
2
1
0
OUT19_Color
R/W-00h
表 40. OUT19_COLOR Register Field Descriptions
Bit
Field
OUT19_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.36 OUT20_COLOR (Address = 23h) [reset = 00h]
OUT20_COLOR is shown in 图 56 and described in 表 41.
Return to 表 4.
图 56. OUT20_COLOR Register
7
6
5
4
3
2
1
0
OUT20_Color
R/W-00h
表 41. OUT20_COLOR Register Field Descriptions
Bit
Field
OUT20_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.37 OUT21_COLOR (Address = 24h) [reset = 00h]
OUT21_COLOR is shown in 图 57 and described in 表 42.
Return to 表 4.
图 57. OUT21_COLOR Register
7
6
5
4
3
2
1
0
OUT21_Color
R/W-00h
表 42. OUT21_COLOR Register Field Descriptions
Bit
Field
OUT21_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.38 OUT22_COLOR (Address = 25h) [reset = 00h]
OUT22_COLOR is shown in 图 58 and described in 表 43.
Return to 表 4.
36
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LP5018, LP5024
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ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
图 58. OUT22_COLOR Register
7
6
5
4
3
2
1
0
OUT22_Color
R/W-00h
表 43. OUT22_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT22_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.39 OUT23_COLOR (Address = 26h) [reset = 00h]
OUT23_COLOR is shown in 图 59 and described in 表 44.
Return to 表 4.
图 59. OUT23_COLOR Register
7
6
5
4
3
2
1
0
OUT23_Color
R/W-00h
表 44. OUT23_COLOR Register Field Descriptions
Bit
Field
OUT23_Color
Type
Reset
Description
7–0
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.40 RESET (Address = 27h) [reset = 00h]
RESET is shown in 图 60 and described in 表 45.
Return to 表 4.
图 60. RESET Register
7
6
5
4
3
2
1
0
Reset
W-00h
表 45. OUT14_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
FFh = Reset all the registers to default value.
7–0
Reset
W
00h
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37
LP5018, LP5024
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
www.ti.com.cn
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP50xx device is an 18- or 24-channel constant-current-sink LED driver. The LP50xx device improves the
user experience in color mixing and intensity control, for both live effects and coding effort. The optimized
performance for RGB LEDs makes it a good choice for human-machine interaction applications.
9.2 Typical Application
The LP50xx design supports up to four devices in parallel with different configurations on the ADDR0 and
ADDR1 pins.
38
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LP5018, LP5024
www.ti.com.cn
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
Typical Application (接下页)
VCC
CVCC
VMCU
VLED
VCC
OUT0
RPULLUP
RPULLUP
EN
OUT1
OUT2
SDA
SCL
ADDR0
ADDR1
MCU
LP5024
OUT21
VCAP
IREF
CVCAP
RIREF
OUT22
OUT23
GND
VCC
CVCC
VLED
VCC
OUT0
EN
OUT1
OUT2
SDA
SCL
ADDR0
ADDR1
LP5024
OUT21
VCAP
IREF
CVCAP
OUT22
OUT23
RIREF
GND
图 61. Driving Dual LP5024 Application Example
9.2.1 Design Requirements
Set the LED current to 15 mA using the RIREF resistor.
9.2.2 Detailed Design Procedure
LP50xx scales up the reference current (IREF) set by the external resistor (RIREF) to sink the output current (IOUT
)
at each output port. The following formula can be used to calculate the external resistor (RIREF):
版权 © 2018, Texas Instruments Incorporated
39
LP5018, LP5024
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
www.ti.com.cn
Typical Application (接下页)
VIREF
RIREF=KIREF
×
ISET
(2)
The SCL and SDA lines must each have a pullup resistor placed somewhere on the line (the pullup resistors are
normally located on the bus master). In typical applications, values of 1.8 kΩ to 4.7 kΩ are used.
VCAP is internal LDO output pin. This pin must be connected through a 1-µF capacitor to GND. Place the
capacitor as close to the device as possible.
TI recommends having a 1-µF capacitor between VCC and GND to ensure proper operation. Place the capacitor
as close to the device as possible.
9.2.3 Application Curves
The test condition for is that the testing is under bank control, using the following register values: 0x02 (0xFF),
0x04 (0xA0), 0x05 (0xA0), 0x06 (0xA0).
The test condition for is that the testing is under bank control, using the following register values: 0x02 (0xFF),
0x04 (0x10), 0x05 (0x10), 0x06 (0x10).
图 62. Current Waveform of OUT0, OUT1, OUT2 and OUT3
图 63. Current Waveform of OUT0, OUT1, OUT2 and OUT3
40
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LP5018, LP5024
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ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
10 Power Supply Recommendations
The device is designed to operate from a VVCC input-voltage supply range between 2.7 V and 5.5 V. This input
supply must be well-regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even in a load-transition condition (start-up or rapid intensity change). The resistance of the input
supply rail must be low enough that the input-current transient does not cause a drop below a 2.7-V level in the
LP50xx VVCC supply voltage.
11 Layout
11.1 Layout Guidelines
To prevent thermal shutdown, the junction temperature, TJ, must be less than T(TSD). If the voltage drop across
the output channels is high, the device power dissipation can be large. The LP50xx device has very good
thermal performance because of the thermal pad design; however, the PCB layout is also very important to
ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is
essential for the long-term reliability of the device.
Use the following guidelines when designing the device layout:
•
Place the CVCAP, CVCCand RIREF as close to the device as possible. Also, TI recommends to put the ground
plane as 图 64 and 图 65.
•
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat
flow path from the package to the ambient is through copper on the PCB. Maximum copper density is
extremely important when no heat sinks are attached to the PCB on the other side from the package.
•
•
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
Use either plated-shut or plugged and capped vias for all the thermal vias on both sides of the board to
prevent solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
版权 © 2018, Texas Instruments Incorporated
41
LP5018, LP5024
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
www.ti.com.cn
11.2 Layout Examples
GND
GND
OUT0
OUT1
OUT2
1
2
3
4
5
6
7
8
To LED
To LED
To LED
24
23
22
21
20
19
18
17
To LED OUT3
GND
To LED
To LED
OUT4
OUT5
To LED OUT6
To LED OUT7
To LED
To LED
OUT17
OUT16
GND
GND
图 64. LP5018 Layout Example
42
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LP5018, LP5024
www.ti.com.cn
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
Layout Examples (接下页)
GND
GND
OUT0
OUT1
OUT2
1
2
3
4
5
6
7
8
To LED
To LED
To LED
24
23
22
21
20
19
18
17
To LED
To LED
To LED
To LED
To LED
To LED
To LED
To LED
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
To LED OUT3
GND
To LED
To LED
OUT4
OUT5
To LED OUT6
To LED OUT7
GND
GND
图 65. LP5024 Layout Example
版权 © 2018, Texas Instruments Incorporated
43
LP5018, LP5024
ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
www.ti.com.cn
12 器件和文档支持
12.1 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 46. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
LP5018
LP5024
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
44
版权 © 2018, Texas Instruments Incorporated
LP5018, LP5024
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ZHCSHV7B –OCTOBER 2018–REVISED OCTOBER 2018
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航面板。
版权 © 2018, Texas Instruments Incorporated
45
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP5018RSMR
LP5024RSMR
ACTIVE
VQFN
VQFN
RSM
32
32
3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 125
-40 to 85
LP
5018
ACTIVE
RSM
3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
LP
5024
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5018RSMR
LP5024RSMR
VQFN
VQFN
RSM
RSM
32
32
3000
3000
330.0
330.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP5018RSMR
LP5024RSMR
VQFN
VQFN
RSM
RSM
32
32
3000
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RSM 32
4 x 4, 0.4 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224982/A
www.ti.com
PACKAGE OUTLINE
RSM0032B
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
B
4.1
3.9
A
0.45
0.25
0.25
0.15
PIN 1 INDEX AREA
DETAIL
OPTIONAL TERMINAL
TYPICAL
4.1
3.9
(0.1)
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2.8 0.05
2X 2.8
(0.2) TYP
4X (0.45)
28X 0.4
9
16
SEE SIDE WALL
DETAIL
8
17
EXPOSED
THERMAL PAD
2X
SYMM
33
2.8
24
0.25
32X
1
SEE TERMINAL
DETAIL
0.15
0.1
C A B
25
32
PIN 1 ID
(OPTIONAL)
0.05
SYMM
0.45
0.25
32X
4219108/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.8)
SYMM
32
25
32X (0.55)
1
32X (0.2)
24
(
0.2) TYP
VIA
(1.15)
SYMM
33
(3.85)
28X (0.4)
17
8
(R0.05)
TYP
9
16
(1.15)
(3.85)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219108/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RSM0032B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.715)
4X ( 1.23)
(R0.05) TYP
25
32
32X (0.55)
1
24
32X (0.2)
(0.715)
(3.85)
33
SYMM
28X (0.4)
17
8
METAL
TYP
16
9
SYMM
(3.85)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 33:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4219108/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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